AU579764B2 – Sidewall spacers for CMOS circuit stress relief/isolation and method for making
– Google Patents
AU579764B2 – Sidewall spacers for CMOS circuit stress relief/isolation and method for making
– Google Patents
Sidewall spacers for CMOS circuit stress relief/isolation and method for making
Info
Publication number
AU579764B2
AU579764B2
AU69959/87A
AU6995987A
AU579764B2
AU 579764 B2
AU579764 B2
AU 579764B2
AU 69959/87 A
AU69959/87 A
AU 69959/87A
AU 6995987 A
AU6995987 A
AU 6995987A
AU 579764 B2
AU579764 B2
AU 579764B2
Authority
AU
Australia
Prior art keywords
isolation
making
sidewall spacers
stress relief
cmos circuit
Prior art date
1986-03-17
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU69959/87A
Other versions
AU6995987A
(en
Inventor
Anthony John Dally
Seiki Ogura
Jacob Riseman
Nivo Rovedo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1986-03-17
Filing date
1987-03-12
Publication date
1988-12-08
1987-03-12
Application filed by International Business Machines Corp
filed
Critical
International Business Machines Corp
1987-09-24
Publication of AU6995987A
publication
Critical
patent/AU6995987A/en
1988-12-08
Application granted
granted
Critical
1988-12-08
Publication of AU579764B2
publication
Critical
patent/AU579764B2/en
2007-03-12
Anticipated expiration
legal-status
Critical
Status
Ceased
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
H01L21/76—Making of isolation regions between components
H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
AU69959/87A
1986-03-17
1987-03-12
Sidewall spacers for CMOS circuit stress relief/isolation and method for making
Ceased
AU579764B2
(en)
Applications Claiming Priority (2)
Application Number
Priority Date
Filing Date
Title
US840180
1986-03-17
US06/840,180
US4729006A
(en)
1986-03-17
1986-03-17
Sidewall spacers for CMOS circuit stress relief/isolation and method for making
Publications (2)
Publication Number
Publication Date
AU6995987A
AU6995987A
(en)
1987-09-24
AU579764B2
true
AU579764B2
(en)
1988-12-08
Family
ID=25281647
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
AU69959/87A
Ceased
AU579764B2
(en)
1986-03-17
1987-03-12
Sidewall spacers for CMOS circuit stress relief/isolation and method for making
Country Status (7)
Country
Link
US
(1)
US4729006A
(en)
EP
(1)
EP0242506B1
(en)
JP
(1)
JPH0680724B2
(en)
AU
(1)
AU579764B2
(en)
BR
(1)
BR8700839A
(en)
CA
(1)
CA1245373A
(en)
DE
(1)
DE3784958T2
(en)
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Harris Corporation
Self-aligned channel stop for trench-isolated island
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Mitsubishi Denki Kabushiki Kaisha
Method of manufacturing semiconductor device including interlaying insulating film
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1990-02-05
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Semiconductor device including interlayer insulating film
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Method for manufacturing semiconductor device
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Method of manufacturing semiconductor device
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Method for increasing latch-up immunity in CMOS devices
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1997-07-25
1999-11-15
윤종용
Method of forming trench isolation using two kinds of oxides films
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1998-10-19
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Taiwan Semiconductor Manufacturing Company
Thermal oxidizing method for forming with attenuated surface sensitivity ozone-teos silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer
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1998-10-21
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Advanced Micro Devices, Inc.
Integrated circuit isolation structure employing a protective layer and method for making same
DE19920333A1
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1999-05-03
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Siemens Ag
Method of manufacturing a semiconductor device
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1999-08-31
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Infineon Technologies Corporation
Disposable spacers for improved array gapfill in high density DRAMs
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삼성전자 주식회사
Semiconductor device having shallow trench isolation structure and method for manufacturing the same
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2002-10-21
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International Business Machines Corporation
Semiconductor device structure including multiple fets having different spacer widths
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Koninkl Philips Electronics Nv
Semiconductor device channel termination
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2003-06-30
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International Business Machines Corporation
High performance CMOS device structures and method of manufacture
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2004-09-09
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International Business Machines Corporation
Structure and method for latchup suppression utilizing trench and masked sub-collector implantation
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(en)
*
2005-05-31
2006-11-28
International Business Machines Corporation
Pixel sensor having doped isolation structure sidewall
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2006-01-13
2007-07-26
Sharp Corp
Semiconductor device and manufacturing method therefor
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1981-06-10
1985-03-12
Tokyo Shibaura Denki Kabushiki Kaisha
Method of making field oxide regions
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1984-06-15
1986-07-15
Harris Corporation
Process of making twin well VLSI CMOS
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Vertically isolated complementary transistors
1986
1986-03-17
US
US06/840,180
patent/US4729006A/en
not_active
Expired – Fee Related
1987
1987-01-09
JP
JP62002007A
patent/JPH0680724B2/en
not_active
Expired – Lifetime
1987-01-23
EP
EP87100962A
patent/EP0242506B1/en
not_active
Expired – Lifetime
1987-01-23
DE
DE87100962T
patent/DE3784958T2/en
not_active
Expired – Lifetime
1987-02-16
CA
CA000529768A
patent/CA1245373A/en
not_active
Expired
1987-02-23
BR
BR8700839A
patent/BR8700839A/en
not_active
IP Right Cessation
1987-03-12
AU
AU69959/87A
patent/AU579764B2/en
not_active
Ceased
Patent Citations (2)
* Cited by examiner, † Cited by third party
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Priority date
Publication date
Assignee
Title
US4504333A
(en)
*
1981-06-10
1985-03-12
Tokyo Shibaura Denki Kabushiki Kaisha
Method of making field oxide regions
US4599789A
(en)
*
1984-06-15
1986-07-15
Harris Corporation
Process of making twin well VLSI CMOS
Also Published As
Publication number
Publication date
JPS62219943A
(en)
1987-09-28
BR8700839A
(en)
1987-12-22
EP0242506A3
(en)
1990-03-14
DE3784958D1
(en)
1993-04-29
AU6995987A
(en)
1987-09-24
DE3784958T2
(en)
1993-09-30
US4729006A
(en)
1988-03-01
EP0242506A2
(en)
1987-10-28
EP0242506B1
(en)
1993-03-24
CA1245373A
(en)
1988-11-22
JPH0680724B2
(en)
1994-10-12
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