GB1078580A - Creación de Inventos y Patentes con Inteligencia Artificial

GB1078580A – Electronic data processing system
– Google Patents

GB1078580A – Electronic data processing system
– Google Patents
Electronic data processing system

Info

Publication number
GB1078580A

GB1078580A
GB53612/65A
GB5361265A
GB1078580A
GB 1078580 A
GB1078580 A
GB 1078580A
GB 53612/65 A
GB53612/65 A
GB 53612/65A
GB 5361265 A
GB5361265 A
GB 5361265A
GB 1078580 A
GB1078580 A
GB 1078580A
Authority
GB
United Kingdom
Prior art keywords
cycle
memory
address
word
timing
Prior art date
1965-01-18
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB53612/65A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

NCR Voyix Corp

National Cash Register Co

Original Assignee
NCR Corp
National Cash Register Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1965-01-18
Filing date
1965-12-17
Publication date
1967-08-09

1965-12-17
Application filed by NCR Corp, National Cash Register Co
filed
Critical
NCR Corp

1967-08-09
Publication of GB1078580A
publication
Critical
patent/GB1078580A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

Classifications

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F9/00—Arrangements for program control, e.g. control units

G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs

G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

G06F13/14—Handling requests for interconnection or transfer

G06F13/16—Handling requests for interconnection or transfer for access to memory bus

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F15/00—Digital computers in general; Data processing equipment in general

G06F15/76—Architectures of general purpose stored program computers

G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit

H—ELECTRICITY

H03—ELECTRONIC CIRCUITRY

H03K—PULSE TECHNIQUE

H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass

H03K5/01—Shaping pulses

H03K5/04—Shaping pulses by increasing duration; by decreasing duration

Abstract

1,078,580. Digital computers; magnetic storage devices. NATIONAL CASH REGISTER CO. Dec. 17, 1965 [Jan. 18, 1965], No. 53612/65. Headings G4A and G4C. A digital electric computer comprising a central processing unit, a magnetic memory and a timing unit operates in a series of operating cycles in which the timing unit defines a first two-step memory cycle wherein a word is read from, and restored into, the memory and, if required, a second two-step memory cycle in which a storage location in the memory is cleared in the first step and a word is written therein in the second step, the logical operation of the central processing unit being performed, in each operating cycle, simultaneously with the second step of the first memory cycle. Thin-film magnetic memory.-(Figs. 5A, 5B, not shown). The memory used is essentially the same as the memory described in Specification 1,035,870, five words, each of 12 bits plus a parity bit being read out in parallel and any of the five words not being required being masked off and returned to their original storage positions. Timing circuit.-(Figs. 2A, 2B, 3, not shown). The timing pulses are essentially produced by tapped delay lines (44-49) an initial pulse (C) being produced by AND and OR gates under the appropriate conditions being applied to the commencement of the delay lines. A further tapped delay line (43) connected to an AND gate (25) to which is also connected the input to the delay line serves to prevent spurious noise pulses from starting the timing unit. An AND gate (41) partway through the delay lines (44-49) serves to terminate the cycle at the end of the first two-step cycle or allows the second two-step cycle to be produced in succession as received. Commands.-Commands may be single address or double address types comprising two or four words. Implicit addressing, where the second word is the operand, direct addressing where the second word is the address, or relative addressing, where the address is the contents of the second word plus a specified index register are possible. Operation-(Figs. 1A, 1B, 1C and 3, not shown). Each system cycle is initiated by the clock pulse C, which also clears the read and write registers for the main memory and an auxiliary » scratch-pad » memory. At the beginning an R-R cycle is a period in which the address of the storage location to be accessed is decoded and then two periods R, R for reading and restoration respectively. Any remaining periods in a cycle are used to allow the sense amplifiers of the memories to recover. A C-W cycle includes a decode period and two periods C, W for clearing and writing in the storage location whose address has been decoded. The logical equations governing the various operations in accordance with the settings of appropriate control transistor flip-flops and progamme counters are described.

GB53612/65A
1965-01-18
1965-12-17
Electronic data processing system

Expired

GB1078580A
(en)

Applications Claiming Priority (2)

Application Number
Priority Date
Filing Date
Title

US42610565A

1965-01-18
1965-01-18

US77028668A

1968-10-24
1968-10-24

Publications (1)

Publication Number
Publication Date

GB1078580A
true

GB1078580A
(en)

1967-08-09

Family
ID=27026913
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB53612/65A
Expired

GB1078580A
(en)

1965-01-18
1965-12-17
Electronic data processing system

Country Status (6)

Country
Link

US
(2)

US3426328A
(en)

BE
(1)

BE675090A
(en)

CH
(1)

CH429241A
(en)

DE
(1)

DE1524200C3
(en)

FR
(1)

FR1466674A
(en)

GB
(1)

GB1078580A
(en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3983541A
(en)

1969-05-19
1976-09-28
Burroughs Corporation
Polymorphic programmable units employing plural levels of phased sub-instruction sets

US4024503A
(en)

1969-11-25
1977-05-17
Ing. C. Olivetti & C., S.P.A.
Priority interrupt handling system

US3656123A
(en)

1970-04-16
1972-04-11
Ibm
Microprogrammed processor with variable basic machine cycle lengths

US3651476A
(en)

1970-04-16
1972-03-21
Ibm
Processor with improved controls for selecting an operand from a local storage unit, an alu output register or both

US3809884A
(en)

1972-11-15
1974-05-07
Honeywell Inf Systems
Apparatus and method for a variable memory cycle in a data processing unit

GB1445767A
(en)

1972-12-21
1976-08-11
Sony Corp
Delay circuit

USRE30331E
(en)

1973-08-10
1980-07-08
Data General Corporation
Data processing system having a unique CPU and memory timing relationship and data path configuration

US4014006A
(en)

1973-08-10
1977-03-22
Data General Corporation
Data processing system having a unique cpu and memory tuning relationship and data path configuration

US3906453A
(en)

1974-03-27
1975-09-16
Victor Comptometer Corp
Care memory control circuit

US4050096A
(en)

1974-10-30
1977-09-20
Motorola, Inc.
Pulse expanding system for microprocessor systems with slow memory

JPS6038740B2
(en)

1976-04-19
1985-09-03
株式会社東芝

data processing equipment

DE2936801C2
(en)

1979-09-12
1982-10-28
Ibm Deutschland Gmbh, 7000 Stuttgart

Control device for executing instructions

US6885994B1
(en)

1995-12-26
2005-04-26
Catalina Marketing International, Inc.
System and method for providing shopping aids and incentives to customers through a computer network

Family Cites Families (9)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US2845548A
(en)

1956-04-25
1958-07-29
Westinghouse Electric Corp
Static time delay circuit

US2892101A
(en)

1956-04-25
1959-06-23
Westinghouse Electric Corp
Transistor time delay circuit

US3061192A
(en)

1958-08-18
1962-10-30
Sylvania Electric Prod
Data processing system

GB896463A
(en)

1960-03-11
1962-05-16
Ass Elect Ind
Improvements relating to electronic trigger circuits

US3223980A
(en)

1961-05-02
1965-12-14
Ncr Co
Computer system

NL278226A
(en)

1961-05-10

BE620569A
(en)

1961-07-25

US3334333A
(en)

1964-04-16
1967-08-01
Ncr Co
Memory sharing between computer and peripheral units

US3332069A
(en)

1964-07-09
1967-07-18
Sperry Rand Corp
Search memory

1965

1965-01-18
US
US426105A
patent/US3426328A/en
not_active
Expired – Lifetime

1965-12-17
GB
GB53612/65A
patent/GB1078580A/en
not_active
Expired

1966

1966-01-14
BE
BE675090D
patent/BE675090A/xx
unknown

1966-01-14
FR
FR45869A
patent/FR1466674A/en
not_active
Expired

1966-01-15
DE
DE1524200A
patent/DE1524200C3/en
not_active
Expired

1966-01-18
CH
CH67366A
patent/CH429241A/en
unknown

1968

1968-10-24
US
US770286A
patent/US3514641A/en
not_active
Expired – Lifetime

Also Published As

Publication number
Publication date

US3426328A
(en)

1969-02-04

BE675090A
(en)

1966-05-03

US3514641A
(en)

1970-05-26

DE1524200A1
(en)

1970-01-29

DE1524200C3
(en)

1974-01-10

FR1466674A
(en)

1967-01-20

CH429241A
(en)

1967-01-31

DE1524200B2
(en)

1973-06-14

Información de contacto