GB1117230A - Creación de Inventos y Patentes con Inteligencia Artificial

GB1117230A – Data processors
– Google Patents

GB1117230A – Data processors
– Google Patents
Data processors

Info

Publication number
GB1117230A

GB1117230A
GB42346/65A
GB4234665A
GB1117230A
GB 1117230 A
GB1117230 A
GB 1117230A
GB 42346/65 A
GB42346/65 A
GB 42346/65A
GB 4234665 A
GB4234665 A
GB 4234665A
GB 1117230 A
GB1117230 A
GB 1117230A
Authority
GB
United Kingdom
Prior art keywords
register
word
field
transmitted
order
Prior art date
1964-10-07
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB42346/65A
Inventor
Werner Ulrich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

AT&T Corp

Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1964-10-07
Filing date
1965-10-06
Publication date
1968-06-19

1965-10-06
Application filed by Western Electric Co Inc
filed
Critical
Western Electric Co Inc

1968-06-19
Publication of GB1117230A
publication
Critical
patent/GB1117230A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

230000000873
masking effect
Effects

0.000
abstract
4

101100188555
Arabidopsis thaliana OCT6 gene
Proteins

0.000
abstract
1

230000002457
bidirectional effect
Effects

0.000
abstract
1

Classifications

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F9/00—Arrangements for program control, e.g. control units

G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs

G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode

G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes

G06F9/355—Indexed addressing

Abstract

1,117,230. Data processor. WESTERN ELECTRIC CO. Inc. 6 Oct., 1965 [7 Oct., 1964], No. 42346/65. Heading G4A. A digital electric processor in eludes a plurality of registers means for representing an instruc tion word, an index adder, means for transmitting to the index adder a variable portion of the instruction word, data contained in one of the registers and part of data contained in another of the registers in accordance with the instruction word. Instruction words from a program store 40 are transmitted to an order word register 28. The address of the word in store 4 is contained in a program address register 38 and continuously incremented by 1 or transmitted to register 38 over cable 52 if order cable XFR is energized. Each instruction word comprises operation, DA or data/ address, IR or index register and LPA fields. Decoder-distributer determines from the operation field the order to be executed and energizes one of the four order cables to execute the order. The DA field can be in two parts, DA 1 , DA 2 . The DA 1 portion is transmitted directly to the index adder 32 which is used only to modify the DA field of an instruction word. DA 2 is transmitted via gate 30 which is normally enabled, to the index adder and the two parts DA 1 , DA 2 may form a single word specifying either data or an address. The index adder adds the word to the contents of a register L, X, Y, Z or buffer register 12 specified by the IR field and read by register reader 16, the word from the index adder being transmitted to the unit enabled by the energized one of the four order cables. Whenever a new word directed by the register director 44 is written in the Y register it is added to the word in the Z register by adder 42 and the result is stored in the Z register, the new word remaining in the Y register. The words may be masked in the masking circuit 14 the masking being determined by a word stored in the L register, a one in any bit position of this word allowing the corresponding bit in the word to be masked to pass and a zero stopping the corresponding bit from passing. The masking circuit is bidirectional so that a word from register reader 16 on line 56 can be masked as well as a word from buffer register 12. Masking only occurs if bit L in the LPA field is a » 1 «. Assuming that the LPA field is zero, a transfer order controls a transfer to a new instruction out of sequence. Order cable XFR is energized by an instruction XFR, 500, Y, 000. Thus the entire DA field, 500, is transmitted to the index adder 32 since P is 0. The contents of the Y register, say 25, are also transmitted to the index adder to produce a sum 525 which is transmitted to data store 10 and gate 74 and to program address register 38. However the data store and gate 79 are not enabled by cable XFR. Thus the next instruction transmitted to the order register is that from location 525. When a word contained in the DA field is to be written in one of the registers order cable W(R) is energized the (R) specifying the register. In operation the contents of the register specified by the IR field are again added to the DA field before the word is written in the appropriate register. The M(R) instruction causes a word in memory to be written in the register specified by the (R) term. The DA field again may be indexed. The (R)M causes a word in one of the registers to be written in the memory. When the P field contains a 1 the above operations are amended. Gate 30 is not inhibited, only the DA 1 field passes to the index adder and the DA 2 field passes the now enabled gate 26 to the shift and read circuits. Read circuit 74 is connected to the stages of the Z register containing the least significant bits, the exact number depending on the maximum number of bits to be transmitted from the Z register in any given application. The DA 2 subfield specifies a number of bits, e.g. 4 and the read circuit reads the four least significant bits in the Z register to the index adder, to be added to the contents of the register specified by the IR field and to the DA 1 field. After the operation of the read circuit the shift circuit operates to shift the contents of the Z register, e.g. four places to the right, i.e. in the direction of least significance to remove the previous four bits and place the next bits to be specified by the DA 2 field in position.

GB42346/65A
1964-10-07
1965-10-06
Data processors

Expired

GB1117230A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

US402272A

US3343138A
(en)

1964-10-07
1964-10-07
Data processor employing double indexing

Publications (1)

Publication Number
Publication Date

GB1117230A
true

GB1117230A
(en)

1968-06-19

Family
ID=23591239
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB42346/65A
Expired

GB1117230A
(en)

1964-10-07
1965-10-06
Data processors

Country Status (6)

Country
Link

US
(1)

US3343138A
(en)

BE
(1)

BE670567A
(en)

DE
(1)

DE1499284C3
(en)

GB
(1)

GB1117230A
(en)

NL
(1)

NL6513019A
(en)

SE
(1)

SE316937B
(en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3906459A
(en)

1974-06-03
1975-09-16
Control Data Corp
Binary data manipulation network having multiple function capability for computers

US4079451A
(en)

1976-04-07
1978-03-14
Honeywell Information Systems Inc.
Word, byte and bit indexed addressing in a data processing system

US4037213A
(en)

1976-04-23
1977-07-19
International Business Machines Corporation
Data processor using a four section instruction format for control of multi-operation functions by a single instruction

JPS54100634A
(en)

1978-01-26
1979-08-08
Toshiba Corp
Computer

US4771281A
(en)

1984-02-13
1988-09-13
Prime Computer, Inc.
Bit selection and routing apparatus and method

Family Cites Families (8)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3015441A
(en)

1957-09-04
1962-01-02
Ibm
Indexing system for calculators

US3048333A
(en)

1957-12-26
1962-08-07
Ibm
Fast multiply apparatus in an electronic digital computer

US3061192A
(en)

1958-08-18
1962-10-30
Sylvania Electric Prod
Data processing system

US3249920A
(en)

1960-06-30
1966-05-03
Ibm
Program control element

NL267513A
(en)

1960-07-25

US3247490A
(en)

1961-12-19
1966-04-19
Sperry Rand Corp
Computer memory system

DE1160222B
(en)

1962-01-04
1963-12-27
Siemens Ag

Circuit arrangement for address modification in a program-controlled digital calculating machine

US3299261A
(en)

1963-12-16
1967-01-17
Ibm
Multiple-input memory accessing apparatus

1964

1964-10-07
US
US402272A
patent/US3343138A/en
not_active
Expired – Lifetime

1965

1965-10-06
GB
GB42346/65A
patent/GB1117230A/en
not_active
Expired

1965-10-06
SE
SE12961/65A
patent/SE316937B/xx
unknown

1965-10-06
DE
DE1499284A
patent/DE1499284C3/en
not_active
Expired

1965-10-06
BE
BE670567D
patent/BE670567A/xx
unknown

1965-10-07
NL
NL6513019A
patent/NL6513019A/xx
unknown

Also Published As

Publication number
Publication date

US3343138A
(en)

1967-09-19

NL6513019A
(en)

1966-04-12

DE1499284B2
(en)

1973-03-22

DE1499284C3
(en)

1973-10-18

SE316937B
(en)

1969-11-03

DE1499284A1
(en)

1972-03-09

BE670567A
(en)

1966-01-31

Información de contacto