GB1132728A - Creación de Inventos y Patentes con Inteligencia Artificial

GB1132728A – Apparatus and method for fabricating an interconnected circuit
– Google Patents

GB1132728A – Apparatus and method for fabricating an interconnected circuit
– Google Patents
Apparatus and method for fabricating an interconnected circuit

Info

Publication number
GB1132728A

GB1132728A
GB51120/66A
GB5112066A
GB1132728A
GB 1132728 A
GB1132728 A
GB 1132728A
GB 51120/66 A
GB51120/66 A
GB 51120/66A
GB 5112066 A
GB5112066 A
GB 5112066A
GB 1132728 A
GB1132728 A
GB 1132728A
Authority
GB
United Kingdom
Prior art keywords
list
positions
assigned
elements
wafer
Prior art date
1965-12-01
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB51120/66A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

International Business Machines Corp

Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1965-12-01
Filing date
1966-11-15
Publication date
1968-11-06

1966-11-15
Application filed by International Business Machines Corp
filed
Critical
International Business Machines Corp

1968-11-06
Publication of GB1132728A
publication
Critical
patent/GB1132728A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

Classifications

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

H01L27/0203—Particular design considerations for integrated circuits

H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F30/00—Computer-aided design [CAD]

G06F30/30—Circuit design

G06F30/39—Circuit design at the physical level

G06F30/392—Floor-planning or layout, e.g. partitioning or placement

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

Abstract

1,132,728. Choosing positions on a substrate for circuit elements. INTERNATIONAL BUSINESS MACHINES CORP. 15 Nov., 1966 [1 Dec., 1965], No. 51120/66. Heading G4A. [Also in Division G3] Circuit elements are assigned to positions on a substrate to make up an interconnected circuit, by utilizing information of the required interconnections to determine the order in which the elements are to be assigned to positions, assigning the first element (to be assigned) to a selected position, and assigning each subsequent element to the best of a number of candidate positions for that element, the candidate positions having been selected in each case in accordance with their relation to positions which had already had an element assigned to them. An integrated circuit is created on a monolithic crystal wafer bearing individual circuit elements, by a wiring device which establishes interconnections between the elements by wrapping wires around selected pins or by moving the wafer relative to a light beam (for photoetching) or a depositing device. The wiring device is controlled by a wiring pattern determining system which is fed with circuit design and interconnection weighting data from punched cards or magnetic tape and with the output of a placement system. The placement system is fed with the circuit design and weighting data above, and with data from a wafer tester optionally via punched cards or magnetic tape. The data from the wafer tester comprises the size (maximum values of X and Y coordinates) and shape of the wafer and which positions on the wafer are not usable. The placement system decides which circuit elements are to be assigned to which positions on the wafer. As a modification, the output of the placement system may be printed out. Placement system.-A 3-dimensional matrix memory (W matrix) is loaded with the weights of the interconnections, the weight of an interconnection to carry a signal from the ith element to the jth element being stored at the intersection of the ith row and jth column. If an interconnection doesn’t exist, the intersection stores zero. A core memory (MACM) has a word location for each position on the wafer and an indicator bit therein which is reset from 1 to 0 if the position is not usable. A W1 list is set up by storing for each element in turn the sum of the weights of all interconnections between that element and other elements, the weights being obtained from the W matrix. Elements are now placed in a T list in the order in which they are to be assigned to positions on the wafer, as follows. The element with the highest entry in the W1 list is stored as the first entry in the T list, and the elements connected to it are stored in a J list. Corresponding to each entry in the J list, an entry is established in a D list giving the sum of the weights of the interconnections between that element and those (so far only one) in the T list. Each of the remaining positions in the T list is filled in turn by looking for the maximum value in the D list. If this value is not zero and only one element has this maximum value, that element is picked for the T list. If more than one element has this non-zero maximum value in the D list, that one of these elements having the highest value in the W1 list is picked for the T list. If two or more elements have this highest value in the W1 list, one is picked arbitrarily. In any event, the J and D list entries for the picked element are set to zero. Then those elements interconnected with the picked element are identified by looking for non-zero weights in the W matrix, and stored in the J list if not already present, the D list also being updated. These operations are repeated until the maximum value in the D list is zero when the T list is complete. The first entry in the T list is now assigned to a fixed position (or one preselected by the operator) near the centre of the wafer, by placing the element’s name in the appropriate word location in the core memory (MACM). If this position is unusable, the first usable position in a spiral path progressing outwards from the centre could be taken. The following sequence is now repeated, once to assign each of the remaining elements in the T list. The X and Y co-ordinates of usable positions, if any, on the wafer which are one position to the left, to the right, above or below the position last assigned an element are placed in a candidate position list provided they are not already in it, and the indicator bits in the core memory (MACM) for these positions are reset to 0. It is the indicator bits which are used to determine if a possible position is usable and not already in the candidate position list. If at this point there are no entries in the candidate position list, the criterion for inclusion in the list is broadened e.g. all usable unfilled positions may be placed in the list (if there are none, the wafer is rejected). Alternatively positions two positions away could be used, or diagonal positions, or a new position could be chosen for the first element in the T list along the spiral path mentioned. With at least one entry present in the candidate position list, the next element in the T list to be assigned is taken (by incrementing a T counter) and for each element already assigned to a wafer position the sum of the weights of the interconnections between the two elements, if non-zero (indicating there are interconnections), is stored in an F list, with the name of the already assigned element being placed in a corresponding position in a B list. The element to be assigned is now assigned to the best of the positions in the candidate position list, the best candidate being that which minimizes the cost of the choice, defined as: the sum over all elements in the B list (already assigned elements interconnected with the element to be assigned) of the product of the weight of the interconnection times the sum of the squares of the X and Y distances between the B list element position and the candidate position. During the computations to find the minimum cost choice, the minimum cost so far is retained as is the location of the best position so far (i.e. that associated with the minimum cost so far) and the sum over all elements in the B list of the difference between the X and Y distances between the B list element and the best so far candidate position. If a computed cost is equal to the minimum so far cost, the choice for which this difference is the smaller is retained as the best so far. With the element assigned to the best position, the position is removed from the candidate position list. The hardware includes two associative memories, each having a maskable argument register for the data to be matched against and a data register for data read-out from or to be written into the memory, the data register being fed from the memory via a first (read) mask and feeding the memory via a second (write) mask. The associative memories store the candidate position list and the other lists respectively.

GB51120/66A
1965-12-01
1966-11-15
Apparatus and method for fabricating an interconnected circuit

Expired

GB1132728A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

US51076765A

1965-12-01
1965-12-01

Publications (1)

Publication Number
Publication Date

GB1132728A
true

GB1132728A
(en)

1968-11-06

Family
ID=24032110
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB51120/66A
Expired

GB1132728A
(en)

1965-12-01
1966-11-15
Apparatus and method for fabricating an interconnected circuit

Country Status (5)

Country
Link

US
(1)

US3654615A
(en)

DE
(1)

DE1538604B2
(en)

FR
(1)

FR1502554A
(en)

GB
(1)

GB1132728A
(en)

NL
(1)

NL6616899A
(en)

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Assignee
Title

US3827031A
(en)

1973-03-19
1974-07-30
Instr Inc
Element select/replace apparatus for a vector computing system

DE2445368A1
(en)

1974-09-23
1976-04-01
Siemens Ag

METHOD OF MANUFACTURING MASK TEMPLATES FOR INTEGRATED SEMICONDUCTOR CIRCUITS

US4495559A
(en)

1981-11-02
1985-01-22
International Business Machines Corporation
Optimization of an organization of many discrete elements

US4613940A
(en)

1982-11-09
1986-09-23
International Microelectronic Products
Method and structure for use in designing and building electronic systems in integrated circuits

JPS59154055A
(en)

1983-02-22
1984-09-03
Hitachi Ltd
Method for arranging element on logic circuit substrate

US4630219A
(en)

1983-11-23
1986-12-16
International Business Machines Corporation
Element placement method

US4615011A
(en)

1983-12-19
1986-09-30
Ibm
Iterative method for establishing connections and resulting product

US4754408A
(en)

1985-11-21
1988-06-28
International Business Machines Corporation
Progressive insertion placement of elements on an integrated circuit

JPH0793358B2
(en)

1986-11-10
1995-10-09
日本電気株式会社

Block placement processing method

JPS63278249A
(en)

1986-12-26
1988-11-15
Toshiba Corp
Wiring of semiconductor integrated circuit device

JP2543155B2
(en)

1988-04-21
1996-10-16
松下電器産業株式会社

Block shape optimization method

US5159682A
(en)

1988-10-28
1992-10-27
Matsushita Electric Industrial Co., Ltd.
System for optimizing a physical organization of elements of an integrated circuit chip through the convergence of a redundancy function

JP3032224B2
(en)

1990-02-21
2000-04-10
株式会社東芝

Logic cell arrangement method for semiconductor integrated circuit

US5237514A
(en)

1990-12-21
1993-08-17
International Business Machines Corporation
Minimizing path delay in a machine by compensation of timing through selective placement and partitioning

US5225991A
(en)

1991-04-11
1993-07-06
International Business Machines Corporation
Optimized automated macro embedding for standard cell blocks

JP2601586B2
(en)

1991-10-15
1997-04-16
富士通株式会社

How to place and route placement elements

US5694328A
(en)

1992-08-06
1997-12-02
Matsushita Electronics Corporation
Method for designing a large scale integrated (LSI) layout

US5513119A
(en)

1993-08-10
1996-04-30
Mitsubishi Semiconductor America, Inc.
Hierarchical floorplanner for gate array design layout

US5535134A
(en)

1994-06-03
1996-07-09
International Business Machines Corporation
Object placement aid

JP3504394B2
(en)

1995-09-08
2004-03-08
松下電器産業株式会社

How to create component array data

US5740067A
(en)

1995-10-19
1998-04-14
International Business Machines Corporation
Method for clock skew cost calculation

US5745735A
(en)

1995-10-26
1998-04-28
International Business Machines Corporation
Localized simulated annealing

US5844811A
(en)

1996-06-28
1998-12-01
Lsi Logic Corporation
Advanced modular cell placement system with universal affinity driven discrete placement optimization

US6099583A
(en)

1998-04-08
2000-08-08
Xilinx, Inc.
Core-based placement and annealing methods for programmable logic devices

JP3167980B2
(en)

1999-03-15
2001-05-21
インターナショナル・ビジネス・マシーンズ・コーポレ−ション

Component placement method, component placement device, storage medium storing component placement control program

US7342414B2
(en)

2002-02-01
2008-03-11
California Institute Of Technology
Fast router and hardware-assisted fast routing method

US7210112B2
(en)

2002-08-21
2007-04-24
California Institute Of Technology
Element placement method and apparatus

US7119607B2
(en)

2002-12-31
2006-10-10
Intel Corporation
Apparatus and method for resonance reduction

US7143381B2
(en)

2002-12-31
2006-11-28
Intel Corporation
Resonance reduction arrangements

US7285487B2
(en)

2003-07-24
2007-10-23
California Institute Of Technology
Method and apparatus for network with multilayer metalization

US20070136699A1
(en)

2005-12-08
2007-06-14
International Business Machines Corporation
Dependency matrices and methods of using the same for testing or analyzing an integrated circuit

US20090138249A1
(en)

2007-11-28
2009-05-28
International Business Machines Corporation
Defining operational elements in a business process model

US9208277B1
(en)

2011-08-19
2015-12-08
Cadence Design Systems, Inc.
Automated adjustment of wire connections in computer-assisted design of circuits

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* Cited by examiner, † Cited by third party

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Priority date
Publication date
Assignee
Title

US3126635A
(en)

1964-03-31

Line terminating system

US3369163A
(en)

1961-12-29
1968-02-13
Hughes Aircraft Co
Straight line motor control for an x-y plotter

US3307154A
(en)

1962-10-11
1967-02-28
Compugraphic Corp
Data processing apparatus for line justification in type composing machines

US3325786A
(en)

1964-06-02
1967-06-13
Rca Corp
Machine for composing ideographs

FR
FR1502554D
patent/FR1502554A/fr
not_active
Expired

1965

1965-12-01
US
US510767A
patent/US3654615A/en
not_active
Expired – Lifetime

1966

1966-11-15
GB
GB51120/66A
patent/GB1132728A/en
not_active
Expired

1966-11-30
DE
DE19661538604
patent/DE1538604B2/en
not_active
Ceased

1966-11-30
NL
NL6616899A
patent/NL6616899A/xx
unknown

Also Published As

Publication number
Publication date

DE1538604A1
(en)

1969-10-09

FR1502554A
(en)

1968-02-07

NL6616899A
(en)

1967-06-02

US3654615A
(en)

1972-04-04

DE1538604B2
(en)

1971-06-24

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