GB1133143A - Creación de Inventos y Patentes con Inteligencia Artificial

GB1133143A – Improvements in or relating to supervisory arrangements for information transfer
– Google Patents

GB1133143A – Improvements in or relating to supervisory arrangements for information transfer
– Google Patents
Improvements in or relating to supervisory arrangements for information transfer

Info

Publication number
GB1133143A

GB1133143A
GB10227/66A
GB1022766A
GB1133143A
GB 1133143 A
GB1133143 A
GB 1133143A
GB 10227/66 A
GB10227/66 A
GB 10227/66A
GB 1022766 A
GB1022766 A
GB 1022766A
GB 1133143 A
GB1133143 A
GB 1133143A
Authority
GB
United Kingdom
Prior art keywords
address
matrix
equipment
translator
bit
Prior art date
1965-03-08
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB10227/66A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Telefonaktiebolaget LM Ericsson AB

Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1965-03-08
Filing date
1966-03-08
Publication date
1968-11-06

1966-03-08
Application filed by Telefonaktiebolaget LM Ericsson AB
filed
Critical
Telefonaktiebolaget LM Ericsson AB

1968-11-06
Publication of GB1133143A
publication
Critical
patent/GB1133143A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

239000011159
matrix material
Substances

0.000
abstract
12

238000001514
detection method
Methods

0.000
abstract
3

239000003990
capacitor
Substances

0.000
abstract
2

238000000034
method
Methods

0.000
abstract
2

238000012360
testing method
Methods

0.000
abstract
2

239000004020
conductor
Substances

0.000
abstract
1

230000002093
peripheral effect
Effects

0.000
abstract
1

238000006467
substitution reaction
Methods

0.000
abstract
1

230000001360
synchronised effect
Effects

0.000
abstract
1

Classifications

H—ELECTRICITY

H04—ELECTRIC COMMUNICATION TECHNIQUE

H04Q—SELECTING

H04Q3/00—Selecting arrangements

H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker

H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised

H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme

H04Q3/54575—Software application

H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis

Abstract

1,133,143. Computer control of telephone systems. TELEFONAKTIEBOLAGET L. M. ERICSSON. 8 March, 1966 [8 March, 1965], No. 10227/66. Heading G4A. [Also in Division H4] In a system having a number of equipments which may be addressed individually by a pair of synchronously operating computers, the equipments are located at the crosspoints of an address matrix, any row of which can be selected by appropriate operation of a crosspoint of a selection matrix. Address data coming from the computers is translated before being applied to the rows and columns of the selection matrix (or matrices). The address matrix is provided with a special column conductor which produces an error signal in the event of a fault occurring during an addressing period whereby a fault detection process is initiated. The process consists in addressing a particular test row of the address matrix whereby if the error signal ceases this indicates that the address matrix is not at fault. Then, utilizing the original address as an input, the translators are disconnected in turn until the error signal again ceases and thereby indicates the faulty translator. The faulty equipment is cut-out of service until it is repaired or replaced. The system is described with reference to a telephone system in which the equipments are line circuits or selector switches whose states (i.e. busy or free) need to be assessed or controlled by a computerized central control system. Computers, D1, D2.-Details of these are not given. They are linked to the peripheral equipments via two bus systems, one of which carries 16 bit address words for selecting a particular equipment and the other of which carries 16 bit data words. Each bit position of the latter words is individual to an equipment and the bit may indicate to the computer the state of the equipment or may represent a command from the computer to the equipment. Fault detection circuitry, including a comparator, are provided for ensuring synchronous operation of the computers. Translators, OV1, OV2.-Each computer has an individual translator which translates 16 bit input words into one, 1 out of 8 code and five, 1 out of 4 codes. Selection matrices UM.-Each of these comprises an 11 x 8 transistor array of which the columns are selected by the 1 out of 8 code emanating from a translator and the rows are selected by some of the 1 out of 4 codes. In order that a crosspoint such as UP1 (Fig. 5) may be operated, its corresponding row AND gate OK1c (Fig. 4) must receive identical and coincident signals from the translators via respective AND gates OK1a and OK1b assuming, as is normally the case, that relays BRr1 and BRr2 are both up. Address matrices AP.-Each of these comprises an 81 x 16 capacitor array, of which a crosspoint only delivers an output pulse, when interrogated, if its associated equipment is busy. Capacitor Cb1 (Fig. 5) is of much larger value than Ca1 and together with resistor R3 in the associated line circuit forms an integrating circuit for rapidly recharging Ca1 after each interrogation. Decoupling diodes G1 are provided. An additional column kk (Fig. 6, not shown) is provided for fault detection purposes. Operation.-During a normal interrogation at least column kk of the required address matrix produces an output. If this does not occur, logic circuitry (Fig. 7, not shown) causes the stored address of that crosspoint which corresponds to row 81 of the address matrix, to be applied to the selection matrix. Provided that kk now supplies an output pulse it is assumed that the address matrix is operating correctly. The logic now opens gate AC1 (left-hand side of Fig. 4) whereby relay B1 falls, followed by BRr1 and BRk1. The original address is supplied entirely by translator OV2 to the selection matrix, since the relays have disconnected OV1. If column kk still produces no output pulse, the logic releases relay B1 (centre right-hand side of Fig. 4) whereby relays BRr2 and BRk2 fall back so as to allow the address to be supplied only from translator OV1. If there is still no output from kk, it is concluded that the selection matrix is faulty. If at any time an output does occur during the substitution testing it is assumed that the currently disconnected equipment is at fault.

GB10227/66A
1965-03-08
1966-03-08
Improvements in or relating to supervisory arrangements for information transfer

Expired

GB1133143A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

SE297965

1965-03-08

Publications (1)

Publication Number
Publication Date

GB1133143A
true

GB1133143A
(en)

1968-11-06

Family
ID=20261133
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB10227/66A
Expired

GB1133143A
(en)

1965-03-08
1966-03-08
Improvements in or relating to supervisory arrangements for information transfer

Country Status (7)

Country
Link

US
(1)

US3492446A
(en)

BE
(1)

BE677513A
(en)

DK
(1)

DK111757B
(en)

FI
(1)

FI42342C
(en)

FR
(1)

FR1470867A
(en)

GB
(1)

GB1133143A
(en)

NL
(1)

NL154905B
(en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3898386A
(en)

1974-01-18
1975-08-05
Gte Automatic Electric Lab Inc
Error detection and protection circuits for duplicated peripheral units

DE2529475C3
(en)

1975-07-02
1981-10-08
Ewald Max Christian Dipl.-Phys. 6000 Frankfurt Hennig

Electrical circuit arrangement for time-dependent measurement of physical quantities

GB2219172B
(en)

1988-03-30
1992-07-08
Plessey Co Plc
A data path checking system

US5838879A
(en)

1995-12-27
1998-11-17
Howard Harris Builders, Inc.
Continuously cleaned pressureless water heater with immersed copper fluid coil

1966

1966-02-16
US
US527818A
patent/US3492446A/en
not_active
Expired – Lifetime

1966-02-21
FI
FI660430A
patent/FI42342C/en
active

1966-03-04
NL
NL666602851A
patent/NL154905B/en
not_active
IP Right Cessation

1966-03-07
DK
DK118666AA
patent/DK111757B/en
unknown

1966-03-08
FR
FR52592A
patent/FR1470867A/en
not_active
Expired

1966-03-08
BE
BE677513D
patent/BE677513A/xx
unknown

1966-03-08
GB
GB10227/66A
patent/GB1133143A/en
not_active
Expired

Also Published As

Publication number
Publication date

FI42342B
(en)

1970-03-31

FI42342C
(en)

1970-07-10

NL154905B
(en)

1977-10-17

DK111757B
(en)

1968-10-07

DE1512016B2
(en)

1972-08-17

BE677513A
(en)

1966-08-01

NL6602851A
(en)

1966-09-09

FR1470867A
(en)

1967-02-24

DE1512016A1
(en)

1969-04-03

US3492446A
(en)

1970-01-27

Información de contacto