GB1221819A – Data processing apparatus
– Google Patents
GB1221819A – Data processing apparatus
– Google Patents
Data processing apparatus
Info
Publication number
GB1221819A
GB1221819A
GB22178/68A
GB2217868A
GB1221819A
GB 1221819 A
GB1221819 A
GB 1221819A
GB 22178/68 A
GB22178/68 A
GB 22178/68A
GB 2217868 A
GB2217868 A
GB 2217868A
GB 1221819 A
GB1221819 A
GB 1221819A
Authority
GB
United Kingdom
Prior art keywords
units
unit
control unit
main
register
Prior art date
1967-07-14
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB22178/68A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1967-07-14
Filing date
1968-05-10
Publication date
1971-02-10
1968-05-10
Application filed by International Business Machines Corp
filed
Critical
International Business Machines Corp
1971-02-10
Publication of GB1221819A
publication
Critical
patent/GB1221819A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F13/10—Program control for peripheral devices
G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
Abstract
1,221,819. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 10 May, 1968 [14 July, 1967], No. 22178/68. Heading G4A. In data processing apparatus, comprising a central processor, main and bulk storage and I/O devices, rows and columns of an array of first units are controlled by respective second units which scan them to ascertain which of them require service, the second units comprising means for initiating first unit sequences for I/O device selection, command, data transmission and ending, means for storing and fetching data to/from storage, and means for controlling record search operations. In Fig. 1, an I/O control system 2 comprises (a) an I/O control unit for controlling data transfers between the I/O devices and the storage, (b) a supervisory control unit for scheduling jobs for the processing means, (c) a remote terminal control unit for directing data transfers to or from remote terminals. The main computing unit shown controls its connection to main storage I which is assigned to it. The I/O control unit in I/O system 2 controls the paths shown between main, bulk and auxiliary storage, and communications with I/O devices (not shown), using the matrix of first units each row and column of which is scanned repeatedly by a respective second unit to see if it requires service, the second units containing hardware for relatively infrequent operations required by the first units, e.g. storing and fetching of data in main or bulk storage, updating of addresses and counts, generation and verification of parity and other redundancy checks &c. The first units each include a series of byte buffers which can store data and also commands for I/O devices or the first units themselves. First units are each permanently related to a respective group of I/O devices, and in general each I/O device will belong to more than one group (thus, more than one first unit). When communication with a particular I/O device is required by a given computing unit (the latter being scanned in sequence), and the I/O device is not busy, the first non-busy first unit related to it is selected to receive the address of the first instruction to control the transfer. The scanning of its row or column of first units by a second unit involves leftmost-one checks in the second unit on urgent and non-urgent vectors one bit of each of which is supplied to the second unit by each of its first units, some bits being ignored in these checks according to a preset mask vector. Provision is made for preventing incorrect operation due to the fact that a given first unit is scanned by two second units (viz. those for its row and column of the matrix of first units). Each second unit includes a word register for disassembling a word from storage into its bytes for transmission to the buffers in a first unit and for assembly during the reverse direction of transfer. The subsidiary computing unit is optimised for character handling and for the compilation and interpretation of computer-oriented languages, performs small programmes for users at the remote terminals, and anticipates data requirements of the main computing unit. The three units, (a), (b), (c) above, of the I/O system 2 each contain a register for communication with each of the others, and the I/O control unit and supervisory control unit, (a) and (b), each contain a register for communication with each of the computing units. As a typical use of these registers, if the main computing unit wants to make an I/O request, it loads the register respective to itself in the I/O control unit with an I/O command and marker bit. The I/O control unit responds to the marker bit, begins to execute the command, and resets the marker bit. The main computing unit may respond to the latter to issue another I/O command or reload the register with a command requesting notification of the status of an I/O operation in progress. When an I/O command is completed, the I/O control unit loads the register respective to itself in the main computing unit with status information and a marker bit. The main computing unit acknowledges receipt of information in its register by resetting this marker bit. The supervisory control unit in the I/O system 2 schedules jobs for both computing units, preparing the next before it is needed to prevent waiting, allocates storage space, determines which waiting remote terminal is to be serviced next by the subsidiary computing unit, diagnoses faults, and exercises control over the other two units in the I/O system 2 and the two computing units. For example, if the main computing unit has exceeded its allotted time for a particular job, the supervisory control unit asks it, via the respective registers above, to terminate it at a convenient point, and in the absence of a satisfactory response, interrupts it to stop execution of the job (after execution of any prefetched instructions). The supervisory control unit can also interrupt the subsidiary computing unit and the I/O control unit.
GB22178/68A
1967-07-14
1968-05-10
Data processing apparatus
Expired
GB1221819A
(en)
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
US65349967A
1967-07-14
1967-07-14
Publications (1)
Publication Number
Publication Date
GB1221819A
true
GB1221819A
(en)
1971-02-10
Family
ID=24621133
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB22178/68A
Expired
GB1221819A
(en)
1967-07-14
1968-05-10
Data processing apparatus
Country Status (3)
Country
Link
US
(1)
US3593299A
(en)
FR
(1)
FR1575939A
(en)
GB
(1)
GB1221819A
(en)
Families Citing this family (21)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US4121284A
(en)
*
1972-09-11
1978-10-17
Hyatt Gilbert P
Computerized system for operator interaction
US4004279A
(en)
*
1970-06-12
1977-01-18
Yokogawa Electric Works, Ltd.
Method and apparatus for controlling data transfer between input and output devices and a direct digital controller
US4183083A
(en)
*
1972-04-14
1980-01-08
Duquesne Systems, Inc.
Method of operating a multiprogrammed computing system
US4142232A
(en)
*
1973-07-02
1979-02-27
Harvey Norman L
Student’s computer
USRE30331E
(en)
*
1973-08-10
1980-07-08
Data General Corporation
Data processing system having a unique CPU and memory timing relationship and data path configuration
US4058850A
(en)
*
1974-08-12
1977-11-15
Xerox Corporation
Programmable controller
DE2547488C2
(en)
*
1975-10-23
1982-04-15
Ibm Deutschland Gmbh, 7000 Stuttgart
Micro-programmed data processing system
US4075691A
(en)
*
1975-11-06
1978-02-21
Bunker Ramo Corporation
Communication control unit
US4124888A
(en)
*
1975-12-24
1978-11-07
Computer Automation, Inc.
Peripheral-unit controller apparatus
US4079454A
(en)
*
1976-01-02
1978-03-14
Data General Corporation
Data processing system using read-only-memory arrays to provide operation in a plurality of operating states
US4149244A
(en)
*
1976-06-07
1979-04-10
Amdahl Corporation
Data processing system including a program-executing secondary system controlling a program-executing primary system
US4096567A
(en)
*
1976-08-13
1978-06-20
Millard William H
Information storage facility with multiple level processors
US4071890A
(en)
*
1976-11-29
1978-01-31
Data General Corporation
CPU-Synchronous parallel data processor apparatus
US4244019A
(en)
*
1978-06-29
1981-01-06
Amdahl Corporation
Data processing system including a program-executing secondary system controlling a program-executing primary system
AR227513A1
(en)
*
1978-09-08
1982-11-15
Fujitsu Ltd
CONTROL PROVISION FOR A PLURALITY OF ENTRY AND EXIT DEVICES
JPS6032217B2
(en)
*
1979-04-02
1985-07-26
日産自動車株式会社
Control computer failsafe device
US4646237A
(en)
*
1983-12-05
1987-02-24
Ncr Corporation
Data handling system for handling data transfers between a cache memory and a main memory
US5960212A
(en)
*
1996-04-03
1999-09-28
Telefonaktiebolaget Lm Ericsson (Publ)
Universal input/output controller having a unique coprocessor architecture
US8238333B2
(en)
*
2006-05-29
2012-08-07
Freescale Semiconductor, Inc.
Method for transmitting data and a device having data transmission capabilities
US7787484B2
(en)
*
2006-05-29
2010-08-31
Freescale Semiconductor, Inc.
Method for transmitting data from multiple clock domains and a device having data transmission capabilities
US20170329797A1
(en)
*
2016-05-13
2017-11-16
Electronics And Telecommunications Research Institute
High-performance distributed storage apparatus and method
Family Cites Families (7)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3061192A
(en)
*
1958-08-18
1962-10-30
Sylvania Electric Prod
Data processing system
US3245045A
(en)
*
1961-11-21
1966-04-05
Ibm
Integrated data processing system
BE621419A
(en)
*
1962-02-23
US3283308A
(en)
*
1963-06-10
1966-11-01
Beckman Instruments Inc
Data processing system with autonomous input-output control
US3344410A
(en)
*
1965-04-28
1967-09-26
Ibm
Data handling system
US3406380A
(en)
*
1965-11-26
1968-10-15
Burroughs Corp
Input-output data service computer
US3462741A
(en)
*
1966-07-25
1969-08-19
Ibm
Automatic control of peripheral processors
1967
1967-07-14
US
US653499A
patent/US3593299A/en
not_active
Expired – Lifetime
1968
1968-05-10
GB
GB22178/68A
patent/GB1221819A/en
not_active
Expired
1968-06-11
FR
FR1575939D
patent/FR1575939A/fr
not_active
Expired
Also Published As
Publication number
Publication date
FR1575939A
(en)
1969-07-25
US3593299A
(en)
1971-07-13
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