GB1354425A – Semiconductor device
– Google Patents
GB1354425A – Semiconductor device
– Google Patents
Semiconductor device
Info
Publication number
GB1354425A
GB1354425A
GB1234972A
GB1234972A
GB1354425A
GB 1354425 A
GB1354425 A
GB 1354425A
GB 1234972 A
GB1234972 A
GB 1234972A
GB 1234972 A
GB1234972 A
GB 1234972A
GB 1354425 A
GB1354425 A
GB 1354425A
Authority
GB
United Kingdom
Prior art keywords
source
drain
deposited
semi
wafer
Prior art date
1971-03-19
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1234972A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
ITT Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1971-03-19
Filing date
1972-03-16
Publication date
1974-06-05
1972-03-16
Application filed by Deutsche ITT Industries GmbH, ITT Industries Inc
filed
Critical
Deutsche ITT Industries GmbH
1974-06-05
Publication of GB1354425A
publication
Critical
patent/GB1354425A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L23/00—Details of semiconductor or other solid state devices
H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
H01L23/293—Organic, e.g. plastic
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 – H01L21/26
H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 – H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
H01L21/3105—After-treatment
H01L21/311—Etching the insulating layers by chemical or physical means
H01L21/31105—Etching inorganic layers
H01L21/31111—Etching inorganic layers by chemical means
H01L21/31116—Etching inorganic layers by chemical means by dry-etching
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
H01L21/76—Making of isolation regions between components
H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/0001—Technical content checked by a classifier
H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/10—Details of semiconductor or other solid state devices to be connected
H01L2924/11—Device type
H01L2924/13—Discrete devices, e.g. 3 terminal devices
H01L2924/1304—Transistor
H01L2924/1306—Field-effect transistor [FET]
H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10S148/00—Metal treatment
Y10S148/053—Field effect transistors fets
Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10S148/00—Metal treatment
Y10S148/117—Oxidation, selective
Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10S148/00—Metal treatment
Y10S148/122—Polycrystalline
Abstract
1354425 IGFETS ITT INDUSTRIES Inc 16 March 1972 [19 March 1971] 12349/72 Heading H1K In making an IGFET a first insulating layer is provided on a semi-conductor wafer at the device site and a second insulating layer elsewhere, then semi-conductor material is deposited over both layers and oxidized throughout its thickness at the source and drain sites. The oxidized semi-conductor and underlying insulation is then removed, dopant diffused into the areas thus exposed to form the source and drain regions, and ohmic contacts provided thereto and to the semi-conductor gate. As described the wafer is of 111 oriented 40hm.cm.N-type silicon. Silicon nitride is initially deposited and then restricted by etching so as to mask the device during oxidation of the rest of the wafer face. After levelling the treated surface by removal of the nitride and some oxide the hitherto masked surface is oxidized to provide gate insulation. Polycrystalline silicon is then pyrolytically deposited overall and a nitride mask provided leaving exposed parts overlying the source and drain sites which are then converted to oxide and etched away together with the underlying oxide. After removal of the masking boron is diffused to form the source and drain regions and dope the remaining parts of the polycrystalline layer. Finally aluminium is deposited to ohmically contact the source, drain and gate via apertures in a deposited silica layer. If an N- channel FET is required a P-type wafer is used and the polycrystalline layer is diffused with boron while entire, and masked during formation of the source and drain by diffusion of phosphorus.
GB1234972A
1971-03-19
1972-03-16
Semiconductor device
Expired
GB1354425A
(en)
Applications Claiming Priority (3)
Application Number
Priority Date
Filing Date
Title
US12621871A
1971-03-19
1971-03-19
US12602571A
1971-03-19
1971-03-19
US12674971A
1971-03-22
1971-03-22
Publications (1)
Publication Number
Publication Date
GB1354425A
true
GB1354425A
(en)
1974-06-05
Family
ID=27383334
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB1234972A
Expired
GB1354425A
(en)
1971-03-19
1972-03-16
Semiconductor device
Country Status (5)
Country
Link
US
(1)
US3761327A
(en)
AU
(1)
AU465819B2
(en)
DE
(2)
DE2211972A1
(en)
FR
(2)
FR2130351B1
(en)
GB
(1)
GB1354425A
(en)
Cited By (1)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
GB2203592A
(en)
*
1987-03-07
1988-10-19
Samsung Semiconductor Tele
Method of manufacturing a semiconductor device
Families Citing this family (23)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3968562A
(en)
*
1971-11-25
1976-07-13
U.S. Philips Corporation
Method of manufacturing a semiconductor device
DE2251823A1
(en)
*
1972-10-21
1974-05-02
Itt Ind Gmbh Deutsche
SEMICONDUCTOR ELEMENT AND MANUFACTURING PROCESS
US3910804A
(en)
*
1973-07-02
1975-10-07
Ampex
Manufacturing method for self-aligned mos transistor
US3883372A
(en)
*
1973-07-11
1975-05-13
Westinghouse Electric Corp
Method of making a planar graded channel MOS transistor
US3880684A
(en)
*
1973-08-03
1975-04-29
Mitsubishi Electric Corp
Process for preparing semiconductor
US3936859A
(en)
*
1973-08-06
1976-02-03
Rca Corporation
Semiconductor device including a conductor surrounded by an insulator
IN140846B
(en)
*
1973-08-06
1976-12-25
Rca Corp
US4005455A
(en)
*
1974-08-21
1977-01-25
Intel Corporation
Corrosive resistant semiconductor interconnect pad
US4127931A
(en)
*
1974-10-04
1978-12-05
Nippon Electric Co., Ltd.
Semiconductor device
US4074304A
(en)
*
1974-10-04
1978-02-14
Nippon Electric Company, Ltd.
Semiconductor device having a miniature junction area and process for fabricating same
US3943542A
(en)
*
1974-11-06
1976-03-09
International Business Machines, Corporation
High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same
US4054989A
(en)
*
1974-11-06
1977-10-25
International Business Machines Corporation
High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same
US3988619A
(en)
*
1974-12-27
1976-10-26
International Business Machines Corporation
Random access solid-state image sensor with non-destructive read-out
US3996657A
(en)
*
1974-12-30
1976-12-14
Intel Corporation
Double polycrystalline silicon gate memory device
US3958323A
(en)
*
1975-04-29
1976-05-25
International Business Machines Corporation
Three mask self aligned IGFET fabrication process
JPS5232680A
(en)
*
1975-09-08
1977-03-12
Toko Inc
Manufacturing process of insulation gate-type field-effect semiconduct or device
NL7510903A
(en)
*
1975-09-17
1977-03-21
Philips Nv
PROCESS FOR MANUFACTURING A SEMI-GUIDE DEVICE, AND DEVICE MANUFACTURED ACCORDING TO THE PROCESS.
US4136434A
(en)
*
1977-06-10
1979-01-30
Bell Telephone Laboratories, Incorporated
Fabrication of small contact openings in large-scale-integrated devices
GB2042801B
(en)
*
1979-02-13
1983-12-14
Standard Telephones Cables Ltd
Contacting semicnductor devices
US4272308A
(en)
*
1979-10-10
1981-06-09
Varshney Ramesh C
Method of forming recessed isolation oxide layers
US4462846A
(en)
*
1979-10-10
1984-07-31
Varshney Ramesh C
Semiconductor structure for recessed isolation oxide
US4271583A
(en)
*
1980-03-10
1981-06-09
Bell Telephone Laboratories, Incorporated
Fabrication of semiconductor devices having planar recessed oxide isolation region
WO2009055782A1
(en)
2007-10-26
2009-04-30
Possis Medical, Inc.
Intravascular guidewire filter system for pulmonary embolism protection and embolism removal or maceration
Family Cites Families (3)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
DE1143374B
(en)
*
1955-08-08
1963-02-07
Siemens Ag
Process for removing the surface of a semiconductor crystal and subsequent contacting
US3122463A
(en)
*
1961-03-07
1964-02-25
Bell Telephone Labor Inc
Etching technique for fabricating semiconductor or ceramic devices
GB1104935A
(en)
*
1964-05-08
1968-03-06
Standard Telephones Cables Ltd
Improvements in or relating to a method of forming a layer of an inorganic compound
1971
1971-03-19
US
US00126025A
patent/US3761327A/en
not_active
Expired – Lifetime
1972
1972-03-13
DE
DE19722211972
patent/DE2211972A1/en
active
Pending
1972-03-13
AU
AU39919/72A
patent/AU465819B2/en
not_active
Expired
1972-03-16
GB
GB1234972A
patent/GB1354425A/en
not_active
Expired
1972-03-17
FR
FR7209313A
patent/FR2130351B1/fr
not_active
Expired
1972-03-17
FR
FR7209314A
patent/FR2130352A1/fr
not_active
Withdrawn
1972-03-17
DE
DE2213037A
patent/DE2213037C2/en
not_active
Expired
Cited By (2)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
GB2203592A
(en)
*
1987-03-07
1988-10-19
Samsung Semiconductor Tele
Method of manufacturing a semiconductor device
GB2203592B
(en)
*
1987-03-07
1990-07-04
Samsung Semiconductor Tele
Method of manufacturing a semiconductor device
Also Published As
Publication number
Publication date
FR2130352A1
(en)
1972-11-03
DE2211972A1
(en)
1972-09-28
FR2130351B1
(en)
1977-12-23
DE2213037C2
(en)
1982-04-22
FR2130351A1
(en)
1972-11-03
DE2213037A1
(en)
1972-10-05
AU465819B2
(en)
1973-09-20
AU3991972A
(en)
1973-09-20
US3761327A
(en)
1973-09-25
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Legal Events
Date
Code
Title
Description
1974-10-09
PS
Patent sealed [section 19, patents act 1949]
1975-01-02
49R
Reference inserted (sect. 9/1949)
1976-03-31
435
Patent endorsed ‘licences of right’ on the date specified (sect. 35/1949)
1978-10-18
PCNP
Patent ceased through non-payment of renewal fee
