GB1363171A – Interconnection package for electrical ciruits
– Google Patents
GB1363171A – Interconnection package for electrical ciruits
– Google Patents
Interconnection package for electrical ciruits
Info
Publication number
GB1363171A
GB1363171A
GB4015672A
GB4015672A
GB1363171A
GB 1363171 A
GB1363171 A
GB 1363171A
GB 4015672 A
GB4015672 A
GB 4015672A
GB 4015672 A
GB4015672 A
GB 4015672A
GB 1363171 A
GB1363171 A
GB 1363171A
Authority
GB
United Kingdom
Prior art keywords
studs
interconnection
conductive
conjoined
plated
Prior art date
1971-10-14
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4015672A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1971-10-14
Filing date
1972-08-30
Publication date
1974-08-14
1972-08-30
Application filed by International Business Machines Corp
filed
Critical
International Business Machines Corp
1974-08-14
Publication of GB1363171A
publication
Critical
patent/GB1363171A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
H—ELECTRICITY
H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
H05K3/00—Apparatus or processes for manufacturing printed circuits
H05K3/46—Manufacturing multilayer circuits
H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
H—ELECTRICITY
H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
H05K1/00—Printed circuits
H05K1/02—Details
H05K1/0272—Adaptations for fluid transport, e.g. channels, holes
H—ELECTRICITY
H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
H05K2201/03—Conductive materials
H05K2201/0302—Properties and characteristics in general
H05K2201/0305—Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
H—ELECTRICITY
H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
H05K2201/03—Conductive materials
H05K2201/0332—Structure of the conductor
H05K2201/0364—Conductor shape
H05K2201/0379—Stacked conductors
H—ELECTRICITY
H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
H05K2201/09—Shape and layout
H05K2201/09209—Shape and layout details of conductors
H05K2201/095—Conductive through-holes or vias
H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
H—ELECTRICITY
H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
H05K2201/09—Shape and layout
H05K2201/09209—Shape and layout details of conductors
H05K2201/095—Conductive through-holes or vias
H05K2201/09563—Metal filled via
H—ELECTRICITY
H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
H05K2201/09—Shape and layout
H05K2201/09209—Shape and layout details of conductors
H05K2201/095—Conductive through-holes or vias
H05K2201/096—Vertically aligned vias, holes or stacked vias
H—ELECTRICITY
H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
H05K3/00—Apparatus or processes for manufacturing printed circuits
H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
H—ELECTRICITY
H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
H05K3/00—Apparatus or processes for manufacturing printed circuits
H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
H—ELECTRICITY
H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
H05K3/00—Apparatus or processes for manufacturing printed circuits
H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
H05K3/42—Plated through-holes or plated via connections
H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
H—ELECTRICITY
H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
H05K3/00—Apparatus or processes for manufacturing printed circuits
H05K3/46—Manufacturing multilayer circuits
H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
H—ELECTRICITY
H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
H05K3/00—Apparatus or processes for manufacturing printed circuits
H05K3/46—Manufacturing multilayer circuits
H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
Abstract
1363171 Soldering INTERNATIONAL BUSINESS MACHINES CORP 30 Aug 1972 [14 Oct 1971] 40156/72 Heading B3R [Also in Division H1] An interconnection package comprises plural laminar dielectric layers 10, 12, 14, 16, e.g. of epoxy glass, of which a ground plane comprises layers 18, 20 of Cu sandwiching an interconnecting Ga layer 22. Interconnection circuit patterns 26, 28 of Cu are separated by dielectric layer 30 and defined by selective etching, and plural studs 32 or plated through holes provide vertical conductive paths bonded by, e.g. Ga at 34 (Fig. 1). In processing (Fig. 2, not shown) the insulant member of, e.g. epoxy glass, ceramic, quartz, polyamide glass, polyethylene terephthalate is perforated, and conductive material, e.g. Cu is plated in the holes to form a stud. Adjacent members with studs therein are conjoined with liquid Ga at the interface and heated under pressure to interdiffuse the Ga and Cu and form a solid bond therebetween. Conductive planes can be similarly bonded, and the studs may terminate coplanar with the surface of the members. Dielectric sections may be conjoined (Fig. 3, not shown) with vertical interconnection paths as above, and horizontal metallized patterns thereon separated by a similar dielectric layer 82. The conductive paths may be of Au, Ag, Ni instead of Cu.
GB4015672A
1971-10-14
1972-08-30
Interconnection package for electrical ciruits
Expired
GB1363171A
(en)
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
US18941671A
1971-10-14
1971-10-14
Publications (1)
Publication Number
Publication Date
GB1363171A
true
GB1363171A
(en)
1974-08-14
Family
ID=22697230
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB4015672A
Expired
GB1363171A
(en)
1971-10-14
1972-08-30
Interconnection package for electrical ciruits
Country Status (4)
Country
Link
JP
(1)
JPS5517519B2
(en)
DE
(1)
DE2242393C2
(en)
FR
(1)
FR2156408B1
(en)
GB
(1)
GB1363171A
(en)
Families Citing this family (1)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
DE3108546A1
(en)
*
1981-03-06
1982-09-16
Siemens AG, 1000 Berlin und 8000 München
Means of making through-contact for multilayer printed-circuit boards
Family Cites Families (3)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3141238A
(en)
*
1960-11-22
1964-07-21
Jr George G Harman
Method of low temperature bonding for subsequent high temperature use
US3193789A
(en)
*
1962-08-01
1965-07-06
Sperry Rand Corp
Electrical circuitry
US3233034A
(en)
*
1964-10-26
1966-02-01
Dimitry G Grabbe
Diffusion bonded printed circuit terminal structure
1972
1972-08-29
DE
DE19722242393
patent/DE2242393C2/en
not_active
Expired
1972-08-30
GB
GB4015672A
patent/GB1363171A/en
not_active
Expired
1972-09-13
JP
JP9135372A
patent/JPS5517519B2/ja
not_active
Expired
1972-10-11
FR
FR7236789A
patent/FR2156408B1/fr
not_active
Expired
Also Published As
Publication number
Publication date
FR2156408A1
(en)
1973-05-25
DE2242393C2
(en)
1983-09-22
JPS5517519B2
(en)
1980-05-12
JPS4846864A
(en)
1973-07-04
DE2242393A1
(en)
1973-04-19
FR2156408B1
(en)
1975-09-12
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Legal Events
Date
Code
Title
Description
1974-12-27
PS
Patent sealed
1983-03-30
PCNP
Patent ceased through non-payment of renewal fee
