GB1389500A – Parity error recovery in computers
– Google Patents
GB1389500A – Parity error recovery in computers
– Google Patents
Parity error recovery in computers
Info
Publication number
GB1389500A
GB1389500A
GB3367973A
GB3367973A
GB1389500A
GB 1389500 A
GB1389500 A
GB 1389500A
GB 3367973 A
GB3367973 A
GB 3367973A
GB 3367973 A
GB3367973 A
GB 3367973A
GB 1389500 A
GB1389500 A
GB 1389500A
Authority
GB
United Kingdom
Prior art keywords
parity
register
address
data
error
Prior art date
1972-07-17
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3367973A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sperry Corp
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1972-07-17
Filing date
1973-07-16
Publication date
1975-04-03
1973-07-16
Application filed by Sperry Rand Corp
filed
Critical
Sperry Rand Corp
1975-04-03
Publication of GB1389500A
publication
Critical
patent/GB1389500A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
238000011084
recovery
Methods
0.000
title
abstract
5
Classifications
G—PHYSICS
G11—INFORMATION STORAGE
G11C—STATIC STORES
G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
G11C29/70—Masking faults in memories by using spares or by reconfiguring
G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
Abstract
1389500 Recovery routines SPERRY RAND CORP 16 July 1973 [17 July 1972] 33679/73 Heading G4A A data processing system having independently accessible storage segments in a store 49 (Fig. 3), effects a first parity error recovery rountine held in one of the storage segments when a parity error is detected in data or addresses relating to a storage segment in which the first parity error rountine is not stored and a second parity error recovery rountine held in a different segment of storage if the erroneous information relates to the storage segment in which the first routine is stored. Data read from a storage segment in response to an address entered into register 24 is fed to an input data register 48, a parity generator 27 deriving a parity bit for each half word of this data for comparison in error logic 26 with parity bits read from the store. Circuitry 30 performs a parity check on read or write data supplied to the stores and feeds its output to the error logic 26 which is connected to interrupt priority logic 23. A comparity 21 compares the most significant bits of the address in register 24 with the address in register 25 of the first parity recovery routine and if coincidence does not exist the priority logic 23 transfers the contents of register 25 to interrupt address register 22 together with a pointer to give the absolute address. Otherwise the contents of auxiliary parity routine register 20 are fed to the register 22 together with a pointer.
GB3367973A
1972-07-17
1973-07-16
Parity error recovery in computers
Expired
GB1389500A
(en)
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
US00272504A
US3806716A
(en)
1972-07-17
1972-07-17
Parity error recovery
Publications (1)
Publication Number
Publication Date
GB1389500A
true
GB1389500A
(en)
1975-04-03
Family
ID=23040080
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB3367973A
Expired
GB1389500A
(en)
1972-07-17
1973-07-16
Parity error recovery in computers
Country Status (9)
Country
Link
US
(1)
US3806716A
(en)
JP
(1)
JPS5634894B2
(en)
AU
(1)
AU471091B2
(en)
CA
(1)
CA982695A
(en)
DE
(1)
DE2336020C3
(en)
FR
(1)
FR2193508A5
(en)
GB
(1)
GB1389500A
(en)
IT
(1)
IT991196B
(en)
SE
(1)
SE380646B
(en)
Families Citing this family (16)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
FR2257213A5
(en)
*
1973-12-04
1975-08-01
Cii
US3963908A
(en)
*
1975-02-24
1976-06-15
North Electric Company
Encoding scheme for failure detection in random access memories
US4010450A
(en)
*
1975-03-26
1977-03-01
Honeywell Information Systems, Inc.
Fail soft memory
DE2518588C3
(en)
*
1975-04-25
1978-07-20
Siemens Ag, 1000 Berlin Und 8000 Muenchen
Method for monitoring the consistency of code signal groups in telecommunications equipment
US3982111A
(en)
*
1975-08-04
1976-09-21
Bell Telephone Laboratories, Incorporated
Memory diagnostic arrangement
US4063081A
(en)
*
1976-06-08
1977-12-13
Honeywell
Computer apparatus
DE2656071C3
(en)
*
1976-12-10
1982-12-30
Multivac Sepp Haggenmüller KG, 8941 Wolfertschwenden
Method and device for shaping plastic film into containers open on one side with a bottom edge
US4224681A
(en)
*
1978-12-15
1980-09-23
Digital Equipment Corporation
Parity processing in arithmetic operations
JPS60183653A
(en)
*
1984-03-01
1985-09-19
Toshiba Corp
Memory provided with bit error detecting function
JPS63175160A
(en)
*
1987-01-12
1988-07-19
サムエンジニアリング株式会社
Foam washing machine
JPH02106489U
(en)
*
1989-02-14
1990-08-23
US5177747A
(en)
*
1989-10-16
1993-01-05
International Business Machines Corp.
Personal computer memory bank parity error indicator
US5313627A
(en)
*
1992-01-02
1994-05-17
International Business Machines Corp.
Parity error detection and recovery
US6151685A
(en)
*
1998-05-15
2000-11-21
International Business Machines Corporation
System and method for recovering a segment directory for a log structured array
US7093190B1
(en)
*
2002-07-12
2006-08-15
Unisys Corporation
System and method for handling parity errors in a data processing system
DE102006035662A1
(en)
*
2006-07-31
2008-02-14
Infineon Technologies Ag
Monitoring correct operation of data processing unit, displaces subsystem from allowed state into non-allowed state before executing partial operational run
Family Cites Families (2)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3619585A
(en)
*
1969-11-17
1971-11-09
Rca Corp
Error controlled automatic reinterrogation of memory
US3693153A
(en)
*
1971-07-09
1972-09-19
Bell Telephone Labor Inc
Parity check apparatus and method for minicomputers
1972
1972-07-17
US
US00272504A
patent/US3806716A/en
not_active
Expired – Lifetime
1973
1973-07-09
AU
AU57875/73A
patent/AU471091B2/en
not_active
Expired
1973-07-11
CA
CA176,234A
patent/CA982695A/en
not_active
Expired
1973-07-13
IT
IT26607/73A
patent/IT991196B/en
active
1973-07-13
SE
SE7309883A
patent/SE380646B/en
unknown
1973-07-13
FR
FR7325818A
patent/FR2193508A5/fr
not_active
Expired
1973-07-14
DE
DE2336020A
patent/DE2336020C3/en
not_active
Expired
1973-07-16
GB
GB3367973A
patent/GB1389500A/en
not_active
Expired
1973-07-17
JP
JP8260973A
patent/JPS5634894B2/ja
not_active
Expired
Also Published As
Publication number
Publication date
JPS4960137A
(en)
1974-06-11
AU471091B2
(en)
1976-04-08
SE380646B
(en)
1975-11-10
IT991196B
(en)
1975-07-30
FR2193508A5
(en)
1974-02-15
US3806716A
(en)
1974-04-23
DE2336020C3
(en)
1978-08-17
DE2336020A1
(en)
1974-02-21
CA982695A
(en)
1976-01-27
DE2336020B2
(en)
1977-10-20
AU5787573A
(en)
1975-01-09
JPS5634894B2
(en)
1981-08-13
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Legal Events
Date
Code
Title
Description
1975-08-13
PS
Patent sealed [section 19, patents act 1949]
1991-03-13
PCNP
Patent ceased through non-payment of renewal fee
