GB1569048A - Creación de Inventos y Patentes con Inteligencia Artificial

GB1569048A – Digital function generator
– Google Patents

GB1569048A – Digital function generator
– Google Patents
Digital function generator

Download PDF
Info

Publication number
GB1569048A

GB1569048A
GB5048/78A
GB504878A
GB1569048A
GB 1569048 A
GB1569048 A
GB 1569048A
GB 5048/78 A
GB5048/78 A
GB 5048/78A
GB 504878 A
GB504878 A
GB 504878A
GB 1569048 A
GB1569048 A
GB 1569048A
Authority
GB
United Kingdom
Prior art keywords
modulo
counter
output
counting means
rom
Prior art date
1977-02-14
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB5048/78A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

CBS Corp

Original Assignee
Westinghouse Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1977-02-14
Filing date
1978-02-08
Publication date
1980-06-11

1978-02-08
Application filed by Westinghouse Electric Corp
filed
Critical
Westinghouse Electric Corp

1980-06-11
Publication of GB1569048A
publication
Critical
patent/GB1569048A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

Classifications

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F1/00—Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00

G06F1/02—Digital function generators

G06F1/03—Digital function generators working, at least partly, by table look-up

G06F1/035—Reduction of table size

G06F1/0353—Reduction of table size by using symmetrical properties of the function, e.g. using most significant bits for quadrant control

Description

PATENT SPECIFICATION ( 11) 1 569 048
( 21) Application No 5048/78 ( 22) Filed 8 Feb 1978 ( 19) ( 31) Convention Application No 768130 ( 32) Filed 14 Feb 1977 ink ( 33) United States of America (US) / ( 44) Complete Specification Published 11 Jun 1980 &;,1 D, ii ( 51) INT CL 3 H 03 K 7/08 S ó _ ( 52) Index at Acceptance H 3 H 13 D 14 B 14 D 6 A 6 B 6 D 6 F 7 B 7 F 1 7 G 7 X 8 B 8 E GW ( 54) DIGITAL FUNCTION GENERATOR ( 71) We, WESTINGHOUSE ELECTRIC CORPORATION of Westinghouse Building Gateway Center, Pittsburgh, Pennsylvania, United States of America a company organised and existing under the laws of the State of Pennsylvania, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by 5
the following statement:
This invention relates to an improved digital function generator, and, more particularly, to a pulse width modulated sine and cosine wave generator.
In the field of numerical control, resolver and Inductosvn feedback devices require two sine waves ninety degrees apart or in quadrature These sine waves can of course be 10 generated with elaborate equipment, but the simplest way to maintain the precise quadrature relationship is by the use of waves derived from a counter driven by a constant frequency clock However, as is well known square waves are rich in harmonic content so that considerable filtering is required It is therefore recognized in the art that it would be helpful to eliminate or suppress the undesired odd harmonics particularly the third fifth 15 and seventh, to reduce filtering requirements.
An article appearing in EDN published by Cahners Publishing Co Inc, Boston Mass.
02116 on January 15, 1971 entitled «Reduce Static Inverter Weight and Cost by Harmonic Neutralization» P W Koetsch, describes a technique for the suppression of the odd harmonics in a square wave output utilizing a pulse width modulation technique In this 20 article there is described a static inverter, operating in the switching mode, that generates a square wave output that contains odd harmonics Since the fundamental only was of interest, the pulse width technique was utilized to eliminate troublesome harmonics In this technique, the on and off switching is controlled to produce a square pulse output wave of variable time width by using a stable oscillator and countdown procedure 25 It is the principal object of this invention to provide an improved digital function generator based on a similar switching principle.
The invention relates to a digital function generator for deriving a particular waveform by pulse width modulation, comprising counting means, storage means responsive to the outputs of said counting means as addresses for providing a first programmed output signal 30 defining said particular waveform and a second programmed output signal defining a modulo, variable modulo counting means responsive to said modulo output for counting until it reaches a state determined by said modulo output and for providing an output signal indicating that said state has been reached to said first-named counting means, and means for clocking connected to said first-named counting means and to said variable modulo 35 counting means, said first-named counting means being responsive to said variable modulo counter output for advancing to its next state to provide the next address for said storage means so that said storage means provides the next programmed modulo to said variable modulo counting means, the modulated width of said particular waveform being a function of the duration of the states of said first-named counting means 40 According to one embodiment of this invention the function generator is used to produce sine and cosine waves A read only memory (ROM) means is used to control the modulo of a counter A first counting means addresses the ROM with all bit outputs save the most significant bit The ROM has programmed outputs two of which provide sine and cosine half cycle outputs (logic ONES and ZEROES) and the remaining programmed 45 1 569 048 outputs are applied to the variable modulo counter When the variable modulo counter has counted to its capacity, it is enabled and an end of state signal is sent to the first counting means, which then advances to its next state, causing the ROM to have impending a new modulus for the variable modulo counter When the variable modulo counter is enabled, it receives the ROM output which is the modulo from the previous state of the first counting 5 means.
Thus the duration of the state of the first counting means determines the duration of the logic ONES and ZEROES in the ROM sine and cosine half cycle outputs The most significant bit of the first counting means, and the logic ONES and ZEROES of the ROM sine and cosine half cycle outputs are applied to circuitry for Boolean algebraic logic 10 operations to derive pulse width modulated sine and cosine waves.
The ROM is programmed to provide a desired pulse width pattern If it is desired to change this pattern to eliminate or minimize certain harmonics this may be accomplished simply by replacing the ROM with one containing the desired data.
This invention will become readily apparent from the following description of an 15 exemplary embodiment thereof when read in conjunction with the accompanying drawings, in which:
Figure 1 is an electrical schematic of a pulse width modulated sinecosine wave generator in accordance with one embodiment of the invention:
Figure 2 A, 2 B are tables showing how the ROM of Figure 1 is programmed to provide 20 variable moduli; and Figures 3 and 4 are wave forms used in explaining the operation of the wave generator.
Referring now to Figure 1, there is shown a preferred embodiment of the invention which comprises a pulse width modulated sine-cosine wave generator as generally indicated at 10.
This circuitry digitally generates: (a) a sine square wave SINSQW (b) a pulse width 25 modulated sin wave PWMSIN and (c) a pulse width modulated cos wave PWMCOS These waves can be used for many applications requiring efficient generation of two sine waves in quadrature.
The sine-cosine wave generator is here illustrated as the excitation for a rotary control transformer (RCT) indicated generally at 12 Two sin waves are required to excite the 30 stator windings SI 53; 52,54 of the rotary control transformer 12 These sine waves must be 900 apart or in quadrature It is important that the quadrature relationship be maintained with a high degree of precision The output of the RCT 12, taken from the rotor windings R 1 R, is an a c signal which is a function of the rotational displacement 0 of the rotor.
(When the RCT 12 is used in the numerical control, the sin square wave (SINSQW) is used 35 as a mark for synchronization with other components).
The pulse width modulated sin-cos generator 10 comprises two binary 4 bit synchronous counters 14, 16 a read only memory (ROM) 18 NOT gate 20, EXCLUSIVE OR gates 22, 24, variable modulo counter 26, and drivers 28 30 32.
Referring now to Figure 2 A and 2 B the ROM 18 is programmed to have the outputs Q, 40 to 08 indicated in the tables Counters 14 and 16 control the ROM address A,.Al A 2,A 3,A 4 The counter 14 addresses the ROM through 16 states 00 to OF (Figure 2 A) At the end of state OF, there is a carry in (Cl) to counter 16 The ROM 18 now receives a ONE on its A 4 address, and is successively addressed 10 through IF.
Looking at line 00 in Figure 2 A, the hexadecimal code E 9 is 1110 1001 i e the outputs 45 Q 8 Q 5; Q 4 Q The number 23 in binary form is 010111: the 2 ‘s complement of this number, 101001, is the ROM output O to Ql The ROM output is loaded into counter 26 and it becomes the modulus The counters 14 16 and 26 are clocked by the clock pulses 4 M Hz The number 23 is the number of 4 M Hz pulses that the counter 26 must count.
Counter 26 counts up, until it reaches all ONES At that time an end of state EOST signal is 50 sent to counter 14 (The EOST signal also enables the counter 26) When the counter 14 receives the EOST signal it goes to the next state, putting in the next address to the ROM 18, which then outputs a new modulo to the counter 26 No new modulo is loaded into the counter 26 until it is enabled (LD) The status quo will be maintained until counter 26 counts up to all ONES and another end of state signal EOST is sent to the counter 14 55 Referring again to Figures 2 A and 2 B the Q 7 and Q% outputs of the ROM are the cosine half cycle COSHC and the sine half cycle SINHC respectively.
The 4 bit synchronous counter 14 has a modulus of 16 As is well appreciated by those in the art, counters (and registers too) cannot distinguish numbers which differ only by an integral multiple of its modulus However, in order to simplify the discussion, the second 60 sequence of the counter will be identified as going from 16-32 the third sequence from 32-48 etc realizing of course, that the actual counter simply repeats itself over and over again.
Referring now to Figures 1 and 3 the generation of the sine square wave (SINSQW) is as follows The output Q 2 of counter 16 is connected to NOT gate 20 so that the inversion of its 65 3 1 569 048 3 logic state is gated to driver 28 At the outset, assume that the outputs of Q, and 02 of counter 16 are logic ZEROES Counter 14 counts up to 16 and a carry in (CI) pulse of 8 kilo Hz is sent to counter 16, whereupon the output Q, of counter 16 is changed to a logic ONE.
(Q 2 remains ZERO) The Q O output of counter 16 is applied to ROM 18 as address A 4.
Counter 14 begins its second sequence which will be identified as counting from 16-32 5 When all ONES are reached, counter 16 sends a C I to counter 16, changing Ql to ZERO, and changing Q 2 to a logic ONE Counter 14 counts now from 32 to 48 and sends Cl to counter 16, changing Q, to a logic ONE (Q O remains a logic ONE) Counter 14 counts from 48 to 64, sending a C I to counter 16 Output Q O goes from logic ONE to logic ZERO, and Q 2 goes from a logic ONE to logic ZERO In summary Q 2 has been a ZERO for two count 10 sequences of counter 14, and has been a ONE for the next two count sequences of counter 14 These logic states are inverted by NOT gate 20 and applied to driver 28 to provide SINSQW.
The generation of the SINHC and COSHC is essentially the same, so that only the SINHC output will be explained The SINHC is the output 08 of ROM 18 As will be seen 15 from a study of Figures 2 A, 2 B, Q O changes from ONE to ZERO in a predetermined sequence.
In order to make clear the generation of SINHC the following table is presented:
Counter 26 20 Line No ROM Modulus SINHC 1 F 23 46 1 00 23 23 1 01 35 23 1 25 02 32 35 0 03 32 32 1 04 26 32 1 49 26 0 06 14 49 1 30 07 32 14 1 08 14 32 1 09 49 14 O OA 26 49 1 35 Assume that the counters 14 16 are at line IF (Figure 2 81) the ROM’s impending output Q 1 to Q 6 is 23, counter 26 has a modulus 46 and SINHC is a ONE When counter 26 counts 46 pulses, an EOST signal is sent to counter 14 and it goes to the next line 00 The EOST singal is also the load signal (LD) to counter 26 and the previous ROM state Q O Q, i e 23.
is now loaded into counter 26; this becomes the new modulo for counter 26 When the 40 counter 14 goes to the next line, 00 ROM 18 receives a new address A,, A, and is now ready to send a new output Q O 6 Q which is again 23 Counter 26 now counts 23 pulses, and EOST is sent to counter 14 At line 01 the ROM’s impending output Q, O Q, is 35, counter 26 receives the output 23 from ROM 18 Counter 26 now counts 23 pulses whereupon the end of state signal EOST is sent to counter 14 sending it to the next line 02 45 and counter 16 receives the ROM output 35 ROM now has the state Q, Q, = 32.
Counter 26 now counts 35 pulses, and then sends EOST to counter 14 indexing it to line 03.
At this point it will be convenient to summarize what has taken place From line 00 to 01, the counter 26 has counted 46 pulses ( 23 + 23) and the SINHC has remained ONE At step 02, counter 26 has counted to 35 and SINHC is a ONE for 46 counts and a ZERO for 35 50 counts.
In line 03 and 04 the counter 26 will count 64 pulses ( 32 + 32) and the SINHC will be ONE For line 05 counter 26 will count 26 pulses and the SINHC will be ZERO For lines 06 to 08, the counter 26 will count 95 pulses ( 49 + 14 + 32) while SINHC will be ONE For line 09 counter 26 will count 14 pulses and the SINHC will be ZERO These counting 55 periods, as well as the logic state of sin HC and COSHC are shown in Figure 3, for one half cycle i e 1000 T.
As had been assumed earlier the output 02 of counter 16 is a ZERO for counts 1-32 and a ONE 32-64 When Q 2 is ZERO, the EXCLUSIVE OR’s 22 and 24 will have a ONE -output only when the other input i e SINHC or COSHC is a ONE When Q 2 becomes a 60 ONE, they will have a ONE ouput only when the other input is ZERO.
In this manner the EXCLUSIVE OR gates deliver the pulse width modulated sin (PWMSIN) and cosine (PWMCOS) wave patterns depicted in Figure 4.
The pulse width pattern is determined by mathematical analysis.
In summary, the counters 14, 16 have 32 states i e a modulo 32 counter The 65
1 569 048 A 1 569 048 variable-modulo counter 26 changes state every 4 M Hz clock pulses The EOST out of counter 26 is one clock period wide and is used to gate a number generated by the ROM to preset the counter 26 at the next clock pulse The EOST signal advances the modulo 32 counter to its next state at the same time as the variable modulo counter 26 is being preset.
The ROM 18 acts as a look up table, selecting the proper number (modulo) to preset the 5 variable modulo counter 26, thus establishing the duration (in terms of 4 M Hz clock pulses) of the next state of the modulo 32 counter The counter ( 14 16) can generate the desired pulse width modulated signals PWMSIN and PWMCOS, if the ROM is programmed such that each state of the modulo counter ( 14, 16) has the desired pulse width or duration.
In order to simplify the design, in the practical embodiment, the maximum duration of 10 the modulo 32 counter is kept at 64 clock pulses In cases where the pulse width requires a longer duration, successive modulo 32 counter ( 14, 16) states are used until the correct duration is attained and/or until all 32 states are used.
The second function of the ROM 18 is to decode the five least significant bits of the modulo 32 counter and output the desired logic state ( 1 or » O «) for the SWMSIN and 15 PWMCOS during that particular state of the modulo 32 counter ( 14 16) Because of the symmetry of the sine and cosine, only a half cycle is encoded and the most significant bit of the modulo 32 counter ( 14, 16) (SINSQW) is utilized by means of a pair of EXCLUSIVE-OR gates to complement the encoded states which repeat for the second half cycle, to produce the desired PWMSIN and PNMCOS waves 20 The use of ROM control of the generator and for decoding the discrete logic states, enable the utilization of minimal circuitry, but nevertheless provides great flexibility in the selection of the pulse wave pattern.
The harmonic content of the PWSIN and PWCOS signals can be tailored to minimize certain harmonics of the carrier frequency to accommodate particular gainbandwidth 25 characteristics of different resolver type devices This can be accomplished by changing the widths or durations of the discrete pulses during a half cycle of the carrier frequency This pulse width customizing is accomplished simply by relacing the ROM 18 with another ROM containing the required modulo outputs.

Claims (3)

WHAT WE CLAIM IS: 30

1 A digital function generator for deriving a particular waveform by pulse width modulation, comprising counting means, storage means responsive to the outputs of said counting means as addresses for providing a first programmed output signal defining said particular waveform and a second programmed output signal defining a modulo variable modulo counting means responsive to said modulo output for counting until it reaches a 35 state determined by said modulo output and for providing an output signal indicating that said state has been reached to said first-named counting means, and means for clocking connected to said first-named counting means and to said variable modulo counting means, said first-named counting means being responsive to said variable modulo counter output for advancing to its next state to provide the next address for said storage means so that said 40 storage means provides the next programmed modulo to said variable modulo counting means, the modulated width of said particular waveform being a function of the duration of the states of said first-named counting means.

2 A digital function generator as claimed in claim 1 for use in deriving sine and cosine waves, wherein said first-named counting means has a plurality of states, comprising a 45 plurality of lesser significant bits and a most significant output bit; said storage means comprises a read only memory (ROM) having a plurality of address inputs for receiving said lesser significant bits and having a plurality of programmed output bits, two of said latter bits defining a sine half cycle (SINHC) and a cosine half cycle (COSHC), the remaining ROM output bits defining a modulo said variable modulo counting means having a 50 plurality of inputs connected to receive said modulo output from said ROM and to deliver an end of state (EOST) signal to said first-named counting means; whereby when the variable modulo counter has counted to its capacity the EOST signal to said first-named counting means; whereby when the variable modulo counter has counted to its capacity the EOST signal is sent to said first-named counting means and said variable modulo counter is 55 enabled, the first-named counting means then advancing to its next state to provide the next ROM address and the next programmed ROM modulo output, the ROM modulus output from the previous state of said first-named counting means now becoming the next modulo for said variable modulo counter, said function generator including logic means for receiving said most significant output bit and said SINHC and COSHC bit signals, for 60 performing algebraic logic operations to provide pulse width modulated sine and cosine waveforms respectively.

3 A digital function generator as claimed in claim 2 wherein said logic means comprises a pair of EXCLUSIVE-OR gates, each having said most significant output bit as one input, the other one input being said SINHC and COSHC bits respectively 65 1 569 048 5 4 A digital function generator as claimed in claim 2 wherein said counting means are first and second 4 bit synchronous counters, said first 4 bit counter receiving said EOST signal and sending a carry in (CI) signal to said second 4 bit counter, one bit output of said second 4 bit counter being one of said plurality of lesser significant bits, another bit output of said second 4 bit counter being said most significant output bit 5 A digital function generator substantially as hereinbefore described with reference to and, as shown in, the accompanying drawings.
RONALD VAN BERLYN Printed for Her Majesty’s Stationery Office, by Croydon Printing Company Limited, Croydon Surrey, 1980.
Published by The Patent Office, 25 Southampton Buildings London, WC 2 A IA Yfrom which copies may be obtained.

GB5048/78A
1977-02-14
1978-02-08
Digital function generator

Expired

GB1569048A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

US05/768,130

US4095275A
(en)

1977-02-14
1977-02-14
Pulse width modulated sine cosine generator

Publications (1)

Publication Number
Publication Date

GB1569048A
true

GB1569048A
(en)

1980-06-11

Family
ID=25081621
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB5048/78A
Expired

GB1569048A
(en)

1977-02-14
1978-02-08
Digital function generator

Country Status (7)

Country
Link

US
(1)

US4095275A
(en)

JP
(1)

JPS6054706B2
(en)

BE
(1)

BE863946A
(en)

DE
(1)

DE2806137A1
(en)

FR
(1)

FR2380672A1
(en)

GB
(1)

GB1569048A
(en)

IT
(1)

IT1093278B
(en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US4348734A
(en)

1980-07-10
1982-09-07
Reliance Electric Company
Converter by stored switching pattern

DE19621086C2
(en)

1996-05-24
1998-12-10
Andreas Grimm Engineering Elek

Function generator

CN102017412B
(en)

2008-04-10
2013-05-22
Nxp股份有限公司
Rotating pulse-width modulator

Family Cites Families (8)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3633017A
(en)

1970-01-07
1972-01-04
Sperry Rand Corp
Digital waveform generator

US3676655A
(en)

1970-07-31
1972-07-11
Chandler Evans Inc
Digital function generator for two independent variables with interpolation

US3657657A
(en)

1970-08-03
1972-04-18
William T Jefferson
Digital sine wave generator

GB1351308A
(en)

1971-08-18
1974-04-24
Ferranti Ltd
Data processing

US3727037A
(en)

1971-08-27
1973-04-10
A Zorn
Variable increment digital function generator

US3739374A
(en)

1971-08-27
1973-06-12
Mandrel Industries
Digital sweep generator for generating analog signals

US3980874A
(en)

1975-05-09
1976-09-14
Burroughs Corporation
Binary to modulo M translation

GB1496571A
(en)

1975-12-24
1977-12-30
Ferranti Ltd
Digital function generation

1977

1977-02-14
US
US05/768,130
patent/US4095275A/en
not_active
Expired – Lifetime

1978

1978-02-08
GB
GB5048/78A
patent/GB1569048A/en
not_active
Expired

1978-02-10
IT
IT20150/78A
patent/IT1093278B/en
active

1978-02-13
FR
FR7804015A
patent/FR2380672A1/en
active
Granted

1978-02-14
DE
DE19782806137
patent/DE2806137A1/en
active
Granted

1978-02-14
BE
BE185157A
patent/BE863946A/en
not_active
IP Right Cessation

1978-02-14
JP
JP53015051A
patent/JPS6054706B2/en
not_active
Expired

Also Published As

Publication number
Publication date

DE2806137C2
(en)

1988-01-28

FR2380672A1
(en)

1978-09-08

JPS6054706B2
(en)

1985-12-02

IT7820150D0
(en)

1978-02-10

US4095275A
(en)

1978-06-13

JPS5399845A
(en)

1978-08-31

BE863946A
(en)

1978-08-14

FR2380672B1
(en)

1984-02-10

DE2806137A1
(en)

1978-08-17

IT1093278B
(en)

1985-07-19

Información de contacto