GB2031195A - Creación de Inventos y Patentes con Inteligencia Artificial

GB2031195A – Circuit arrangement for withdrawing data stored in system data memories for diagnostic purposes
– Google Patents

GB2031195A – Circuit arrangement for withdrawing data stored in system data memories for diagnostic purposes
– Google Patents
Circuit arrangement for withdrawing data stored in system data memories for diagnostic purposes

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Publication number
GB2031195A

GB2031195A
GB7929820A
GB7929820A
GB2031195A
GB 2031195 A
GB2031195 A
GB 2031195A
GB 7929820 A
GB7929820 A
GB 7929820A
GB 7929820 A
GB7929820 A
GB 7929820A
GB 2031195 A
GB2031195 A
GB 2031195A
Authority
GB
United Kingdom
Prior art keywords
output
unit
memory
circuit
data
Prior art date
1978-08-29
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Granted

Application number
GB7929820A
Other versions

GB2031195B
(en

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Italtel SpA

Original Assignee
Societa Italiana Telecomunicazioni Siemens SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1978-08-29
Filing date
1979-08-28
Publication date
1980-04-16

1979-08-28
Application filed by Societa Italiana Telecomunicazioni Siemens SpA
filed
Critical
Societa Italiana Telecomunicazioni Siemens SpA

1980-04-16
Publication of GB2031195A
publication
Critical
patent/GB2031195A/en

1982-08-11
Application granted
granted
Critical

1982-08-11
Publication of GB2031195B
publication
Critical
patent/GB2031195B/en

Status
Expired
legal-status
Critical
Current

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Classifications

H—ELECTRICITY

H04—ELECTRIC COMMUNICATION TECHNIQUE

H04M—TELEPHONIC COMMUNICATION

H04M3/00—Automatic or semi-automatic exchanges

H04M3/08—Indicating faults in circuits or apparatus

H—ELECTRICITY

H04—ELECTRIC COMMUNICATION TECHNIQUE

H04Q—SELECTING

H04Q3/00—Selecting arrangements

H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker

H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised

H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme

H04Q3/54575—Software application

H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis

Description

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SPECIFICATION
Improvements in or relating to circuit arrangements for withdrawing data stored in data memories of 5 operative systems
The present invention relates to a circuit arrangement suitable for withdrawing data stored in a data memory of operative systems and for sending the
» 10 data to a display, such as kinescope screen monitor which displays them to make it possible to effect a diagnosis of malfunctioning or failures in the operative system.
It is desirable to make a diagnosis of failures in 15 particularly complicated operative systems having no programme of internal self-diagnosis arranged to signal possible failures to suitable units.
A number of telecommunication systems include particularly complicated operative systems general-20 ly comprising a control unit designed to write, in a central memory having a plurality of memory zones, data on a plurality of peripheral units such as telephone translators or repeators. An operative system of this kind is disclosed in Italian patent no. 25 979,855. As the operative systems of this kind generally lack programmes of internal self-diagnosis, it is particularly difficult to spot possible failures. A generally adopted method of diagnosing in the first place failures in operative systems of this 30 kind is to identify the peripheral unit out of order by testing the message stored in the data memory zone allocated to the peripheral unit in question. If a given peripheral unit is out of order, it processes some characters of the message incorrectly and thus it is 35 possible to diagnose a failure by testing the message which is the result of its processing operation.
The messages are usually tested by means of «logic analysers» having a screen on which some messages may be displayed. Thus, the logic analys-40 ers comprise a probe which is connected to the data memory of the operative system. The content of a memory zone is read by means of a sync pulse and is then displayed.
Besides being very expensive, logic analysers 45 require a deep knowledge of the hardware of the operative system to be analysed and make it possible to photograph the result of the processing operation of a given peripheral unit in operative systems of the kind in which the number of memory
* 50 zones is equal to the number of peripheral units, and thus a rigid mutual relation exists between memory zones and peripheral units. An operator knows
* which is the memory zone relating to the peripheral unit to be analysed.
55 In some operative systems the number of memory zones differs (i.e. is greater or smaller) from the peripheral units, and thus a random relationship exists (for example with the first free memory zone) between peripheral units the memor/ zones. In such 60 a case, the operator does not know which is the memory zone engaged by the peripheral unit to be analysed, and thus it is almost impossible to find outfits respective message. Consequently, spotting a failure becomes a very long and costly operation. 65 According to the invention, there is provided a circuit arrangement for use with a display for receiving data stored in a data memory of an operative system comprising a plurality of peripheral units connected to a control unit which has, 70 besides the data memory which is subdivided into a plurality of memory zones for storing a message formed by a predetermined number of characters, a counter for counting addresses of the data memory, the circuit arrangement comprising: a buffer mem-75 ory whose input is arranged to be connected to the output of the data memory; selection and comparison means whose input is arranged to be connected to the output of the data memory and to the output of the data memory and to the output of the address 80 counter, the selection means and comparison means being arranged to enable data storing and reading control means when the data and/or the addresses given by the operative systems are equal to selected ones; the data storing and reading control means 85 which is arranged to control storing or blanking of data supplied to the buffer memory in response to the presence or absence of an enabling signal generated by the selection and comparison means, and to control data transmission in response to a 90 control signal generated by the display; transcoding means arranged to transcode from the code of the data at the output of the buffer memory into the code used by the display; and means for counting the number of engaged memory zones in the data 95 memory.
It is possible to provide a particularly simple and ecomonic circuit arrangement which cooperates with, as a display device, kinescope-screen monitors generally already available for different purposes in 100 telecommunication systems.
It is also possible to provide a circuit arrangement the use of which does not involve specific knowledge of the hardware of the system to be analysed, the circuit arrangement making is possible to easily 105 test even operative systems in which peripheral units have random access to memory zones or areas.
The invention will be further described, by way of example with reference to the accompanying draw-110 ings, in which:
Figure 1 shows the connection of a circuit arrangement constituting a preferred embodiment of the invention to the control unit of the operative system and a kinescopic monitor;
115 Figure 2 is a block diagram of a circuit arrangement constituting a preferred embodiment of the invention;
Figure 3 shows a detail of a memory address selection unit SIM of Figure 2;
120 Figure 4 shows in detail a peripheral-unit selection unit SUP of Figure 2;
Figure 5 shows in detail a unit SMS of Figure 2, for the selection of memories engaged by the same peripheral unit;
125 Figure 6 shows in detail a processing condition selection unit SSE of Figure 2;
Figure 7 shows an engaged memory zone counting unit CAM of Figure 2;
Figure 8 shows a data storing control unit CM of 130 Figure 2; and
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Figure 9 shows a data reading control unit CE of Figure 2.
Figure 1 shows a control unit UC for controlling an operative system, only those components pertaining 5 to the invention being illustrated in detail.
The unit UC comprises a data memory MD which is assumed to be of recirculation type, e.g. having four delay lines in parallel, and operates with 4 x 16,144 bits, which makes it possible to record 573 10 messages, termed RET below, concerning an equal number of peripheral units comprising for example telephone translators. Each message includes 28 characters, also termed phases below.
The drawings also show an input UE of the 15 memory MD which is caused to step forward by pulses CK which are also sent to an address counter CI. The address counter CI comprises a first counter that has a counting capacity of 28 and is connected in cascade to a second counter having a counting 20 capacity of 573.
The circuit arrangement forms an interface unit U! between the control unit UC (to which it is connected byway of 15 wires a from the outputs of the counter CI and by way of four wires b from the outputs of the 25 memory MD) and a visual display unit or kinescopic monitor VCto which it is connected by way of seven output wires c through which data coded in the ASCY code are transmitted and by way of two input wires through which it receives signals enabling 30 the transmission of the above mentioned data.
Figure 2 illustrates a block diagram of a circuit arrangement constituting a preferred embodiment of the invention, the arrangement comprising a buffer memory MT which receives the data available 35 at the output b of the memory MD and which is controlled by data writing and reading control means MME.
The means MME is enabled by the kinescopic monitor VC and by means MSC designed to select 40 information to be displayed and to identify the information so selected. The means MME comprises a first unit CM arranged to control storing or blanking of data sent to the buffer memory MTin response to the presence or absence of enabling 45 signals generated by the selection and comparison means MSC. The means mme also comprises a unit CE arranged to control reading of data stored in the buffer memory in response to a data request by the kinescopic monitor VC.
50 Transcoding means TR are provided at the output of the buffer memory MT, and are arranged to transcode into the ASCY code data in the binary code.
The circuit arrangement also comprises counting 55 means CAM for counting the number of engaged memory zones, as will be further described below with reference to Figure 7.
The selection and comparison means MSC comprises a memory address selection unit SIM which is 60 designed .to be used for analysing operative systems in which a rigid association exists between the peripheral units connected to the unit UC and the memory zones of the unit MD. With systems of this kind, the operator knows in advance the address of 65 the memory zone allocated to the peripheral unit to be analysed, and thus he is able to display the data concerning such a peripheral unit by selecting such an address.
The unit SIM is shown in detail in Figure 3, in 70 which DSi indicates a first selection device by means of which the operator writes in binary code the address of the memory zone allocated to the peripheral unit to be analysed. The binary configuration available at the output of the device DS-i is 75 forwarded to a first input of a first comparison circuit CCt whose second input receives the outputs a of the address counter CI. When the binary configuration available at the output of the unit CI is equal to the binary configuration available on the output of 80 the unit DS1f the unit CC-i energizes its output e.
Such an event is detected by the means MME which enable the buffer memory MT to store the data available at the output of the memory MD.
When the kinescopic monitor VC sends a data 85 request, the unit MME controls data transmission by way of the means TR and the data are then displayed in the form of characters, thereby making it possible for the operator to effect an easy analysis for spotting possible failures by checking whether the 90 displayed message differs from an expected message.
By means of the circuit arrangement, the operator is able to check on the screen of the kinescopic monitor the course of the content of a message by 95 simulating for example a telephone call and by checking the modifications in the messages due to changes in the state of the telephone connection.
Assuming that, at the instant at which the first messsage is displayed on the first line of the 100 kinescopic monitor, the telephone connection controlled by the telephone translator to which the message relates is in an engagement phase, the memory cycle of the unit MD following the selection of the first digit by the calling user results in the 105 control unit UC writing the selected digit in a predetermined phase of the message RET associated with such a translator. If the operator does not effect any controlling operation, when the count reached in the address counter CI is equal to the 110 location address previously selected by the unit DSi the output e of the unit SIM is energized, and thus the buffer memory is enabled and this message is displayed in such a way that the character corresponding to the first selection digit must be different 115 from the same previously displayed character.
Similarly, after the second digit has been selected the unit UC controls its writing in a phase adajcentto the preceding one and when the above mentioned identity occurs storing and displaying of the relative 120 message are enabled, whereby the operator is able to check whether such second digit has been written and any event is written in a correct way in the data memory, and can diagnose possible failures in the components of the operative system by detecting 125 missing recordings of such events or erroneous recordings.
The circuit arrangement thus makes it possible to follow the processing evolution. The above mentioned logic analysers make it possible instead to 130 analyse one message at a time. The unit SIM is used
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for analysing operative systems in which a rigid association exists between a peripheral unit and memory zones of the unit MD. Whem, instead, the analysis of operative systems is required in which 5 random engagement of the memory zones of the unit MD is provided, a selection unit SUP of the peripheral units belonging to the selection and comparison means MSC is used.
As each peripheral unit is characterised by an ■ 10 address known to the operator and the control unit of the control system writes, when it engages a memory zone, such an address in predetermined phases of the RET (such as the phases 7,8 and 9), the operator selects, by means of a selection device DS2 15 of Figure 4 the address of peripheral unittobe analysed so as to analyse systems which engage randomly memory zones. The unit SUP also comprises a decoding unit DCt which receives on its input the outputs a of the first section of the address 20 counter CI and is arranged to detect the time phases 7,8 and 9 in which the address of the peripheral unit is written.
When the unit DCn detects the beginning of the time phase 7, it energizes its own output, thereby 25 enabling a comparison circuit CC2. The first input of the comparison circuit CC2 receives the binary configuration selected by the unit DS2 and its second input receives the binary configuration available at the output b of the memory MD. When the unit CC2 30 detects identity of the binary configurations at its inputs, it energizes its output f.
Bearing in mind that an entire message is to be displayed and the comparison is not effected at the beginning of the RET, to prevent information from 35 being lost, the memory MT is enabled to store any message. Should the unit CC2 have its outDut f energized, such an event is detected by a i nit SMS which energizes its output g to enable the data storing and reading means MME which are arranged 40 to preserve the message when the signal g is energized, or to cancel it if no energization occurs.
Once the message has been stored, its display occurs in the way previously described.
Energization of the output f is governed by the 45 energization of a signal n, as will be explained below with reference to Figure 8, the signal n being designed to enable a gate circuit P-|.
It is possible to display the course of the processing even when «random-engagement» operative . 50 systems must be analysed, in which case the unit SUP makes it possible to effect a particularly simple and rapid analysis even of systems of the type in , which the operator can easily diagnose failures.
The unit SMS is also arranged to detect the 55 number of memory zones engaged by the same peripheral unit owing to failures. The operator sometimes needs to know the number of memory zones that have been erroneously allocated to a peripheral unit. The addess of the peripheral unit to 60 be analysed is selected by means of the unit SUP which generates an output pulse feach time it detects in the time phase 7,8 and 9 the presence of an address equal to the selected one.
Figure 5 illustrates in detail the unit SMS which 65 comprises a counter CN-i which is designed to count the pulses f available at the output of the unit SUP. A display device DV-i is connected to the unit CNi and enables the operator to read the number of memory zones which are allocated to the peripheral unit whose address has been selected.
The operator can also display on the screen of the kinescopic monitor VC the content of one of more memory zones among those engaged by the same peripheral unit. Assuming that the operator wishes to display the content of the fourth memory zone engaged by the peripheral unit, the unit SMS comprises a selection device DS3 by means of which the operator sets the «four» code in binary code. The binary configuration thus set is applied to the first input of a comparison circuit CC3 whose second input receives a binary configuration available at the output of the counter CN^ When the counted amount in the unit CIS^ is equal to the digit four, the unit CC3 generates a pulse g which is detected by the means MME which controls storing of the message which is supplied to the buffer memory MT at that instant.
The selection and comparison means MSC also comprises a unit SSE designed to select the processing state of the peripheral unit to be analysed. The unit SSE is illustrated in detail in Figure 6.
Sometimes the operator needs to check whether a predetermined peripheral unit during its processing correctly follows a specific predetermined programme. Bearing in mind that the state in which the peripheral units are is stored in predetermined phases of each RET, the unit SSE comprises a decoding unit DC2 which is fed by the outputs a of the first section of the address counter CI and is designed to energize its own output when the unit CI scans such phases.
The operator presets, by means of the selection device of the unit SUP, the address of the peripheral unit to be analysed and also presets, by means of a selection device DS4 of the unit SSE, the address of the processing state to be checked. The binary configuration of the selected state is applied to the first input of a comparison circuit CC4 whose second input receives the outputs b of the memory MD.
When the unit CC4 detects identity between the binary configurations from its inputs, it generates a pulse h which is sent to the means MME which control, if they detect the presence of the pulse gat the output of the unit SMS, storing of the data at the input of the memory MT. The message is then displayed, thereby making it possible for the operator to check whether the peripheral unit in question passes through the state that has been selected.
Figure 7 illustrates in detail the unit CAM arranged to count the memory zones engaged for detecting the engagement rate of the peripheral units, and in this specific case for detecting the telephone traffic.
Bearing in mind that the free or engaged state of a predetermined memory zone is written in a predetermined phase, the unit CAM comprises a decoding unit DC3 which is supplied by the outputs a of the first section of the address counter CI and is designed to energize its own output when the unit CI scans such a phase.
The unit DC3 enables a comparison circuit CC5 to
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energize its own output each time it detects identity between a predetermined binary configuration corresponding to an engaged state of the memory zone and the binary configuration b available at the 5 output of the memory MD. The output of the unit CC5 is connected to a counter CN2 whose content is displayed by a display device DVZ.
Figure 8 shows the message loading unit CM which comprises a key T-i which is actuated by the 10 operator when he wishes to analyse operative systems randomly allocating memory zones to peripheral units.
When one requires analysis of random-allocation operative systems, the key Ti is kept open, and thus 15 when the memory address selection unit SIM energizes its output e, a gate circuit P2 is enabled to being controlled by a signal h by means of a key T2 which is depessed when one message only is to be displayed should the peripheral unit to which the 20 message refers take a predetermined state (by being selected by the unit DS4).
Energization of the output/7 of the unit P2 results in a gate circuit P3 being enabled. The gate circuit P3 then enables, byway of a logic adding circuit S, a 25 gate circuit P4 which generates output pulse CK which, on the output 1 control loading of data corresponding to the output of the memory MD, in the memory MT.
When one wishes to enable data loading only if 30 the peripheral unit to be analysed passes through a predetermined state, the key T2 is closed or depressed, and thus energization of the output n is detected only when the unit SSE generates the signal h.
The signal n is also used to enable the gate circuit 35 P-i and thus, while analysing random-allocation operative systems, it is also possible to obtain that the display of a message concerning the peripheral unit, whose address has been selected by way of the unit DS2, depends on the peripheral unit taking a 40 predetermined state.
When one requires the analysis of random-allocation operative systems, the key ^ is depressed and a gate circuit P5 is enabled, the second input of the circuit P5 being connected to the output of a first 45 bistable circuit FFn which is switched to its ON state by the pulse available at the output g of the unit SMS. The unit P5 also receives the output of a fourth decoding unit DC4 designed to energize this output when the address counter CI counts the phase a 27 50 indicating the end of a message (RET). The unit DC4 is also designed to energize a second output,
thereby causing the unit FFt to be switched to its OFF state when the address counter CI scans the cycle end.
55 Energization of the output of the unit P5 results in a second bistable circuit FF2 being switched to its ON state, the bistable circuit FF2 being switched to its OFF state by a pulse available at the output of a fifth gate circuit P6 which receives at its inputs the 60 outputs of the units FFt and DC4.
Assuming that, at the instant in which the switch or key Ti is closed, the address counter CI is scanning the address of a character preceding the last character of the message, when the unit CI scans 65 the phase a 27, the unit DC4 energizes the first output, thereby enabling the gate circuit P5 which generates an output pulse that by way of the output 12 reaches the memory MT, thereby blanking or cancelling its contents. This pulse also reaches the inputs s of the unit FF2, thereby causing the same to be switched. Consequently, the unit P4 is enabled by means of the unit S and generates output pulses CK which by way of the output ^ control loading or writing of data available at the input of the memory MT.
If the message being stored relates to the peripheral unit whose address has been selected, during the time phases, 7,8 and 9 the unit SUP energizes its output f, thereby energizing the output g of the unit SMS, and thus the unit FFt is switched to enable the gate circuit P6. When the unit DC4 indicates the end of the message being stored, the unit P6 energizes its output, thereby causing the unit FF2to be switched to prevent pulses CKfrom being generated by the gate P4, which results in data writing in the memory MT being terminated to allow data transfer to the unit VC.
Figure 9 illustrates in detail the data generating unit CE of Figure 2 which comprises a monostable circuit MN having a release time longerthan the period of the pulses CK, the circuit MN being fed with pulses CK available at the output 1i of the unit CM. The unit MN has the function of enabling data reading after a time interval equal to its release time, after the last character of the message has been stored. To this end, the output of the unit MN enables a gate circuit P7 which receives from the memory MT a signal 13 which is active when the first character of a given message is received at its input. Energization of the output of the unit P7 enables a gate circuit P8 which receives on a second input a signal d7l which is active when the monitor VC is ready to receive data, and on a third input it receives a signal d2 generated by the kinescopic screen VC and comprising a timing pulse sequence CK’ designed to be used to read the memory MT.
It is possible to substitute other means for the kinescopic monitor, such means being capable of displaying information contained in the buffer memory MT, such as in the form of printed information.

Claims (11)

1. A circuit arrangement for use with a display for receiving data stored in a data memory of an operative system comprising a plurality of peripheral units connected to a control unit which has, besides the data memory which is subdivided into a plurality of memory zones for storing a message formed by a predetermined number of characters, a counter for counting addresses of the data memory, the circuit arrangement comprising:
a buffer memory whose input is arranged to the connected to the output of the data memory;
selection and comparison means whose input is arranged to be connected to the output of the data memory and to the output of the address counter, the selection and comparison means being arranged to enable data storing and reading control means when the data and/or the addresses given by the
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operative system are equal to selected ones;
the data storing and reading control means which is arranged to control storing or blanking of data supplied to the buffer memory in response to the 5 presence or absence of an enabling signal generated by the selection and comparison means, and to control data transmission in response to a control signal by the display;
transcording means arranged to transcode from 10 the code of the data at the output of the buffer memory into the code used by the display; and means for counting the number of engaged memory zones in the data memory.

2. A circuit arranged as claimed in claim 1, in 15 which the selection and comparison means comprises:
a memory address selection unit arranged to receive the output of the address counter and comprising means for selecting the address of the 20 memory area in which data to be displayed are stored, the memory address selection unit being arranged to energize its output when the selected address is equal to that provided by the operative system;
25 a first selection unit arranged to select peripheral units, the first selection unit being arranged to receive the output of the address counter and the output of the data memory and having means for selecting the address of a peripheral unitto be 30 analysed, the first selection unit being arranged to enerigixe its output when data relating to the peripheral unit to be analysed correspond to the output of the data memory;
a second unit for selecting memory zones en-35 gaged by a perpherial unit, connected to the output of the first selection unit, the second selection unit comprising means for counting the number of memory zones engaged by the same peripheral unit and being arranged to energize its output when the 40 content of one of the memory zones corresponds to the output of the data memory; and a third selection unit for selecting the processing state, the third selecting unit being arranged to receive the output of the address counter and the 45 output of the data memory and comprising means for selecting a binary configuration indicating a processing state, the third selecting unit being arranged to energize its output when the output of the data memory corresponds to a binary configura-50 tion indicating a state equal to the selected one.

3. A circuit arrangement as claimed in claim 2, in which the memory address selection unit comprises a first comparison circuit a first input of which is arranged to receive the binary configuration avail-
55 able at the output of the address counter and a second input of which is connected to receive the binary configuration at the output of a first selection device.

4. A circuit arrangement as claimed in claim 2 or 60 3, in which the first selection unit comprises a first decoding unit arranged to enable a second comparison circuit when the address counter scans time phases in which the address of the peripheral units is stored, and a second comparison circuit having a 65 first input arranged to receive the binary configuration at the output of the data memory and a second input connected to receive the binary configuration available at the output of a second selection device, the output of the second comparison circuit being connected to a first gate circuit arranged to be enabled by the data storing and reading control means.

5. A circuit arrangement as claimed in any one of claims 2 to 4, in which the second selection unit comprises a first counter whose output is connected to a first display device and to a first input of a third comparison circuit whose second input is connected to receive the binary configuration at the output of a third selection device.

6. A circuit arrangement as claimed in any one of claims 2 to 5, in which the third selection unit comprises a second decoding unit arranged to enable a fourth comparison circuit when the address counter scans a time phase storing the current state of an associated peripheral unit, a first input of the fourth comparison circuit being arranged to receive the-binary configuration at the output of the data memory and a second input of the fourth comparison circuit being connected to receive the binary configuration at the output of a fourth selection device.

7. A circuit arrangement as claimed in any one of the preceding claims, in which the means for counting the number of engaged memory zones comprises a third decoding unit arranged to enable a fifth comparison circuit when the address counter scans a time phase in which the state of the memory zone is stored, a first input of a fifth comparison circuit being arranged to receive the binary configuration available at the output of the data memory and a second input of the fifth comparison circuit being arranged to receive a binary configuration indicating an «engaged» state, a second counter being arranged to receive pulses from the output of the fifth comparison circuit and having an output connected to a second display device.

8. A circuit arrangement as claimed in any one of the preceding claims, in which the data storing and reading control means comprises a unit arranged to control data storing and having a second gate circuit controlled by an inverted signal at the output of the third selection unit by means of a first key and a signal at the output of the memory address selection unit, the second gate circuit being arranged to enable a third gate circuit which is controlled by means of a second key the output of the third gate circuit, when energized serving to enable a fourth gate circuit which is connected to receive a timing pulse sequence from the address counter of the data memory, the unit further comprising a fifth gate circuit arranged to be controlled by a signal at the output of the second selection unit via afirst bistable circuit, by the second key, and by the signal at the output of a fourth decoding unit arranged to detect the last time phase of each message, the fifth gate circuit being arranged to generate an output pulse for blanking the buffer memory and for switching a second bistable circuit to its ON state, the output of the second bistable circuit being arranged to enable the fourth gate circuit, the second bistable circuit
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being arranged to be switched to its OFF state by a signal at the output of a sixth gate circuit which is arranged to be controlled by the fourth decoding j unit and the first bistable circuit.
5

9. A circuit arrangement as claimed in claim 8, in which the data storing and reading control means comprises a further unit arranged to control reading of data stored in the buffer memory and comprising a monostable circuit connected to receive a signal at 10 the output of the fourth gate circuit and having a release time longer than the period of the timing pulses, the monostable circuit being arranged to enable a seventh gate circuit whose second input is connected to receive a signal which is active when a 15 first character is present in the buffer memory the output of the seventh gate circuit being arranged to enable an eighth gate circuit whose second and third inputs are arranged to receive a control pulse generated by the display when it is available to 20 receive data and a further sequence of timing pulses.

10. A circuit arrangement substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

11. A combination of a circuit arrangement, as 25 claimed in anyone of the preceding claims, connected to an operative system and a display.
Printed for Her Majesty’s Stationery Office by Croydon Printing Company Limited, Croydon Surrey, 1980.
Published by the Patent Office, 25 Southampton Buildings, London, WC2A1 AY,
from which copies may be obtained.

GB7929820A
1978-08-29
1979-08-28
Circuit arrangement for withdrawing data stored in system data memories for diagnostic purposes

Expired

GB2031195B
(en)

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Priority Date
Filing Date
Title

IT7827086A

IT7827086D0
(en)

1978-08-29
1978-08-29

CIRCUIT ARRANGEMENT FOR THE COLLECTION OF DATA CONTAINED IN THE DATA MEMORY OF OPERATING SYSTEMS.

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GB2031195A
true

GB2031195A
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1980-04-16

GB2031195B

GB2031195B
(en)

1982-08-11

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GB7929820A
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GB2031195B
(en)

1978-08-29
1979-08-28
Circuit arrangement for withdrawing data stored in system data memories for diagnostic purposes

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US4314328A
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BR7905474A
(en)

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DE2934959C2
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ES
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ES483241A1
(en)

FR
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FR2435089A1
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GB
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GB2031195B
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US5088025A
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1989-02-21
1992-02-11
Unisys Corporation
Input/output processor control system with a plurality of staging buffers and data buffers

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Circuit arrangement for telecommunication switching systems, in particular telephone switching systems with operating status memories and playback devices

1978

1978-08-29
IT
IT7827086A
patent/IT7827086D0/en
unknown

1979

1979-08-08
ES
ES483241A
patent/ES483241A1/en
not_active
Expired

1979-08-20
FR
FR7920951A
patent/FR2435089A1/en
not_active
Withdrawn

1979-08-27
US
US06/070,035
patent/US4314328A/en
not_active
Expired – Lifetime

1979-08-27
BR
BR7905474A
patent/BR7905474A/en
unknown

1979-08-28
GB
GB7929820A
patent/GB2031195B/en
not_active
Expired

1979-08-29
DE
DE2934959A
patent/DE2934959C2/en
not_active
Expired

Also Published As

Publication number
Publication date

ES483241A1
(en)

1980-04-01

GB2031195B
(en)

1982-08-11

DE2934959A1
(en)

1980-03-13

DE2934959C2
(en)

1982-01-28

US4314328A
(en)

1982-02-02

BR7905474A
(en)

1980-05-20

IT7827086D0
(en)

1978-08-29

FR2435089A1
(en)

1980-03-28

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