AU2063097A – Method of encapsulating a semiconductor package
– Google Patents
AU2063097A – Method of encapsulating a semiconductor package
– Google Patents
Method of encapsulating a semiconductor package
Info
Publication number
AU2063097A
AU2063097A
AU20630/97A
AU2063097A
AU2063097A
AU 2063097 A
AU2063097 A
AU 2063097A
AU 20630/97 A
AU20630/97 A
AU 20630/97A
AU 2063097 A
AU2063097 A
AU 2063097A
AU 2063097 A
AU2063097 A
AU 2063097A
Authority
AU
Australia
Prior art keywords
encapsulating
semiconductor package
package
semiconductor
Prior art date
1996-03-07
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU20630/97A
Inventor
Thomas H Distefano
Joseph Fjelstad
Konstantine Karavakis
Craig S. Mitchell
John W Smith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Solutions LLC
Original Assignee
Tessera LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1996-03-07
Filing date
1997-03-04
Publication date
1997-09-22
1996-03-07
Priority claimed from US08/610,610
external-priority
patent/US5834339A/en
1997-03-04
Application filed by Tessera LLC
filed
Critical
Tessera LLC
1997-09-22
Publication of AU2063097A
publication
Critical
patent/AU2063097A/en
Status
Abandoned
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 – H01L21/326, e.g. sealing of a cap to a base of a container
H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
H01L21/568—Temporary substrate used as encapsulation process aid
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 – H01L21/326, e.g. sealing of a cap to a base of a container
H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 – H01L21/326, e.g. sealing of a cap to a base of a container
H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
H01L21/565—Moulds
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L23/00—Details of semiconductor or other solid state devices
H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L23/00—Details of semiconductor or other solid state devices
H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L23/00—Details of semiconductor or other solid state devices
H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L23/00—Details of semiconductor or other solid state devices
H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
H01L23/495—Lead-frames or other flat leads
H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, «first-level» interconnects; Manufacturing methods related thereto
H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, «first-level» interconnects; Manufacturing methods related thereto
H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
H01L24/93—Batch processes
H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, «first-level» interconnects; Manufacturing methods related thereto
H01L2224/10—Bump connectors; Manufacturing methods related thereto
H01L2224/11—Manufacturing methods
H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, «first-level» interconnects; Manufacturing methods related thereto
H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 – H01L2224/90
H01L2224/92—Specific sequence of method steps
H01L2224/921—Connecting a surface with connectors of different types
H01L2224/9212—Sequential connecting processes
H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
H01L2224/93—Batch processes
H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/01—Chemical elements
H01L2924/01015—Phosphorus [P]
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/01—Chemical elements
H01L2924/01033—Arsenic [As]
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/01—Chemical elements
H01L2924/01047—Silver [Ag]
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/01—Chemical elements
H01L2924/01058—Cerium [Ce]
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/01—Chemical elements
H01L2924/01082—Lead [Pb]
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/013—Alloys
H01L2924/0132—Binary Alloys
H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/10—Details of semiconductor or other solid state devices to be connected
H01L2924/11—Device type
H01L2924/12—Passive devices, e.g. 2 terminal devices
H01L2924/1204—Optical Diode
H01L2924/12042—LASER
AU20630/97A
1996-03-07
1997-03-04
Method of encapsulating a semiconductor package
Abandoned
AU2063097A
(en)
Applications Claiming Priority (5)
Application Number
Priority Date
Filing Date
Title
US08/610,610
US5834339A
(en)
1996-03-07
1996-03-07
Methods for providing void-free layers for semiconductor assemblies
US08610610
1996-03-07
US08726697
1996-10-07
US08/726,697
US5776796A
(en)
1994-05-19
1996-10-07
Method of encapsulating a semiconductor package
PCT/US1997/003273
WO1997033312A1
(en)
1996-03-07
1997-03-04
Method of encapsulating a semiconductor package
Publications (1)
Publication Number
Publication Date
AU2063097A
true
AU2063097A
(en)
1997-09-22
Family
ID=27086294
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
AU20630/97A
Abandoned
AU2063097A
(en)
1996-03-07
1997-03-04
Method of encapsulating a semiconductor package
Country Status (3)
Country
Link
US
(1)
US5776796A
(en)
AU
(1)
AU2063097A
(en)
WO
(1)
WO1997033312A1
(en)
Families Citing this family (78)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
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Tessera, Inc.
Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
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Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
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Framed sheet processing
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Semiconductor device and manufacturing method thereof
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Semiconductor device, method for manufacturing the same, circuit board, and flexible substrate
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Packaged microelectronic elements with enhanced thermal conduction
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Method of encapsulating a microelectronic assembly utilizing a barrier
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Texas Instruments Incorporated
Quencher clamping operation using an electromagnet
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Seiko Epson Corporation
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Methods of encapsulating a semiconductor chip using a settable encapsulant
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Sony Corp
Semiconductor device and electronic parts
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1998-03-23
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Seiko Epson Corporation
Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
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1998-04-22
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Adhesive and encapsulating material with fluxing properties
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Intel Corporation
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Alphasem AG
Method and apparatus for encapsulating an electronic device, especially a semiconductor chip
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1999-02-22
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Univ Dresden Tech
Electronic and/or optical component mounting method for rear side of flexible printed circuit board has molded material used for encasing components on front side of circuit board before inversion of latter
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Method of coating semiconductor wafer with resin and mold used therefor
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1999-07-28
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1999-08-20
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Texas Instruments Incorporated
Method of encapsulating thin semiconductor chip-scale packages
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Intel Corporation
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1999-09-22
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Texas Instruments Incorporated
Direct attachment of semiconductor chip to organic substrate
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Tessera, Inc.
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1999-11-30
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Samsung Electronics Co Ltd
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2000-03-28
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2001-02-22
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Nec Corp
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Megica Corporation
Structure and manufacturing method of chip scale package
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2001-05-22
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日立電線株式会社
Manufacturing method of semiconductor device
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2001-06-13
2002-04-11
Walsin Advanced Electronics
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2001-10-26
2003-04-03
Univ Dresden Tech
Rear-sided surface mounting method for flexible circuit board components uses pins of pin plate for supporting circuit board with rear side facing upwards
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2001-10-31
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Hewlett-Packard Development Company, L.P.
Methods and systems for forming a die package
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patent/AU2063097A/en
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1998-07-07
WO1997033312A1
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1997-09-12
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