AU4382672A – Phase locked loop
– Google Patents
AU4382672A – Phase locked loop
– Google Patents
Phase locked loop
Info
Publication number
AU4382672A
AU4382672A
AU43826/72A
AU4382672A
AU4382672A
AU 4382672 A
AU4382672 A
AU 4382672A
AU 43826/72 A
AU43826/72 A
AU 43826/72A
AU 4382672 A
AU4382672 A
AU 4382672A
AU 4382672 A
AU4382672 A
AU 4382672A
Authority
AU
Australia
Prior art keywords
locked loop
phase locked
phase
loop
locked
Prior art date
1971-07-29
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
AU43826/72A
Other versions
AU470507B2
(en
Inventor
BERNHARD MADER and ROGER MAURICE HOCHREUTINER HEINZ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Services Ltd
Original Assignee
Standard Telephone and Cables Pty Ltd
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1971-07-29
Filing date
1972-06-23
Publication date
1974-01-03
1972-06-23
Application filed by Standard Telephone and Cables Pty Ltd, Standard Telephone and Cables PLC
filed
Critical
Standard Telephone and Cables Pty Ltd
1974-01-03
Publication of AU4382672A
publication
Critical
patent/AU4382672A/en
1976-03-18
Application granted
granted
Critical
1976-03-18
Publication of AU470507B2
publication
Critical
patent/AU470507B2/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
H—ELECTRICITY
H04—ELECTRIC COMMUNICATION TECHNIQUE
H04J—MULTIPLEX COMMUNICATION
H04J3/00—Time-division multiplex systems
H04J3/02—Details
H04J3/06—Synchronising arrangements
H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
H04J3/073—Bit stuffing, e.g. PDH
AU43826/72A
1971-07-29
1972-06-23
Phase locked loop
Expired
AU470507B2
(en)
Applications Claiming Priority (2)
Application Number
Priority Date
Filing Date
Title
GB3564771
1971-07-29
GBGB35647/71
1971-07-29
Publications (2)
Publication Number
Publication Date
AU4382672A
true
AU4382672A
(en)
1974-01-03
AU470507B2
AU470507B2
(en)
1976-03-18
Family
ID=10380048
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
AU43826/72A
Expired
AU470507B2
(en)
1971-07-29
1972-06-23
Phase locked loop
Country Status (8)
Country
Link
US
(1)
US3731219A
(en)
AU
(1)
AU470507B2
(en)
BE
(1)
BE786798A
(en)
CH
(1)
CH551119A
(en)
DE
(1)
DE2236265A1
(en)
FR
(1)
FR2147696A5
(en)
GB
(1)
GB1348546A
(en)
IT
(1)
IT962963B
(en)
Families Citing this family (15)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
JPS4999260A
(en)
*
1973-01-26
1974-09-19
US4075577A
(en)
*
1974-12-30
1978-02-21
International Business Machines Corporation
Analog-to-digital conversion apparatus
US4354164A
(en)
*
1979-09-27
1982-10-12
Communications Satellite Corporation
Digital phase lock loop for TIM frequency
US4308619A
(en)
*
1979-12-26
1981-12-29
General Electric Company
Apparatus and methods for synchronizing a digital receiver
US4820994A
(en)
*
1986-10-20
1989-04-11
Siemens Aktiengesellschaft
Phase regulating circuit
AR242878A1
(en)
*
1986-11-27
1993-05-31
Siemens Ag
Method and circuit for the recovery of the clock and/or the phase of a synchronous or plesiochronous data signal
WO1990006017A1
(en)
*
1988-11-07
1990-05-31
Level One Communications, Inc.
Frequency multiplier with non-integer feedback divider
US5059924A
(en)
*
1988-11-07
1991-10-22
Level One Communications, Inc.
Clock adapter using a phase locked loop configured as a frequency multiplier with a non-integer feedback divider
US5077529A
(en)
*
1989-07-19
1991-12-31
Level One Communications, Inc.
Wide bandwidth digital phase locked loop with reduced low frequency intrinsic jitter
US5068628A
(en)
*
1990-11-13
1991-11-26
Level One Communications, Inc.
Digitally controlled timing recovery loop
JP2639315B2
(en)
*
1993-09-22
1997-08-13
日本電気株式会社
PLL circuit
US5493243A
(en)
*
1994-01-04
1996-02-20
Level One Communications, Inc.
Digitally controlled first order jitter attentuator using a digital frequency synthesizer
KR100207656B1
(en)
*
1996-02-08
1999-07-15
윤종용
Compensation of digital phase locked loop
GB9606114D0
(en)
*
1996-03-22
1996-05-22
Digi Media Vision Ltd
Improvements in or relating to digital satellite receivers
US6249557B1
(en)
1997-03-04
2001-06-19
Level One Communications, Inc.
Apparatus and method for performing timing recovery
Family Cites Families (1)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3502976A
(en)
*
1966-12-30
1970-03-24
Texas Instruments Inc
Method and system for measuring and indicating the frequency and phase differences between a plurality of precision frequency sources
0
BE
BE786798D
patent/BE786798A/en
unknown
1971
1971-07-29
GB
GB3564771A
patent/GB1348546A/en
not_active
Expired
1972
1972-06-13
US
US00262402A
patent/US3731219A/en
not_active
Expired – Lifetime
1972-06-23
AU
AU43826/72A
patent/AU470507B2/en
not_active
Expired
1972-07-19
IT
IT27136/72A
patent/IT962963B/en
active
1972-07-24
DE
DE2236265A
patent/DE2236265A1/en
active
Pending
1972-07-25
CH
CH1109572A
patent/CH551119A/en
not_active
IP Right Cessation
1972-07-27
FR
FR7227017A
patent/FR2147696A5/fr
not_active
Expired
Also Published As
Publication number
Publication date
BE786798A
(en)
1973-01-29
IT962963B
(en)
1973-12-31
AU470507B2
(en)
1976-03-18
FR2147696A5
(en)
1973-03-09
US3731219A
(en)
1973-05-01
GB1348546A
(en)
1974-03-20
CH551119A
(en)
1974-06-28
DE2236265A1
(en)
1973-02-08
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None