AU2063097A - Creation of Inventions and Patents with Artificial Intelligence

AU2063097A – Method of encapsulating a semiconductor package
– Google Patents

AU2063097A – Method of encapsulating a semiconductor package
– Google Patents
Method of encapsulating a semiconductor package

Info

Publication number
AU2063097A

AU2063097A
AU20630/97A
AU2063097A
AU2063097A
AU 2063097 A
AU2063097 A
AU 2063097A
AU 20630/97 A
AU20630/97 A
AU 20630/97A
AU 2063097 A
AU2063097 A
AU 2063097A
AU 2063097 A
AU2063097 A
AU 2063097A
Authority
AU
Australia
Prior art keywords
encapsulating
semiconductor package
package
semiconductor
Prior art date
1996-03-07
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Abandoned

Application number
AU20630/97A
Inventor
Thomas H Distefano
Joseph Fjelstad
Konstantine Karavakis
Craig S. Mitchell
John W Smith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Adeia Semiconductor Solutions LLC

Original Assignee
Tessera LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1996-03-07
Filing date
1997-03-04
Publication date
1997-09-22

1996-03-07
Priority claimed from US08/610,610
external-priority
patent/US5834339A/en

1997-03-04
Application filed by Tessera LLC
filed
Critical
Tessera LLC

1997-09-22
Publication of AU2063097A
publication
Critical
patent/AU2063097A/en

Status
Abandoned
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

Classifications

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer

H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 – H01L21/326, e.g. sealing of a cap to a base of a container

H01L21/56—Encapsulations, e.g. encapsulation layers, coatings

H01L21/568—Temporary substrate used as encapsulation process aid

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 – H01L21/326, e.g. sealing of a cap to a base of a container

H01L21/56—Encapsulations, e.g. encapsulation layers, coatings

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 – H01L21/326, e.g. sealing of a cap to a base of a container

H01L21/56—Encapsulations, e.g. encapsulation layers, coatings

H01L21/565—Moulds

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere

H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping

H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L23/00—Details of semiconductor or other solid state devices

H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings

H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device

H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L23/00—Details of semiconductor or other solid state devices

H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection

H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape

H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L23/00—Details of semiconductor or other solid state devices

H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection

H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape

H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed

H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L23/00—Details of semiconductor or other solid state devices

H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor

H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions

H01L23/495—Lead-frames or other flat leads

H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto

H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, “first-level” interconnects; Manufacturing methods related thereto

H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto

H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process

H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto

H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto

H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected

H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto

H01L24/93—Batch processes

H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips

H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, “first-level” interconnects; Manufacturing methods related thereto

H01L2224/10—Bump connectors; Manufacturing methods related thereto

H01L2224/11—Manufacturing methods

H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate

H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto

H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected

H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus

H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 – H01L2224/90

H01L2224/92—Specific sequence of method steps

H01L2224/921—Connecting a surface with connectors of different types

H01L2224/9212—Sequential connecting processes

H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector

H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/93—Batch processes

H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips

H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/01—Chemical elements

H01L2924/01015—Phosphorus [P]

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/01—Chemical elements

H01L2924/01033—Arsenic [As]

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/01—Chemical elements

H01L2924/01047—Silver [Ag]

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/01—Chemical elements

H01L2924/01058—Cerium [Ce]

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/01—Chemical elements

H01L2924/01082—Lead [Pb]

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/013—Alloys

H01L2924/0132—Binary Alloys

H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/10—Details of semiconductor or other solid state devices to be connected

H01L2924/11—Device type

H01L2924/12—Passive devices, e.g. 2 terminal devices

H01L2924/1204—Optical Diode

H01L2924/12042—LASER

AU20630/97A
1996-03-07
1997-03-04
Method of encapsulating a semiconductor package

Abandoned

AU2063097A
(en)

Applications Claiming Priority (5)

Application Number
Priority Date
Filing Date
Title

US08/610,610

US5834339A
(en)

1996-03-07
1996-03-07
Methods for providing void-free layers for semiconductor assemblies

US08610610

1996-03-07

US08726697

1996-10-07

US08/726,697

US5776796A
(en)

1994-05-19
1996-10-07
Method of encapsulating a semiconductor package

PCT/US1997/003273

WO1997033312A1
(en)

1996-03-07
1997-03-04
Method of encapsulating a semiconductor package

Publications (1)

Publication Number
Publication Date

AU2063097A
true

AU2063097A
(en)

1997-09-22

Family
ID=27086294
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

AU20630/97A
Abandoned

AU2063097A
(en)

1996-03-07
1997-03-04
Method of encapsulating a semiconductor package

Country Status (3)

Country
Link

US
(1)

US5776796A
(en)

AU
(1)

AU2063097A
(en)

WO
(1)

WO1997033312A1
(en)

Families Citing this family (78)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US6232152B1
(en)

1994-05-19
2001-05-15
Tessera, Inc.
Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures

US6359335B1
(en)

1994-05-19
2002-03-19
Tessera, Inc.
Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures

US5688716A
(en)

1994-07-07
1997-11-18
Tessera, Inc.
Fan-out semiconductor chip assembly

US6228685B1
(en)

1994-07-07
2001-05-08
Tessera, Inc.
Framed sheet processing

US6541852B2
(en)

1994-07-07
2003-04-01
Tessera, Inc.
Framed sheets

JP2891665B2
(en)

1996-03-22
1999-05-17
株式会社日立製作所

Semiconductor integrated circuit device and method of manufacturing the same

US20040061220A1
(en)

1996-03-22
2004-04-01
Chuichi Miyazaki
Semiconductor device and manufacturing method thereof

KR100616479B1
(en)

1996-10-17
2006-08-28
세이코 엡슨 가부시키가이샤
Semiconductor device, method for manufacturing the same, circuit board, and flexible substrate

US6127724A
(en)

1996-10-31
2000-10-03
Tessera, Inc.
Packaged microelectronic elements with enhanced thermal conduction

US6130116A
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1996-12-13
2000-10-10
Tessera, Inc.
Method of encapsulating a microelectronic assembly utilizing a barrier

US5950069A
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1997-02-27
1999-09-07
Texas Instruments Incorporated
Quencher clamping operation using an electromagnet

EP0913866B1
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1997-03-10
2005-07-20
Seiko Epson Corporation
Semiconductor Device and Circuit Board Having the Same Mounted Thereon

US6080605A
(en)

1998-10-06
2000-06-27
Tessera, Inc.
Methods of encapsulating a semiconductor chip using a settable encapsulant

US6217972B1
(en)

1997-10-17
2001-04-17
Tessera, Inc.
Enhancements in framed sheet processing

JPH11186462A
(en)

1997-12-19
1999-07-09
Sony Corp
Semiconductor device and electronic parts

KR100247463B1
(en)

1998-01-08
2000-03-15
윤종용
Method for manufacturing semiconductor integrated circuit device having elastomer

US6333565B1
(en)

1998-03-23
2001-12-25
Seiko Epson Corporation
Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument

AU3617999A
(en)

1998-04-22
1999-11-08
Hugh Patrick Craig
Adhesive and encapsulating material with fluxing properties

JP3063846B2
(en)

1998-04-28
2000-07-12
日本電気株式会社

Semiconductor device

US6300231B1
(en)

1998-05-29
2001-10-09
Tessera Inc.
Method for creating a die shrink insensitive semiconductor package and component therefor

KR100266693B1
(en)

1998-05-30
2000-09-15
김영환
Stackable ball grid array semiconductor package and fabrication method thereof

WO2000008685A1
(en)

1998-08-03
2000-02-17
Shinko Electric Industries Co., Ltd.
Wiring substrate, method of manufacture thereof, and semiconductor device

US6100114A
(en)

1998-08-10
2000-08-08
International Business Machines Corporation
Encapsulation of solder bumps and solder connections

US6655022B1
(en)

1998-09-24
2003-12-02
Intel Corporation
Implementing micro BGA assembly techniques for small die

SG87769A1
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1998-09-29
2002-04-16
Texas Instr Singapore Pte Ltd
Direct attachment of semiconductor chip to organic substrate

US6429530B1
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1998-11-02
2002-08-06
International Business Machines Corporation
Miniaturized chip scale ball grid array semiconductor package

US8021976B2
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2002-10-15
2011-09-20
Megica Corporation
Method of wire bonding over active area of a semiconductor circuit

US6455354B1
(en)

1998-12-30
2002-09-24
Micron Technology, Inc.
Method of fabricating tape attachment chip-on-board assemblies

EP1018760A1
(en)

1999-01-07
2000-07-12
Alphasem AG
Method and apparatus for encapsulating an electronic device, especially a semiconductor chip

DE19907295C1
(en)

1999-02-22
2001-02-08
Univ Dresden Tech
Electronic and/or optical component mounting method for rear side of flexible printed circuit board has molded material used for encasing components on front side of circuit board before inversion of latter

US6294825B1
(en)

1999-02-22
2001-09-25
Micron Technology, Inc.
Asymmetrical mold of multiple-part matrixes

SG92685A1
(en)

1999-03-10
2002-11-19
Towa Corp
Method of coating semiconductor wafer with resin and mold used therefor

US6543131B1
(en)

1999-03-10
2003-04-08
Tessera, Inc.
Microelectronic joining processes with temporary securement

JP2001102486A
(en)

1999-07-28
2001-04-13
Seiko Epson Corp
Substrate for semiconductor device, semiconductor-chip mounting substrate, semiconductor device, their manufacturing method, circuit board and electronic device

US6544816B1
(en)

1999-08-20
2003-04-08
Texas Instruments Incorporated
Method of encapsulating thin semiconductor chip-scale packages

US6472295B1
(en)

1999-08-27
2002-10-29
Jmar Research, Inc.
Method and apparatus for laser ablation of a target material

US6489557B2
(en)

1999-08-30
2002-12-03
Intel Corporation
Implementing micro BGA™ assembly techniques for small die

EP1085566A1
(en)

1999-09-16
2001-03-21
“3P” Licensing B.V.
Method and apparatus for partially encapsulating semiconductor chips

US7042070B2
(en)

1999-09-22
2006-05-09
Texas Instruments Incorporated
Direct attachment of semiconductor chip to organic substrate

US6602740B1
(en)

1999-11-24
2003-08-05
Tessera, Inc.
Encapsulation of microelectronic assemblies

TWI228616B
(en)

1999-11-30
2005-03-01
Samsung Electronics Co Ltd
Liquid crystal display device

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1999-12-20
2002-08-27
Ericsson Telefon Ab L M

Polymer gel electrolyte, polymer battery cell with polymer electrolyte and use of polymer gel electrolyte and polymer battery cell

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2000-03-28
2009-03-18
株式会社日立製作所

Manufacturing method of electronic device

US6531333B2
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2000-04-05
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Hong-Ming Lin
Chip photoelectric sensor assembly and method for making same

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Mcom Solutions Inc
Circuit board arrangement and funds transaction device

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2000-09-29
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Tessera, Inc.
Methods of making microelectronic packages

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2000-10-20
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Lightwave Microsystems
Apparatus and method to dice integrated circuits from a wafer using a pressurized jet

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2000-11-15
2002-05-16
Signey Ferdinand S.
Method and system for cutting integrated circuit packages

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2001-01-10
2004-05-11
Tim Schnell
Motion detector camera

JP2002250826A
(en)

2001-02-22
2002-09-06
Nec Corp
Chip, manufacturing method for the same and chip storing module

US7498196B2
(en)

2001-03-30
2009-03-03
Megica Corporation
Structure and manufacturing method of chip scale package

JP4103342B2
(en)

2001-05-22
2008-06-18
日立電線株式会社

Manufacturing method of semiconductor device

TW483134B
(en)

2001-06-13
2002-04-11
Walsin Advanced Electronics
Micro BGA package

DE10152330C1
(en)

2001-10-26
2003-04-03
Univ Dresden Tech
Rear-sided surface mounting method for flexible circuit board components uses pins of pin plate for supporting circuit board with rear side facing upwards

US6698092B2
(en)

2001-10-31
2004-03-02
Hewlett-Packard Development Company, L.P.
Methods and systems for forming a die package

TW544882B
(en)

2001-12-31
2003-08-01
Megic Corp
Chip package structure and process thereof

TW584950B
(en)

2001-12-31
2004-04-21
Megic Corp
Chip packaging structure and process thereof

US6673698B1
(en)

2002-01-19
2004-01-06
Megic Corporation
Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers

TW517361B
(en)

2001-12-31
2003-01-11
Megic Corp
Chip package structure and its manufacture process

TW503496B
(en)

2001-12-31
2002-09-21
Megic Corp
Chip packaging structure and manufacturing process of the same

US6873039B2
(en)

2002-06-27
2005-03-29
Tessera, Inc.
Methods of making microelectronic packages including electrically and/or thermally conductive element

US20040009628A1
(en)

2002-07-10
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Application Filing

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Publication number
Publication date

US5776796A
(en)

1998-07-07

WO1997033312A1
(en)

1997-09-12

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