AU4990679A – Improved i/o interrupt sequencing
– Google Patents
AU4990679A – Improved i/o interrupt sequencing
– Google Patents
Improved i/o interrupt sequencing
Info
Publication number
AU4990679A
AU4990679A
AU49906/79A
AU4990679A
AU4990679A
AU 4990679 A
AU4990679 A
AU 4990679A
AU 49906/79 A
AU49906/79 A
AU 49906/79A
AU 4990679 A
AU4990679 A
AU 4990679A
AU 4990679 A
AU4990679 A
AU 4990679A
Authority
AU
Australia
Prior art keywords
improved
sequencing
interrupt
interrupt sequencing
Prior art date
1978-10-02
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
AU49906/79A
Other versions
AU531595B2
(en
Inventor
Robert Lowell Adams Jr.
Carl Henry Grant
Karl Wayhe Stevens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1978-10-02
Filing date
1979-08-14
Publication date
1980-04-17
1979-08-14
Application filed by International Business Machines Corp
filed
Critical
International Business Machines Corp
1980-04-17
Publication of AU4990679A
publication
Critical
patent/AU4990679A/en
1983-09-01
Application granted
granted
Critical
1983-09-01
Publication of AU531595B2
publication
Critical
patent/AU531595B2/en
1999-08-14
Anticipated expiration
legal-status
Critical
Status
Ceased
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F13/14—Handling requests for interconnection or transfer
G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
AU49906/79A
1978-10-02
1979-08-14
Improved i/o interrupt sequencing
Ceased
AU531595B2
(en)
Applications Claiming Priority (2)
Application Number
Priority Date
Filing Date
Title
US948070
1978-10-02
US05/948,070
US4275440A
(en)
1978-10-02
1978-10-02
I/O Interrupt sequencing for real time and burst mode devices
Publications (2)
Publication Number
Publication Date
AU4990679A
true
AU4990679A
(en)
1980-04-17
AU531595B2
AU531595B2
(en)
1983-09-01
Family
ID=25487213
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
AU49906/79A
Ceased
AU531595B2
(en)
1978-10-02
1979-08-14
Improved i/o interrupt sequencing
Country Status (8)
Country
Link
US
(1)
US4275440A
(en)
EP
(1)
EP0009678B1
(en)
JP
(1)
JPS5847050B2
(en)
AU
(1)
AU531595B2
(en)
BR
(1)
BR7906341A
(en)
CA
(1)
CA1115850A
(en)
DE
(1)
DE2964214D1
(en)
ES
(1)
ES484505A1
(en)
Families Citing this family (50)
* Cited by examiner, † Cited by third party
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Priority date
Publication date
Assignee
Title
JPS57113162A
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1980-12-29
1982-07-14
Fujitsu Ltd
High-speed external storage device
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1981-12-17
1985-12-10
Honeywell Information Systems Inc.
Pause apparatus for a memory controller with interleaved queuing apparatus
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1983-08-18
1986-09-09
Pitney Bowes Inc.
Bus grant circuit
FR2551236B1
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1983-08-30
1990-07-06
Canon Kk
IMAGE PROCESSING SYSTEM
US4636944A
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*
1984-01-17
1987-01-13
Concurrent Computer Corporation
Multi-level priority micro-interrupt controller
JPH0690700B2
(en)
*
1984-05-31
1994-11-14
富士通株式会社
Semiconductor integrated circuit
US4713751A
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*
1984-10-24
1987-12-15
International Business Machines Corporation
Masking commands for a second processor when a first processor requires a flushing operation in a multiprocessor system
US4701845A
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*
1984-10-25
1987-10-20
Unisys Corporation
User interface processor for computer network with maintenance and programmable interrupt capability
US4779187A
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1985-04-10
1988-10-18
Microsoft Corporation
Method and operating system for executing programs in a multi-mode microprocessor
US4837677A
(en)
*
1985-06-14
1989-06-06
International Business Machines Corporation
Multiple port service expansion adapter for a communications controller
US4716523A
(en)
*
1985-06-14
1987-12-29
International Business Machines Corporation
Multiple port integrated DMA and interrupt controller and arbitrator
US4751634A
(en)
*
1985-06-14
1988-06-14
International Business Machines Corporation
Multiple port communications adapter apparatus
US4779195A
(en)
*
1985-06-28
1988-10-18
Hewlett-Packard Company
Interrupt system using masking register in processor for selectively establishing device eligibility to interrupt a particular processor
US4724520A
(en)
*
1985-07-01
1988-02-09
United Technologies Corporation
Modular multiport data hub
US4719569A
(en)
*
1985-10-11
1988-01-12
Sun Microsystems, Inc.
Arbitrator for allocating access to data processing resources
DE3782335T2
(en)
*
1987-04-22
1993-05-06
Ibm
MEMORY CONTROL SYSTEM.
JP2539021B2
(en)
*
1987-05-01
1996-10-02
ディジタル イクイプメント コーポレーション
Interrupt request generation node that sends an interrupt request to the pending bus
US4953072A
(en)
*
1987-05-01
1990-08-28
Digital Equipment Corporation
Node for servicing interrupt request messages on a pended bus
JPH01258163A
(en)
*
1988-04-08
1989-10-16
Fujitsu Ltd
Direct memory access controller
JPH01277928A
(en)
*
1988-04-30
1989-11-08
Oki Electric Ind Co Ltd
Printer
US5029124A
(en)
*
1988-05-17
1991-07-02
Digital Equipment Corporation
Method and apparatus for providing high speed parallel transfer of bursts of data
CA2066440A1
(en)
*
1989-09-08
1991-03-09
Daryl D. Starr
Vmebus protocol utilizing pseudosynchronous handshaking and block mode data transfer
US5379381A
(en)
*
1991-08-12
1995-01-03
Stratus Computer, Inc.
System using separate transfer circuits for performing different transfer operations respectively and scanning I/O devices status upon absence of both operations
JP2519860B2
(en)
*
1991-09-16
1996-07-31
インターナショナル・ビジネス・マシーンズ・コーポレイション
Burst data transfer apparatus and method
US5319753A
(en)
*
1992-09-29
1994-06-07
Zilog, Inc.
Queued interrupt mechanism with supplementary command/status/message information
AU700863B2
(en)
*
1993-02-11
1999-01-14
National Digital Electronics, Inc.
Telemetry and control system
JPH0713772A
(en)
*
1993-06-29
1995-01-17
Mitsubishi Electric Corp
Data processor
EP0732658B1
(en)
*
1995-03-13
2000-09-27
Sun Microsystems, Inc.
Virtual input/output processor
KR100197646B1
(en)
*
1995-05-15
1999-06-15
김영환
Burst mode termination detection apparatus
JP2792501B2
(en)
*
1996-02-28
1998-09-03
日本電気株式会社
Data transfer method and data transfer method
FR2759177B1
(en)
*
1997-01-31
1999-04-23
Sextant Avionique
PROCESS AND DEVICE FOR PROCESSING MULTIPLE TECHNICAL APPLICATIONS WITH EACH OF THE SAFETY THAT IS PROPER TO IT
US5862353A
(en)
*
1997-03-25
1999-01-19
International Business Machines Corporation
Systems and methods for dynamically controlling a bus
US5978867A
(en)
*
1997-08-21
1999-11-02
International Business Machines Corporation
System for counting clock cycles stolen from a data processor and providing the count value to a second processor accessing the data processor cycle resources
US6058461A
(en)
*
1997-12-02
2000-05-02
Advanced Micro Devices, Inc.
Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation
US6434592B1
(en)
*
1998-01-05
2002-08-13
Intel Corporation
Method for accessing a network using programmed I/O in a paged, multi-tasking computer
US6438628B1
(en)
*
1999-05-28
2002-08-20
3Com Corporation
System and method for data pacing
US6735715B1
(en)
2000-04-13
2004-05-11
Stratus Technologies Bermuda Ltd.
System and method for operating a SCSI bus with redundant SCSI adaptors
US6691257B1
(en)
2000-04-13
2004-02-10
Stratus Technologies Bermuda Ltd.
Fault-tolerant maintenance bus protocol and method for using the same
US6687851B1
(en)
2000-04-13
2004-02-03
Stratus Technologies Bermuda Ltd.
Method and system for upgrading fault-tolerant systems
US6708283B1
(en)
2000-04-13
2004-03-16
Stratus Technologies, Bermuda Ltd.
System and method for operating a system with redundant peripheral bus controllers
US6820213B1
(en)
2000-04-13
2004-11-16
Stratus Technologies Bermuda, Ltd.
Fault-tolerant computer system with voter delay buffer
US6633996B1
(en)
2000-04-13
2003-10-14
Stratus Technologies Bermuda Ltd.
Fault-tolerant maintenance bus architecture
US6629178B1
(en)
2000-06-15
2003-09-30
Advanced Micro Devices, Inc.
System and method for controlling bus access for bus agents having varying priorities
US6948010B2
(en)
2000-12-20
2005-09-20
Stratus Technologies Bermuda Ltd.
Method and apparatus for efficiently moving portions of a memory block
US6766479B2
(en)
2001-02-28
2004-07-20
Stratus Technologies Bermuda, Ltd.
Apparatus and methods for identifying bus protocol violations
US7065672B2
(en)
2001-03-28
2006-06-20
Stratus Technologies Bermuda Ltd.
Apparatus and methods for fault-tolerant computing using a switching fabric
US6971043B2
(en)
2001-04-11
2005-11-29
Stratus Technologies Bermuda Ltd
Apparatus and method for accessing a mass storage device in a fault-tolerant server
US6996750B2
(en)
*
2001-05-31
2006-02-07
Stratus Technologies Bermuda Ltd.
Methods and apparatus for computer bus error termination
US7013357B2
(en)
*
2003-09-12
2006-03-14
Freescale Semiconductor, Inc.
Arbiter having programmable arbitration points for undefined length burst accesses and method
EP2567379A4
(en)
*
2010-05-07
2014-01-22
Mosaid Technologies Inc
Method and apparatus for concurrently reading a plurality of memory devices using a single buffer
Family Cites Families (8)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3508206A
(en)
*
1967-05-01
1970-04-21
Control Data Corp
Dimensioned interrupt
US3543246A
(en)
*
1967-07-07
1970-11-24
Ibm
Priority selector signalling device
US3543242A
(en)
*
1967-07-07
1970-11-24
Ibm
Multiple level priority system
US3705388A
(en)
*
1969-08-12
1972-12-05
Kogyo Gijutsuin
Memory control system which enables access requests during block transfer
US3643229A
(en)
*
1969-11-26
1972-02-15
Stromberg Carlson Corp
Interrupt arrangement for data processing systems
US3866181A
(en)
*
1972-12-26
1975-02-11
Honeywell Inf Systems
Interrupt sequencing control apparatus
US3961312A
(en)
*
1974-07-15
1976-06-01
International Business Machines Corporation
Cycle interleaving during burst mode operation
JPS5493934A
(en)
*
1978-01-06
1979-07-25
Hitachi Ltd
Input/output control system
1978
1978-10-02
US
US05/948,070
patent/US4275440A/en
not_active
Expired – Lifetime
1979
1979-08-14
AU
AU49906/79A
patent/AU531595B2/en
not_active
Ceased
1979-08-17
JP
JP54104172A
patent/JPS5847050B2/en
not_active
Expired
1979-08-24
CA
CA334,531A
patent/CA1115850A/en
not_active
Expired
1979-09-12
DE
DE7979103408T
patent/DE2964214D1/en
not_active
Expired
1979-09-12
EP
EP79103408A
patent/EP0009678B1/en
not_active
Expired
1979-09-27
ES
ES484505A
patent/ES484505A1/en
not_active
Expired
1979-10-02
BR
BR7906341A
patent/BR7906341A/en
unknown
Also Published As
Publication number
Publication date
EP0009678A1
(en)
1980-04-16
AU531595B2
(en)
1983-09-01
JPS5847050B2
(en)
1983-10-20
EP0009678B1
(en)
1982-12-08
JPS5549727A
(en)
1980-04-10
DE2964214D1
(en)
1983-01-13
CA1115850A
(en)
1982-01-05
US4275440A
(en)
1981-06-23
BR7906341A
(en)
1980-06-24
ES484505A1
(en)
1980-04-16
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