AU601784B2

AU601784B2 – Data processing system having a bus command generated by one subsystem on behalf of another subsystem
– Google Patents

AU601784B2 – Data processing system having a bus command generated by one subsystem on behalf of another subsystem
– Google Patents
Data processing system having a bus command generated by one subsystem on behalf of another subsystem

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Publication number
AU601784B2

AU601784B2
AU82144/87A
AU8214487A
AU601784B2
AU 601784 B2
AU601784 B2
AU 601784B2
AU 82144/87 A
AU82144/87 A
AU 82144/87A
AU 8214487 A
AU8214487 A
AU 8214487A
AU 601784 B2
AU601784 B2
AU 601784B2
Authority
AU
Australia
Prior art keywords
signal
smf
command
bus
data
Prior art date
1986-12-18
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Ceased

Application number
AU82144/87A
Other versions

AU8214487A
(en

Inventor
George J. Barlow
Elmer W. Carroll
James W. Keeley
Chester M. Nibby Jr.
Arthur Peters
Richard C. Zelley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Bull HN Information Systems Inc

Original Assignee
Honeywell Bull Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1986-12-18
Filing date
1987-12-07
Publication date
1990-09-20

1987-12-07
Application filed by Honeywell Bull Inc
filed
Critical
Honeywell Bull Inc

1988-06-23
Publication of AU8214487A
publication
Critical
patent/AU8214487A/en

1990-09-20
Application granted
granted
Critical

1990-09-20
Publication of AU601784B2
publication
Critical
patent/AU601784B2/en

2007-12-07
Anticipated expiration
legal-status
Critical

Status
Ceased
legal-status
Critical
Current

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Classifications

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

G06F13/38—Information transfer, e.g. on bus

G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation

G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus

G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus

G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Description

iii 601 COMMONWEALTH OF AUSTRALIA FORM PATENTS ACT 1952
COMPLETE
S PECIFI CAT I ON FOR OFFICE USE: Class Int.Class Application Number: Lodged: r r.
fc^ Complete Specification Lodged: Accepted: C Published: -KPriority: Related Art: Name of Applicant: HONE Name of Applicant: HONE This d’y:urnent contains the amendments made under Section 49 and is correct for prining YWELL BULL INC.
Address of Applicant: Ac Actual Inventor: 13350 U.S. Hwy. 19 So. (MS 141-4A) Clearwater, Florida, 33546-7290, United States of America Arthur Peters, Richard C. Zelley, Elmer W.
Carroll, George J. Barlow, Chester M.
Nibby, Jr., and James W. Keeley i,
B
i Address for Service: SHELSTON WATERS, 55 Clarence Street, Sydney Complete Specification for the Invention entitled: “DATA PROCESSING SYSTEM HAVING A BUS COMMAND GENERATED BY ONE SUBSYSTEM ON BEHALF OF ANOTHER SUBSYSTEM” The following statement is a full description of this invention, including the best method of performing it known to me/us:- 1 1A RELATED APPLICATIONS The following patent applications which are assigned to the same assignee as the instant application have related subject matter.
1. Apparatus for Loading and Verifying a Control Store Memory of a Central Subsystem, invented by Chester M. Nibby, Jr., Richard C. Zelley, Kenneth E. Bruce, George J. Barlow and James W. Keeley, Australian Application No.
82146/87.
W 2. Universal Peripheral Controller Self-Configuring c Bootloadable Ramware, invented by John A. Klashka, Sidney L. Kaufman, Krzysztof A. Kowal, Richard P. Lewis, Susan L.
Raisbeck and John L. McNamara Jr., US 4,803,623.
3. System Management Apparatus for a Multiprocessor System, invented by George J. Barlow, Elmer W. Carroll, James W. Kecley, Wallace A. Martland, Victor M. Morganti, SArthur Peters and Ricard C. Zelley, Australian Application No. 73456/87.
4i *I i -2- BACKGROUND OF THE INVENTION Field of the Invention This invention relates to data processing systems and more particularly to the use of commands on a system bus which are sent by one subsystem to tell another subsystem to send a response command to a third subsystem.
Description of the Prior Art U.S. Patent No. 4,030,075 entitled “Data Processing System Having Distributed Priority Network”, invented by George J. Barlow, describes a data processing system in which a number of subsystems are coupled in common by a system bus. The subsystems communicate with each other by sending commands out on the system bus. A command may include a channel number idenitifying a receiving unit, a channel number identifying a sending subsystem and a function code C, C specifying an operation to be performed by the receiving subsystem. The function code may require that the receiving subsystem generate a response command. This response or second half bus cycle command includes the channel number identifying the sending subsystem. The sending subsystem responds to its channel number and acknowledges the receiving of the second half bus cycle command.
-yja-fr” i’s 1 1 Fild o theInvetio tehis ineto eae odtapoesn ytm n atcual oteueo omad nasse u w -3i, OBJECTS OF THE INVENTION i-s an object of the invention to have an improved data sing system. is another object of the invention to have an improved rocessing system wherein all subsystems are coupled in to a system bus.
is a. further object of the invention to have a data sing system with a more versatile command system for itting commands over the system bus.
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i i r -n i i, I II I I; 4 According to the invention there is provided a data processing system comprising: a system bus; a first subsystem coupled to said system bus for generating a command requiring a response command; a second subsystem coupled to said system bus for receiving said command and generating said response 00 0 command; 0000 “os0 said command including a first field identifying a 0000 ~Go0 1 10 third subsystem, a second field identifying said second 0 0 *0 0o subsystem and a third field specifying the action said 0 00 S0 0 Son0 second subsystem is to perform; said third subsystem coupled to said system bus for receiving said response command.
S A Preferably, a main memory, a central subsystem (CSS) 0 G 0 and a system management facility (SMF) are all coupled in 0 *o o. common to a system bus. The SMF sends a memory reference read command to main memory and receives the contents of the location specified by the command. The command includes an address in main memory and a channel number of the SMF. This enables the main memory to include the SMF channel number in the second half bus cycle command /7 sending the data to the SMF from main memory.
Preferably also, the SMF can send the memory reference read command which includes the channel number of a port of the CSS as the sending unit. Main memory will send the second half bus cycle command containing the addressed data word to the CSS. The SMF includes n 4i 2 y i u*arrrr~- -uamr~i~r ii-L -LLI .I i ^111_~ 4A apparatus for resetting the read command when it receives the acknowledge signal from main memory indicating that the command was received. Normal operation is for the sending unit to keep the read command logic active until the second half bus cycle command is received by the sending unit.
C
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i~-i n; ;1, i:e I: BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a block diagram of the data processing system.
Figure 2 shows a block diagram of the systems management facility.
Figure 3 shows a block diagram of a system bus interface.
Fiaure 4 shows a block diagram of a central subsystem.
Figures 5A through 5E show the formats of various commands that are applied to a system bus.
10 Figure 6 is a flow diagram of the firmware that loads the control store.
Figure 7 is a timing diagram of the central subsystem signals that control the loading and verifying of the control store load.
r C C SCC C
C’
C C *e r
C
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:r a.’ r-‘ I- DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 shows a tightly coupled multiprocessor data processing unit (DPU) 1 which includes a plurality of central subsystems (CSS) 3 through 5 coupled to a system bus interface 2-10A and 2-10B respectively; and a plurality of main memories 10 through 12, a plurality of peripheral controllers 14 through 16 and a system management facility (SMF) 20, all coupled in common to a system bus 2 via their respective system bus interface 2-10.
10 A plurality of devices 1 18 are coupled to peripheral controller 1 14 and a plurality of devices N 17 are coupled to peripheral controller N 16. The plurality of peripheral controllers 14 through 16 may include disk controllers, tape controllers, communication controllers and unit record controllers to which are coupled their respective disk drives, tape devices, communication lines, and unit record rr’o devices.
re.