AU620073B2

AU620073B2 – Multiprocessor intelligent cell for a network which provides sensing, bidirectional communications and control
– Google Patents

AU620073B2 – Multiprocessor intelligent cell for a network which provides sensing, bidirectional communications and control
– Google Patents
Multiprocessor intelligent cell for a network which provides sensing, bidirectional communications and control

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Publication number
AU620073B2

AU620073B2
AU29018/89A
AU2901889A
AU620073B2
AU 620073 B2
AU620073 B2
AU 620073B2
AU 29018/89 A
AU29018/89 A
AU 29018/89A
AU 2901889 A
AU2901889 A
AU 2901889A
AU 620073 B2
AU620073 B2
AU 620073B2
Authority
AU
Australia
Prior art keywords
cell
register
memory
registers
instruction
Prior art date
1987-11-10
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
AU29018/89A
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AU2901889A
(en

Inventor
Bruce T. Eisenhard
Wendell B. Sander
Stephen R. Smith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Echelon Corp

Original Assignee
Echelon Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1987-11-10
Filing date
1988-11-02
Publication date
1992-02-13

1988-11-02
Application filed by Echelon Systems Corp
filed
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Echelon Systems Corp

1989-06-01
Publication of AU2901889A
publication
Critical
patent/AU2901889A/en

1992-02-13
Application granted
granted
Critical

1992-02-13
Publication of AU620073B2
publication
Critical
patent/AU620073B2/en

2008-11-02
Anticipated expiration
legal-status
Critical

Status
Expired
legal-status
Critical
Current

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Classifications

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F15/00—Digital computers in general; Data processing equipment in general

G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

G06F15/163—Interprocessor communication

G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Abstract

A plurality of intelligent cells each of which comprises an integrated circuit having a processor and input/output section coupled to a network for providing sensing, communications and control are described. Each cell includes a multiprocessor (100), input/output section (107-110), memory (115) and associated timing circuits; oscillator (112), and timing generator (111). The multiprocessor (100) is a stack oriented processor having four sets of registers (101), providing inputs to an arithmetic logic unit (ALU) (102). The ALU (102) may comprise two separate ALU’s. One portion of memory (115) is used for storing instructions, ROM code (115a). The next portion of the memory is a random-access memory (115b). The third portion of the memory comprises an electrically erasable and electrically programmable read-only memory (EEPROM) (115c). Timing and control are provided to the registers, ALU and memory, whereby each cell is realized.

Description

Ii~ tf OPI DATE 01/06/89 APPLN. ID 29018 89
I
S O A p wAOJP DATE 06/07/89 PCT NUMBER PCT/US88/03906 STUNA V NA APPL ATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (51) International Patent Classification 4 (11) International Publication Number: WO 89/ 04521 G06F 15/16, 7/00 Al (43) ]nternational Publication Date: 18 May 1989 (18.05.89) (21) International Application Number: PCT/US88/03906 (74) Agents: TAYLOR, Edwin, H. et al.; Blakely, Sokoloff, Taylor Zafman, 12400 Wilshire Boulevard, Seventh (22) International Filing Date: 2 November 1988 (02.11.88) Floor, Los Angeles, CA 90025 (US).
(31) Priority Application Number: 119,331 (81) Designated States: AT, AT (European patent), AU, BB, BE (European patent), BG, BR, CH, CH (European (32) Priority Date: 10 November 1987 (10.11.87) patent), DE, DE (European patent), DK, FI, FR (European patent), GB, GB (European patent), HU, IT (33) Priority Country: US (European patent), JP, KP, KR, LK, LU, LU (European patent), MC, MG, MW, NL, NL (European patent), NO, RO, SD, SE, SE (European patent), SU.
(71) Applicant: ECHELON SYSTEMS [US/US]; 727 University Avenue, Los Gatos, CA 95030 (US).
Published (72) Inventors: EISENHARD, Bruce, T. 310 Almendra With international search report.
Avenue, Los Gatos, CA 95030 SMITH, Stephen, Before the expiration of the time limit for amending the R. 611 Navarra Drive, Scotts Valley, CA 95066 claims and to be republished in the event of the receipt SANDER, Wendell, B. 112 Harwood Court, Los of amendments.
Gatos, CA 95032 (US).
(54) Title: MULTIPROCESSOR INTELLIGENT CELL FOR A NETWORK WHICH PROVIDES SENSING, BIDI- RECTIONAL COMMUNICATIONS AND CONTROL i C-111 1 TIMING 4 roI /-r100 G SET OF I GENERATOR
REGISTERS
AD. ALU D.ALU -102
MULTI-PROCESSOR
(57) Abstract A plurality of intelligent cells each of which comprises an integrated circuit having a processor and input/output section coupled to a network for providing sensing, communications and control are described. Each cell includes a multiprocessor (100), input/output section (107-110), memory (115) and associated timing circuits; oscillator (112), and timing generator (111). The multiprocessor (100) is a stack oriented processor having four sets of registers (101), providing inputs to an arithmetic logic unit (ALU) (102). The ALU (102) may comprise two separate ALU’s. One portion of memory (115) is used for storing instructions, ROM code (115a). The next portion of the memory is a random-access memory (115b). The third portion of the memory comprises an electrically erasable and electrically programmable read-only memory (EE- PROM) (1 15c). Timing and control are provided to the registers, ALU and memory, whereby each cell is realized.
WO 89104521 PCT/US88/03906 MULTIPROCESSOR INTELLIGENT CELL FOR A NETWORK WHICH PROVIDES SENSING, BIDIRECTIONAL COMMUNICATIONS AND CONTROL BACKGROUND OF THE INVENTION 1. Field of the Invention The invention relates to the field of networks with distributed intelligence, configuration and control and intelligent cells used in networks, primarily where the networks are used for sensing, communicating and controlling.
2. Prior Art.
There are many commercially available products which provide sensing, control and communications in a network environment. These products range from very expensive, elaborate systems, to simple systems having little intelligence.
As will be seen, the present invention is directed towards providing a system having a relatively large amount of intelligence and computational power but at a low cost.
One commercially available system provides control, by way of example, between a light switch and a light. When the light switch is operated, a code pattern is transmitted over the power lines to a receiver at the light. The code pattern is transmitted twice, once in its true form and once in its complementary form. When the code is received by the receiver, it is interpreted, and thereby used to control the light.
Mechanical addressing means are employed to allow the
A
-2transmitter at the switch to communicate with the specific desired receiver at the light.
As will be seen, the present invention provides substantially more capability and flexibility than current systems.
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t 9IO13I.cIdscLO~2~1B~pe,2 -3- SUMMARY OF THE INVENTION In accordance with the present invention there is provided a cell for use in a network that provides sensing, communication, and control, comprising: input and output means coupled to the network for providing communication with the network; a memory; a multiprocessor coupled to the input and output means for simultaneously performing a plurality of processes, wherein the multiprocessor comprises an arithmetic logic unit; a plurality of sets of registers, wherein each of the sets of registers is associated with one of the processes, wherein each of the sets of registers is j 0 coupled to the arithmetic logic unit, the sets of registers, and the memory, and 15 wherein each set of the registers includes S: an instruction register for storing an instruction; and logic means coupled to the instruction register for interpreting the instruction stored in the instruction register; control means coupled to the sets of registers, the arithmetic logic unit, and the memory for providing control signals for causing an output from one set of the registers to be provided as an input to the arithmetic logic unit for a first v one of the processes while simultaneously causing an output of the arithmetic logic unit to be provided as an input to the memory for a second one of the processes while simultaneously causing an output of the memory to be provided as an input 25 to another one of the sets of the registers for a third one of the processes.
S The present invention also provides a cell for use in a communication and S control network, comprising: input and output means coupled to the network for providing one of the functions of sensing, communicating, and controlling; a memory; a plurality of processors for simultaneously performing a plurality of 910131 ,eId.pjOl0,2901 8pe,3 .tf j’ -4processes, wherein the plurality are coupled to the memory and to the input and output means, wherein the plurality of processors comprise: an arithmetic logic unit shared by the processors and a plurality of register groups, wherein each register group is associated with a respective processor, wherein outputs from the register groups are coupled to the arithmetic logic unit, wherein an output of the arithmetic logic unit is coupled to the memory, and wherein an output of the memory is coupled as an input to the register groups, and wherein each of the register groups comprises a base pointer register for storing a memory base pointer for a respective processor; an instruction pointer register for storing a memory pointer that points to an instruction for a respective processor; an instruction register for storing an instruction for a respective processor; I 15 a stack pointer register for storing a memory stack pointer for a respective processor; a return pointer register for storing a memory return pointer for a 6 respective processor; control means for providing control signals for simultaneously transferring data from one of the register groups to the arithmetic logic unit while *simultaneously transferring data associated with another one of the register groups from the arithmetic logic unit to the memory while simultaneously transferring data associated with another one of the register groups from the memory, wherein the control means are coupled to the register groups, wherein the control means comprise: 6 a plurality of counters associated with the instruction registers; circuit means for providing initial settings to the counters, wherein the circuit means are coupled to receive the instructions stored in the instruction registers; a logic array coupled to receive as inputs the contents of the counters and instructions stored in the instruction registers; rin 14;. l9133 l,etdspcD1i2901S.pc,4 v delay means for delaying a plurality of outputs from the logic array, wherein outputs of the logic array and the delay means comprise the control signals.
The present invention further provides a multiprocessor having N processors, wherein N is an integer greater than one, comprising: a multiprocessor having N processors, wherein N is an integer greater than one, comprising: N sets of register means for storing data, wherein each set of register means includes an instruction means for storing an instruction, and wherein each of the N sets of registers is associated with one of a plurality of processes; an arithmetic logic unit coupled to the N sets of register means, wherein an output from the sets of register means is provided as an input to the arithmetic logic unit; a memory coupled to the sets of register means and to the arithmetic 15 logic unit; o(D) control means coupled to the N sets of registers, the arithmetic logic unit, and the memory for providing control signals for causing an output from one set of the register means to be provided as an input to the arithmetic logic unit for a first process of the plurality of processes while simultaneously causing an output from the arithmetic logic unit to be provided as an input to the memory for a :second process of the plurality of processes while simultaneously causing an output from the memory to be provided as an input to another set of the register means for a third process of the plurality of processes, wherein the control means comprise a plurality of counters associated with the instruction registers, circuit means for providing initial settings to the counters, wherein
SO.
the circuit means are coupled to receive the instructions stored in the instruction registers; a logic array coupled to receive as an input the contents of the counters and the instructions stored in the instruction registers; delay means for delaying a plurality of outputs from the logic array, S-AI01i31,erldpe 10.29018Jspc,5 2 wherein outputs of the logic array and the delay means comprise the control signals.
Other aspects of the invented network and cell will be apparent from the detailed description hereinafter of preferred *embodiments of the invention.
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77 91013,Isp.010,29018sMc6 WO 89/04521 PCT/US88/03906 6 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a -block diagram illustrating typical application for the present invention.
Figure 2 is a diagram used to illustrate the grouping of cells.
Figure 3 is another block diagram similar to Figure 2 used to illustrate the grouping of cells.
Figure 4 is a diagram used to describe subchannels.
Figure 5 is a diagram illustrating a plurality of cells; this diagram is used to describe cell group formation employing the present invention.
Figure 6 is a chart illustrating the packet format used with the present invention.
Figure 7 is a chart illustrating the designation list portion of the packet format of Figure 6.
Figure 8 illustrates a series of steps used in forming a group of cell with the preser invention.
Figure 9 is a chart illustrating the code assignments for the three-of-six encoding used with the present invention.
Figure 10 is a block diagram of the communication and control cell.
WO 89/04521 PCT/US88/03906 7 Figure II is a block diagram of a portion of the instruction decoding logic used within the processor of the cell of Figure Figure 12 is a detailed block diagram of the process of Figure Figure 13 is a timing diagram for the processor of Figure this diagram also shows latches and ‘registers used to provide the pipelining employed by the cell.
Figure 14 is a block diagram illustrating the presently preferred embodiment of the three-of-six encoder.
Figure 15 is a block diagram showing the presently preferred embodiment of the three-of-six decoder.
Figure 16 is a block diagram showing the presently preferred embodiment of the three-of-six code verifier.
Figure 17 is an electrical schematic of the buffer section of one of the I/O sections.
Figure 18 is an electrical schematic of the counting and timing functions for an I/O subsection.
Figure 19 is an electrical schematic of the control and state machine for an I/O section.
SFigure 20 is an electrical schematic for the sample and hold means associated with the I/O subsections.
I
II
I
1 2 WO 89/04521 PCT/US88/03906 Figure 21 illustrates the network formed within an I/O subsection to do digital-to-analog conversion.
Figure 22 illustrates the network formed within an I/O section for analog-to-digital conversion.
Figure 23 is an electrical schematic showing the communications portion of an I/O subsection.
Figure 24 is a state diagram used for the I/O subsections and for transmission contentions.
Figure 25 is a state diagram for the link level ARQ.
Figure 26 is a state diagram for primary station connections.
Figure 27 is a state diagram for secondary station connections.
Figure 28 is a block diagram for a grouping device.
Figure 29 is a diagram showing the form in which the system !D is encoded for transmission by the packet and encoded within a cell.
Figure 30 is a diagram used to describe the operation of the input/output section and semaphore register.
i 71 WO 89/04521 PCT/US88/03906 9 DETAILED DESCRIPTION OF THE PRESENT INVENTION An apparatus and method for providing a communications, sensing and control in a network is described. Where the network contains a plurality of intelligent cells, the cells in general are programmable single chip remote control, sensing and communication devices that, when interconnected (via various media) with other cells, have distributed sensing, communication, control and network configuration intelligence, configuration and control. The system comprises a network of cells organized in a hierarchy based on communications needs. Cells are organized into working “groups” independent of the network hierarchy.
Groups of cells generally are used to perform a group function.
This function is carried out by the assignment of tasks to cells within the groups. Cells communicate, control and sense information. In general, each cell has a unique identification number and perform information processing tasks such as: bidirectional communications protocol, input/output, packet processing and analog and digital sensing and control. .In general, the system comprised of the cells has the characteristic of storing network configuring information that is distributed throughout the system; and communicates automatically routed messages among cells. Each system also has a unique WO 89/04521 PcT/US88!,3906 identification (ID) which in the presently preferred embodiment is 48 bits. Moreover, it contains versatile programmable input/output I/O circuits with digital versatile programming to configure cells to specific sensing, communication, control and I/O, analog I/O, communication I/O and communications bit rate sensing.
In the following description, numerous specific details are set forth such as specific frequencies, etc., in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that these details are not required to practice the invention. In other instances, wellknown circuits, methods and the like are not set forth in detail in order not to unnecessarily obscure the present invention.
I.
OVERVIEW OF AN APPLICATION OF THE PRESENT
INVENTION
Before describing the present invention in detail, an understanding of a typical application will aid in appreciation of the details to follow. In Figure 1, a simple, typical application is shown based on the use of the present invention in a home. In WO 89/04521 PCT/US88/03906 11 Figure I, the switch 22 is used through the present invention to control the light 23.
The arrangement 20 comprises a cell 27 which is connected to the switch 22. The cell is also connected to a transceiver 29 which couples data onto the lines 24 and 25. Power for the transceiver and cell are provided from the power supply 30 which receives power from the lines 24 and 25. For this example, the lines 24 and 25 are ordinary household wiring 110VAC) and the power supply 30, a five volt DC supply. The cell 27 is preferably an integrated circuit which is described in more detail beginning with Figure 10. The transceiver 29 may be any one of many well-known devices for receiving and transmitting digital data and as presently contemplated does not perform any processing on transmitted data. The entire arrangement 20 may be small enough to fit within an ordinary wallmounted electrical box which normally contains an electrical switch.
The arrangement 21 again may be small enough to fit within a typical electrical outlet box and includes a power supply 31 and transceiver 33 which may be identical in construction to the power supply 30 and transceiver 29, respectively. This cell 28 is coupled to the t;’ansceiver 30 and power supply 29 as well as the solenoid operated power switch 32. Cell 28 may be identical to
I
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WO 89/04521 PCr/US88/03906 12 cell 27 except for programming and an identification number which shall be discussed later. An output from the cell 28 controls the solenoid 32 to operate a power switch which in turn connects the light 23 to the power lines 34 and 35. The cell 28, as will be seen, can provide a digital or analog output, which can control a rheostat (not shown) or the like, thus enabling the dimming of the light 23.
The break 26 in the power lines 24 and 25 is used to indicate that the power lines 24 and 25 may not necessarily be on the same circuit as power lines 34 or 35. As will be seen, the transceiver 29 may not necessarily communicate directly with transceiver 33, but rather communication between the transceivers may require linkage through another cell and transceiver which repeats packets sent between the arrangements 20 and 21.
In Figure I, the transceivers 29 and 33 communicate over power lines. The transceivers may communicate with one another in numerous different ways over countless media and at any baud rate. They may, for example, each transmit and receive radio frequency or microwave frequency signals through antennas. The transceivers could be connected to a communications lines, such as an ordinary twisted pair or fiberoptic cable and thus L~i WO 89/04521 pCT/US88/03906 13 communicate with one another independent of the power lines.
Other known communications medium may be employed between the transceivers such as infrared or ultrasonic transmissions.
Typical transmission rates are 10K bits per second (KBPS) for power lines. Much higher transmission rates are possible for radio frequency, infrared, twisted pairs, fib/aroptic links and other media.
Cell 27 senses the opening or closing of the switch 22, then prepares a packet which includes a message initiating the state of the switch 22; the packet is communicated to the cell 28 through transceiver 29, lines 24 and 25, lines 34 and 35, and transceiver 33. The cell 28 acknowledges the message by ii returning a packet to the cell 27 and also acts upon the message V it received by turning on or off the light 23 by operating the so’anoid controlled power switch 32.
Each cell has a unique 48 bit identification number (ID number), sometimes referred to as the cell address. In the currently preferred embodiment, each cell as part of the manufacturing process, receives this permanent and unique ID number. (It cannot be changed following manufacturing.) As will L be appreciated, with approximately 248 possible ID numbers, each I cell will have a unique ID number no matter how large a network WO 89/04521 PCT/US88/03906 14 becomes for practical purposes, or no matter how many networks are interconnected. The grouping device then accesses the individual cell IDs and assigns a system ID to each cell. In addition, the grouping device configures the cells into groups to perform group related functions.
For the illu-tration of Figure I, cell 27 is designated as “A” to indicate that its primary function is to “announce” that is, transmit the state of switch 22 on the network communications lines 24 and 25, and 34 and 35. On the other hand, cell 28 is designated with the letter since its primary function in Figure I is to “listen” to the network and in particular to listen to messages from cell 27. In subsequent figures, the and “L” designations are used, particularly in connection with a group formation of multiple cells to indicate an announcer arrangement, such as arrangement 20 and a listener arrangement, such as arrangement 21. For purposes of discussion the cells themselves are sometimes referred to as transmitting or receiving data without reference to transceivers. (In some cases, the transceivers may be a simple passive network or simple wires, which couple the input/output of a cell onto a line. As will be seen the I/O section of the cells can provide output signals that lj
L
WO 89/04521 PCT/US88/03906 can drive a twisted pair or the like. Thus the cells themselves can function as a transceiver for some media.) The cells 27 and 28 as will be described subsequently are processors having multiprocessor attributes. They may be programmed prior to or after installing tb perform their required function, such as an announcer or listener and for grouping combinations.
i WO 89/04521 PCT/US88/03906 16
II.
NETWORK ORGANIZATION AND DEFINITIONS A. Definitions Cell: A cell is an intelligent, programmable element or elements providing remote control, sensing and/or communications, that when interconnected with other like elements form a communications, control and sensing network or system with distributed intelligence.
Announcer: An announcer is a source of group messages.
Listener: A listener is a sink of group messages.
(An announcer in some cases may request state information from a listener.) Repeater: A repeater is a cell which in addition to other functions reads packets from a medium and rebroadcasts them.
Group: A set of cells which work together for a common function (for example, a switch controlling a set of lights) is referred to as a “group”.
In Figure 2, the group 37 has an announcer 37a, listeners 37b, and 37c, and a listener 40. A group 38 includes an announcer 38a, listeners 38b and 38c and the listener 40. Figure 2 illustrates that a single cell (cell 40) may be a listener in two WO 89/04521 PCT/US88/03906 17 groups. If announcer 37a has a light switch function, it can control lights through cells 37b, 37c and 40. Similarly, a switch associated with announcer 38a can control lights through cells 37c, 37b, and In Figure 3, a group 42 includes announcers 44, 45 and listeners 46 and 47. The group 43 shares cell 44 with group 42; however, cell 44 is a listener for group 43. The group 41 shares cell 47 with group 42; cell 47 is an announcer for group 41 and for example, can announce to the listener 48 of group 41. Cell 47 also operates as a listener for group 42. A single cell as shown may be an announcer for one group and a listener for another group (cells are programmed to perform these functions, as will be discussed). However, as presently contemplated, a single cell cannot announce for more than one group.
(In the currently preferred embodiment each cell has three input/output pairs of lines and a select line. Each pair shares a common set of resources. The lines may be used independently for some functions where the required shared resources do not conflict. In other functions, the lines are used as pairs. In this example, a pair of leads from cell 27 are coupled to a light I- switch and another pair are used for communications from the announcer, cell 27.) It rfl WO 89/04521 PCT/US88/03906 18 Subchannel: In Figure 4, a first plurality of cells are shown communicating through a common medium such as a twisted pair (cells are shown as announcers as and listeners as This twisted pair 50) is defined as a subchannel, that is, a set of cells all of which communicate directly with one another over the same medium. A broadcast by any member of the subchannel, such as the cell 49, will be heard by all members of that subchannel over the twisted pair Channel: A channel comprises two or more subchannels where all the cells communicate using the same medium. In Figure 4, another plurality of cells are shown coupled to twisted pair 52 forming another subchannel. Assume cells 56 and 57 communicate between one another through a twisted pair 72.
They form yet another subchannel. The cells associated with the twisted pairs 50, 52 and 72 comprise a single channel. It is possible that the twisted pairs 50, 52 and 72 are one continuous twisted pair with one subchannel 50 so far apart from the second subchannel 52 that the only communications between subchannels is over the portion of the twisted pair 72 running between cells 56 and 57. In this case the cells 56 and 57 are assigned to be S”repeaters” in addition to whatever other function they may serve announcer or listener).
I-
WO 89/04521 PCT/US88/03906 19 A group 55 is illustrated in Figure 4 which comprises an announcer and listener in the two different subchannels. Another group 75 is illustrated comprising an announcer on one subchannel 51 and subchannel 52, where the subchannels are not part of the same channels since they use different media.
Gateway: A gateway reads packets from two different media and rebroadcasts them. A cell may be a gateway.
Communications between channels is through gateway 54.
In Figure 4, an additional subchannel which includes the cell 58 is coupled to another medium 51, for example, a common power line. The cell 58 is shown connected to channel gateway 54 which in turn communicates with the twisted pair 52. The gateway 54 does not necessarily perform either an announcer or listener function, but rather for the illustrated embodiment, performs only a channel gateway function by providing communication between two different media.
Subnetwork: A subnetwork comprises all the cells having the same system identification (system ID). For example, all the cells in a single family home may have the same system ID.
Therefore, the channels of Figure 4 may be part of the same subnetwork in that they share the same system ID.
PCT/US88/03906 WO 89/04521 Full Network: A full network may comprise a plurality of subnetworks each of which has a different system ID; a communications processor is used for exchanging packets between subnetworks. The communications processor translates packets changing their system ID, addressing and other information. Two factory buildings may each have their own system ID, but control between the two is used by changing system IDs. (The word “network” is used in this application in its more general sense and therefore refers to other than a “full network” as defined in this paragraph.) Other terms used later are: Probe Packet: A packet routed by flooding which accumulates routing information as it travels through the network.
Grouping Device: A device that controls determination of routes among cells, assigns cells to groups, and assigns function to group members.
Contention: The state which exists when two or more cells attempt to transmit a broadcast on the same subchannel at the same time and their signals interfere.
4-I WO 89/04521 PCT/US88/03906 21 B. jROUP FORMATION 1. Cells Assigned to a aroup by a postinstallation arouDirf, device.
Assume that the plurality of cells shown in Figure 5 are all connected to communicate over the power lines in a home and are part of the same channel. Further assume that one cell, announcer is to be grouped with the listener 65. The lines between the cells such as line 59 is used to indicate which of the cells can i communicate directly with one another, for instance, announcer 60 and cell 61 can communicate with one another. (Cells 61, 62, 63, 64 and 66 of course may be announcers or listeners in other groups, but for purposes of explanation are shown as in Figure Since announcer 60 and cells 61, 62, and 63 all communicate with one another, they are on the same subchannel. Similarly, cells 62, 64, 65 and 66 are another subchannel. (There are other subchannels in Figure Importantly, however, announcer 60 and listener 65 are in different subchannels of the channel of Figure and there are numerous routes by which a message can be passed from announcer 60 to listener 65, for example, through cells 61 and 64 or through cells 62 and 64, etc.
SNote that even though all the cells are on the same power system of a house, they may not communicate directly with one WO 89/04521 PCT/US88/03906 22 another. For instance, the announcer 60 may be on one circuit which is only coupled to the listener 65 through long lengths of wire running the length of a home and a low impedance bus bar of a circuit breaker panel. The high frequency communication messages may be sufficiently attenuated through this path to prevent direct communications between cells even though they are physically close to one another.
For the following description, it is assumed that each of the cells can broadcast without interfering with the broadcast of other cells. That is, messages do not interfere with one another.
The case where some contention occurs is dealt with under the protocol section of this application.
In one embodiment, the group of announcer 60 and listener is formed by using the grouping device shown in Figure 28.
Note that before this group is formed the announcer 60 and listener 65 are ordinary cells, not designated to be an announcer and listener. Each grouping device may be assigned a unique 48 bit system ID at time of manufacture (in the presently preferred embodiment a 48 bit number is used). In the presently preferred embodiment, a cell is included with each grouping device. The cell’s ID becomes the system iD. This assures that each system has a unique system ID. By way of example, each home has its WO 89/04521 PCT/US88/03906 23 own “grouping” device and hence, its own system ID for the subnetworks used in the home. This system ID is used in cell packets for the subnetwork. In this example, the grouping device has available the cell IDs of cells 60 and 65. (Various methods of obtaining cell IDs will be described later.) The grouping device is connected to cell 60 by communicating through one of its three pairs of input/output lines of the cell (or the select pin) and the grouping device reads the 48 bit ID number of the cell 60. (Different methods of determining the cell’s IDs are described in the next section.) The grouping device next generates a random bit binary number which in the presently preferred embodiment is 10 bits. This number functions as a group identification number (also referred to as the group address) for the group comprising the announcer 60 and listener 65. The grouping device checks this number against other group IDs which it has previously assigned to determine if the group ID has previously been used. If it has been already used it generates another number. (A single grouping device, for instance keeps track of all the group IDs assigned in a single home.) The grouping device programs the cell 60 designating it as an announcer.
WO 89/04521 PCT/US88/03906 24 The grouping device may cause the announcer 60 to broadcast the group number in a special packet which asks all cells in the network to acknowledge the message if they have been designated as a member of this group. This is another way to verify that the group ID has not been used.
The grouping device now determines the ID number of the cell 65. This may be done by connecting the grouping device directly to the cell 65 even before the cell is installed or by other methods discussed in the next section. (A cell and a group can be assigned ASCII names, for example, “porchlight” (cell name) and “exterior lights” (group name). This is used to allow selection of cell IDs or group IDs by accessing the ASCII name.
Now the grouping device causes the announcer 60 to transmit a probe packet. The probe packet contains the ID of cell 65. The packet directs all cells receiving the packet to repeat it and directs cell 65 to acknowledge the packet. Each cell receiving the probe packet repeats it and adds to the repeated packet its own ID number. Each cell only repeats the packet once (the mechanism for preventing a probe packet from being repeated more than once is described later.) The cell 65 receives the probe packet through numerous routes, including those which in the diagram appear to be most WO 89/04521 PCT/US88/03906 direct (via cell 62) and those which are longer, for example, via cells 61 and 64. It is assumed that the first probe packet to arrive at cell 65 took the most direct route and is therefore the preferred routing. (Assume that this is via cell 62.) Cell receives a packet which indicates that the probe packet was transmitted* by cell 60, repeated by cell 62 and intended for cell The other probe packets received by cell 6Z after this first packet are discarded by cell Cell 65 now .transmits an acknowledgement back to announcer 60. This packet includes the routing of the probe packet repeated by cell 62). The packet directs cell 62 to repeat the packet to confirm its receipt.
After announcer 60 receives the acknowledgement packet for cell 65 it determines that cell 62 must be a repeater. The grouping devices causes announcer 60 to send a repeater assignment packet which includes the unique ID number of cell 62, the group number and a message which informs cell 62 that it V is assigned a repeater function for the group. This causes cell 62 to repeat all those packets for the group comprising announcer cell 60 and 65. Another message is sent from announcer GO under control of the grouping device repeated by cell 62, designating cell 65 as a listener, causing it to act upon messages for the i’ WO 89/04521 PCT/US88/03906 26 group (cell 65 becomes a group member.) The grouping device assigns members a member number whch is stored by member cells.
The group formation described above is shown in Figure 8 by steps or blocks 68 through 72. Block 68 illustrates the broadcasting of the probe packet cell 60 transmits the initial probe packet to all cells). The packet includes the address of a destination cell. As the packet proceeds through the network, the packet and accumulates the ID numbers of those cells repeating the packet (block 69). Block 70 shows the acknowledgement (reply) to the probe packet from the destination cell cell 65). This packet returns the ID numbers of the repeaters contained in the first received probe packet. Repeater assignment packets are sent out by the announcer causing each repeater to rebroadcast packets for the group; this is shown by block 71. Finally, as shown by block 72, the destination cell such as cell 65 is designated as a listener.
2. Cells assigned to a arouo by a oreinstallation arouping device.
There may be several types of preinstallation grouping devices, for example, see Figure 28 for a device which may be used. One type is a device that a manufacturer uses to preassign cells to groups. Another type of preinstallation grouping device WO 89/04521 PCT/US88/03906 27 is one that a retailer or other cell vendor may use to assign cells to groups before installation.
A grouping device assigns a cell to a group and assigns the cell’s function(s) for that group. The grouping device may also assign a system ID to the cell. The system ID assigned by a preinstallation grouping device is not necessarily a unique system ID. (Postinstallation grouping devices assign a unique system ID to each system.) One method that may be used by preinstallation grouping devices to generate a system ID is to choose a system ID from a range of the 48 bit address and system ID numbers that have been set aside for use as preinstallation system IDs. Just as the cell IDs in the range 1-1023 have been set aside for use as group IDs and group addresses, the cell IDs in the range 1024-2047 can be set aside for use as preinstallation system IDs.
It is desirable that grouping devices and other network control devices be able to identify preinstallation system IDs as opposed to postinstallation system IDs. Since postinstallation sytem IDs are generated by copying a cell ID, cell IDs should not be assigned in the range set aside for preinstallation system IDs.
Therefore, ID numbers in that range would not be assigned to cells as cell IDs.
i WO 89/04521 PCr~US8/03906 28 Cells may be sold in sets that have been preassigned to a group by the manufacturer. The type of preinstallation grouping device used by the manufacturer assigns cel!s to groups by writing the appropriate codes into the cells’ nonvolatile memory.
The user may install such a set of cells and it will operate without assignment by a postinstallation grouping device provided that the set of cells may communicate via a single subchannel.
A user may assign cells to a group at the time cells are purchased or at any other time before installation. Such cells, unlike the case previously discussed, are not assigned to groups by the manufacturer and are called unassigned cells. Unassigned cells all have the same system ID, a system ID number that has been set aside for use only by unassigned cells.
The user assigns a set of cells to a group by using a preinstallation grouping device that may be different from the preinstallation grouping device used by a manufacturer.
Typically, such a grouping device will operate on one cell at a time. The operator commands the grouping device to generate a new group ID and system ID and then each cell is connected to the device in turn. The operator commands the grouping device to assign a cell to the group while the cell is connected to the WO 89/04521 PCT/US88/03906 29 grouping device. The grouping device assigns cells the same group ID and system ID until it is commanded by the operator to generate a new group ID and system ID.
The user may install such a set of cells and it will operate without use of a postinstallation grouping device provided that the set of cells can communicate via a single subchannel.
3. Unassigned Cells Groupina and Self-Assignment After Installation.
Unassigned cells may create a group and assign themselves to the group after installation in the following manner.
The first announcer cell that is stimulated via its sensor input light switch) controls the group formation process. It chooses a system ID number at random from the range of system ID numbers that have been set aside for preinstallation grouping devices. It chcoses a group ID number at random. It then broadcasts the group ID number in a packet that requests a reply frcm any cells that are members of that group. If the transmitting cell receives any such replies, it chooses another group ID at random. The cell continues this process of selecting a random group ID and testing to see if it is already in use until it finds a group ID that is unused in the system in which it is operating.
WO 89/04521 PCT/US88/03906 An unassigned cell’s default configuration information programmed at the factory identifies its function as either a listener or an announcer. If the unassigned cell is an announcer, it waits for its sensing input to be stimulated, and when it is stimulated, the cell transmits a packet addressed to a group.
If an unassigned cell is a listener, it listens after power-up for a packet. The cell takes the group ID from the first packet it receives and assigns itself to that group. The cell then sends a reply to the announcer cell. This reply is not an acknowledgement only packet; it is a packet that identifies the cell as a listener in the group and the packet must be acknowledged by the announcer.
This assures that all of the listener identification packets will arrive at the announcer even though there will be contention and collisions in the process.
The cell that transmitted the group announcement builds a list of group members as each reply comes in. It then sends a packet to each listener assigning that listener a group member number.
4. Unassianed Cells Joining Preexisting Grouo After Installation.
Unassigned cells may be added to existing systems and assigned to a group in a manner similar to the above method WO 89/04521 PCT/US88/03906 31 discussed in Section 3 above. A listener joins the system and a group by the same method as in Section 3 above.
In the above example, the announcer waits to be stimulated via its sensor input. An unassigned announcer waits for its first sensor input stimulation or its first received packet. Of those two events, the event that occurs first determines the subsequent actions of the announcer cell.
If the cell is stimulated first, it controls a group formation process just as in the above example. If the announcer cell receives a group packet first, it joins that group as an announcer.
It then sends a packet to the group announcer requesting configuration information about the group (group size, number of announcers,etc.) and the assignment of a group member number.
a- YrlJ WO 89/04521 PCT/USS8/03906 32 C. METHODS OF IDENTIFYING A CELL FOR GROUPING In order for a grouping device to go through the steps necessary to form a group or add a cell to a group, it must know the IDs of the cells to be added to the group. The grouping device then uses those cell IDs to ad;dress commands to the cells during the grouping process. The methods that a user with a grouping device may use to obtain the cell IDs are listed below. Note that a grouping device or other control device’s ability to communicate with a cell in the following example may be limited by security procedures if used. The security procedures, limitations on communications and levels of security are not critical to the present invention. The following example assumes that no security procedures are in place. In particular, it may be impossible for a grouping device to communicate with installed cells unless the grouping device has the system key (system ID and encryption keys.) 1. Direct connection to the cell.
The grouping device may be connected to an I/O line of the cell package and then send a message to the cell requesting its ID.
Physical connection can be used to find a cell’s ID either before or after the cell is installed. Known means can be used a fuse WO 89/04521 PCT/US88/03906 33 or a programmed disable command) to allow a user to disable this function in an installed cell to protect the security of the system.
2. Selection of the Cell Through Use of Special Pin The user may use the grouping device or some other selection device to physically select the cell by stimulating a cell input pin that has been designated to serve the selection function. The grouping device communicates with the cell through the normal communications channels and sends a broadcast message requesting that all selected cells reply with their ID. Only one cell is selected so only that cell will reply to the request. Physical selection can be used to find a cell’s ID either before or after the cell is installed. Again, a means can be provided to allow a user to disable this feature to protect the security of the system.
3. Query All Names of Previously Grouped Cells It is assumed in this example that ASCII “groups” and “cell” names have been previously assigned to the cells. For this method, the grouping device queries all of the cells in .a system to report their group and cell names (ASCII name). The user scrolls through the list of group names by using the grouping device. The user selects the name of the group that is believed to contain the target cell. The grouping device displays the names of all of the I WO 89/04521 PCT/US88/03906 34 cells that are in the group and their assigned tasks (announcer, listener, repeater). The user selects the name of the cell that is believed to be the target cell.
If the selected cell is an announcer, the grouping device prompts the user to activate the announcer by stimulating its input. For example; if the cell is attached to a light switch, the user turns the switch on and off. The cell sends announcement packets to the group. The grouping device listens to the communications channel and discovers the group and member numbers or other codes of the activated announcer.
If the selected cell is a listener cell, the grouping device sends packets to the cell (using the group and member numbers for addressing) commanding it to toggle its output. For example, if the cell controls a light, the light will flash on and off. This allows the user to verify that he has selected the correct cell.
The grouping device sends a packet (using group and member numbers for addressing) to the target cell with a command for the target cell to return its cell ID. The grouping device now knows the target ID and can proceed with the group assignment process.
Querying names is used to find a cell’s ID before or after the cell is installed.
WO 89/04521 PCT/US88/03906 4. Stimulate Group.
This method is used in a network in which group and cell ASCII names have been assigned. The user commands the grouping device to wait for the next group announcement. Then the user stimulates the announcer in the group of interest. For example, if the announcer is a light switch, the user throws the switch. The grouping device hears the announcement packet and extracts the group ID from it.
The user may verify that this group ID is for the desired group by causing the grouping device to send packets to all of the group listeners commanding them to toggle their outputs. The user verifies that it is the desired group by observing the actions of the listener cells (for example, if the group consists of lighting controls, the light flashes).
Now using that group ID, the grouping device broadcasts a packet to the group requesting that each cell reply with its cell name until the cell of interest is found. The user selects that name and the grouping device, knowing that cell’s ID, can proceed with the group assignment process.
If a user elects, the ID of the cell may be verified before proceeding with the grouping procedure, The following procedure 1 is used to verify that the ID is for the target cell.
WO 89/04521 PCT/US88/03906 36 If the selected cell is an announcer, the grouping device prompts the user to activate the announcer by stimulating its input. For example: if tne cell is attached to a light switch, the user turns the switch on and off. The grouping device is then able to discover the group address and member number of the cell.
If the selected cell is a listener, the grouping device sends packets to the cell (using the group and member numbers, for addressing) commanding it to toggle its output. For example, if the cell controls a light, the light will flash on and off. This allows the user to verify that he has selected the correct cell.
Stimulate Announcer.
This method is used in a network in which no group or cell ASCII names have been assigned but announcers and listeners have been assigned. The grouping device sends a packet to all cells in the network commanding each announcer to broadcast a packet containing its ID the next time it is stimulated. The grouping device the,: prompts the user to stimulate the announcer by activating its sensed device; for instance, turn on a light switch for a light switch announcer. Since the user will stimulate only one announcer, the grouping device will receive only one packet with a cell ID.
1 WO 89/04521 PCT/US88/03906 37 There is a chance that another announcer cell will be stimulated at the same time. Perhaps someone else throws a light switch or a temperature sensor detects a temperature change. The user may want to verify that the ID received is for the correct cell. To verify that the cell ID is the correct one, the user goes through the announcer stimulation process a second time and verifies that the same results occur.
6. Toggle Listener This method is used in a network in which no group or cell names have been assigned. The grouping device broadcasts a packet that queries cells that are listeners to reply with their ID.
The grouping device needs to limit the number of cells replying so the packet contains an ID bit mask to limit replies to a subset of the possible cell IDs. When the grouping device has developed a list of listener IDs, it allows the user to toggle each listener, causing the listener cell to turn its output on and off. The user continues through the list of listener cells until he observes the target cell toggling its output, The user has then identified the cell to the grouping device and it can proceed with the grouping operation.
WO 89/04521 PCT/US88/03906 38 D. PACKET FORMAT Each packet transmitted by a cell contains numerous fields.
For example, a format used for group announcements is shown in Figure 6. Other packet formats are set forth in Appendix A.
Each packet begins with a preamble used for synchronizing the receiving cells’ input circuitry (bit synch). The particular preamble code used in the currently preferred embodiment is described as part of the three-of-six combinatorial codes (Figure A flag field of 6 bits begins and ends each of the packets. The flag field code is also described in Figure 9.
As currently preferred, each of the cells reads-in the entire packet, does a cyclic redundancy code (CRC) calculation on the packet except for the contention timer field and compares that result with the CRC field of the received packet. The ALU 102 of Figure 12 has hardvwre for calculating the packet CRC and CRC registers 130 for storing intermediate results. If the packet CRC cannot be verified for an incoming packet, the packet is discarded. The packet CRC field is 16 bits as calculated, then converted into 24 bit fields for transmission in a 3-of-6 code using the encoding of Figure 9. (For the remainder of discussion of packet fields in this section, the field length is described prior to encoding with the 3-of-6 combinatorial codes of Figure In WO 89/04521 PCT/US88/03906 39 the currently preferred embodiment the CRC is a CCITT standard algorithm
(X
16 +X 1 2 X 5 The system ID is a 32 bit field as currently preferred. The other 16 bits of the 48 bit system ID are included in the CRC calculation but not transmitted as part f the packet (Figure 29).
The link address field is a 48 bit field. When this field is all zeroes the packet is interpreted as a system wide broadcast which is acted upon by all the cells. For instance, a probe packet h&r arn zero field for the link address. Group addresses are contained within the link address. For group addresses the first 38 bits are zero and the remaining 10 bits contain the group address. (The cell ID numbers assigned at the factory mentioned Iearlier range from 1024 to 248 since 210 addresses are reserved for groups.) The link address, in some cases, is an individual’s cell’s address. (For example, when a cell is being assigned the task of repeater or listener.) The contention timer is a 10 bit field with an additional 6 bits for a CRC field (or other check sum) used to verify the bits of the timer field. Each cell which repeats a packet operates upon this field if the cell must wait to transmit the packet. If I ‘packets are being transmitted by other cells a cell must wait to i WO 89/04521 PCT/US88/03906 transmit its packet, the time it waits is indicated by counting down the contention timer field. The rate at which this field is counted down can be programmed in a cell and this rate is a function of the type of network. The field starts with a constant which may be selected by the type of network. Each cell repeating the packet counts down from the number in the field at the time the packet is received. Therefore, if a packet is repeated four times and if each of the four cells involved wait for transmitting, the number in the contention field reflects the sum of the times waited subtracted from a constant all ones).
When the contention timer field reaches all zeroes, the cell waiting to transmit the packet discards the packet rather than transmit it. This prevents older packets from arriving and being interpreted as being a new packet.
As mentioned, the contention timer has its own 6 bit CRC field. If the contention timer field were included ‘n the packet CRC, the packet CRC could not be computec, until a packet could actually be transmitted. This would require many calculations in the last few microseconds before a transmission. To avoid this problem a separate CPC field is used for the contention timer field. If the contention timer field cannot be verified by its 6 bit CRC, the packet is discarded.
WO 89/04521 PC-/US88/03906 41 The hop count field records the number of hiops or retransmissions that a packet takes before arriving at its destination. This 4 bit field starts with a number which is the maximum number of retransmissions allowed for a particular packet and is decremented by each cel! repeating a packet. For example, in a packet originated by a group announcer the starting “hop” count is the maximum number of retransmissions that the packet must undergo to reach all of the cells in a group. When this field becomes all zeroes, the packet is discarded by the cell, rather than being retransmitted Therefore, 16 hops or retransmissions is the limit as currently implemented.
The link control fi6ld provides the link protocol and consists of 8 bits. This field is discussed in a subsequent section covering other layers of the protocol.
The random/pseudo random number field contains an 8 bit random number which is generated for each packet by the cell originally transmitting the packet. This number is not regenerated when a packet is repeated. This number is used as will be explained in conjunction with Figure 8 to limit rebroadcasting of probe packets; it also may be used in conjunction with encryption where the entire packet is to be encrypted.
WO 89/04521 PCT/USS&/03906 42 The network control field (4 bits) indicates routing type or packet type, for instarice, network control, group message, probe message, etc.
The source address field (variable size) contains, by way of example, the 48 bit ID number of the ceii originating a packet.
For a probe packet this field contains the ID number of the announcer. For an acknowledgement the field contains the ID of the listener. For a packet addressed to a group, this field contains the source cell’s group member number.
The destination list is described in conjunction with Figure 7.
The message field is variable in length and contains the particular message being transmitted by the packet. Typical messages are contained in Appendix B. In the case of a probe packet the field includes the routing; that is, each cell repeating includes its ID number to this field. The messages, once a group is formed, will, for instance, is used by announcer 60 to tell listener 65 to turn-on a light, etc.
The encryption field, when used, contains 16 bits used to verify the authenticity of an encrypted packet typically this i portion of a packet is not changed when a packet is repeated.
Well-known encryption techniques may be used.
WO 89/04521 pCT/US88/03906 43 The bracket 99 of Figure 6 represents the portion of a packet which remains unaltered when a packet is repeated. These fields are used to limit repeating as will be described in conjunction with Figure 8.
The destination list field of the packet of Figure 6 is shown f in Figure 7. The destination list begins with a 4 bit field which indicates the number of members in a group designated to receive a message in the packet. Therefore the packet can be directed to up to 16 members of a group. The number of each of the members within the group is then transmitted in subsequent 8 bit fields.
The group number contained in the link address and member number contained in the destination list forms an address used to convey messages once the group is formed. If the destination number is zero, the packet is addressed to all members of the i 15 group. For some packet types this field contains the ID of the receiving cell (see Appe~ndix A).
E. MECHANISM FOR PREVENTING REBROADCASTING OF CERTAIN PACKETS As previously meritioned, the probe packets are repeated only once by each of the cells after the packet is initially WO 89/04521 PCT/US88/03906 44 broadcast. A special mechanism programmed into each of the cells allows the cells to recognize packets which it has recently repeated.
First, it should be recalled that as each cell transmits, or retransmits a packet, it calculates a packet CRC field which precedes the end flag. For packets that are repeated, a new CRC is needed since at least the hop count will change, requiring a new packet CRC field for the packet. This CRC field is different from the CRC field discussed in the next paragraph.
As each packet requiring repeating is received, a repeater CRC number is calculated for the fields extending from the beginning of the link control to the end of the destination list as indicated by bracket 99 of Figure 6. As a cell rebroadcasts a packet it stores the 16 bit repeater CRC results in a circular list of such numbers if the same number is not already stored.
However, the packet is repeated only if the circular list does not contain the repeater CRC results calculated for the field 99.
Therefore, as each packet is received which requires repeating, the CRC is computed for the field 99. This is shown by block 73a of Figure 8. This number is compared with a list of 8 numbers stored within the RAM contained within the cell indicated by block 73b. if the number is not found within the WO 89/04521 PCT/US88/03906 stored numbers, the new repeater CRC results are stored as indicated by block 73c and the packet is repeated. On the other hand, if the number is found then the packet is not repeated. As presently implemented, 8 numbers are stored in a circular list, that is, the oldest numbers are discarded as new ones are computed.
The use of the repeater CRC calculation associated with the field 99 and the use of the circular list wi!l prevent repeating of a previously rebroadcasted packet. Note that even if an announcer continually rebroadcasts the same sequence of messages, for example, as would occur with the continuous turning on and turning off of a light, a cell designated as a repeater will rebroadcast the same message since the packet containing messages appears to be different. This is true because the random number sent with each of the identical messages will presumably be different. However, in the instance where a cell receives the same message included within the same field 99 (same random number), the packet with its message will not be rebroadcast. This is particularly true for probe packets. Thus, for the establishment of groups discussed above, the broadcast probe packets quickly “die out” in the network, otherwise they may echo Ili- I P WO 89/04521 PCT/US88/03906 46 for some period of time, causing unnecessary traffic in the network.
F. THREE-OF-SIX-COMBINATORIAL CODING In many networks using the synchronous transmission of digital data, encoding is employed to embed timing information within the data stream. One widely used encoding method is Manchester coding. Manchester or other coding may be used to encode the packets described above, however, the coding described below is presently preferred.
A three-of-six combinatorial coding is used to encode data for transmission in the presently preferred embodiment. All data is grouped into 4 bit nibbles and for each such nibble, six bits are transmitted. These six bits always have three ones and three zeroes. The transmission of three ones and three zeroes in some combination in every six bits allows the input circuitry of the byte synchronized as will be discussed in connection with the I/O section. Also once synchronized (out of hunt mode) the I transitions in the incoming bit stream are used to maintain synch.
I 20 The righthand column of Figure 9 lists the 20 possible cC cmbinations of 6 bit patterns where 3 of the bits are ones and 3 are zeroes. In the iefthand column, the corresponding 4 bit 1 I
R
WO 89/04521 PCT/US88/03906 pattern assigned to the three-of-six pattern is shown. For example, if the cell is to transmit the nibble 0111, it is converted to the bit segment 010011 before being transmitted.
Similarly, 0000 is converted to 011010 before being transmitted.
When a cell receives the 6 bit patterns, it converts them back to the corresponding 4 bit patterns.
There are 20 three-of-six patterns and only 16 possible 4 bit combinations. Therefore, four three-of-six patterns do not have corresponding 4 bit pattern assignments. The three-of-six pattern 010101 is used as a preamble for all packets. The flags for all packets are 101010. The preamble and flag patterns are particularly good for use by the input circuitry to establish data synchronization since they have repeated transitions at the basic data rate. The two three-of-six patterns not assigned can be used for special conditions and instructions.
Accordingly, a cell prepares a packet generally in integral number of bytes and each nibble is assigned a 6 bit pattern before transmission. The preamble and flags are then added. The circuitry for converting from the 4 bit pattern to the 6 bit patterns and conversely, for converting from the 6 bit patterns to the 4 bit patterns is shown in Figures 14 and WO 89/04521 PCT/US88/03906 48 COMMUNICATION AND CONTROL CELL A. Overview of the Cell Referring to Figure 10, each cell includes a multiprocessor 100, input/output section 107-110, memory 115 and associated timing circuits shown specifically as oscillator 112, and timing generator III. Also shown is a voltage pump 116 used with the memory 115. This cell is realized with ordinary integrated I circuits. By way of example, the multiprocessor 100 may be fabricated using gate array technology, such as described in U.S.
Patent 4,642,487. The preferred embodiment of the cell comprises the use of CMOS technology where the entire cell of Figure 10 is fabricated on a single silicon substrate as an integrated circuit. (The multiprocessor 100 is sometimes referred to in the singular, even though, as will be described, it is a multiprocessor, specifically four processors.) The multiprocessor 100 is a stack oriented processor having four sets of registers 101, providing inputs to an arithmetic logic lA- unit (ALU) 102. The ALU 102 comprises two separate ALU’s in the Spresently preferred embodiment.
WO 89/04521 PCT/US88/03906 49 The memory 115 provides storage for a total of 64KB in the currently preferred embodiment, although this particular size is not critical. One portion of the memory is used for storing instructions (ROM code 115a). The next portion of the memory is a random-access memory 115b which comprises a plurality of ordinary static memory cells (dynamic cells can be used). The third portion of the memory comprises an electrically erasable and electrically programmable read-only memory (EEPROM) 115c.
In the currently preferred embodiment, the EEPROM 115c employs memory devices having floating gates. These devices require a higher voltage (higher than the normal operating voltage) for programming and erasing. This higher potential is provided from an “on-chip” voltage pump 116. The entire address space for memory 115 addressed through the ALU 102a which is one part of the ALU 102.
The ROM 115a stores the routines used to implement the various layers of the protocol discussed in this application. This ROM also stores routines needed for programming the EPROM 115c. The application program for the ceil is stored in ROM 115a and, in general, is a routine which acts as a “state machine” driven by variables in the EEPROM 115c and RAM 115b. RAM 115b stores communications variables and messages, applications WO 89/04521 PCT/US88/03906 variables and “state machine” descriptors. The cell ID, system ID and communications and application parameters group number, member number,’ announcer/repeater/listener assignments) are stored in the EEPROM 115c. The portion of the EEPROM 115c storing the cell ID is “write-protected” that is, once programmed with the cell ID, it cannot be reprogrammed The input/output section of the cell comprises four subsections 107, 108, 109 and II0. Three of these subsections 107, 108 and 109 have leads 103, 104, and 105 respectively for communicating with a network and/or controlling and sensing devices connected to the cell. The remaining subsection 110 has a single select pin 106 which can be used to r’ d in commands such as used to determine the cell’s ID. As presently implemented, the subsection 110 is primarily used for timing and counting. The input/output section is addressed by the processor through a dedicated address space, and hence, in effect appears to the processor as memory space. Each 1/O subsection can be coupled to each cf the subprocessors. This feature, along with the multiprocessor architecture of processor 100, provides for the continuous (non-interrupted) operation of the processor. The I/O section may be fabricated from well-known circuitry; the WO 89/04521 PCT/US88/03906 51 presently preferred embodiment is shown in Figures 17 through 23.
The cell of Figure 10 also includes an oscillator 112 and timing generator III, the latter provides the timing signals particularly needed for the pipelining shown in Figure 13.
Operation at a 16mHz rate for the phases 1-4 of Figure 13 is currently preferred, thus providing a 4mHz minor instruction cycle rate. Other well-known lines associated with the cell of Figure 10 are not shown power).
All of the cell elements associated with Figure 10 are, in the preferred embodiment, incorporated on a single semiconductor chip, as mentioned.
B. PROCESSOR The currently preferred embodiment of the processor 100 is 15 shown in Figure 12 and includes a plurality of registers which communicate with two ALU’s 102a and 102b. (Other processor architectures may be used such as one having a “register” based system, as well as other ALU and memory arrangements.) The address ALU 102a provides addresses for the memory 115 and for accessing the 1/0 subsections. The data ALU 102b provides data i for the memory and I/O section. The memory output in general is WO 89/04521 PCT/US88/03906 52 coupled to the processor registers through registers 146 to DBUS 223.
The 16-bit ABUS 220 provides one input to the address ALU 102a. The base pointer registers 118, effective address registers 119 and the instruction pointer registers 120 are coupled to this bus. (in the lower righthand corner of the symbols used to designate these registers, there is shown an arrow with a designation This is used to indicate that, for example, the base pointer register is 4 deep, more specifically, the base pointer register comprises 4 16-bit registers, one for each processor. This is also true for the effective address registers and the instruction pointer registers.) The BBUS 221 provides up to a 12 bit input to the ALU 102a or an 8 bit ;iput to the data ALU 102b through register 142. The 4 deep top of stack registers 122, stack pointer registers 123, return pointer registers 124 and instruction registers 125 are coupled to the BBUS.
The CBUS 222 provides the other 8-bit input to the ALU 102 through register 143. The CBUS is coupled to the instruction pointer registers 120, the 4 deep top of stack registers 122, the four carry flags 129, and the 4 deep CRC registers 130 and the 4 deep next registers 131.
1 WO 89/04521 PCT/US88/03906 53 The MBUS, coupled to the output of the memory, can receive data from the output of the ALU 102b through register 145b, or from the memory or I/O sections (107-110). This bus through register 146 and the DBUS 223 provides inputs to registers 118, 119, 120, 122, 123, 124, 125, 130, 131 and to the carry flags 129.
There is a 16-bit path 132 from the output of the address ALU 102a to the registers 120. The ALU 102b includes circuitry for performing CRC calculations. This circuitry directly connects with the CRC registers 130 over the bidirectional lines 133. The top of stack registers 122 are connected to the next registers 131 over lines 138. These lines allow the contents of register 122 to be moved into registers 131 or the contents of register 131 to be moved into registers 122. As currently implemented, a bidirectional, (simultaneous) swap of data between these registers is not implemented. Four bits of data from the output of the memory may be returned directly either to the instruction pointer registers 120 or the instruction registers 125 through lines 139.
The pipelining (registers 141,142, 143, 145 and 146) of data and addresses between the registers, ALU, memory and their respective buses is described in conjunction with Figure 13.
L
t WO 89/04521 PCT/US88/03906 54 The data in any one of the stack pointer registers 123 or any one of the return pointer registers 124 may be directly incremented or decremented through circuit 127.
Both ALU’s 102a and 102b can pass either of their inputs to their output terminals, can increment and can add their inputs.
ALU 102b in addition to adding, provides subtracting, shifting, sets carry flags 124 (when appropriate), ANDing, ORing, exclusive ORing and ones complement arithmetic. The ALU 102b in a single step also can combine the contents of next registers 131 and CRC registers 130 (through paths 222 and 133) and combine it with the contents of one of the top of stack registers 122 to provide the next number used in the CRC calculations.
Additionally, ALU 102b performs standard shifting and provides a special nibble feature allowing the lower or higher four bits to be shifted to a higher or lower four bits, respectively. Also, ALU 102b performs a 3-of-6 encoding or decoding described in Section
F.
In the preferred embodiment with a single semiconductor chip for a cell there are basic contact pads on the die for power and ground and all the liO pins A and B and the “read only” pin 106 (subsections 107, 108, 105 and 110, Figure 12). These contact WO 89/04521 PCT/US88/03906 pads are used for attachment to package pins for a basic inexpensive package.
In addition to the basic contact pads additional pads in the presently preferred embodiment will be provided with connections to the ADBUS 224 and the MBUS 225 of Figure 12.
One control contact pad may be provided to disable internal memory. By activating the control contact the internal memory is disabled and the data over ADBUS and MBUS is used by the processors. This allows the use of a memory that is external to the cell. It is assumed that the additional contact pads may not be available for use when the cell is in an inexpensive package.
These additional contacts may be accessed by wafer probe contacts or from pins in packages that have more than the minimum number of pins.
The cell as manufactured requires an initialization program.
At wafer probe time the external memory is used for several purpose, one or which is to test the cell. Another use is to provide a program to write the cell ID into the EEPROM during the manufacturing process. Any necessary EEPROM instructions to allow power up boot when the cell is iater put in use may be added at this time. Initialization programs ad test programs are well-known in the art.
WO 89/04521 PCT/US88/03906 56 C. PROCESSOR OPERATION In general, memory fetches occur when the ALU 102a provides a memory address. The memory address is typically a base address or the like on the ABUS from one of the base points in registers 118, effective address registers 119 or instruction pointer register 120 combined with an offset on the BBUS from the stack pointer register 123, return pointer register 124, top of stack registers 122 or the instruction registers 125 Calculations in the ALU 102b most typically involve one of the top of stack registers 122 (BBUS) and the next registers 131 (CBUS) or data which may be part of an instruction from one of the instruction registers 125.
While in the presently preferred embodiment, the processor operates with the output of the memory being coupled to the DBUS 223 through register 146, the processor could also be implemented with data being coupled directly to the input of ALU 102b. Also, the function performed by some of .he other registers, such as the effective address registers 119 can be performed by other registers, although the use of the effective address registers, and for example, the CRC registers, improve the operation of the processor.
WO 89/04521 PCT/US88/03906 57 In general, for memory addressing, a base pointer is provided by one of the registers 118, 119 or 120 with an offset from one of registers 122, 123, 124 or 125. The address ALU 120a provides these addresses. Also, in general, the ALU 120b operates on the contents of the top of stack and next register; there are exceptions, for example, the instruction register may provide an immediate, input to the ALU 102b. Specific addressing and other instructions are described below.
D. MULTIPROCESSOR OPERATION The processor is effectively a multiprocessor (four processors) because of the multiple registers and the pipelining which will be described in conjunction with Figure 13. As mentioned, one advantage to this multiprocessor operation is that interrupts are not needed, particularly for dealing with input and output signals. The multiprocessor operation is achieved without the use of separate ALUs for each processor. In the currently preferred embodiment, economies of layout are obtained by using two ALUs, (102a and 102b) however, only one of the ALUs operates at any given time. (Note the BBUS provides an input to both ALUs.) Therefore, the multiprocessor operation of the present invention may be obtained using a single ALU.
WO 89/04521 PCT/US88/03906 58 The processing system has four processors sharing an address ALU, a data ALU and memory. A basic minor cycle takes four clock cycles for each processor. The ALUs take one clock cycle and the memory takes one clock cycle. The minor cycles for each processor are offset by one clock cycle so that each processor can access memory and ALUs once each basic minor cycle. Since each processor has its own register set it can run independently at its normal speed. The system thus pipelines four processors in parallel.
Each register of Figure 12 is associated with one of four groups of registers and each group facilitates the multiprocessor operation and is associated with a processor of Figure 13.
Si Each of the four groups includes one base pointer register, effective address register, instruction pointer register, top of stack register, stack pointer register, return pointer register, instruction register, CRC register, next register, and a carry flag.
Each related group of registers corresponds to one of the four processors. Each processor executes instructions in minor cycles, each minor cycle consisting of four clock cycles. During the first clock cycle a processor will gate the appropriate registers onto the ABUS, BBUS and CBUS. In the next clock cycle ]the ALUs will be active generating data from their inputs of the WO 8904521 PCT/US88/03906 59 ABUS, BBUS and CBUS. Memory or I/O will be active during the third clock cycle, with the address coming from the ALU 102a anc’ data either being sourced by memory or the ALU 102b. The fourth and final clock cycle will gate the results from memory or the ALU 102b into the appropriate register via the DBUS.
A processor can be viewed as a wave of data propagating through the sequence described above. At each step the intermediate results are clocked into a set of pipeline registers.
By using these pipeline registers it is possible to separate the individual steps in the sequence and therefore have four steps executing simultaneously. The four processors can operate without interfering with one another even though they share the ALUs, memory, I/O and many control circuits.
The control of a processor including the pipelining is best understood from Figure 11. For each processor there is a 3 bit counter and an instruction register. These are shown in Figure 11 as counters 137a through 137d, each of which is associated with one of the instruction registers 125a through 125d, respectively.
Each of the instruction registers is loaded through the DBUS. As an instruction register is loaded, the instruction is coupled to a PLA 212. This PLA determines from the instruction how many I *minor cycles are required to execute the instruction and a 3 bit WO 89/04521 PCT/US88/03906 binary number is then loaded into the coun* 113a or 113b or 113c or 113d, associated with the instruction register 125a, or 125b, or 125c or 125d being loaded. For instance, for a CALL instruction loaded into instruction register 125c, the binary number 010 (indicating three minor cycles) is loaded into counter 137c. (Up to 8 minor cycles can be used for a given instruction, however, only up to 6 minor cycles are used for any of the instructions in the currently preferred embodiment.) The count value “000” is used to cause a new instruction to be fetched.
The count 3 bits) in a counter and the instruction 12 bits) in its associated instruction register from a 15 bit input to the PLA 136. These 15 bit inputs from each of the respective four sets of count registers and four sets of instruction registers are sequentially coupled to the PLA 136 as will be described. The output of the PLA controls the operation of the processors. More specifically: lines 213 control data flow on the ABUS, BBUS and CBUS; lines 214 control the ALU 102; lines 215 control the memory; (and, as will be described later I/O operation of subsections 107, 108, 109 and 220) and lines 216 control data flow on the DBUS. The specific outputs provided by the PLA 136 for a given instruction is best understood from the instructions set, set forth later in this application. The action taken by the d i, I ,r !i- WO 89/04521 PCT/US88/03906 61 processors to execute each of the instructions is described with the instruction set.
The outputs from the PLA on lines 213 are coupled directly to the devices controlling data flow on the ABUS, BBUS, and CBUS. The signals controlling the ALU are coupled through a one clock phase delay register 217 before being coupled to the ALU via the lines 214. Since all the registers 217 are clocked at the same rate, the register 217 performs delay functions as will be described. Those signals from the PLA 136 used for memory control are coupled through two stages of delay registers 217 before being coupled to the memory, thus the signals on lines 215 are delayed for two clock phases related to the signals on lines 213. The control signals for the DBUS after leaving the PLA 136 are coupled through 3 sets of delay registers 217 before being coupled to the lines 216 and therefore are delayed three clock phases related to those on lines 213. The registers 217 are clocked at a 6mHz rate, thus when the PLA 136 provides output control signals for a given instruction contents of instruction register 125a) the control signals during a first clock phase are coupled to lines 213, during a second clock phase, lines 214; during a third clock phase, 215; and during a fourth clock phase to lines 216. During the first clock phase of each WO 89/04521 PCT/US88/03906 62 instruction cycle, the contents of the counter 137a and the instruction register 125a are coupled to the PLA 136. During the second clock phase, the contents of the counter 137b and instruction register 125b are coupled to the PLA 136 and so on for the third and fourth clock phases.
Assume now that instructions have been loaded into the instruction registers 125a through 125d and the counters 137a through 137d have been loaded with the corresponding binary counts for the minor cycles needed to perform each of the instructions. For example, assume that register 125a is loaded with a CALL instruction and that 010 has been loaded into counter 137a. During a first instruction minor cycle, 010 and the 12 bit instruction for CALL are coupled to the PLA 136. From this 15 bit input PLA 136 provides at its output all the control signals needed to complete the first minor cycle of the CALL instruction four clock phases) fo: the ABUS, BBUS CBUS, the ALU, the memory and the DBUS. Since the system uses pipelining multiprocessing, the control signals on lines 213 used to carry j out the first clock phase of the CALL instruction which is the inputs to the ALUs.(During this first clock phase the other control 1- lines are controlling the ALU, the memory and the DBUS of other processors, for different instructions in the pipelines.)During WO 89/04521 PCT/US88/03906 63 phase 2, the count in counter for 137b and the instruction in register 125b are coupled to the PLA 136. During phase 2, the signals on lines 213 now control the ABUS, BBUS and CBUS inputs to the ALUs for the second processor to carry out the instruction contained in register 125b. During this second clock phase, the signals on lines 214 control the first processor and the ALU to perform the functions needed to carry out the second clock phase of the CALL instruction contained in register 125a. (Note a delay equal to one phase was provided by register 217.) Similarly, during the third phase, the signals on lines 213 control the ABUS, BBUS, and CBUS for the third processor to carry out the instruction contained in register 125c; the signals on lines 214 control the ALU to carry out the instruction contained in register 125b, and the signals on lines 215 control the memory to carry out the instructions in register 125a for the first processor.
And, finally, during the fourth clock phase, the instruction from register 125d, along with the count in counter 137d are coupled to the PLA 136. The signals on lines 213 control the ABUS, BBUS and CBUS to carry out the instruction contained within register 125d fourth processor; the signals on lines 214 control the ALU to carry out the instruction in register 125c for the third processor; the signals on lines 215 control the memory to carry WO 89/04521 PCT/US88/03906 64 out the instruction in register 125b for the second processor; and the signals on lines 216 control the DBUS to carry out the instruction in register 125a for the first processor.
After four cycles of the 16mHz clock the count in register 137a decrements to 001. Each register is decremented on the clock cycle following the use of the contents of the counters contained by the PLA 136. The input to the PLA 136 thus changes even though the instruction within register 125a is the same.
This allows the PLA 136 to provide new output signals needed for the second minor cycle of the CALL instruction. These control signals are rippled through the control through the control lines 213, 214, 215 and 216 as described above. When the count in a counter reaches 000, this is interpreted as an instruction fetch for its associated processor.
Therefore, each of the four processors may simultaneously execute an instruction where each of the instructions has a different number of cycles. The control signals reaching the imaginary line 219 for any given clock cycle represent control signals for four different instructions and for four different processors. For example, the control signals associated with the Xf^ first processor during a first cycle appear on lines 213; during a second cycle on lines 214; during a third cycle on lines 215; and i ;i -L- WO 89/04521 PCT/IJS8/03906 during a fourth cycle on lines 216. The control signals needed by the second processor follow behind; those needed by the third and fourth processors following behind those used by the second processor.
The pipelining of the signals is illustrated in Figure 13.
The multiprocessor operation of the processor 100 of Figure 10 is shown in Figure 13 as four processors, processors I, 2, 3 and 4.
Each one of the groups of registers is associated with one of the processors. The four phases of a single instruction cycle are shown at the top of Figure 13. In Figure 13, registers 101 are used to indicate that the contents from the specific registers called for in an instruction are placed on the ABUS, BBUS and CBUS. The registers are 118, 119 and 120 on the ABUS; 122, 123, 124 and 125 on the BBUS; 120, 122, 129, 130 and 131 on the
CBUS.
During a first phase, signals previously stored in the group I .registers two of them) are gated from the registers onto the ABUS, BBUS and CBUS. While this is occurring, signals associated with the group 2 registers are gated from the registers 141, 142, 143 into the ALU 102a and 102b. This is shown in Figure 13 as processor 2 under the first phase column. Simultaneous signals are gated from registers 145a and 145b into the memory for
I
WO 89/04521 PCT/US88/03906 66 group 3 registers for processor 3. And, finally, during this first phase, signals associated with the group 4 registers are gated from registers 146 onto the DBUS. During the second phase, signals associated with a group I registers are coupled from the ALU to registers 145. The data associated with group 2 registers are coupled to memory. The data associated with the group 3 registers is coupled from the register 146 onto the DBUS. Those associated with the group 4 registers are gated onto the ABUS, BBUS and CBUS And, similarly, during the third and fourth phase of each instruction cycle, this pipelining continues as shown in Figure 13, thus effectively providing four processors.
E. PROCESSOR INSTRUCTIONS In this section each instruction of the processor is set forth, along with the specific registers and memory operations.
Lower case letters are used below to indicate the contents of a register. For example, the contents of the instruction register are shown as The registers and flags are set forth below i with their correlation to Figure 12.
WO 89/04521 PC/US88/03906 FIGURE 12
IDENTIFICATION
ip instruction pointer (14 bits) (fixed range of 0000 3FFF) (not accessible to ROM based programs) i r instruction register (12 bits) (not accessible to ROM based programs) bp base page pointer (14 bits) (fixed range of 8000 -FFFF) (write only) ea effective address pointer (16 bits) (not accessible to ROM basu programs) sp data stack pointer (8 bits) (positive offset from bp, grows down) rp return stack pointer (8 bits) (positive offset from bp, grows up) 120 125 118 119 123 124 i PCT/US88/03906 WO 89/04521
I
i S1.
i| J ltii tos top of data stack (8 bits) 122 next item below top of data stack (8 bits) 131 crc used as scratch or in CRC calculations (8 bits) 130 129 flags carry flags, (1 bit) processor ID (2 bits) The top element of the return stack is also addressable as a register, even though it is physically located in RAM.
!instruction Table
CALL
CALL lib
BR
laaa aaaa aaaa 0000 aaaa aaaa 0010 laaa aaaa Subroutine call Library call Branch Branch on TOS==0 BRZ 0010 0Oaa aaaa WO 89/04521 WO 8904521PCr/US88/ 03906
BRC
CALL interseg ‘1 ~1
LIT
LDC
ALU
RET
0010 llaa aa2a 0011 LLLL LLLL 0000 hhhh hhhh 0101 lffh bbbb 0101 111h bbbb 0101 O0ef ffff 0101 0011 1101 Two word instructions Constant op TOS Load Constant Top of Stack and NEXT Return or Bit set in other instruction Read/Write 1/0 Registei Load, Store Load, Store Load, Store CPU reg Branch on Carry set (Subroutine)
INIOUT
LD,ST bp~ia LD,ST (bp+p)+a 0100 Owrr rrrr 0100 lwaa aaaa 011ip pwaa aaaa 0101 010Ow rrrr LDR,STR r WO 89/04521 PCT/US88/0390 6 For each instruction, the operation, encoding and timing are set forth below in standard C language notation.
CALL Call Procedure Operation: lowbyte (ip); hibyte (ip); ip dest; Encoding: intra-segment: laaa aaaa aaaa dest ip a 1; displacement a is always negative inter-segment: 0011 LLLL LLLL 0000 HHHH HHHH I dest H:L; 16 bit absolute address WO 89/04521 71 library: 0 0 00 aaaa aaaa dest x8000+*(0x8001 a); Timing: CALL type #clocks specific intra-seg 3 2 r+ 1 rp* 0 ir L 15 interseg 4 lobyte 3 hibyte 1 r+ 0 i library 4 PCT/t]S88/03906 table lookup call 7/ memory operation lobyte (ip) hibyte (ip) p *dest) (ea) i+ (ea) *ip lobyte (ip) hibyte (ip) p *dest) WO 89/04521 ‘2 PCT/US88/03906 3 rp++ lobyte (ip) 2 rp++ hibyte (ip) 1 ip =dest 0 ir =*ip BR Branch always Operation: ip =dest; Encoding: 0010 laaa aaaa dest ip a 1; displacement a is sign extended Timing:
I
#clocks specific memory Operation 0 ir *(ip dest) WO 89/04521 WO 8904521PCT/US88/03906 BRC Branch on carry Operation: if CF ip dest; else ip++; Encoding: 0 010 0O1aa a dest =ip a 1;:1* a aa a is, sign extended Timing- #clocks specific memory operation 0 ir *(jp =dest) or 0 ir -7 WO 89/04521 BRZ Branch on TOS==0 Operation: if (tos==O, tos=next, nex else ++ip; Encoding: 0 010 00 dest ip a 1; disp Timing: PCT/US88/03906 t= ip =-dest; aa aaaa )lacement a is sign extended #clocks specific memory operation 1 tos next; next 0 ir *(ip dest) WO 89/04521 WO 89/452 1PCT/US88/03906 or 0 ir LDR Move register to TOS (includes certain indirect, indexed memory reference) Operation: next; if (reg) {next tos; tos reg else {next bp+TOS or next (bp+2p)+TOS Encoding: 0 10 1 0 10 0 r r rr reg r I* see table Timing: #clocks specific memory operation (if (bp~p)+TOS) 4 lobyte(ea) =*(bp+i2p) 3 hibyte(ea) =*(bp+2p+1) (if reg, bp+TOS) 3 2 next if (reg) next tos; 1 if (reg) tos reg else next=bp+TOS, ea+TOS WO 89/04521 7 PCT/US88/03906 76 0 ir Store TOS. to register (includes certain indirect, indexed memory reference)
STR
Operation: if (reg) else next= Encoding: {reg tos; tos next; I {bp+TOS next or (bp+2p)+TOS next 0 10 1 0 1 01 r rr r reg r see table Timing: #clocks (if (bp+p)+TOS) specific memory operation 4 lobyte(ea) *(bp+2p) 3 hibyte(ea) =*(bp+2p+l) if (reg, bp+TOS) 2 if (reg) reg tos; else bp+TOS,ea+TOS =next 1 if (reg) tos next; next 0 ir i) WO 89/04521 Register assignments 0 000 0 010 1 0 0 10 0 01 1 0 10 0 0 10 1 0 11 0 0 1 11 1 00 0 PCT/US88/03906 2 Flags CF x ID1 [DO CRC low byte (high byte in TOS) lowbyte (bp) write next (“OVER” instruction) read highbyte (bp) write tos (“DUP” instruction) I* read sp rp see RPOP, RPUSH (bp+TOS) p+ 0)+TO S) I’ indexed fetch,store indexed indirect 100 1 101(*(bp+2)+TOS) indexed indirect *1 WO 89/04521 WO 8904521PCT/US88/ 03906 1 01 0 1 01 1 p +TO S) indexed indirect indexed indirect RPOP pop return stack Operation: next; next =tos; tos =*rp- Encoding: 0 1 01 0 1 00 1 11 0 Timing: #clocks #clocksspecific memory operation WO 89/04521 P-iT/US88/03906 2 sp– next next =tos; 1 tos r-; 0 ir RPUSH push tos onto return stack Operation: tos next; next Encoding: I
F
-4 0 10 1 01 01 1 (11 0 Timing: #clocks specific memory operation
L
1 IS WO 89104521 pCr/US88/03906 2 tos; 1 tos =next; next 0 ir IN Move 110 register to TOS Operation: next; next tos; tosc reg; Encoding: 01 000 0 r r r r rr Timing: #clocks 3 specific memory operation 2 sp– next 27 WO 89/04521
OUT
Operatic re~ to~ ne Encoding Timing: PCT/US88/ 03906 next =tos; tos reg ir i) Store TOS to 1/O register n: =tos; =next; xt 01 00 01lr r r rr r #clocks specific memory operation 2 reg tos; 1 next; WO 89/04521 WO 8904521PCT/US88/03906 next 0 ir i) LDC load constant (into TOS) Operation: =next; next =tos; tos =constant; 0 10 1 1 1 1H b b bb if constant 0000:bbbb; else constant bbbb:0000 Timing: #clocks specific memory operation 2 =next; next tos;, WO 89/04521 WO 8904521PCT/US88/03906 1 tos constant; 0 ir LID (bp+a) load from base page Operation-.
sp– next nt =tos tos (bp+source); Encoding-.
0100 l0aa aaaa source =aa aaaa Timing: #clocks specific memory operation 3 2 next; next tos; WO 99/04521 PC/US88/03906 84 1 tos =*(bp+source); 0 ir (ip LID (bp+p)+a load indirect (TOS with byte addressed by pointer at bp+offset then indexed by TOS) Operation: *sp next; next =tos tos (*(bp+2p)+offset);, Encoding: t 15 011p p0aa, aaaa offset =aa aaaa Timing: #clocks specific memory operation 4 lobyte(ea) (bp+2p) 3 hibyte(ea) =*(bp+2p+1) 2 PCT/US88/03906 WO 89/04521 2 next; next =tos; 1 tos=*(ea+offset) 0 ir ST (bp+a) store into base page Operation: *(bp+dest) =tos tos =next; next Encoding: 0100 llaa aaaa dest aa aaaa Timing: #clocks specific memory operation 2 *(bp+dest) tos;
A]
WO 89/04521 PCT/US88/03906 1 tos =next; next s) 0 ir ST’ (bp+p)+a store indirect (TOS into byte addressed by pointer at bp+2p offset by a) Qperat ioim *(*(bp+2p)+offset)=tos; tos =next; next Encoding: 0O1l1p pl1a a a aa a offset aa aaaa Timing: #clocks #clocksspecific memory operation -2 WO 89/0452 1 (ALU Gro Operation: if (r= pipe tos swit< PCT/US88/03906 4 lobyte(ea) *(bp+2p) 3 hibyte(ea) =*(bp+2p+1) 2 *(ea+off)=tos 1 tos =next; next 0 ir up I hibyte(ip) *rp-, Iobyte(ip) *rptos; tos op next; :h case 0: next n case 1: next I* internal processor pipeline ~xt; typical unary op typical binary op,~ WO 89/04521 WO 8904521PCT/US88/03906 Encoding: 0 1 01 0O0r f f ff f op =fffff s equal to high order f bit s =(1==unary op), (O==binary op) Op Table: code operation carry state 00000 00001 00010 0001 1 00100 00101 001 00111 01000 tos next tos next carwry next tos next tos carry arith arith arith arith arith carry carry borrow borrow borrow tos next tos AND nextunhne unchanged 7 WO 89/04521 PCT/US88/03906 01001 01010 01011 01100 swap-drop 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 tos OR next tos XOR next unchanged unchanged drop unchanged 01101 unchanged CRC step as! (TOS) asr (TOS) rotate left(tos) rotate right (tos) to 5 3of6 encode unchanged tos7 0 tos7 toso parity(TOS) set if not valid I 7 WO 89/04521 110 110 110 110C ill S 151 150 200 '00 01 110 11l 00 01 11 Isi (TOS) lsr (TOS) shift left b shift left lb swap tos (NOP) NOT(TOS) 3of6 decode PCT/US88/03906 '4 '4 specific memory operation 3 hibyte(ip) *p- 2 lobyte(ip) 1 tos =alu output 0 ir 4 hibyte(ip) *rp-- 3 lobyte(ip) 2 tos alu output #clocks 2 (4) (if (if r==1) 3 (if r==1) (if r==1) WO 89/04521 i -7_ PCT/US88/03906 1 next 0 ir SWAP special case The exchange of TOS with NEXT is a special case of the ALU ops using the direct data path between TOS and NEXT. The NEXT register receives a cc of the TOS via a pipeline register, prior to TOS being loaded with the conter of NEXT (non-simultaneous transfer). NOP Operation: ii Encoding: short 0010 1000 0000 0101 0001 1101 long WO 89/04521 WO 8904521PCT/US88/03906 Timing: #clocks specific memory operation short (BR +1) 0 ir long tos tos ir RET* return from subroutine Operation: hibyte(ip) lobyte(ip) *rprp-- Encoding: 0 1 01 0 0 11 1 10 1 Timing: WO 89/04521 WO 89/452 1PC/US88/03906 #clocks specific memory operation 3 hibyte(ip) 2 lobyte(ip) 1 tos =tos 0 ir LITERAL Group Operation: tos tos op constant; Encoding: 01 01 1lff H op ff cc c if constant 0000:cccc else constant cccc:0000 Op Table: code operation carry state L6. "ri WO 89/04521 PCT/US88/03906 tos constant tos constant tos AND constant constant (see LDC) arith carry arith borrow Timing: #clocks specific memory operation 2 1 tos alu output 0 ir F. THREE-OF-SIX CIRCUITRY As previously mentioned, the ALU 102b contains means for encoding four bit nibbles into six bit words for transmission (encoder of Figure 14) and for decoding six bit words into the four bit nibbles (decoder of Figure 15). Both the encoder and decoder use hardwired logic permitting the conversion to be performed very quickly in both directions. Moreover, there is a circuit shown in Figure 16 to verify that each six bit word received by the cell is in fact a three-of-six code, that is, three zeroes and three ones (Figure 9). I-I WO 89/04521 PCT/US88/03906 Referring to Figure 14 the register 142 is illustrated with four bits of th register containing data DO through D3. If the ALU is commanded to encode this data, the resultant six bits will be coupled into the latch register145b. To obtain the conversion shown in Figure 9, the DO bit is directly coupled into first stage of register 145b and becomes E0, the encoded bit. Also, the bit D3 is directly coupled into the register and becomes E5. Each of the remaining bits E1 through E4 are provided by the logic circuits 153 through 150, respectively. Each of these logic circuits are coupled to receive DO, D1, D2 and D3. Each logic circuit contains ordinary gates which implement the equation shown within its respective block. These equations are shown in standard language logical AND, logical NOT, and logical OR.) These equations can be implemented with ordinary gates. The decoder of Figure 15 is shown in a similar format. This time the six bits of the encoded data are shown in register 142. The decoded four bits of data are shown in the register145. To implement the pattern assignment shown in Figure 9, the E0 bit is coupled directly to the register 145 and becomes DO. The E5 bit is coupled directly to the register145 and becomes the D3 bit. Logic circuits 154 and 155 provide the bits D2 and D1, respectively. Circuit 154 is coupled to receive the bits E0, E3, E4 I WO 89/04521 PCT/US88/03906 96 and E5 while the circuit 155 receives E0, El, E3, and E5 (E2 is not used to provide the Do through D3 bits.) (Some of the six bit patterns are not used and others are used for synchrorhization and thus do not require conversion into a data nibble.) The circuits 154 and 155 are constructed from ordinary logic gates and implement the equations shown. The symbol A represents the exclusive OR function in the equations. The circuit of Figure 16, as mentioned, verifies that the received six bit words do contain three zeroes and three ones. The encoded words are shown coupled from the top of stack register 122 into the two full adders, 157 and 158. These adder stages are contained within the ALU 102b. Each adder receives an X, Y and carry input and provides a sum and carry output. These ordinary adder stages are each coupled to receive one bit of the encoded word as shown. (Any coupling of each bit to any input of address 157 and 158 may be used.) The carry outputs of the adders 157 and 158 are coupled to the exclusive OR gate 159; the sum outputs of the adders 157 and158 are coupled to the exclusive OR gate 160. The output of the gates 159 and 160 are coupled to the input terminals of an AND gate 161. If the output of this AND gate is in its high state the word in the register 102 contains three ones and three zeroes. Otherwise, the output of r:. WO 89/04521 PCT/fUS88/03906 97 the gate 161 is in its low state (abort condition). The incoming packets are checked to determine that each six bit word is valid, while it is decoded into the four bit nibbles. IV. INPUT/OUTPUT SECTION A. General The I/O section includes a plurality of circuit elements such as a ramp generator, counter, comparator, etc., which are interconnected in different configurations under software control. Examples of this are shown below for the analog-todigital (A to D) and digital-to-analog (D to A) operations. These elements with their software configurable interconnections provide great flexilibity for the cell, allowing it to perform many tasks. The entire I/O section is preferably fabricated on the same "chip" which includes the processor. B. Buffer Section As shown in Figure 10 and previously discussed, each of the cells includes four input/output I/O subsections; three of the subsections 107, 108, and 109 each have a pair of leads, identified as Pin A and Pin B. The fourth subsection 110 has a single "read only" pin 106. Any of the four subsections can communicate with any of the four subprocessors. As shown in WO 89/04521 PCT/US88/03906 98 Figure 12, this is easily implemented by connecting the address bus (ADBUS) and the memory bus (MBUS) to each of the four I/O subsections. Use of the MBUS through the register 146 to the DBUS allows the I/O subsections to communicate with the processor registers. Each Pin A and Pin B can receive and provide TTL level signals and is tristated. In the currently preferred embodiment, each pin can sink and source approximately 40milliamps (except for pin 106). All the Pin A's can be programmed to provide an analog output signal and a digital-to-analog converter is included in three of the I/O subsections 107, 108 and 109 to provide an analog output on Pin B. An analog input signal on any of the Pin B's can be converted to a digital count since three of the I/O subsections include A to D converters coupled to these pins. Each pin pair (Pin A and Pin B) can operate as a differential amplifier for input signals, a differential receiver, and a differential transmitter and a differential voltage comparator. The I/O subsections can be used to perform many different functions, from simple switching to, by way of example, having two pin pairs coupled to drive the windings of a stepping motor. The circuits shown in Figures 17-23 are repeated in subsections 107, 108 and 109. Those circuits associated with WO 89/04521 PCT/US88/03906 99 Pin A and Pin B (such as the buffer sections of Figure 17) are not fully contained in the I/O subsection 110. Only sufficient buffering to allow data to be read on Pin 106 is needed. Referring to the I/O buffer section of Figure 17, outgoing i 4 data is coupled to Pin A through the buffer 163. Similarly, outgoing data is coupled to Pin B through the buffer 164 after the data passes through the I/O control switch 165. This outgoing data, by way of example, is coupled to Pin A from the register 206 of Figure 23 through gate 208 of Figure 19. The control switch 165 is used to enable outputs to Pin A through the buffer 163, when enable A (EN.A) is high (line 166). Moreover, the switch enables the output to Pin B when enable B (EN.B) is high (line 167) and enables outputs to both pins (with the output to Pin B being inverted) when enable RS-485 is high (line 168). The outgoing analog signal to Pin A is provided through the switch 175 when the enable analog output signal is high. Incoming signals to Pin A are coupled to one input terminal of the differential amplifier 169. The other terminal of this signal receives a reference potential 2.5 volts). This A 20 amplifier also includes the commonly used hysteresis mode to i prevent detection of noise. This mode is activated when the enable hysteresis (Pin A) signal coupled to amplifier 169 is high. WO 89/04521 PCT/US88/03906 100 The output of amplifier 169 is coupled to a transition detection circuit 171 which simply detects each transition, that is, a zero to one, or one to zero. The inputs to Pin B are coupled to one terminal of a differential amplifier 170 which may be identical to amplifier 169. The amplifier 170 receives the enable hysteresis (Pin B) signal. The other input to amplifier 170 (line 176) can be coupled to receive one of several signals. It can receive a DC signal used for voltage comparisons, a ramp which shall be discussed later, the signal on Pin A for differential sensing, or a reference potential 2.5 volts). The output of the amplifer 170 can be inverted through the exclusive OR gate 177 for some modes of operation. A transition detector 172 is associated with the Pin B inputs, again to detect transitions of zero to one or one to zero. C. I/O Counting/Timing Each of the cells includes a timing generator (RC oscillator) ki for providing a 16mHz signal. This signal is connected to a rate multiplier 178 contained in the I/O section (Figure 18): The multiplier 178 provides output frequencies to each I/O j 20 subsection. This multiplier provides a frequency fo equal to: fT o 16MhZ X (LOADED VALUE) 216 WO 89/04521 PCT/US88/03906 101 The loaded value is a 16 bit word loaded into a register of a rate multiplier 178. The rate multiplier comprises four 16-bit registers and a 16-bit counter chain. Four logic circuits allow selection of four different output signals, one for each subsection. Two bus cycles (8 bits each) are used to load the 16 bit words into the register of the rate multiplier 178. As can be seen from the above equation, a relatively wide range of output frequencies can be generated. These frequencies are used for many different functions as will be described including bit synchronization. The output of the multiplier 178 in each of the subsection is ccupled to an 8 bit counter 179. The counter can be initially loaded from a counter load register 180 from the data bus of the processors. This register can, for example, receive data from a program. The count in the counter is coupled to a register 181 and to a comparator 182. The comparator 182 also senses the 8 bits in a register 183. The contents of this register are also loaded from the data bus of the processors. When a match between the contents in the counter and the contents of register 183 is detected by comparator 182; the comparator provides an Sevent signal to the state machine of Figure 19 (input to multiplexers 190 and 191) The contents of the counter 179 can WO 89/04521 PCT/US88/03906 102 be latched into register 181 upon receipt of a signal from the state machine (output of the execution register 198 of Figure 19). The same execution register 198 can cause the counter 179 to be loaded from register 180. When the counter reaches a full count (terminal count) a signal is coupled to the state machine of Figure 19 (input to multiplexers 190 and 191). D. I/O CONTROL AND STATE MACHINE Referring to Figure 19, the processor MBUS communicates with registers 185 and 186 both of which perform masking functions. Three bits of the register 185 control th, selection of one of the five lines coupled to the multiplexer 190; similarly, 3 bits of the register 186 control the selection of one of the five lines coupled to the input of the multiplexer 191. The output of the masking registers 185 and 186 are coupled to a multiplexer 187. The five bits from the multiplexer 187 are coupled to a register 1'98. Each of these bits define a different function which is, in effect, executed by the state machine. Specifically, the bits control load counter,latch count, enable ramp switch, pulse Pin and pulse Pin B. The multiplexers 190 and 191 both receive the terminal count signal from counter 179 of Figure 18, the compare signal WO 89/04521 PCT/US88/03906 103 from comparator 182, the ramp start signal from the ramp generator 200 of Figure 20, and the transition A and B signals from the transition detectors 171 and 172, respectively of Figure 17. The one bit output from each of the multiplexers 190 and 191 is coupled to an OR gate 188. This OR gate is biased in that if an output occurs simultaneously from both multiplexers 190 and 191, priority is given to multiplexer 190. The output of the multiplexer 190 controls the multiplexer 187 with the signal identified as "which event". This signal is also stored in the 3x3 first-in, first-out (FIFO) buffer 199. This signal indicates which MUX 190 or 191 has received an event and this data is stored along with the inputs to Pin A and Pin B (Figure 17) in the FIFO 199. The state machine for each of the I/O subsections comprises 4 D-type flip-flops connected in series as shown in Figure 19 within the dotted line 189. The flip-flops 194 and 196 receive the 8mHz signal whereas the flip-flops 193 and 195 receive the complement of this timing signal. The clocking signal (CLK) is obtained from the Q output of the flip-flop 194 and is coupled to register 198 and FIFO 199. The clear signal received from the Q terminal of flip-flop 196 is coupled to the register 198. WO 89/04521 PCT/US88/03906 104 In operation, the masking registers 185 and 186 are loaded under software contro). The bits from register 185, for instance, cause the selection of one of the input lines to multiplexer 190, for example, terminal count. Then the circuit of Figure 19 waits for the signal terminal count. When the signal terminal count occurs the state machine begins operating and the five bits of data from register 185 are connected through multiplexer 187 into register 198. The state machine causes an output to occur on one of the lines from register 198 causing, for example, a pulse to be generated on pin A. Similarly, a word in register 186 can be used to cause, again by way of example, the counter to be loaded. The flip-flops 203 and 204 are clocked by the output of register 198. These flip-flops allow the output signal to be controlled. The OR gate 208 permits data from a shift register 206 of Figure 23 to be coupled to Pin A. This register is discussed later. The low order 6 bits of the ADBUS are input to decoders in the I/O subsections 107, 108, 109 and 110 of FIgure 12. Two of the bits are used to select a specific I/O element and the rest are decoded to control an operation. The PLA 136 of Figure 11 has generalized outputs 215 connected in parallel to all I/O I subsections 107, 108, 109 and 110 to select the ABUS clock cycle WO 89/04521 PCT/US88/03906 105 for data to be used for controlling operation of the I/O subsections. E. ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERSION Referring first to Figure 20, the I/O subsystem includes a ramp generator 200 which continually generates ramps of a known period. The output of the ramp generator is buffered through buffer 201 and selected by switch 202. The switch, as will be described, is selected at some count (time) following the start of each ramp, thereby coupling the same potential to the capacitor 203. This capacitor becomes charged and potential is coupled through buffer 204 to Pin A when the switch 175 is closed. (Switch 175 is shown in Figure 17.) The switch 202, capacitor 203, and buffer 204 act as a sample and hold means. In Figure 21 several of the circuit elements previously described have been redrawn to describe how a digital to analog conversion occurs and to show how the circuit elements of the I/O subsection can be reconfigured through software by the I/O control and state machine of Figure 19 to perform different functions. For a digital to analog conversion an appropriate frequency (fo) is selected from the rate multiplier 178 or counter 179 of WO 89/04521 PCT/US88/03906 106 Figure 18, which corresponds to the period of the ramps being generated by ramp generator 200 (Figure 21). A digital value which corresponds to the desired output analog signal is loaded into the register 183. When a ramp begins the ramp start signal is coupled through the state machine 189 of Figure 19 (for example, through the multiplexer 190) and the flip-flops). This causes the counter 179 to be cleared all zeroes). The fo signal then counts into counter 179. The comparator 182 then compares the contents of the counter179 with the contents of signal is applied through multiplexer 191 again causing the state machine to be activated as indicated by "SMi" 189 and the switch 202 of the sample and hold means to close. For each ramp generated by the ramp generator, the ramp switch 202 is closed for 500 nanoseconds) causing the capacitor 203 to be charged to a DC voltage which corresponds to the digital number placed in register 183. One manner in which the A-D conversion can be performed is shown in Figure 22. The input analog signal is applied to one input terminal of the differential amplifier 170. The ramp is applied to the other terminal of the amplifier 170. Initially, when the ramp is started, the state machine 189 causes the WO 89/04521 PCT/US88/03906 107 counter 179 to be loaded from register 180 all zeroes). The counter is clocked at a frequency (fo) suitable to the period of the ramps. When the transition detection 172 detects that the potential on Pin B and the ramp have the same potential, the state machine 189 causes the count in the counter 179 to be latched into latch 181. The digital word in latch 181 corresponds to the DC potential on Pin B, thereby providing the analog to digital conversion. F I/O COMMUNICATIONS As previously discussed, for instance, in conjunction with Figure 1, each cell can transmit data over communications lines or other links. The cells in a subchannel transmit data at the same rate typically determined by the communications link being employed, for example, 10K BPS in a noisy environment such as for power lines. In the currently preferred embodiment, the cells do not have crystal oscillators but rather rely upon RC oscillators. The latter are not particularly stable and frequency variations occur both with temperature and as a result of processing variations. Moreover, there is no synchronization provided between cells, thus, each cell must provide synchronization to the incoming data in order to property read the data. One feature of all cells is that they detect and store the i WO 89/04521 PCT/US88/03906 108 frequency of the incoming data and when acknowledging a packet they can transmit at the frequency that the original packet was transmitted. This reduces the burden on cells to synchronize when they are receiving an acknowledgement packet. Referring to Figure 23 during the hunt mode, an I/O subsection is hunting for data. During this mode, the rate multiplier provides a frequency (fo) to the counter 179 and a number is loaded into register 183 from the MBUS. Matches occur and are detected by comparator 182 at a frequency corresponding to the expected incoming data rate. Specifically, the terminal count of counter 179 is synchronized to the transitions. As indicated by the dotted line 201, the processor continually searches for transitions from the transition detectors 171 and 172 of Figure 17. When transitions occur, the processor determines whether the transitions occurred before or after the terminal count and then adjusts the frequency (fo) until the terminal count occurs at the same time that the transitions are detected. This frequency is the shifting rate for the shift register 206. (The steps performed by the processor are shown in Figure 23 as blocks 210 and 211.) The number loaded into register 183 provides a phase shift between the time at which transitions occur and the ideal time to shift data in the register WO 89/04521 PCT/US88/03906 109 206. This prevents the shifting of data during transitions. Note counter 179 is reloaded all zeroes) each time it reaches a terminal count. When bit synchronization occurs, rate needed for the synchronization (16 bit word) is stored within the processor memory and used to set the transmit frequency when acknowledging the packet for which the rate was developed. This stored bit rate as discussed later is used in the contention backoff algorithm allowing slot periods to be matched to the last received bit rate. The comparator output is used as a shift rate for a six bit shift register 206. During the hunt mode, the data from Pin B is continually shifted through register 206. The preamble to a packet as shown in Figure 9 (010101-bit synch) is shifted along the shift register 206 and the shifting rate adjusted so that synchronization/lock occurs. When the packet beginning flag appears (nibble synch-101010) the last two stages of the register 206 will contain ones and this will be detected by the AND gate 207. A binary one at the output of gate 207 ends the hunt mode and provides the nibble synchronization. When this occurs, the data is clocked out of the shift register (6 bits) into a data latch 235 and from there the data can be clocked into the WO 89/04521 PCT/US88/03906 110 processor and converted into 4 bit nibbles. Another circuit means is present to detect all zeroes in the shift register 206. When this occurs, the processor and shift register return to the hunt mode. The number loaded into register 183 provides a phase shift between the time at which transitions occur and the ideal time to shift data in and out of the register 206. This prevents the shifting of data during transitions. Data which is to be transmitted is transferred into the data register 205. (Note only 6 bits representing a four bit nibble are transferred into the data register 205.) These 6 bits are then transferred into the shift register 206 and shifted out at the shift rate. As mentioned, if the packet being shifted out represents an acknowledgement, the shift rate corresponds to the rate of the incoming data. If the outgoing packet on the other hand is being sent to several cells, the shift rate is the nominal shift rate for the transmitting cell. (Note that in Figure 23, data is shown leaving the register to only Pin A. For differential modes, the complement of Pin A is driven onto Pin B and other variations are possible.) WO 89/04521 PCT/US88/03906 111 G. 1/O REGISTERS AND RESOURCE SHARING Each I/O subsection has a number of registers w'hich have bidirectional connections to the MBUS. These registers are in the I/O subsections 107, 108, 109 and 110 of Figure 12. The reading and writing of these registers under processor program control configures the I/O subsystems for proper operation. Figure 12 illustrates the four I/O subsections 107, 108, 109 and 110 and shows the connections to the low eight bits of the MBUS and the low six bits of ADBUS. Two ADBUS bits select one of the four I/O units and the remaining four bits are decoded to select one of the I/O control and status registers (described below) of that subsection. There are two lines from the PLA 136 of Figure 11 to control the action of the I/O subsections. One line is "Read" and the other line is "Write". When appropriate these lines are active on phase 3 of the clock cycles. The iO0 registers, functions and bit definitions are described below: WRITE REGISTERS: (Controlled by the "Write" line). Event 0 Configuration Register:register, masking, 185 Figure 19: Bit 0: Upon event Toggle pin A Bit 1: Upon event Toggle pin B Bit 2: Upon event Latch 8 bit count Bit 3: Upon event close Ramp switch (momentary on) WO 89/04521 PCT/US88/03906 112 Bit 4: Upon event Load 8 bit counter Bits5-7: Input Multiplexer: MUX 190, Figure 19. 000 Transition on pin A 001 Transition on pin B 010 Terminal Count event 011 Count Compare event 100 Ramp start event 101 Pin B compare event Event 1 Configuration Register: masking register 186,Figure 19; Bit 0: Upon event Toggle pin A Bit 1: Upon event Toggle pin B Bit 2: Upon event Latch 8 bit count Bit 3: Upon event close Ramp switch (momentary on) Bit 4: Upon event Load 8 bit counter Bits5-7: Input Multiplexer: MUX 191, Figure 19 000 Transition on pin A 001 Transition on pin B 010 Terminal Count event 011 Count Compare event 100 Ramp start event 101 Pin B compare event I/O REGISTERS AND RESOURCE SHARING 8 Bit Counter Load Register: Counter load register 180; Figure 18 Bits 0-7 count Write Communications Data Out REgister: data register 205, Figure 23; Bits 0-7 data Write Communications Configuration Register: (not shown) (loaded from MBUS) Used to configure the communications subsystem for 1' i i ii I LI WO 89/04521 PCT/US88/03906 113 transmit Bit 0: 0 Bit 1: Bit 2: Bit 3: Bit 4: Bit 5: Bit 6: Bit 7; and receive functions. Receive, 1 Transmit NOP NOP Shift Register enable Enter Hunt Mode NOP NOP NOP Output Configuration Register 0: (not shown) (loaded from MBUS) Used for setting analog and digital pin configurations. Bit 0: Enable pin A analog out Bit 1: Enable pin A digital out Bit 2: Enable pin A pullup Bit 3: Enable pin A pulldown Bit 4: Enable pin B inversion Bit 5: Enable pin B digital out Bit 6: Enable pin B pullup Bit 7: Enable pin B pulldown Output Configuration Register 1: (now shown) (loaded from MBUS) Used for enable and compare functions. Bit 0: Enable 8 bit counter Bit 1: Compare pin B to TTL reference Bit 2: Compare pin B to adjustable D.C reference Bit 3: Compare pin B to Ramp voltage Bit 4: Compare pin B to pin A Bit 5: Enable RS-485 driver Bit 6: Enable input hysteresis on pin A Bit 7: Enable input hysteresis on pin B Output Configuration Register 2: (not shown) (loaded from MBUS) Used for setting pin logic levels. Bit 0: Execute, load 8 bit counter with value in 8 bit Counter Load Register WO 89/04521 PCT/US88/03906 114 Bit 1: Bit 2: Bit 3: Bit 4: Set pin A to logic level 1 Set pin A to logic level 0 Set pin B to logic level 1 Set pin B to logic level 0 Lower Half of Rate Multiplier Register: Figure 18 Lower byte of rate multiplier rate multiplier 178, Upper Half of Rate Multiplier Register: rate multiplier 178, Figure 18 8 Bit Compare Load Register: compare load register 183, Figure 18 Byte for comparison READ REGISTERS: (controlled by "Read" line); Read Event Bit 0: Bit 1: Bit 2: FIFO: FIFO 199, Figure 19 0=Event 1 occurred 1=Event 0 occurred Pin A level during occurrence of event Pin B level during occurrence of event Read I/O Condition Register: I/O Status: Bit 0: Input pin A Bit 1: Input pin B Bit 2: 1=ramp compare Bit 3: NOP Bit 4: NOP Bit 5: 1=FIFO has data 0-FIFO empty 8 Bit Counter Latch: register 181, Figure 18 Count Byte WO 89/04521 PCT/US88/03906 115 Communications Data Register: data latch 235, Figure 23 Data Byte Communications Status Register: (not shown) (reads onto MBUS) Bit 0: Receive mode: 1=data available in shift register Transmit mode: 0=transmit latch ready Bit 1: 1=in Hunt Modi from Figure 23 WO 89/04521 PCT/US88/03906 116 RESOURCE SHARING: In the presently preferred embodiment there are five resources shared among the processors. They are the EEPROM and the four 1/O subsections. A hardware "Semaphore Register" (SR) and five words in RAM are used in controlling resource sharing. Figure 30 illustrates how the multiprocessors share common resources. The SR 95 of Figure 12 reads and writes to bit 0 of the MBUS. Each RAM word will contain one state: Idle, Proc.#1, Proc.#2, Proc. #3 or Proc. A processor may interrogate a RAM location before assignment of resource to see if a resource is busy. If the resource is not assigned it will then access the Semaphore Register as described below. (Alternately, a processor may, skip the initial RAM interrogation step and check the RAM location after it has accessed the Semaphore Register). If the resource already busy the processor must clear the Semaphore Register to and wait to try again. If the resource is "Idle" the processor assigns a resource by changing the state of the RAM Register from "Idle" to "Proc.#x" and then clearing the Semaphore Register to When the processor is finished with the resource, clears the RAM location to "Idle". The SR is a one bit hardware register. During phase 3 of its respective cycle, if required, each processor may access the SR. In time sequence, this means that the processors may access the SR 295 WO 89/04521 PCT/US88/03906 117 once on one of four successive clock cycles phases). The SR 295 is normally set to In Figure 30, processors #1 and #3 are not requesting use of the SR 295 Processor #2 is shown accessing the If it receives a at the beginning of the cycle it knows nothing is being currently assigned or cleared and it sets the appropriate RAM location and if it contains "Idle" the processor inserts its "Proc. thus assigning the resource and then "clears" the SR to If the processor found that another processor was using the shared resource it does not assign its Proc. and it then "clears" the SR to In this event it must wait and try again. Some operations such as those on the EEPROM may take many clock cycles so the processor should "assign" the RAM register but release the SR 295 while it is using the shared resource. When the processor is through with its operation using the assigned RAM location it accesses the SR again until it finds a It then "clears" the RAM location to "idle" and "clears" the SR 295 to Whenever a processor accesses the SR 295 and finds a it leaves the SR 295 in the state and must wait to try again. In the example in Figure 30 Processor #4 is shown as needing a shared resource. It interrogates the SR to find out if it is free. The processor uses a "test&set" operation and since the SR 295 was already the test set operation leaves the register with a It WO 89/04521 PCT/US88/03906 118 must now wait and try again. It will keep trying until it gets access to the SR 295 and it finds the resource in the RAM word is "idle". V. PROTOCOL A. CONTENTION IN GENERAL In a typical application the communications network among the cells is lightly loaded and the cells will experience little or no contention delay. In the case of heavy traffic, the network can saturate. A heavy load will generate collisions and hence require retransmissions. If retransmissions continue to collide, the network can possibly saturate. te contention backoff algorithm used in the network quickly spreads the traffic over a longer time period so that the system can recover from saturation. If the traffic is not spread over a long time period, the system will be unstable; it will not recover from saturation. Access to a subchannel under contention conditions is regulated by two mechanisms, deferring and backing off. Deferring is a collision avoidance technique used in group acknowledgements. Backing off is a traffic or load leveling technique. WO 89/04521 PCT/US88/03906 119 Deferring consists of counting free slots. When the number of free slots that the cell has seen equals the defer count, the cell transmits its packet in the next available slot. When backing off, the cell increases its waiting time before attempting to retransmit a packet that has suffered a collision. The amount of this increase is a function of the number of collisions or retransmissions. The algorithm implementing this function is called the backoff or contention algorithm. The network uses a carrier sense multiple access method of resolving contention for the communications channel. When a cell is ready to transmit it first listens to the communications channel. If it hears another cell transmitting, it waits for a clear channel. Once it detects a clear channel, a cell may delay before transmitting. The method of determining that delay is determined by the contention algorithm. Time on the channel is measured in slots, each slot being M bits at the most recently detected receive baud rate shift rate). When a cell delays before transmitting, it waits an integral number of slots. When a cell detects a clear channel, it may delay and then when it is ready to transmit, it attempts to transmit on a slot boundary. If a cell is transmitting a packet that has suffered a collision, it delays a time period determined 1 WO 89/04521 PCT/US88/03906 120 by the backoff algorithm. Backoff delay is randomized uniformly over N slots, N is adjusted by the backoff algorithm. Its smallest value is 2 and it is adjusted upward by the backoff algorithm before each retransmission of a packet. Its maximum value is 9 210. B. GROUP ACKNOWLEGEMENT PACKET CONTENTION A packet from a group announcer to a set of group listeners will cause each of those listeners to send an acknowledgement to the announcer. Without a method of arbitrating contention among those acknowledgements, they will always collide. To avoid this problem, a built in reservation system for group acknowledgements is used. A listener cell uses its group member number to determine which slot to use for its acknowledgement. Group member 5 will transmit its acknowledgement in the free slot following reception of the original packet. The result is that group member 1 will transmit its acknowledgement in the first slot following the original packet. Group member two will transmit its acknowledgement in the first slot following first group member's acknowledgement. This process continues until the last group member has replied to the original packet. If a L v WO 89/04521 PCT/US88/03906 121 group member does not reply and thus leaves its reply slot empty, the next group member replies in the next slot. The contention and I/O state diagram is shown in Figure 24. The following table sets forth the states and their descriptions. Contention States State 0 1 2 3 4 Name Idle Bit Sync Byte Sync Rcv IPG Delay Description Time the slot boundaries while looking for receive data transitions. Establish baud rate synchronization with received signal. Wait for the start of packet flag. Receive the packet. Inter Packet Gap Delay. Delay for n bit times after the end of the last packet on the subchannel (whether this neuron transmitted it or received it). Wait M slots where M was set by the last execution of the backoff algorithm or by the ARQ protocol software. Transmit a packet in the next slot, Transmit a jam pattern (all ones) for the jam period (specified in bit times). Execute the backoff algorithm to set the backoff slot count. Backoff Delay 6. Xmt 7. Jam L i- WO 89/04521 PCT/US88/03906 122 Contention State Transitions State 0. Idle 0. Idle 1. Bit Sync 1. Bit Sync 2. Byte Sync 2. Byte Sync 3. Rcv 3. Rcv 3. Rcv Event A. Transitions Detected L. Packet to Xmt B. Sync Achieved G. No Transitions Byte Sync F. Hunt Timeout C. Starting Flag Detected E. Abort Detected D. Ending Flag N. Packet Too Long Action none none none none none none Next State 1. Bit Sync 5. Backoff Delay 2. Byte Sync 4. IPG Delay 1. Bit Sync 3. Rcv none Set Pckt none Rcvd Flag 1. Bit Sync 4. IPG Delay 1. Bit Sync 4. IPG Delay M. Delay Done Backoff Delay Backoff Delay J. Delay Done A. Transitions Detected I. Collision Detected H. Xmt Done K. Jam Done none none none 0. Idle 6. Xmt 1. Bit Sync 6. Xmt 6. Xmt 7. Jam Calculate Backoff Delay none 7. Jam 0. idle none 5. Backoff Delay C. COLLISION DETECTION In the curesntly implemented embodiment collision detection is not used. Ordinary circuits can be used to provide WO 89/04521 PCT/US88/03906 123 this feature with the cells providing responses as set forth in IEEE802.3. Upon detecting a collision, the cell can transmit a jamming signal for one slot time to make sure that all cells on the channel detect the collision. It then ceases transmitting and executes the backoff algorithm. The backoff algorithm adjusts the contention randomization interval. IEEE802.3 uses the number of collisions experienced by the packet to calculate the backoff interval. The cell network may not always have collision detection so the cell's backoff algorithm may use the protocol's inferred collision to calculate the backoff interval. If the cell has collision detection, it detects a collision in the same slot in which it occurs and retries the transmission (after the backoff interval). For cells without collision detection where a collision occurs, the cell discovers it when the protocol timeout period Sexpires. If a cell is sending a packet to multiple destinations (the normal case), it infers a collision if at the end of the protocol timeout period, no replies have been received from any of the destinations. If even one reply is received, there was no coll' ion at the transmit point and the retransmission takes place without an increased delay due to backoff. The cell then executes the I backoff algorithm just as it does with collision detection, using WO 89/04521 PCT/US88/03906 124 the inferred collision count. After the backoff interval, the cell transmits the packet. STherefore, the difference between collision detection and collision inference is in the length of time it takes the cell to discover that a collision has occurred. D. BACKOFF ALGORITHM The backoff algorithm used in the currently preferred embodiment is set forth in IEEE802.3 standard, a truncated binary exponential backoff. The backoff interval is an exponential function of the number of collisions (detailed or inferred) since the last successful transmission. An exponential backoff algorithm gives the system the stability it needs to recover from saturation conditions. By exponentially spreading out the load in a saturated system, the algorithm allows the system to recover. S 15 Backoff interval in slots R such that R random number linearly i distributed over the interval: i 0 Download PDF in English