AU648866B2 - Creation of Inventions and Patents with Artificial Intelligence

AU648866B2 – Apparatus for receiving digital data and performing error correction decoding
– Google Patents

AU648866B2 – Apparatus for receiving digital data and performing error correction decoding
– Google Patents
Apparatus for receiving digital data and performing error correction decoding

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Publication number
AU648866B2

AU648866B2
AU10813/92A
AU1081392A
AU648866B2
AU 648866 B2
AU648866 B2
AU 648866B2
AU 10813/92 A
AU10813/92 A
AU 10813/92A
AU 1081392 A
AU1081392 A
AU 1081392A
AU 648866 B2
AU648866 B2
AU 648866B2
Authority
AU
Australia
Prior art keywords
data
error correction
error
series
correction
Prior art date
1987-06-03
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

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Application number
AU10813/92A
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AU1081392A
(en

Inventor
Makoto Furuhashi
Katsumi Yamaoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Sony Corp

Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1987-06-03
Filing date
1992-02-07
Publication date
1994-05-05

1987-06-03
Priority claimed from JP62139124A
external-priority
patent/JPS63303421A/en

1987-06-03
Priority claimed from JP62139122A
external-priority
patent/JPS63302628A/en

1987-08-13
Priority claimed from JP62201031A
external-priority
patent/JP2576523B2/en

1992-02-07
Application filed by Sony Corp
filed
Critical
Sony Corp

1992-04-16
Publication of AU1081392A
publication
Critical
patent/AU1081392A/en

1994-05-05
Application granted
granted
Critical

1994-05-05
Publication of AU648866B2
publication
Critical
patent/AU648866B2/en

2008-05-30
Anticipated expiration
legal-status
Critical

Status
Ceased
legal-status
Critical
Current

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Classifications

H—ELECTRICITY

H03—ELECTRONIC CIRCUITRY

H03M—CODING; DECODING; CODE CONVERSION IN GENERAL

H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words

H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits

H03M13/13—Linear codes

H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F1/00—Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00

G06F1/24—Resetting means

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F11/00—Error detection; Error correction; Monitoring

G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance

G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes

G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9’s or 11’s

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F11/00—Error detection; Error correction; Monitoring

G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance

G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes

G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9’s or 11’s

G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9’s or 11’s in individual solid state devices

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers

G06F3/0601—Interfaces specially adapted for storage systems

G—PHYSICS

G11—INFORMATION STORAGE

G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER

G11B19/00—Driving, starting, stopping record carriers not specifically of filamentary or web form, or of supports therefor; Control thereof; Control of operating function ; Driving both disc and head

G11B19/02—Control of operating function, e.g. switching from recording to reproducing

G—PHYSICS

G11—INFORMATION STORAGE

G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER

G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor

G11B20/00086—Circuits for prevention of unauthorised reproduction or copying, e.g. piracy

G—PHYSICS

G11—INFORMATION STORAGE

G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER

G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor

G11B20/00086—Circuits for prevention of unauthorised reproduction or copying, e.g. piracy

G11B20/00166—Circuits for prevention of unauthorised reproduction or copying, e.g. piracy involving measures which result in a restriction to authorised contents recorded on or reproduced from a record carrier, e.g. music or software

G—PHYSICS

G11—INFORMATION STORAGE

G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER

G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor

G11B20/10—Digital recording or reproducing

G—PHYSICS

G11—INFORMATION STORAGE

G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER

G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor

G11B20/10—Digital recording or reproducing

G11B20/12—Formatting, e.g. arrangement of data block or words on the record carriers

G11B20/1217—Formatting, e.g. arrangement of data block or words on the record carriers on discs

G11B20/1252—Formatting, e.g. arrangement of data block or words on the record carriers on discs for discontinuous data, e.g. digital information signals, computer programme data

G—PHYSICS

G11—INFORMATION STORAGE

G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER

G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor

G11B20/10—Digital recording or reproducing

G11B20/18—Error detection or correction; Testing, e.g. of drop-outs

G11B20/1806—Pulse code modulation systems for audio signals

G11B20/1809—Pulse code modulation systems for audio signals by interleaving

G—PHYSICS

G11—INFORMATION STORAGE

G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER

G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor

G11B20/10—Digital recording or reproducing

G11B20/18—Error detection or correction; Testing, e.g. of drop-outs

G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information

G—PHYSICS

G11—INFORMATION STORAGE

G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER

G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel

G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel

G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier

G11B27/28—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording

G11B27/30—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording

G11B27/3027—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording used signal is digitally coded

G—PHYSICS

G11—INFORMATION STORAGE

G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER

G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel

G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel

G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier

G11B27/3063—Subcodes

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F2211/00—Indexing scheme relating to details of data-processing equipment not covered by groups G06F3/00 – G06F13/00

G06F2211/007—Encryption, En-/decode, En-/decipher, En-/decypher, Scramble, (De-)compress

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers

G06F3/0601—Interfaces specially adapted for storage systems

G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure

G06F3/0671—In-line storage system

G06F3/0673—Single storage device

G—PHYSICS

G11—INFORMATION STORAGE

G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER

G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor

G11B20/10—Digital recording or reproducing

G11B20/12—Formatting, e.g. arrangement of data block or words on the record carriers

G11B20/1217—Formatting, e.g. arrangement of data block or words on the record carriers on discs

G—PHYSICS

G11—INFORMATION STORAGE

G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER

G11B2220/00—Record carriers by type

G11B2220/20—Disc-shaped record carriers

G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology

G11B2220/2508—Magnetic discs

G11B2220/2512—Floppy disks

Description

P/00/011 Regulation 3.2
AUSTRALIA
PATENTS ACT 1990 4 COMPLETE SPECIFICATION FOR A STANDARD PATENT Name of Applicant: Address of Applicant: Actual Inventors: Address for Service: SONY CORPORATION 7/35 KITASHINAGAWA 6-CHOME, SHINAGAWA-KU, TOKYO, JAPAN MAKOTO FURUHASHI and KATSUMI YAMAOKA GRIFFITH HACK CO., Patent Trade Mark Attorneys, 601 St. Kilda Road, Melbourne, Victoria 3004, AUSTRALIA *r
A
*0 0 0* *0 Standard Complete Specification for the invention entitled: APPARATUS FOR RECEIVING DIGITAL DATA AND PERFORMING ERROR CORRECTION DECORDING Details of Associated Provisional Applications: Details of Parent Application for Divisional Applications: Australian Patent Application No. 16760/88 filed May 30, 1988 The following is a full description of this invention, including the best method of performing it known to me:- APPARATUS FOR RECEIVING DIGITAL DATA AND PERFORMING ERROR CORRECTION DECODING This invention relates to a data processing apparatus and a method used therein for correcting data errors.
In a variety of data processing apparatus, such as personal computers or word processors, the disk-shaped recording medium, such as the floppy disk, is widely used as the external storage medium.
The data writing and reading in the disk apparatus is usually so performed that the host computer issues a series of control instructions to the disk for sequentially actuating a variety of functional blocks such as rotary drive means or data processing means and the computer operation is performed sequentially in such a manner that, after the end of a predetermined control operation is ascertained, the computer proceeds to the next control operation.
In the conventional floppy disk apparatus, it is therefore up to the host computer to control the operation of the disk apparatus since the start until the end of data recording and reproduction. Thus a major portion of the processing capacity of the host computer is dedicated to controlling the disk operation such that the processing o efficiency of the host computer is lowered considerably.
On the other hand, when correcting the errors of the data recorded with error correction codes, flags are employed in the error correction or parity codes in the conventional triple erasure correcting routine in such a manner that, although the state of error correction is generally satisfactorily for raneom errors, the risk is high that a double error correction routine is executed on occurrence of burst errors, such that, when a 3-symbol error, for example, is taken for a 2-symbol error, the possibility is high that the correction is not feasible and the errors remain uncorrected.
It is a general object of the present invention to provide a data processing apparatus free of the above problems and a method employed therein for correcting data errors.
9* o 3 According to the present invention there is provided an apparatus for receiving digital data encoded in an error correction code including a first and a second error correction codes, and performing an error correction decoding, comprising: a first memory area for storing received data, a second memory area for storing readout flag data during writing of said received data into said first memory area, processing means for performing said error correction decoding on said received data, and a third memory area for storing flag data corresponding to a result of said error correction decoding, wherein said second memory area and said third memory area are provided in the same byte within a single memory, said second memory area and said third memory area are set from a first value to a second value during writing of said received data in said first memory area, and said second memory area is set to said first value during said error correction decoding of said received data while said third memory area is set to a value corresponding to the result of said error correction decoding, wherein said error correction decoding is performed by decoding the first error correction codes and subsequently decoding said second error correction codes on the basis of results of decoding the first error correction codes.
The present invention will be further described :hereinafter with reference to the following description of an exemplary embodiment and the accompanying drawings, in which: Figs. 1 to 4 are diagrammatic views showing data 35 formats employed in the disk data recording/reproducing to which the present invention is applied.
3A Figs. 5A and 5B are diagrammatic views showing sub-code data formats composed of the sub-data having the formats shown in Figs. 3 and 4.
Fig. 6 is a diagrammatic view showing the arrangement of the error correction codes having the format shown in Fig. 4.
e** So e 4 Fig. 7 is a block diagram showing the disk data recording/reproducing apparatus to which the present invention is applied.
Fig. 8 is a block diagram showing the memory control unit shown in Fig. 7.
Fig. 9 is a diagrammatic view showing a memory map of the buffer memory shown in Fig. 7.
Figs. 10A and 10B are diagrammatic views for understanding the read correction flag area on the memory map shown in Fig. 9.
Fig. 11 is a flow chart showing an example of application of the error correction algorithm of the present invention to the correction of the coding data.
Before proceeding to description of the disk data recording/reproducing apparatus to which the data processing apparatus and the error correcting method according to the present invention are applied, the data formats employed therein will be explained-by referring to Figs. 1 to 6.
However, those formats are pertinent directly to the present 20 invention are not explained for simplicity.
First, the data format for the floppy disk will be explained.
Track Format Fig. 1 shows a track format. Each track is formed by an index and four sectors 40 to Thus, from the start position on, each track is constituted by a gap 0 (pre-index gap), index, gap 1 (post-index gap), sector gap 2 (sector gap), sector W1, gap 2 (sector gap), sector gap 2 (sector gap), sector 03, and a gap 3 (the last gap). The index is a continuous Tmax signal. It is noted that one frame is composed of 44 bytes in this ordr, with each byte including 10 channel bits.
PG denotes a rotational phase detection signal that is produced upon rotation of a spindle motor adapted for rotationally driving the floppy disk. The signal is correlated with the index.
Sector Format Fig. 2 shows a sector format. Each sector is formed by a preamble data “2BH”, a sync frame, sub-frame, coding data (data frames 0 to 127 through n, and a post-amble data “2BH”, in this order, and has a length of 5765 bytes.
Sub-frame Format Fig. 3 shows a sub-frame format. Each sub-frame is 4 formed by sync data, sub-data, frame address, parity codes for the sub-data and address, mode data, track number, sector number #2 or head number, copy protection code, reserve area and parity codes (4 symbols) for data following the frame address and mode data, in this order, and has a 4* length of 44 bytes.
Data Frame Format .Fig. 4 shows a data frame format. Each data frame is formed by sync data, sub-data, frame address, parity codes for sub-data and address, coding data (32 symbols), C 2 and C 1 parity codes (each 4 symbols) as later described, in this order, and has a length of 44 bytes.
Sub-Code Format The sub-code is formed as a sub-code assembly formed by 128 bytes each being the 1i-byte sub-data of the data frame shown in Fig. 4 and each being collected from each of the 128 data frames for one sector, as shown in Fig. 5A. It is constituted by the sub-codes #2 and As shown in Fig. 5B, each sub-code is formed by a mode data, track number, sector number, head number, copy protection code, reserve area and parity codes (4 symbols) for the above data, in this order, and has a length of 32 bytes.
Data Frame Error Correction Code Format The C 2 and C 1 parity codes of the above described data frame will be explained by referring to Fig. 6, wherein,
S
among the data constituting one sector, the data frames
S.
**taking part in the formation of the C 2 and C 1 parity codes and the sub-frame taking part in the formation of the C 1 parity code, are shown. The C 2 parity codes are constituted by plural symbols of the C 2 series or the coding data 5.55 obtained on interleaving from a large number of symbols arranged in a matrix in a direction extending from the upper left towards the lower right in the figure. The C 1 parity codes are constituted by plural symbols of the C 1 series extending vertically from the upper side towards the lower side in the figure, that is, the frame address, coding data and the C 2 parity codes. For these C 1 and C 2 parity codes, the Reed-Solomon codes, for example, are employed.
Disk Data Recording/Reproducing Apparatus The apparatus for recording and/or reproducing the data having the above described data formats cn or from the disk will be explained by referring to Fig. 7.
The data to be recorded are supplied from a host computer 1 to a buffer memory 2 by way of an interface circuit 11 and a disk controller 12 within a disk control section 10. An S-RAM having the storage capacity of the order of 8 k bytes for each sector, for example, is employed as the buffer memory 2. The data written into the buffer memory 2 are subjected to an encoding processing shown in Fig. 6, that is, the formation and annexation of the C 2 and CI parity codes, by an error correction processor 13 having the encoding and decoding functions. The encoded output from the buffer memory 2 is supplied to a modulating circuit 14, where it is subjected to a processing such as 8/10 conversion, before it is supplied to a magnetic head 4 via recording/reproducing circuit 3 so as to be recorded on a floppy disk 5. The floppy disk is driven rotationally at 3600 rpm, for example, by a spindle motor 7 controlled by a microcomputer 6 adapted to control the mechanical system.
The movement of the magnetic head 4 is also controlled by the microcomputer 6. A serial/parallel interface 15 is provided between the microcomputer 6 and the disk controller 12 to effect serial communication. It will be noted that the recording/reproducing circuit 3 also has the function as an erasure circuit.
The data read-out by the magnetic head 4 from the floppy disk 5 is supplied via recording/reproducing circuit 3 to a demodulating circuit 16. These data are subjected to a processing including 10/8 conversion in the demodulating circuit 16 after which they are sent to and written in the buffer memory 2. The one-sector data written in the buffer memory 2 are subjected to a predetermined decoding, such as error correction by the CI and C 2 parity codes and removal of redundancy bits, before they are supplied via disk controller 12 and interface circuit 11 to the host computer 1 .The disk control.er 12 is constituted by a microprogram control section 12a and an instruction command section 12b.
The microprogram control section 12aA interpre or construes simple instructions supplied from the host computer 1 via interface circuit 11 to supply the micro-codes to the instruction execute section 12b for cortrolling a series of write/read control operations.
The control data formed in the disk controller 12 is supplied via internal bus to a memory management unit 17.
The disk control section 10, including the interface circuit 11, disk controller 12, an error correction processor 9 13, demodulating circuit 16, memory management unit 17 and the serial/parallel interface 15, may comprise, for example, a one-chip LSI (large-scale integrated circuit).
e* Memory Manacement Unit The memory management unit 17 respc, ble for address management of the buffer memory 2 and having the configuration as shown in Fig. 8 is able not only to read or write data on the sector basis in the aforementioned recording or reproducing mode, but also to read or write any desired number of data other than the number of one-sector unit data of 4096 bytes or the number of unit data prescribed by the operating system (OS) of the host computer 1, from and to desired addresses of the buffer memory 2, by way of transferring data between the buffer memory 2 and the host computer 1.
The memory management unit 17 is composed of a start address register 30 for previously storing data indicating the access start address when -an access is had to the buffer memory 2 from the host computer 1 to effect data transfer to Swrite or read data, that is, the transfer start address data,
S**
a data number register 31 for previously storing the number of the transferred data, a memory address counter 32 for presetting the transfer start address data stored in the start address register 30, a data number counter 33 for presetting data concerning the number of the data stored in the data number register 31, and a control circuit 34 for preset and count control of the memory address counter 32 and the data number counter 33. The unit 17 performs the memory control of the buffer memory 2 in the following mrannr.
When accessing the buffer memory 2 from the host computer I to effect data transfer to write or read data, the memory management unit 17 is previously supplied with data indicating the transfer start address data and the number of the transferred data from the host computer 1. The unit 17 also has transfer start address data and data number data stored in the start address register 30 and the data number register 31, respecively. Before starting data transfer, the control circuit 34 causes the transfer start address data and the data indicating the transferred data to be preset in the memory address counter 32 and in the data number counter 33 and accesses to the buffer memory from the address indicated in the transfer start address data preset in the memory address counter. The data t’ransfer is then started. Each time one-byte data transfer is completed, the control circuit 34 causes count pulses to be supplied to the memory address counter 32 and the data number counter 33 to increment the memory address counter 32 while simultaneously decrementing the data number counter 33. Thus the data is transferred until the value of the data number counter 33 is reduced to zero, that is, a number of data equal to the value preset in the data number register 31 is transferred, before the data transfer is terminated.
Thus the buffer memory 2 may be accessed from the host computer 1 from a given address to another given address to write or read a desired number of data, so that, when transferring a number of data other than the number equal to a number raised to the powers of 2 or an integral number of time thereof, any wasteful access time to the buffer memory may be eliminated to improve the data transfer efficiency.
Buffer Memory MaD Referring to Fig. 9, each sector of the buffer memory 2 has a capacity of 8 k(8192) bytes, of which 6 k(6144) bytes represent a usable area. The area shown by hatched lines is not pertinent directly to the present invention and therefore the related description is omitted for simplicity. The 128frame or one-sector coding data is written in the left half 32×128 byte portion in the figure. The C 2 and CI parity codes are written in the 4×128-byte area adjacent to the area where the coding data are written. The C, correction flags .000 S dependent on the results of the error correction decoding by the C 1 parity codes and the read flag indicatingA-e- data opercdon S write-44 me are written in the 1×128 byte area at the righthand side of the figure. The read flags and the C 1 correction flags are set for each frame, with the read and C 1 correction flags for each frame being written in the same 8bit byte. The frame address is written in the 1×128 byte area adjacent to this area. The sub-codes SC0 to SC 3 having the same contents as described above are written in the 1×128 byte area adjacent to the area where the frame address is written. In the figure, the upper 4-byte area of the ix128 byte area adjacent to this area is reserved for the correction flags by the parity codes of the sub-codes, while the lower 7-byte area is used as the internal register for the ECC processor 13.
The read flags and the C, correction flags will be described in detail. As shown to an enlarged scale in Fig.
the reading flao- and the C 1 correction flags for each frame are written in the 1-byte or 8- bit area in the buffer memory 11. The upper five bits D 3 to D 7 and the three bits
D
O to D 2 represent the area for the read flags and the area for the C 1 correction flags, respectively. As shown in Fig.
10B, when the data are written into the buffer memory 2, all the bits are When the error correction and decoding is performed by the C, parity codes, the upper 5-bits for reading flags are all while the lower 3 bits for C 1 correction flags are or depending upon the results of correction and decoding. Thus they are “000” when there is no error, “001” when one error is to be corrected, “011” when 2 errors are to be corrected and “111” when the correction is impossible. In other words, a flag is set at FO bit in case of one error correction, flags are set at FO and F 1 bits in case of two error correction, and flags are set at the three bits F 0
F
1 and F 2 in case the correction is not possible.
It is noted that the above C- correction flag is intended for error correction by the C 2 parity codes as later described.
In this manner, the memory area for the reading flags and that for the C 1 correction flags are provided in one and the same byte so that only one byte suffices for the flag area for each frame. Since the upper five bits for the reading flags are all that is, reset automatically, at the time of error correction by the C 1 parity codes, it becomes unnecessary to reset the reading flag again for reproducing the next sector.
These flag states are transferred as the occasion may require to the aforementioned status register 22.
9* Error Correction A typical method for correcting the error in the data frame and sub-code will be explained.
Error Correction for Data Frame An algorithm of error correction of the data frame will e be explained first by referring to Fig. 11. At step 301, the data contained in the C, code of each frame are sequentially read from the buffer memory 2 and transmitted to the error correction processor 13. At step 302, the error correction processor calculates the ,ndrome using the C, parity codes, and finds the number of the errors based on the syndrome status. It is then checked at step 303 whether the error is the 2 symbol error. If the result is negative, it is checked at step 304 whether the error is the 1 symbol error. If the result is negative, it is checked at step 305 whether there is no error or the error is the error of 3 or more symbols.
If the error is determined to be the 1-symbol error at step 304, the error location is found at step 306 using the syndrome, and the error symbol is corrected. If the error is determined to be the 2 symbol error at step 303, the error location is found at step 307 using the syndrome and the error symbol is corrected. At the next step 308, the flags
F
1 of the correction flag area of the buffer memory 2 shown in Figs. 9 and 10A are set as indicated in Fig. 10B. In case of no error or of effecting 1-symbol or 2-symbol error correction, it is checked at step 309 whether continuity exists between the frame address of the frame and the frame address of the frame immediately before it. In case of discontinuity or in case the error of three or more symbols is found is found at step 305 so that correction is not possible, the flags F 0 Fi and F 2 are set at the next step 310 as indicated in Fig. The above steps are repeatedly executed for each frame.
If it is found at step 311 that the processing of all of the frames is terminated, decoding of the next C 2 series is performed. The error correction for the sub-frames is performed in the similar manner and in advance of the above described processing of the data frames.
In the error correction for the C 2 series, the data of the C 2 series interleaved from the buffer memory 2 are read out at step 312 and the syndrome is calculated at step 313.
The number of errors is then determined from the syndrome status. It is then checked at step 314 whether the error is the 2-symbol error. If the result is negative, it is checked at step 315 whether the error is the 1-symbol error. If the result is negative, it is checked at step 316 whether there is no error or whether the error is the error of three or more symbols. If the error is found to be the 1 -symbol error at step 315, the error location is found at step 317 and the error symbol is corrected. “In more detail, referring to Table 1, when the error location is not coincident with the location of the symbol to which the F 2 flag has been afforded in the C 1 correction processing, it is checked by S the number of the F 2 flags whether the correction is to be performed. If the correction is not made, the current state is mainained. In the Table 1, N 1 and N 2 denote the numbers of the symbols to which the flags F, and F 2 are afforded and that are coincident in locations to the error locations. k i and k2 denote the numbers of the FI and F 2 flags and X means “don’t care”.
Table I error flag condition opera te .0 no correct N2 II error correct *I N2=0 V2 ;S3 1 error correct X 2 :4 uncorroct
S
S
NI =2 NI =2 111=2 N1 2 NI:=2 N1=1 III= I R11=4 KI =3 HI ;5 HI’ Z;5 SI1= 4 RI 25 V I–S2 N2 =2 H’2=1 N12 =0 N12 =0 N12 =0 X2=3 1(2=3 1(2=3 X(2= 3,4 1(2; 4 12=2 1(2 2 X(2 =0 K 11 4 91 1 5 1(1;53 KJ Z 4 1(2 2 (112 =1) (IN2 =0) K2= 1,2 K(2= 1,2 1(2 2 1(2;5 2 2 error correct 2 error correct 2 error correct.
2 error correct uncorrect 2 error correct uncorrect tincorrec t 3 erastire correct 2 erasure I error correct uncorrec t 4 erasure correct uncorrec t 3 erasure correct 2erasure Ierror correct uncorrec t 4 erasure correct uncorrect uncorre: t more than 3 X(2=3 (12 K2=3 (N2 =0) X2 #3 number of flags corresponding with the number of flags corresponding with the number of Fl flag number of F2 flag don’ t care error location error lort ion When the error is determined to be the 2-symbol error at step 314, the number of the F 2 f lags is determined at step 318. When the error is-t-he error of 2 or less symbols, the 2-symbol error correction processing is performed at step 319. When the error is the error of more than two symbols, an erasure correction processing as later described is performed. It is determined at step 319 whether the 2-symbol error correction should be performed under the condition shown in Table I, or the data should be left as are without error correction.
When it is determined that there exist errors of three or more symbols at step 316 or the number of F 2 flags exceeds two at step 318, it is determined at steps 320 and 321 whether the number of F 1 flags is 3 or 4. When it is three, a 3-erasure correction is performed at step 322 and, when it is four, a 4-erasure correction is performed at step 323.
When it is determined at steps 320, 321 that the number of F 1 flags is neither 3 nor 4, the numbers of F 1 and F 2 flags are determined at step 324. A 2 -erasure correction and a 1-error correction are performed at step 322 only when the number of F 1 flags is not less than 5 and the number of F 2 flags is 3.
When the correction is not made in the above procedure, “the data are treated as error.
The above steps are repeated for each series and, when it is determined at step 325 that the processing of these series is terminated, the correction is terminated.
At the time of the correction by the C 2 parity codes, when it is determined above all that there exist errors of two or more symbols, an erasure correction routine is performed when the number of F 2 flags set for symbols contained in the C 2 series exceeds 2, that is, 3 or more, and a 2-error correction routine or double error correction is performed when the above number does not exceed two. It is when the errors of 3 or more symbols or burst errors are caused that the F 2 flags are set in the course of correction by the Ci parity codes. However, in a majority of cases, it is the burst errors that are caused, if the symbol error rate is not higher than 10-3. In this manner, wasteful 2-error correction routines are not executed on accurrence of the burst errors and the uncorrectable errors otherwise caused S. during the correction routines may be avoided with a significantly improved correction capability for ‘burst errors. The result would be most favorable when the burst error length is 8 to 14 frames.
SIt will be appreciated from the foregoing description that, in the present embodiment, when it is determined that there are caused errors of a number of symbols larger than the number that may be corrected for errors, such as two simbols, an erasure correction is or is not executed according as the number of flags indicating that the correction is not possible by the C, parity codes and that are set for symbols contained in the C 2 series exceeds or does not exceed a predetermined number, such that the correction capability for burst errors may be improved significantly.
It is noted that up to double errors can be corrected by the C, parity codes, while up to quadruple e-rrors can be corrected by the C 2 parity codes. In more detail, error correction of m symbols and/or erasure correction of n symbols are possible with the C 2 parity codes, wherein m and n are given by the formula 2m n d 1 where the minimum distance between the codes d=5. In case of 4-symbol errors, the following formulas hold for the syndromes SO, Si, S 2 and S 3 So= e e e e (1) e e” SSt, ‘e 1 aJ Cke e teL (2) Sz= a”e aZJej a+”ek+ Ct et (3) ocatio a”e onl’e, arke, w a n ed i (4)
C
where ei, ek, e k and et represent error patterns, represents the root satisfying the irreducible polynominal F(x)=0 on the galois field CF(2M), where, for example, M=8, and i, j, k and e represent error locations. In case of a 3symbol error, e The error locations i, j and k only are known in the triple erasure correction, while the error locations i and j only are known in the double error correction plus single error correction.
Solving the simultaneous equations to with respect to the error patterns e i e- ek and e l the following equations for the quadruple erasure correction are obtained.
S
0 (x -J k L )S (a-J-k S:
S
e (1i C 01C- (041 So4 (tx- IX l)S 1 S3 ej (6) So a- a -J)S a( k+ -)S2i 4 S3 (u t ons t o (1 -O) (1to -r’ro a’)S 1 j +a t i tS (8) In case of the triple erasure correction or the double erasure correction plus single error correction, the simultaneous equations to (el=0) are solved with respect to the error patterns ei, e- and ek to give the following equations to (12) wherein, in the double error correction plus single error correction, k that is, the error location, is also found.
S, L’ iSz(c’ S3 (9) So e -I S +S2 So a S (a c k) +S 2 e (cYi a J) (r Q+-a Sot +SI (C 1 I Ce )+S 2 (12) (c Q-J)
S
k In this manner, in the cases of qadruple erasure a.
correction, triple error correction and double error correction plus single error correction, the arithmetic operations by separate equations are usually carried out, with an increased program volume and time involved in the arithmetic operations.
Thus the quadruple erasure correction and triple erasure correction (or double erasure correction plus single error correction) are carried out using the common terms for the two sets of equations, that is, the set of equations to for finding the quadruple error patterns and the set of equations to (12) for..finding the triple error patterns, instead of carrying out separate arithmetic operations using these sets o-f eQuations. -In the present embo[3i-ment, these common terms are expressed by the following equations.
A 1 B- (14) C=S A+ S 2 B3+S 3 D=SoA-i-S,U3+S 2 (16) Using these equations (13) to (16) for the above common terms, the equations (15) to (18) for finding the quadruple error patterns may be expressed by the following formulas to *9 C SO+01C~k j .0(0 Usn (17)eeuain 1)to(6,teeqain 9 to (1 (18)rf n~gth.til errptersmyb expressed by the followiqg formulas (21 to (24):
C
S. (21)
D
D
e (22) (ci r 1) C cr So ‘+SS I
S
(a )e e j= (22)
B
e So I ek j (24) o The above common terms are found in advance and substituted into the equations (17) to (20) to find the error S patterns ei, ej, ek and eI in the.case of the quadruple error correction and into the equations (21) to (24) to find the error patterns ei, ej and ek in the case of the triple S erasure correction and double error correction plus single error correction. It is noted that 0 ok is to be found only o in the case of the dudble erasure correction plus single error correction.
In this manner, when carrying out the arithmetic operations for error correction and/or erasure correction of different numbers of symbols, those portions common to these operations are computed in advance for reducing the program volume for the arithmetic operations and shortening the computing time- The methods of deriving the equations (17) to (20) for finding the quadruple error patterns and the equations (21 to (24) for finding the triple error patterns will be hereafter explained. First, the equations for finding the quadruple error patterns are derived in the following manner.
By multiplying denominators and the numerators of the equations and by c~ i+j~k and c 0 ‘ij+l, respectively, the following equations, we obtain *0 *0 0 0 00,( a +C i”‘SIi(e’ X1 X S e, LX *Y C )S1 2 X’ X SIi(U’ XJ 2 (CL a) (dI+ La’) (c Ee) Voo.. CY S.4 (e a 4 S, iSz) 1~ a ‘SH Ox Ce’ 2 4 LX 1 a’Zr a’ ak By introducing the above equations (1 3) to (1 6) f or the above common terms, the equation (17) and (18) are obtained from the above equations (25) and Also, by finding the equation (1)x cK I plus equation the following equations.
=LISo- S cx )ej- cx)e (ar (27) CY’Soi S,i (ce’s a’ e,,4 (a’4 e, e j (28) SI J are obtained. Bu introducing the equation the equation (19) may be obtained from the equation Also the equation (20) may be obtained from the equation The equation for finding the triple error patterns are derived in the following manner. The equation (21) and (22) may be obtained by introducing the above equations (13) to (16) for the commoni terms into the equations and (12).
Also, by setting ei=O in the equa.tion we obtain cX’S.iSti (‘Yx ‘k)ek e j (29) so that, by introducing the equation the equation (23) may be obtained from the equation The equation (24) may be obtained by setting el=0 in the equation It will be appreciated from above that, according to the error correction and decoding method of the present invention, those portions. common to the arithmetic operations for the error correction and/or erasure correction with 27 different numbers of symbols are computed in advance, such that the program volume and the computing time necessary for those arithmetic operations may be reduced.
Attention is directed to our copending application 8812941.6 (GB-A-2,205,423) from which this application was divided and also to our copending applications: 9106141.6 (GB-A-2,241,803); 9106142.4 (GB-A-2,241,804) and 9106143.2 (GB-A-2,241,805) which were also divided thereon.
0* 6 e i

Claims (3)

3. An apparatus according to claim 1 or 2, wherein said first memory area is also provided in the same memory as said second and third memory areas.

4. An apparatus according to claim 1, 2 or 3, wherein 5c6. a e the inform~tion data includco 4 first error correction codesA formed from a first series of data, and second error &re correction codesAformed from a- second series of data which are interleaved with the first series of data, and said means for performing said error correction decoding comprises: first decoding means for performing decoding of respective first error correction codes; e means for generating flag data indicating error correction impossible with regard’ to respective first series of data when correction of erroneous data included in the

9. 15 respective first series of data is impossible; second decoding means for performing decoding of respective second error correction codes, and comprising: means for determining the number of erroneous data included in the respective second series of data; means for correcting erroneous data included in the respective second series of data when the number of erroneous data is determined to exceed a first predetermined number and the number of said flag data i tlating to the data of said second series of data does not exceed a second predetermined 30 number; means for erasure correcting erasure data included in the respective second series of data when the number of erroneous data is determined to exceed a first predetermined number and the number of flag data added to the second series of data exceeds a second predetermined number. An apparatus according to claim 1, 2 or 3, wherein said first and second error correction codes have a minimum code distance equal to d, where d is an integer, and wherein the means for performing said error correction decoding decodes said first and second error correction codes satisfying the equation; 2m n d 1 where, m is a number of erroneous symbols to be corrected and n is a number of erasure symbols to be corrected. 6. An apparatus according to claim 1, substantially as herein described with reference to and as illustrated by the accompanying drawings. se**: 9oe* Dated this 22nd day of February, 1994. SONY CORPORATION By its Patent Attorneys: 9 GRIFFITH HACK CO. Fellows Institute of Patent Attorneys of Australia. 99** 9 DO 31 ABSTRACT PROCESSING DATA Method and apparatus for processing data wherein control dependency on a host computer 1 during data recording/reproduction is lowered through use of an external controller 10 with the aid of a simple program, and an error correction method wherein the error correction capability for burst errors may be improved Commands from the host computer are held in a register in the controller and interpreted, 12, as microprograms. An error correction process 13 handles double-encoded interleaved data. Flags ari maintained indicating firstly when encoded datu are written into a memory and secondly the result of decoding. Erroneous data are corrected by erasure or by use of error syndromes. Transmission of encoded data may be repeated, all but the first received data being decoded. f *o S o.. o* esS.

AU10813/92A
1987-06-03
1992-02-07
Apparatus for receiving digital data and performing error correction decoding

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1987-06-03

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1987-06-03
1987-06-03
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JPS63302628A
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1987-06-03
1987-06-03
Error correction method

JP62-139124

1987-06-03

JP62-201031

1987-08-13

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Publication date

GB2241805A
(en)

1991-09-11

AU648640B2
(en)

1994-04-28

GB2241803A
(en)

1991-09-11

GB2241363A
(en)

1991-08-28

GB2241804B
(en)

1992-02-19

US5548599A
(en)

1996-08-20

GB9106143D0
(en)

1991-05-08

AU1081392A
(en)

1992-04-16

FR2616247A1
(en)

1988-12-09

GB9106144D0
(en)

1991-05-08

CA1317029C
(en)

1993-04-27

CA1321651C
(en)

1993-08-24

DE3818881A1
(en)

1989-01-12

HK44995A
(en)

1995-04-07

AU1081492A
(en)

1992-04-16

AU622626B2
(en)

1992-04-16

GB2205423B
(en)

1992-02-19

AU648639B2
(en)

1994-04-28

FR2616247B1
(en)

1995-06-02

GB8812941D0
(en)

1988-07-06

GB9106141D0
(en)

1991-05-08

GB2241804A
(en)

1991-09-11

GB2241805B
(en)

1992-02-19

AU1081592A
(en)

1992-04-16

AU1676088A
(en)

1988-12-08

GB2241363B
(en)

1992-02-19

GB2205423A
(en)

1988-12-07

GB9106142D0
(en)

1991-05-08

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