AU6520674A – Memory arrangement
– Google Patents
AU6520674A – Memory arrangement
– Google Patents
Memory arrangement
Info
Publication number
AU6520674A
AU6520674A
AU65206/74A
AU6520674A
AU6520674A
AU 6520674 A
AU6520674 A
AU 6520674A
AU 65206/74 A
AU65206/74 A
AU 65206/74A
AU 6520674 A
AU6520674 A
AU 6520674A
AU 6520674 A
AU6520674 A
AU 6520674A
Authority
AU
Australia
Prior art keywords
memory arrangement
memory
arrangement
Prior art date
1973-05-14
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
AU65206/74A
Inventor
Robert J Frankenberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1973-05-14
Filing date
1974-02-05
Publication date
1975-08-07
1974-02-05
Application filed by Hewlett Packard Co
filed
Critical
Hewlett Packard Co
1975-08-07
Publication of AU6520674A
publication
Critical
patent/AU6520674A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F11/00—Error detection; Error correction; Monitoring
G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
G06F11/16—Error detection or correction of the data by redundancy in hardware
G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F12/00—Accessing, addressing or allocating within memory systems or architectures
G06F12/02—Addressing or allocation; Relocation
G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F13/14—Handling requests for interconnection or transfer
G06F13/16—Handling requests for interconnection or transfer for access to memory bus
G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F13/38—Information transfer, e.g. on bus
G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
AU65206/74A
1973-05-14
1974-02-05
Memory arrangement
Expired
AU6520674A
(en)
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
US05/360,286
US4028675A
(en)
1973-05-14
1973-05-14
Method and apparatus for refreshing semiconductor memories in multi-port and multi-module memory system
Publications (1)
Publication Number
Publication Date
AU6520674A
true
AU6520674A
(en)
1975-08-07
Family
ID=23417363
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
AU65206/74A
Expired
AU6520674A
(en)
1973-05-14
1974-02-05
Memory arrangement
Country Status (8)
Country
Link
US
(1)
US4028675A
(en)
JP
(1)
JPS5019331A
(en)
AU
(1)
AU6520674A
(en)
BR
(1)
BR7403902D0
(en)
DE
(1)
DE2422802A1
(en)
FR
(1)
FR2230018B3
(en)
GB
(1)
GB1468231A
(en)
IT
(1)
IT1021542B
(en)
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Method for providing a substitute memory in a data processing system
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International Business Machines Corporation
Processor controlled memory refresh
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Dynamic memory system which includes apparatus for performing refresh operations in parallel with normal memory operations
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Memory refresh means including means for providing refresh addresses during power failures
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Memory access system for a computer system adapted to accept a memory expansion module
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1984-04-02
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Sperry Corporation
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1986-01-29
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Apparatus and method for providing distributed control in a main memory unit of a data processing system
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1986-01-29
1990-09-04
Digital Equipment Corporation
Apparatus and method for providing distribution control in a main memory unit of a data processing system
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Memory organization with arrays having an alternate data port facility
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Vlsi Technology, Inc.
Decoupled refresh on local and system busses in a PC/at or similar microprocessor environment
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1992-09-24
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インターナショナル・ビジネス・マシーンズ・コーポレイション
Memory access method and system
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1993-02-18
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日本アイ・ビー・エム株式会社
Data supply device
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Computing device having instructions which access either a permanently fixed default memory bank or a memory bank specified by an immediately preceding bank selection instruction
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2000-09-28
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2004-07-30
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System, method and storage medium for a multi-mode memory buffer device
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System, method and storage medium for providing fault detection and correction in a memory subsystem
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System, method and storage medium for providing a high speed test interface to a memory subsystem
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System, method and storage medium for bus calibration in a memory subsystem
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International Business Machines Corporation
Providing indeterminate read data latency in a memory system
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Systems and methods for providing remote pre-fetch buffers
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Design structure for selecting memory busses according to physical memory organization information stored in virtual address translation tables
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High density high reliability memory module with a fault tolerant address and command bus
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Title
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1966-12-13
Ibm
Memory expansion
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1973
1973-05-14
US
US05/360,286
patent/US4028675A/en
not_active
Expired – Lifetime
1974
1974-02-05
AU
AU65206/74A
patent/AU6520674A/en
not_active
Expired
1974-02-07
GB
GB562473A
patent/GB1468231A/en
not_active
Expired
1974-05-09
FR
FR7416075A
patent/FR2230018B3/fr
not_active
Expired
1974-05-10
DE
DE2422802A
patent/DE2422802A1/en
active
Pending
1974-05-10
IT
IT50900/74A
patent/IT1021542B/en
active
1974-05-13
BR
BR3902/74A
patent/BR7403902D0/en
unknown
1974-05-14
JP
JP49054296A
patent/JPS5019331A/ja
active
Pending
Also Published As
Publication number
Publication date
GB1468231A
(en)
1977-03-23
JPS5019331A
(en)
1975-02-28
DE2422802A1
(en)
1974-12-05
BR7403902D0
(en)
1974-12-03
FR2230018B3
(en)
1978-05-12
US4028675A
(en)
1977-06-07
FR2230018A1
(en)
1974-12-13
IT1021542B
(en)
1978-02-20
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