GB1091514A – Circuit arrangement to compare two information items
– Google Patents
GB1091514A – Circuit arrangement to compare two information items
– Google Patents
Circuit arrangement to compare two information items
Info
Publication number
GB1091514A
GB1091514A
GB25867/65A
GB2586765A
GB1091514A
GB 1091514 A
GB1091514 A
GB 1091514A
GB 25867/65 A
GB25867/65 A
GB 25867/65A
GB 2586765 A
GB2586765 A
GB 2586765A
GB 1091514 A
GB1091514 A
GB 1091514A
Authority
GB
United Kingdom
Prior art keywords
cores
bit
pulse
winding
numbers
Prior art date
1964-06-20
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB25867/65A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Standard Electric Corp
Original Assignee
International Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1964-06-20
Filing date
1965-06-18
Publication date
1967-11-15
1965-06-18
Application filed by International Standard Electric Corp
filed
Critical
International Standard Electric Corp
1967-11-15
Publication of GB1091514A
publication
Critical
patent/GB1091514A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
G06F7/02—Comparing digital values
Abstract
1,091,514. Comparators. INTERNATIONAL STANDARD ELECTRIC CORPORATION. June 18, 1965 [June 20, 1964 (2)], No. 25867/65. Heading G4M. A comparator has two cores per bit place of one binary comparand, each comparand being presented over a respective set of leads including a 1 lead and a 0 lead for each bit, the leads threading the cores. In a first embodiment, twelve leads carrying signals representing two 3-bit numbers in true and complement form are threaded through six magnetic cores as follows. The true lead of a given bit of one number threads in one sense a core which is threaded in the other sense by the complement lead of the correspondng bit in the other number. The same statement is also true with the words ” true ” and ” complement ” interchanged. Accordingly, if the numbers are equal, all cores are saturated in one direction or the other, and a pulse applied to a supervisory winding threading all the cores meets a low impedance and therefore emerges to actuate an indicator. Correct operation is monitored by applying the pulse with no numbers applied, a further winding threaded through all the cores in alternating senses delivering a signal in the case of malfunction. In a second embodiment, a pulse is applied to a winding on one of two respective cores for each bit of one number, a short-circuit having been completed in a winding on one of the two cores according to the corresponding bit of the second number. If the two numbers are equal, each core which the pulse attempts to switch has a short-circuited winding so no pulse is induced in an output winding threading all the cores. As a modification, one of two cores can be saturated for each bit of the second number, then application of the pulse will switch no cores if the numbers are equal.
GB25867/65A
1964-06-20
1965-06-18
Circuit arrangement to compare two information items
Expired
GB1091514A
(en)
Applications Claiming Priority (2)
Application Number
Priority Date
Filing Date
Title
DEST22287A
DE1211426B
(en)
1964-06-20
1964-06-20
Circuit arrangement for comparing two pieces of information
DEST022285
1964-06-20
Publications (1)
Publication Number
Publication Date
GB1091514A
true
GB1091514A
(en)
1967-11-15
Family
ID=25994244
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB25867/65A
Expired
GB1091514A
(en)
1964-06-20
1965-06-18
Circuit arrangement to compare two information items
Country Status (6)
Country
Link
US
(1)
US3319224A
(en)
BE
(1)
BE665597A
(en)
DE
(1)
DE1211426B
(en)
FR
(1)
FR88402E
(en)
GB
(1)
GB1091514A
(en)
NL
(1)
NL6507827A
(en)
Families Citing this family (2)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3622987A
(en)
*
1969-05-05
1971-11-23
Us Army
Count comparison circuit
DE3104941A1
(en)
*
1981-02-11
1982-08-26
Siemens AG, 1000 Berlin und 8000 München
MICROCALCULATOR SYSTEM FOR RAPIDLY DETECTING LABEL BLOCKS
Family Cites Families (7)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US2905931A
(en)
*
1955-02-03
1959-09-22
Underwood Corp
Comparator
US2973508A
(en)
*
1958-11-19
1961-02-28
Ibm
Comparator
US2997692A
(en)
*
1959-01-30
1961-08-22
Ibm
Binary comparator
US3195108A
(en)
*
1960-03-29
1965-07-13
Sperry Rand Corp
Comparing stored and external binary digits
NL272711A
(en)
*
1960-12-23
1900-01-01
US3239810A
(en)
*
1961-07-26
1966-03-08
Bell Telephone Labor Inc
Magnetic core comparator and memory circuit
US3222645A
(en)
*
1962-10-17
1965-12-07
Sperry Rand Corp
Magnetic parallel comparison means for comparing a test word with a plurality of stored words
1964
1964-06-20
DE
DEST22287A
patent/DE1211426B/en
active
Pending
1965
1965-06-07
US
US461814A
patent/US3319224A/en
not_active
Expired – Lifetime
1965-06-18
GB
GB25867/65A
patent/GB1091514A/en
not_active
Expired
1965-06-18
FR
FR21396A
patent/FR88402E/en
not_active
Expired
1965-06-18
BE
BE665597D
patent/BE665597A/xx
unknown
1965-06-18
NL
NL6507827A
patent/NL6507827A/xx
unknown
Also Published As
Publication number
Publication date
NL6507827A
(en)
1965-12-21
BE665597A
(en)
1965-12-20
FR88402E
(en)
1967-02-03
US3319224A
(en)
1967-05-09
DE1211426B
(en)
1966-02-24
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