GB1136314A - Creation of Inventions and Patents with Artificial Intelligence

GB1136314A – Data processing systems
– Google Patents

GB1136314A – Data processing systems
– Google Patents
Data processing systems

Info

Publication number
GB1136314A

GB1136314A
GB13744/66A
GB1374466A
GB1136314A
GB 1136314 A
GB1136314 A
GB 1136314A
GB 13744/66 A
GB13744/66 A
GB 13744/66A
GB 1374466 A
GB1374466 A
GB 1374466A
GB 1136314 A
GB1136314 A
GB 1136314A
Authority
GB
United Kingdom
Prior art keywords
cores
column
pulse
row
passes
Prior art date
1965-03-31
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB13744/66A
Inventor
Evan Ezra Davidson
William Mark Regitz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

AT&T Corp

Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1965-03-31
Filing date
1966-03-29
Publication date
1968-12-11

1966-03-29
Application filed by Western Electric Co Inc
filed
Critical
Western Electric Co Inc

1968-12-11
Publication of GB1136314A
publication
Critical
patent/GB1136314A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

Classifications

H—ELECTRICITY

H03—ELECTRONIC CIRCUITRY

H03K—PULSE TECHNIQUE

H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking

H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used

H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices

H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors

H03K17/62—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors

H03K17/6221—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors combined with selecting means

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F11/00—Error detection; Error correction; Monitoring

G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance

G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes

G06F11/085—Error detection or correction by redundancy in data representation, e.g. by using checking codes using codes with inherent redundancy, e.g. n-out-of-m codes

H—ELECTRICITY

H03—ELECTRONIC CIRCUITRY

H03K—PULSE TECHNIQUE

H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking

H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used

H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices

H—ELECTRICITY

H03—ELECTRONIC CIRCUITRY

H03K—PULSE TECHNIQUE

H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking

H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used

H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices

H03K17/64—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors having inductive loads

Abstract

1,136,314. Magnetic matrix memory. WESTERN ELECTRIC CO. Inc. 29 March, 1966 [31 March, 1965(2)], No. 13744/66. Heading G4C. [Also in Division H3] A selection circuit for a memory comprises two selection matrices each having a plurality of individually actuable circuit paths including two state switchable means for actuating one of the paths, means for supplying drive current pulses to the actuated path and means in one of the paths for indicating that the drive current supplied to the path is less than the full drive current pulse supplied by the means for supplying. In one embodiment (Fig. 3) a matrix driver supplies current pulses to row elements 39, 40 on line 53 and to column elements 41, 42 on line 56 of a memory row selector. A particular transistor 49, 50 is enabled in the row elements and a particular transistor 51, 52 is enabled in the column elements to allow a read or write pulse to pass through load 33, 36, 37 or 38 and operate the required row of the memory. A similar unit (18, Fig. 1, not shown) operates the columns. A read drive pulse thus passes along line 53, operates cores 58, 57 and then passes along line 39 for instance. To do this the pulse passes through core 57 again in such a manner as to reset it. The pulse, via diode 43, the transistor switch and diode 33R, for instance, passes load 33, enters column, 41, passes through the switch 51, through core 59, core 60, core 59 again and returns to the matrix driver. Thus at the end of a correct operation two cores 58, 60 are set and two are reset. Each read or write pulse is followed by an interrogate pulse (Fig. 2), formed by applying the read and write pulse to monostable flip-flops (23, 26 Fig. 1, not shown). The interrogating pulses are of the same polarity but of smaller magnitude than the read or write pulse and have sufficient current only to switch the cores 57, 58, 59, 60. The interrogation pulses are fed to a loop 61 which traverses all the cores. The pulses thus set any row or column check cores that have not already been set. The switching of the row cores is picked up on loop 62 and fed to a detection circuit 27, with a similar operation occuring to the column check cores. The pulse picked up is rectified, amplified and supplied to transistor 69, which is only allowed to conduct during the interrogate period by means of transistors 76, 77, 78 and lines 70, 71. For normal operation a pulse is supplied via amplifier 67 to transistor 69 which conducts and indicates correct operation. Certain faults which may occur in the translator or in the selection matrix cause the drive current pulses to be supplied to two rows or two columns. In which case, for instance on a read pulse the full current passes first through cores 57, 58 then the current divides and only half the full value passes through the cores the second time. This is less than the current required to reset the cores. The current passes through the matrix, is recombined in one column, sets one core 60 and sets and resets the other core 59. Thus on interrogation the column check circuit 32 is correct but since cores 57, 58 are both set there is no output on line 62 and the detector shows a fault condition. In a second embodiment (Figs. 4, not shown, and 5), varistors are used in place of the check cores. Each varistor is coupled to the primary winding of a transformer, the secondary windings being coupled in series to the detection circuit, such that the voltages developed across the secondaries of the column transformers 156, 157 oppose the voltages developed across the secondaries of the row transformers 156, 157. Under normal circumstances only one row varistor and one column varistor are raised to their high impedance state by the drive current and their voltages received in the detection loop 55 oppose each other. If a fault causes two columns and one row or two rows and one column to conduct then the voltages produced in the loop unbalance and the detection circuit 122 shows a fault condition. The detection circuit is illustrated in detail, Fig. 7, not shown, and includes a source of pulses for checking amplifier operation. The secondaries of the rows of the vertical and horizontal selection matrices may be connected in series and in opposition to all the column secondaries of the selection matrices as illustrated in Fig. 6 (not shown) to check against an open circuit fault as well as the faults previously discussed.

GB13744/66A
1965-03-31
1966-03-29
Data processing systems

Expired

GB1136314A
(en)

Applications Claiming Priority (2)

Application Number
Priority Date
Filing Date
Title

US44434565A

1965-03-31
1965-03-31

US44434665A

1965-03-31
1965-03-31

Publications (1)

Publication Number
Publication Date

GB1136314A
true

GB1136314A
(en)

1968-12-11

Family
ID=27033876
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB13744/66A
Expired

GB1136314A
(en)

1965-03-31
1966-03-29
Data processing systems

Country Status (5)

Country
Link

US
(2)

US3460093A
(en)

BE
(1)

BE678467A
(en)

DE
(2)

DE1774991B1
(en)

GB
(1)

GB1136314A
(en)

NL
(1)

NL6604063A
(en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3614771A
(en)

1969-09-18
1971-10-19
Hewlett Packard Co
Display apparatus

DE2061674A1
(en)

1969-12-30
1971-07-01
Honeywell Inf Systems

Test procedure for checking electronic memories

US3618030A
(en)

1970-05-04
1971-11-02
Gte Automatic Electric Lab Inc
Method including a program for testing selection matrices

US3660829A
(en)

1970-07-15
1972-05-02
Technology Marketing Inc
Bipolar current switching system

US3731275A
(en)

1971-09-03
1973-05-01
Stromberg Carlson Corp
Digital switching network

Family Cites Families (7)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3172087A
(en)

1954-05-20
1965-03-02
Ibm
Transformer matrix system

US2926334A
(en)

1955-04-20
1960-02-23
Bell Telephone Labor Inc
Error detection circuit

NL244992A
(en)

1958-11-06

GB932223A
(en)

1961-01-23
1963-07-24
Bendix Corp
Random access memory bistable elements

NL292619A
(en)

1962-05-18

US3337849A
(en)

1963-11-26
1967-08-22
Bell Telephone Labor Inc
Matrix control having both signal and crosspoint fault detection

US3371315A
(en)

1964-08-05
1968-02-27
Bell Telephone Labor Inc
Error detection circuit for translation system

1965

1965-03-31
US
US444346A
patent/US3460093A/en
not_active
Expired – Lifetime

1965-03-31
US
US444345A
patent/US3460092A/en
not_active
Expired – Lifetime

1966

1966-03-25
BE
BE678467D
patent/BE678467A/xx
not_active
Expired

1966-03-28
NL
NL6604063A
patent/NL6604063A/xx
unknown

1966-03-29
GB
GB13744/66A
patent/GB1136314A/en
not_active
Expired

1966-03-29
DE
DE1774991A
patent/DE1774991B1/en
active
Pending

1966-03-29
DE
DE1524001A
patent/DE1524001B2/en
active
Pending

Also Published As

Publication number
Publication date

US3460093A
(en)

1969-08-05

BE678467A
(en)

1966-09-01

DE1774991B1
(en)

1974-07-11

US3460092A
(en)

1969-08-05

DE1524001A1
(en)

1971-06-03

NL6604063A
(en)

1966-10-03

DE1524001B2
(en)

1974-06-20

Contact information