GB1136342A – Clock pulse generators
– Google Patents
GB1136342A – Clock pulse generators
– Google Patents
Clock pulse generators
Info
Publication number
GB1136342A
GB1136342A
GB48179/66A
GB4817966A
GB1136342A
GB 1136342 A
GB1136342 A
GB 1136342A
GB 48179/66 A
GB48179/66 A
GB 48179/66A
GB 4817966 A
GB4817966 A
GB 4817966A
GB 1136342 A
GB1136342 A
GB 1136342A
Authority
GB
United Kingdom
Prior art keywords
pulse
input
output
cycle
clock
Prior art date
1965-12-17
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB48179/66A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1965-12-17
Filing date
1966-10-27
Publication date
1968-12-11
1966-10-27
Application filed by International Business Machines Corp
filed
Critical
International Business Machines Corp
1968-12-11
Publication of GB1136342A
publication
Critical
patent/GB1136342A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F1/00—Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
H—ELECTRICITY
H03—ELECTRONIC CIRCUITRY
H03K—PULSE TECHNIQUE
H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
H03K3/78—Generating a single train of pulses having a predetermined pattern, e.g. a predetermined number
H—ELECTRICITY
H03—ELECTRONIC CIRCUITRY
H03K—PULSE TECHNIQUE
H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
Abstract
1,136,342. Clock pulse generators. INTERNATIONAL BUSINESS MACHINES CORP. 27 Oct., 1966 [17 Dec., 1965], No. 48179/66. Heading G4A. A clock pulse generator comprises means for generating an ordered sequence of electrical pulses and a plurality of latch circuits each actuated in response to the generation of a respective one of a plurality of said pulses and inhibiting means operative to inhibit generation of a pulse in response to non-actuation of the latch circuit corresponding to the expected preceding pulse. A clock pulse generator comprises four NAND latches L1, L2, L3, L4 two delays 5, 32 and various NAND gates, inverters and amplifiers. In response to a pulse 12 on a “single cycle” input, the generator performs one cycle during which it produces first, second and third output clock pulses on respective output lines in turn. The single-cycle sequence is shown schematically in Fig. 2. In this, apart from the two boxes “I2 rise” and “I2 fall” which “produce” output signals when the I2 input pulse rises and falls respectively, each box performs the function named therein and “produces” a signal on each of its outputs, when all its inputs have signals thereon. If a pulse is applied to a “free-running” input rather than the “single cycle” input, a series of whole cycles will be performed ending at the end of the cycle during which the input pulse ends. In this mode, production of the third output pulse is a necessary condition for resetting of latch L2 which is a necessary condition for the subsequent setting of latch L1 to start the next cycle. Hence in both modes, production of each output pulse is conditional upon production of the preceding. If, due to malfunction, one of the three outputs remains on while the next output comes on, the clock will stop at that point. If a signal is applied to an “inhibit” input, the clock freezes on its current output and when the signal is removed continues from that point. If a pulse is applied to a “reset” input, the latches L1, L2, L3, L4 are reset. Three further inputs are provided for causing the clock to freeze on the next first, second and third output pulses respectively, the clock continuing where it left off when the input signal is removed. Six terminals (P, Q, R, S, T, U) are provided in the circuit which can be connected together in pairs to positively ensure non-overlapping of the output pulses. If a pulse on the “single cycle” or the “freerunning” input rises and falls while the third output pulse of a cycle is being generated, it nevertheless sets the latch L1 and will initiate the next cycle when the present cycle ha s finished. The invention may be used in a computer for gating data and control information
GB48179/66A
1965-12-17
1966-10-27
Clock pulse generators
Expired
GB1136342A
(en)
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
US51450165A
1965-12-17
1965-12-17
Publications (1)
Publication Number
Publication Date
GB1136342A
true
GB1136342A
(en)
1968-12-11
Family
ID=24047448
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB48179/66A
Expired
GB1136342A
(en)
1965-12-17
1966-10-27
Clock pulse generators
Country Status (8)
Country
Link
US
(1)
US3437938A
(en)
JP
(1)
JPS4415631B1
(en)
CH
(1)
CH458798A
(en)
DE
(1)
DE1462722C3
(en)
FR
(1)
FR1506071A
(en)
GB
(1)
GB1136342A
(en)
NL
(1)
NL6617463A
(en)
SE
(1)
SE337234B
(en)
Families Citing this family (5)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3755694A
(en)
*
1972-01-05
1973-08-28
Rca Corp
Monostable/astable multivibrator
CA998746A
(en)
*
1972-02-14
1976-10-19
Yoshikazu Hatsukano
Digital circuit
US3913021A
(en)
*
1974-04-29
1975-10-14
Ibm
High resolution digitally programmable electronic delay for multi-channel operation
US4112380A
(en)
*
1976-07-19
1978-09-05
Sperry Rand Corporation
Clock sequencing apparatus having more states than clock phase outputs
JPWO2006087806A1
(en)
*
2005-02-18
2008-07-03
富士通株式会社
Clock generation device, clock generation method, clock generation program, operation verification device, operation verification method, and operation verification program
Family Cites Families (1)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3320539A
(en)
*
1964-03-11
1967-05-16
Rca Corp
Pulse generator employing a controlled oscillator driving a series of gates and each being controlled by external timing signals
1965
1965-12-17
US
US514501A
patent/US3437938A/en
not_active
Expired – Lifetime
1966
1966-10-25
JP
JP7005966A
patent/JPS4415631B1/ja
active
Pending
1966-10-27
GB
GB48179/66A
patent/GB1136342A/en
not_active
Expired
1966-12-10
DE
DE1462722A
patent/DE1462722C3/en
not_active
Expired
1966-12-13
NL
NL6617463A
patent/NL6617463A/xx
unknown
1966-12-15
CH
CH1810166A
patent/CH458798A/en
unknown
1966-12-15
FR
FR8222A
patent/FR1506071A/en
not_active
Expired
1966-12-16
SE
SE17265/66A
patent/SE337234B/xx
unknown
Also Published As
Publication number
Publication date
DE1462722C3
(en)
1974-05-02
JPS4415631B1
(en)
1969-07-11
US3437938A
(en)
1969-04-08
NL6617463A
(en)
1967-06-19
DE1462722B2
(en)
1973-10-04
FR1506071A
(en)
1967-12-15
DE1462722A1
(en)
1968-12-05
SE337234B
(en)
1971-08-02
CH458798A
(en)
1968-06-30
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RING THREE-PHASE DISTRIBUTION IMPULSES
None