GB1246294A – Method of manufacturing semiconductor devices
– Google Patents
GB1246294A – Method of manufacturing semiconductor devices
– Google Patents
Method of manufacturing semiconductor devices
Info
Publication number
GB1246294A
GB1246294A
GB57279/68A
GB5727968A
GB1246294A
GB 1246294 A
GB1246294 A
GB 1246294A
GB 57279/68 A
GB57279/68 A
GB 57279/68A
GB 5727968 A
GB5727968 A
GB 5727968A
GB 1246294 A
GB1246294 A
GB 1246294A
Authority
GB
United Kingdom
Prior art keywords
layer
seeding
seeding site
layers
exposed
Prior art date
1967-12-12
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB57279/68A
Inventor
Isamu Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1967-12-12
Filing date
1968-12-03
Publication date
1971-09-15
1968-12-03
Application filed by Sony Corp
filed
Critical
Sony Corp
1971-09-15
Publication of GB1246294A
publication
Critical
patent/GB1246294A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/02104—Forming layers
H01L21/02365—Forming inorganic semiconducting materials on a substrate
H01L21/02367—Substrates
H01L21/0237—Materials
H01L21/02373—Group 14 semiconducting materials
H01L21/02381—Silicon, silicon germanium, germanium
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/02104—Forming layers
H01L21/02365—Forming inorganic semiconducting materials on a substrate
H01L21/02518—Deposited layers
H01L21/02521—Materials
H01L21/02524—Group 14 semiconducting materials
H01L21/02532—Silicon, silicon germanium, germanium
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/02104—Forming layers
H01L21/02365—Forming inorganic semiconducting materials on a substrate
H01L21/02612—Formation types
H01L21/02617—Deposition types
H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
H01L21/02639—Preparation of substrate for selective deposition
Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10S148/00—Metal treatment
Y10S148/043—Dual dielectric
Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10S148/00—Metal treatment
Y10S148/051—Etching
Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10S148/00—Metal treatment
Y10S148/085—Isolated-integrated
Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10S148/00—Metal treatment
Y10S148/10—Lift-off masking
Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10S148/00—Metal treatment
Y10S148/122—Polycrystalline
Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10S438/00—Semiconductor device manufacturing: process
Y10S438/969—Simultaneous formation of monocrystalline and polycrystalline regions
Abstract
1,246,294. Semi-conductor devices. SONY CORP. 3 Dec., 1968 [12 Dec., 1967], No. 57279/68. Heading H1K. A monocrystalline semi-conductor substrate is prepared for the side-by-side deposition of mono- and poly-crystalline regions as follows. The surface is masked with a first layer and a seeding site layer deposited at least on the surfaces exposed through the mask, then a second masking layer is formed covering at least the areas exposed by the first mask and the parts of the seeding layer left exposed are etched away. Finally both masking layers are removed to expose the required seeding site layer. Vapour deposition of semi-conductor material then results in a layer which is polycrystalline over areas covered by the seeding site layer and monocrystalline elsewhere. Typically the substrate and seeding site layers are of silicon and the masking layers of silicon oxide or nitride. The masks are shaped using photo-resist and etching steps and the exposed parts of the seeding site layer etched away in a hydrofluoric-nitric acid mix. The seeding site layer is at least 50 thick so that areas covered by it can be visually distinguished from the adjacent oxide to facilitate registration of the masks. Where substrate and seeding site layers are of germanium, sodium hypochlorite is used as an etchant.
GB57279/68A
1967-12-12
1968-12-03
Method of manufacturing semiconductor devices
Expired
GB1246294A
(en)
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
JP7996167
1967-12-12
Publications (1)
Publication Number
Publication Date
GB1246294A
true
GB1246294A
(en)
1971-09-15
Family
ID=13704886
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB57279/68A
Expired
GB1246294A
(en)
1967-12-12
1968-12-03
Method of manufacturing semiconductor devices
Country Status (10)
Country
Link
US
(1)
US3692574A
(en)
AT
(1)
AT283448B
(en)
BE
(1)
BE725244A
(en)
CH
(1)
CH486774A
(en)
DE
(1)
DE1814029C3
(en)
FR
(1)
FR1593881A
(en)
GB
(1)
GB1246294A
(en)
NL
(1)
NL140101B
(en)
NO
(1)
NO123439B
(en)
SE
(1)
SE354382B
(en)
Cited By (3)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
GB2129019A
(en)
*
1982-09-30
1984-05-10
Western Electric Co
Method of forming a heterostructure comprising a heteroepitaxial multiconstituent material
GB2228617A
(en)
*
1989-02-27
1990-08-29
Philips Electronic Associated
A method of manufacturing a semiconductor device having a mesa structure
GB2234263A
(en)
*
1989-06-16
1991-01-30
Intel Corp
Novel masking technique for depositing gallium arsenide on silicon
Families Citing this family (9)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US4396933A
(en)
*
1971-06-18
1983-08-02
International Business Machines Corporation
Dielectrically isolated semiconductor devices
US3928092A
(en)
*
1974-08-28
1975-12-23
Bell Telephone Labor Inc
Simultaneous molecular beam deposition of monocrystalline and polycrystalline III(a)-V(a) compounds to produce semiconductor devices
US4022928A
(en)
*
1975-05-22
1977-05-10
Piwcyzk Bernhard P
Vacuum deposition methods and masking structure
GB1520925A
(en)
*
1975-10-06
1978-08-09
Mullard Ltd
Semiconductor device manufacture
DE2967388D1
(en)
*
1978-09-20
1985-03-28
Fujitsu Ltd
Semiconductor memory device and process for fabricating the device
FR2525389A1
(en)
*
1982-04-14
1983-10-21
Commissariat Energie Atomique
METHOD FOR POSITIONING AN INTERCONNECTION LINE ON AN ELECTRIC CONTACT HOLE IN AN INTEGRATED CIRCUIT
US6090646A
(en)
1993-05-26
2000-07-18
Semiconductor Energy Laboratory Co., Ltd.
Method for producing semiconductor device
KR100355938B1
(en)
*
1993-05-26
2002-12-16
가부시키가이샤 한도오따이 에네루기 켄큐쇼
Semiconductor device manufacturing method
KR100186886B1
(en)
*
1993-05-26
1999-04-15
야마자끼 승페이
Semiconductor device manufacturing method
1968
1968-11-29
FR
FR1593881D
patent/FR1593881A/fr
not_active
Expired
1968-12-03
GB
GB57279/68A
patent/GB1246294A/en
not_active
Expired
1968-12-05
AT
AT11854/68A
patent/AT283448B/en
not_active
IP Right Cessation
1968-12-05
US
US781542A
patent/US3692574A/en
not_active
Expired – Lifetime
1968-12-09
NL
NL686817602A
patent/NL140101B/en
unknown
1968-12-09
CH
CH1833168A
patent/CH486774A/en
not_active
IP Right Cessation
1968-12-11
NO
NO4947/68A
patent/NO123439B/no
unknown
1968-12-11
DE
DE1814029A
patent/DE1814029C3/en
not_active
Expired
1968-12-11
BE
BE725244D
patent/BE725244A/xx
unknown
1968-12-12
SE
SE17000/68A
patent/SE354382B/xx
unknown
Cited By (5)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
GB2129019A
(en)
*
1982-09-30
1984-05-10
Western Electric Co
Method of forming a heterostructure comprising a heteroepitaxial multiconstituent material
GB2228617A
(en)
*
1989-02-27
1990-08-29
Philips Electronic Associated
A method of manufacturing a semiconductor device having a mesa structure
GB2234263A
(en)
*
1989-06-16
1991-01-30
Intel Corp
Novel masking technique for depositing gallium arsenide on silicon
GB2234263B
(en)
*
1989-06-16
1993-05-19
Intel Corp
Novel masking technique for depositing gallium arsenide on silicon
US5256594A
(en)
*
1989-06-16
1993-10-26
Intel Corporation
Masking technique for depositing gallium arsenide on silicon
Also Published As
Publication number
Publication date
DE1814029A1
(en)
1969-08-14
DE1814029B2
(en)
1978-02-09
NL6817602A
(en)
1969-06-16
NO123439B
(en)
1971-11-15
DE1814029C3
(en)
1979-08-23
AT283448B
(en)
1970-08-10
SE354382B
(en)
1973-03-05
US3692574A
(en)
1972-09-19
NL140101B
(en)
1973-10-15
CH486774A
(en)
1970-02-28
FR1593881A
(en)
1970-06-01
BE725244A
(en)
1969-05-16
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