GB1252293A - Creation of Inventions and Patents with Artificial Intelligence

GB1252293A – – Google Patents

Info

Publication number
GB1252293A

GB1252293A

GB1252293DA
GB1252293A
GB 1252293 A
GB1252293 A
GB 1252293A

GB 1252293D A
GB1252293D A
GB 1252293DA
GB 1252293 A
GB1252293 A
GB 1252293A
Authority
GB
United Kingdom
Prior art keywords
polycrystalline
silicon
regions
layer
diffused
Prior art date
1967-11-14
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1967-11-14
Filing date
1968-11-14
Publication date
1971-11-03

1968-11-14
Application filed
filed
Critical

1971-11-03
Publication of GB1252293A
publication
Critical
patent/GB1252293A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

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Classifications

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor

H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer

H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 – H01L21/268

H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current

H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation

H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers

H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System

H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof

H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70

H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts

H01L21/743—Making of internal connections, substrate contacts

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate

H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components

H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology

H01L21/8222—Bipolar technology

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region

H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type

H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

Abstract

1,252,293. Semi-conductor devices. SONY CORP. 14 Nov., 1968 [14 Nov., 1967; 21 Dec., 1967], No. 54119/68. Heading H1K. Electrical connection to deep-lying layers in a semi-conductor structure is made through heavily doped polycrystalline regions which extend to the surface of the structure. Such regions are produced in otherwise monocrystalline structures by depositing semi-conductor material on to a monocrystalline substrate provided at selected regions with seeding sites for polycrystalline growth, so that the deposited material grows with both monocrystalline and polycrystalline portions. Diffusion into polycrystalline material is faster than into monocrystalline material so that deep and heavy doping may be affected in these connecting zones. Seeding sites may be deposits of sodium chloride, carbon, silicon dioxide, silicon monoxide, or of polycrystalline silicon or germanium. Seeding sites may be formed by roughening (e.g., sand-blasting) or scratching the semi-conductor surface. They may also be formed by alloying A1, In, Ga, Sb, P or As with the semi-conductor or by diffusing such impurities into the semi-conductor surface at very high concentrations. Fig. 1I shows part of an integrated structure containing a resistor formed in a P-type layer and an NPN transistor. As shown the N+ regions 4, 41 are formed by diffusion, seeding sites 5 of polycrystalline silicon are deposited, and layer 6 is then grown. Impurities from the N+ layers 4, 41 and from the bulk of the substrate 1 may be diffused into the grown layer during or after its growth. If insufficient N-type impurity diffuses into the polycrystalline material 8, diffusion of more impurities may be allowed by exposing the upper surface when the emitter 20 is being formed. The width of the collector electrode 241 (typically aluminium) may be less than, the same as, or greater than the width of the polycrystalline zone. In a variant, P-type impurity is diffused into the P- regions between devices during the formation of the resistor 15 and base region 14. If silicon oxide is used as alternative seeding material to silicon, diffusion from the N+ layers into the polycrystalline material takes place round the edges of the seeding site. If an alloy zone or heavily diffused region is used as seeding site this will itself act as a diffusion source. In variant structures the N+ layers may be replaced by a single epitaxial or diffused layer on the starting substrate. Fig. 2F shows a beam lead structure comprising a transistor and resistor. The starting material is an N+ silicon substrate and the site for the collector connection is seeded with silicon. Contacts are platinum silicide with beam leads constituted by successive vapour deposited layer of titanium and gold and a final electrodeposited gold layer. Fig. 3 (not shown) depicts a diode in which connection from the top-surface electrode 7 to the low resistivity base layer is through a polycrystalline channel; the annular anode 4 is provided in the higher resistivity grown upper layer 3. Fig. 4G (not shown) depicts a structure like that of Fig. 1 but in which the devices are separated by heavily diffusion doped polycrystalline isolation walls 12. In operation the devices are isolated by applying a reverse bias across a contact on the polycrystalline wall and contacts on the devices such as one on heavily diffused region 25. Fig. 5 (not shown) depicts a structure comprising two double gate JUGFETs, the lower gate regions 4 of which are connected to the upper surface by annular polycrystalline regions 8. Fig. 6F shows a high capacitance diode in which the junctions are connected in parallel by a P-type diffused polycrystalline region 36A and an N-type diffused polycrystalline region 361A. A structure may be designed to give a greater change of capacitance with applied voltage. Reference has been directed by the Comptroller to Specification 1,146,943.

GB1252293D
1967-11-14
1968-11-14

Expired

GB1252293A
(en)

Applications Claiming Priority (2)

Application Number
Priority Date
Filing Date
Title

JP7315567

1967-11-14

JP8205367

1967-12-21

Publications (1)

Publication Number
Publication Date

GB1252293A
true

GB1252293A
(en)

1971-11-03

Family
ID=26414310
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB1252293D
Expired

GB1252293A
(en)

1967-11-14
1968-11-14

Country Status (8)

Country
Link

BE
(1)

BE723823A
(en)

CH
(1)

CH509663A
(en)

DE
(1)

DE1808926B2
(en)

FR
(1)

FR1596671A
(en)

GB
(1)

GB1252293A
(en)

NL
(1)

NL157148B
(en)

NO
(1)

NO123436B
(en)

SE
(2)

SE354544B
(en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

DE2846671C2
(en)

1977-10-26
1982-09-09
Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa

A method of manufacturing a semiconductor device

IT1110843B
(en)

1978-02-27
1986-01-06
Rca Corp

Sunken contact for complementary type MOS devices

1968

1968-11-13
SE
SE1537868A
patent/SE354544B/xx
unknown

1968-11-13
SE
SE1702370A
patent/SE361778B/xx
unknown

1968-11-13
NL
NL6816188A
patent/NL157148B/en
not_active
IP Right Cessation

1968-11-13
NO
NO449268A
patent/NO123436B/no
unknown

1968-11-13
CH
CH1690568A
patent/CH509663A/en
not_active
IP Right Cessation

1968-11-14
FR
FR1596671D
patent/FR1596671A/fr
not_active
Expired

1968-11-14
BE
BE723823D
patent/BE723823A/xx
unknown

1968-11-14
GB
GB1252293D
patent/GB1252293A/en
not_active
Expired

1968-11-14
DE
DE19681808926
patent/DE1808926B2/en
not_active
Ceased

Also Published As

Publication number
Publication date

DE1808926B2
(en)

1979-08-02

CH509663A
(en)

1971-06-30

NL157148B
(en)

1978-06-15

DE1808926A1
(en)

1969-07-17

SE354544B
(en)

1973-03-12

NL6816188A
(en)

1969-05-19

BE723823A
(en)

1969-04-16

SE361778B
(en)

1973-11-12

NO123436B
(en)

1971-11-15

FR1596671A
(en)

1970-06-22

Contact information