GB1289251A – – Google Patents
GB1289251A – – Google Patents
Info
Publication number
GB1289251A
GB1289251A
GB1289251DA
GB1289251A
GB 1289251 A
GB1289251 A
GB 1289251A
GB 1289251D A
GB1289251D A
GB 1289251DA
GB 1289251 A
GB1289251 A
GB 1289251A
Authority
GB
United Kingdom
Prior art keywords
inverter
nand
output
gates
maintains
Prior art date
1970-05-08
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1970-05-08
Filing date
1971-05-10
Publication date
1972-09-13
1971-05-10
Application filed
filed
Critical
1972-09-13
Publication of GB1289251A
publication
Critical
patent/GB1289251A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
H—ELECTRICITY
H03—ELECTRONIC CIRCUITRY
H03K—PULSE TECHNIQUE
H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
H03K19/088—Transistor-transistor logic
H—ELECTRICITY
H03—ELECTRONIC CIRCUITRY
H03K—PULSE TECHNIQUE
H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
H03K3/037—Bistable circuits
H—ELECTRICITY
H03—ELECTRONIC CIRCUITRY
H03K—PULSE TECHNIQUE
H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
Abstract
1289251 Bi-stable logic circuits HONEYWELL INFORMATION SYSTEMS ITALIA SpA 10 May 1971 [8 May 1970] 14077/71 Heading H3T A bi-stable consists of AND gates 2, 3, 4, a NOR gate 5, and an inverting stage such as a NAND gate 8, all interconnected as shown and receiving a data signal D, and a control signal C, and its inverse which may be obtained by inverter 1. When D is high and the control (clock) C goes high, AND 4 causes NOR 5 to give a low output Q. This causes NAND 8 to give a high output Q, because R is normally high. Q enables AND gates 2, 3 so that until C ends, AND 3 maintains reciprocal coupling; and when C ends and the output of inverter 1 goes high, AND 2 maintains the reciprocal coupling. A low input to R resets independently of C and D. The NAND 8 may be alternatively a NOR (9, Fig. 4, not shown) with a normally low input, or it may be a simple inverter (6, Fig. 2, not shown). Diode transistor logic is used (Figs. 6, 7, not shown) or transistor-transistor logic (Fig. 8, not shown); and a shift register uses a plurality of the bistables (Fig. 5, not shown) having common C and R inputs. ‘
GB1289251D
1970-05-08
1971-05-10
Expired
GB1289251A
(en)
Applications Claiming Priority (3)
Application Number
Priority Date
Filing Date
Title
IT2430170
1970-05-08
US13933471A
1971-05-03
1971-05-03
US00288191A
US3845330A
(en)
1970-05-08
1972-09-11
Bistable electronic circuit
Publications (1)
Publication Number
Publication Date
GB1289251A
true
GB1289251A
(en)
1972-09-13
Family
ID=27273388
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB1289251D
Expired
GB1289251A
(en)
1970-05-08
1971-05-10
Country Status (4)
Country
Link
US
(1)
US3845330A
(en)
DE
(1)
DE2123513A1
(en)
FR
(1)
FR2093470A5
(en)
GB
(1)
GB1289251A
(en)
Families Citing this family (4)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3764920A
(en)
*
1972-06-15
1973-10-09
Honeywell Inf Systems
Apparatus for sampling an asynchronous signal by a synchronous signal
US4334157A
(en)
*
1980-02-22
1982-06-08
Fairchild Camera And Instrument Corp.
Data latch with enable signal gating
US4695743A
(en)
*
1985-10-23
1987-09-22
Hughes Aircraft Company
Multiple input dissymmetric latch
AU1913500A
(en)
1998-11-25
2000-06-13
Nanopower, Inc.
Improved flip-flops and other logic circuits and techniques for improving layouts of integrated circuits
Family Cites Families (1)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3454935A
(en)
*
1966-06-28
1969-07-08
Honeywell Inc
High-speed dual-rank flip-flop
1971
1971-05-05
FR
FR7116198A
patent/FR2093470A5/fr
not_active
Expired
1971-05-07
DE
DE19712123513
patent/DE2123513A1/en
active
Pending
1971-05-10
GB
GB1289251D
patent/GB1289251A/en
not_active
Expired
1972
1972-09-11
US
US00288191A
patent/US3845330A/en
not_active
Expired – Lifetime
Also Published As
Publication number
Publication date
FR2093470A5
(en)
1972-01-28
US3845330A
(en)
1974-10-29
DE2123513A1
(en)
1971-11-25
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Legal Events
Date
Code
Title
Description
1973-01-24
PS
Patent sealed [section 19, patents act 1949]
1980-01-03
PCNP
Patent ceased through non-payment of renewal fee
