GB1332470A - Creation of Inventions and Patents with Artificial Intelligence

GB1332470A – Data processor system
– Google Patents

GB1332470A – Data processor system
– Google Patents
Data processor system

Info

Publication number
GB1332470A

GB1332470A
GB6022770A
GB6022770A
GB1332470A
GB 1332470 A
GB1332470 A
GB 1332470A
GB 6022770 A
GB6022770 A
GB 6022770A
GB 6022770 A
GB6022770 A
GB 6022770A
GB 1332470 A
GB1332470 A
GB 1332470A
Authority
GB
United Kingdom
Prior art keywords
list
register
timing
processed
word
Prior art date
1969-12-23
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB6022770A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

AT&T Corp

Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1969-12-23
Filing date
1970-12-18
Publication date
1973-10-03

1970-12-18
Application filed by Western Electric Co Inc
filed
Critical
Western Electric Co Inc

1973-10-03
Publication of GB1332470A
publication
Critical
patent/GB1332470A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

Classifications

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F9/00—Arrangements for program control, e.g. control units

G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs

G06F9/46—Multiprogramming arrangements

G06F9/48—Program initiating; Program switching, e.g. by interrupt

G06F9/4806—Task transfer initiation or dispatching

G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

G06F9/4825—Interrupt from clock, e.g. time of day

Abstract

1332470 Data processing systems WESTERN ELECTRIC CO Inc 18 Dec 1970 [23 Dec 1969] 60227/70 Heading G4A A real time data processing system, e.g. controlling a telephone switching network or manufacturing process, includes a memory in which a plurality of locations are allocated to timing lists and a further location is allocated to a pointer, the lists being processed one at a time to recognize timing conditions in the operation of the system and the pointer being altered after processing each list to point to the next list in a predetermined sequence. In the described exemplary embodiment, a memory block is allocated to a head cell table containing 60 head cells each defining a corresponding one of 60 timing lists by specifying the first and last of the service circuit registers making up the list, intermediate registers in the list being linked to each other by addresses stored therein. An executive program activates a timing program at one second intervals to examine the timing list defined by the head cell which is pointed to by the present pointer word PP in memory, PP being incremented when the list has been processed so that the lists are processed at one second intervals, each list being processed at one minute intervals. When the executive program determines that a service circuit requires timing, e.g. to time a call, a task program stores timing interval T1 and time out return data TR in a corresponding service circuit register in the memory. The timing interval word T1 in minutes M and seconds S represents the time for which the register is to remain on a timing list. S is added to PP to form a word RPP which is stored in the register and serves as a pointer to the head cell defining the timing list to which the register is to be added, i.e. that list which will be processed S seconds after the next list to be processed. Insertion of the register to the end of the list pointed to is performed by conventional programming techniques with appropriate up-dating of the link addresses in the listed registers and the head cell, and a GPTC word in the newly added register is set to M representing the number of list processing operations to be performed on that register. The timing program, in examining a list, tests the GPTC word in each register, decrementing it if it is not zero. If the GPTC word is found to be zero, the timing program stores its own return address and transfers control to the instruction atthe address specified by TR in that register to enable the register to be updated, after which the timing program resumes processing of the list. A register can be removed from a list, e.g when a subscriber flashes the switch-hook to request operator assistance during a call, while saving any unexpired time. The displacement RI between the head cell of the list containing the register and the head cell of the next list to be processed is calculated from RI = RPP-PP + 1 to indicate the remaining seconds of the timing interval and the remaining minutes are transferred from GPTC to another word AC in the register before the register is removed from the list. Timing which has been interrupted in this way can be resumed by transferring the contents of AC back to GPTC in the relevant register and adding PP to RI to calculate the appropriate head cell defining the timing list to which the register is to be added.

GB6022770A
1969-12-23
1970-12-18
Data processor system

Expired

GB1332470A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

US88751769A

1969-12-23
1969-12-23

Publications (1)

Publication Number
Publication Date

GB1332470A
true

GB1332470A
(en)

1973-10-03

Family
ID=25391318
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB6022770A
Expired

GB1332470A
(en)

1969-12-23
1970-12-18
Data processor system

Country Status (2)

Country
Link

US
(1)

US3633181A
(en)

GB
(1)

GB1332470A
(en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

FR2201811A5
(en)

1972-09-29
1974-04-26
Honeywell Bull Soc Ind

US3909795A
(en)

1973-08-31
1975-09-30
Gte Automatic Electric Lab Inc
Program timing circuitry for central data processor of digital communications system

US4220990A
(en)

1978-09-25
1980-09-02
Bell Telephone Laboratories, Incorporated
Peripheral processor multifunction timer for data processing systems

US4482982A
(en)

1980-09-29
1984-11-13
Honeywell Information Systems Inc.
Communication multiplexer sharing a free running timer among multiple communication lines

JPS63123218A
(en)

1986-11-12
1988-05-27
Nec Corp
Timer/counter circuit

US5933655A
(en)

1996-09-30
1999-08-03
Allen-Bradley Company, Llc
System for scheduling periodic events having varying rates by cascading a plurality of overlapping linked list data structure

US6996645B1
(en)

2002-12-27
2006-02-07
Unisys Corporation
Method and apparatus for spawning multiple requests from a single entry of a queue

1969

1969-12-23
US
US887517A
patent/US3633181A/en
not_active
Expired – Lifetime

1970

1970-12-18
GB
GB6022770A
patent/GB1332470A/en
not_active
Expired

Also Published As

Publication number
Publication date

US3633181A
(en)

1972-01-04

Contact information