GB1332653A – Intergrated circuits
– Google Patents
GB1332653A – Intergrated circuits
– Google Patents
Intergrated circuits
Info
Publication number
GB1332653A
GB1332653A
GB1332653DA
GB1332653A
GB 1332653 A
GB1332653 A
GB 1332653A
GB 1332653D A
GB1332653D A
GB 1332653DA
GB 1332653 A
GB1332653 A
GB 1332653A
Authority
GB
United Kingdom
Prior art keywords
type
transistor
earth
conductive
channel
Prior art date
1971-04-19
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Electronics Ltd
Original Assignee
Marconi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1971-04-19
Filing date
1971-04-19
Publication date
1973-10-03
1971-04-19
Application filed by Marconi Co Ltd
filed
Critical
Marconi Co Ltd
1973-10-03
Publication of GB1332653A
publication
Critical
patent/GB1332653A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
H—ELECTRICITY
H03—ELECTRONIC CIRCUITRY
H03K—PULSE TECHNIQUE
H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
H03K19/096—Synchronous circuits, i.e. using clock signals
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
H01L27/0722—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with lateral bipolar transistors and diodes, or capacitors, or resistors
H—ELECTRICITY
H03—ELECTRONIC CIRCUITRY
H03K—PULSE TECHNIQUE
H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
Abstract
1332653 Transistor logic circuits MARCONI CO Ltd 19 April 1971 [16 May 1970] 23819/70 Heading H3T [Also in Division H1] An integrated circuit having a N-type silicon substrate 1 (Figs. 1a, 1b) comprises a MOS transistor having source 3 and drain 2 formed by P-type diffusion separated by channel 4 overlain by insulant oxide layer 5 and gate 6, and a lateral PNP-bipolar transistor having P-type emitter 7 formed by diffusion, channel 4 and substrate base overlain by oxide insulant 8: electrical connections being made by contact pads 9 connected through windows of the oxide layer. In operation, the MOS transistor is made conductive by connecting substate 1 and source 3 to reference potential and gate 6 and drain 2 over, e.g. resistive load to more negative potential, and its channel has low impedance due to electron migration from the layer underlying the oxide converting it from N-type to P-type, so that the P-type regions 4 and 7 are separated by N-type substrate to constitute a P-type lateral transistor whose collector is the MOS channel region 4. Fig. 2a shows one stage of a 4-phase dynamic shift register including 6 identical MOS transistors M1 to M6 and a bipolar PNP transistor T1 as described. Negative going clock pulses #1, #2, #3, #4 (Fig. 2b not shown) referred to earth are provided and an input signal is supplied at I/P. While #1, #2 are -ve, gate capacitance C of M6 is charged negative over M1 from #1, which returns to earth to close transistor M1 whereby C remains charged until a path to earth is provided over M3 or T1; M2 being conductive for duration of #2 and a “0” logic voltage on I/P rendering M3 conductive, so that C is discharged and the gate of M6 is earthed. During the subsequent interval in which #3 and #4 are negative the output is held negative by #3 over M4, and the input capacitance of a further register stage is charged. When #3 returns to earth, this input charge remains since M5 is held conductive by #3 and M6 is non-conductive since capacitance C is discharged. The output O/P remains at “0” logic level transferred from I/P, and similarly a “1” logic level (earth potential) at I/P would be transferred to the output during the cycle. Two MOS transistors may be provided with the channel of one serving as collector and that of the other as emitter of a lateral PNP transistor. The transistors may be surrounded by a negatively biased guard ring of P-type silicon.
GB1332653D
1971-04-19
1971-04-19
Intergrated circuits
Expired
GB1332653A
(en)
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
GB2381970
1971-04-19
Publications (1)
Publication Number
Publication Date
GB1332653A
true
GB1332653A
(en)
1973-10-03
Family
ID=10201825
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB1332653D
Expired
GB1332653A
(en)
1971-04-19
1971-04-19
Intergrated circuits
Country Status (1)
Country
Link
GB
(1)
GB1332653A
(en)
Cited By (1)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
DE2607177A1
(en)
*
1975-03-14
1976-09-30
Ibm
DEVICE FOR STABILIZATION OF INTEGRATED SEMI-CONDUCTOR ARRANGEMENTS
1971
1971-04-19
GB
GB1332653D
patent/GB1332653A/en
not_active
Expired
Cited By (1)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
DE2607177A1
(en)
*
1975-03-14
1976-09-30
Ibm
DEVICE FOR STABILIZATION OF INTEGRATED SEMI-CONDUCTOR ARRANGEMENTS
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Legal Events
Date
Code
Title
Description
1974-02-13
PS
Patent sealed
1976-11-17
PLNP
Patent lapsed through nonpayment of renewal fees
