GB1352577A - Creation of Inventions and Patents with Artificial Intelligence

GB1352577A – Multi-processor processing system having inter-processor interrupt transfer apparatus
– Google Patents

GB1352577A – Multi-processor processing system having inter-processor interrupt transfer apparatus
– Google Patents
Multi-processor processing system having inter-processor interrupt transfer apparatus

Info

Publication number
GB1352577A

GB1352577A
GB2682971*A
GB2682971A
GB1352577A
GB 1352577 A
GB1352577 A
GB 1352577A

GB 2682971 A
GB2682971 A
GB 2682971A
GB 1352577 A
GB1352577 A
GB 1352577A
Authority
GB
United Kingdom
Prior art keywords
interrupt
processor
word
handler
interruptable
Prior art date
1970-04-09
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB2682971*A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Unisys Corp

Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1970-04-09
Filing date
1971-04-19
Publication date
1974-05-08

1971-04-19
Application filed by Burroughs Corp
filed
Critical
Burroughs Corp

1974-05-08
Publication of GB1352577A
publication
Critical
patent/GB1352577A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

238000000034
method
Methods

0.000
abstract
2

230000008520
organization
Effects

0.000
abstract
1

Classifications

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

G06F13/14—Handling requests for interconnection or transfer

G06F13/20—Handling requests for interconnection or transfer for access to input/output bus

G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Abstract

1352577 Interrupt handling BURROUGHS CORP 19 April 1971 [9 April 1970] 26829/71 Heading G4A A data processing system includes first and second means for requesting an interrupt condition to be processed, first and second interrupt handlers normally respectively associated with the first and second interrupt requesting means and each having an interruptable and a non- interruptable state and being operative in the latter state to transfer an interrupt request from its associated interrupt requesting means to the other interrupt handler. Each processor of a multiprocessor system operates in one of two states, viz normal and control, the operating state being denoted by a flag flip-flop. In the control state the processor is non-interruptable and is handling, e.g. input/ output transfers. As shown two input/output channels are connected via respective multiplexors to respective interrupt handlers with which they are normally associated. The interrupt handlers may be self contained hardware or program controlled devices. Each handler has an associated left-to-right (LTR) and rightto-left (RTL) transfer circuit which consists of a number of gates and which assigns interrupts to the processors 7A and 7B. Control signals, which may if required be changed, are supplied to the gates to determine the normal allotment of interrupts to the processors. The occurrence of an interrupt normally associated with a handler in a non-interruptable state causes operation of the transfer circuits to re-allot the interrupt to a different handler and processor. Where more than two processors are involved the re-allotment is made on a system of priorities, the highest priority available processor being selected. The Specification briefly describes the organization within each processor. First in-last out stacks are provided for storing operands and instruction sequences. The stacks are accessed from a register which includes a field specifying the top word in the stack which is then accessed word by word using a counter. Each stack may specify the next in the sequence. For entering a new procedure, e.g. in response to an interrupt, the point reached in the interrupted sequence together with intermediate results &c. are stored in a stack specified by a return control word and the new procedure is entered by means of a program control word which may itself be a return control word. The input/output units may be magnetic tapes, discs or card readers and the main memory 12 may be a magnetic core.

GB2682971*A
1970-04-09
1971-04-19
Multi-processor processing system having inter-processor interrupt transfer apparatus

Expired

GB1352577A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

US2694470A

1970-04-09
1970-04-09

Publications (1)

Publication Number
Publication Date

GB1352577A
true

GB1352577A
(en)

1974-05-08

Family
ID=21834701
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB2682971*A
Expired

GB1352577A
(en)

1970-04-09
1971-04-19
Multi-processor processing system having inter-processor interrupt transfer apparatus

Country Status (6)

Country
Link

US
(1)

US3665404A
(en)

JP
(2)

JPS5535743B1
(en)

BE
(1)

BE764964A
(en)

CA
(1)

CA951829A
(en)

FR
(1)

FR2085966B1
(en)

GB
(1)

GB1352577A
(en)

Families Citing this family (56)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

GB1393898A
(en)

1971-08-17
1975-05-14
Systemware Ltd
Electronic data processing apparatus

US3812463A
(en)

1972-07-17
1974-05-21
Sperry Rand Corp
Processor interrupt pointer

IT988956B
(en)

1973-06-12
1975-04-30
Olivetti & Co Spa

MULTIPLE GOVERNMENT

JPS5616457B2
(en)

1973-07-18
1981-04-16

FR2254999A5
(en)

1973-12-12
1975-07-11
Honeywell Bull Soc Ind

US3947823A
(en)

1973-12-26
1976-03-30
International Business Machines Corp.
Means for coordinating asynchronous main store accesses in a multiprocessing system using virtual storage

JPS5434500B2
(en)

1973-12-30
1979-10-27

US4318182A
(en)

1974-04-19
1982-03-02
Honeywell Information Systems Inc.
Deadlock detection and prevention mechanism for a computer system

US3967246A
(en)

1974-06-05
1976-06-29
Bell Telephone Laboratories, Incorporated
Digital computer arrangement for communicating data via data buses

US4130865A
(en)

1974-06-05
1978-12-19
Bolt Beranek And Newman Inc.
Multiprocessor computer apparatus employing distributed communications paths and a passive task register

JPS5178643A
(en)

1974-12-29
1976-07-08
Fujitsu Ltd
Sabuchaneru memori akusesuseigyohoshiki

US4000487A
(en)

1975-03-26
1976-12-28
Honeywell Information Systems, Inc.
Steering code generating apparatus for use in an input/output processing system

US4152761A
(en)

1976-07-28
1979-05-01
Intel Corporation
Multi-task digital processor employing a priority

US4080649A
(en)

1976-12-16
1978-03-21
Honeywell Information Systems Inc.
Balancing the utilization of I/O system processors

US4268904A
(en)

1978-02-15
1981-05-19
Tokyo Shibaura Electric Co., Ltd.
Interruption control method for multiprocessor system

US4161786A
(en)

1978-02-27
1979-07-17
The Mitre Corporation
Digital bus communications system

US4231015A
(en)

1978-09-28
1980-10-28
General Atomic Company
Multiple-processor digital communication system

US4241330A
(en)

1978-09-28
1980-12-23
General Atomic Company
Multiple-processor digital communication system

US4309753A
(en)

1979-01-03
1982-01-05
Honeywell Information System Inc.
Apparatus and method for next address generation in a data processing system

NL7907179A
(en)

1979-09-27
1981-03-31
Philips Nv

SIGNAL PROCESSOR DEVICE WITH CONDITIONAL INTERRUPT UNIT AND MULTIPROCESSOR SYSTEM WITH THESE SIGNAL PROCESSOR DEVICES.

JPS57121750A
(en)

1981-01-21
1982-07-29
Hitachi Ltd
Work processing method of information processing system

USRE37496E1
(en)

1981-01-21
2002-01-01
Hitachi, Ltd
Method of executing a job

US4451882A
(en)

1981-11-20
1984-05-29
Dshkhunian Valery
Data processing system

US4703419A
(en)

1982-11-26
1987-10-27
Zenith Electronics Corporation
Switchcover means and method for dual mode microprocessor system

US4633387A
(en)

1983-02-25
1986-12-30
International Business Machines Corporation
Load balancing in a multiunit system

US5067071A
(en)

1985-02-27
1991-11-19
Encore Computer Corporation
Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus

US4858173A
(en)

1986-01-29
1989-08-15
Digital Equipment Corporation
Apparatus and method for responding to an aborted signal exchange between subsystems in a data processing system

US4831518A
(en)

1986-08-26
1989-05-16
Bull Hn Information Systems Inc.
Multiprocessor interrupt rerouting mechanism

GB8815042D0
(en)

1988-06-24
1988-08-03
Int Computers Ltd
Data processing apparatus

JPH04246763A
(en)

1991-01-31
1992-09-02
Nec Corp
Multi-processor circuit

JPH04318654A
(en)

1991-02-13
1992-11-10
Hewlett Packard Co
Redirection system for interruption to microprocessor

US5590380A
(en)

1992-04-22
1996-12-31
Kabushiki Kaisha Toshiba
Multiprocessor system with processor arbitration and priority level setting by the selected processor

US6393530B1
(en)

1998-04-17
2002-05-21
Intelect Communications, Inc.
Paging method for DSP

US6163829A
(en)

1998-04-17
2000-12-19
Intelect Systems Corporation
DSP interrupt control for handling multiple interrupts

US6678801B1
(en)

1998-04-17
2004-01-13
Terraforce Technologies Corp.
DSP with distributed RAM structure

US6456628B1
(en)

1998-04-17
2002-09-24
Intelect Communications, Inc.
DSP intercommunication network

US6189065B1
(en)

1998-09-28
2001-02-13
International Business Machines Corporation
Method and apparatus for interrupt load balancing for powerPC processors

US6295573B1
(en)

1999-02-16
2001-09-25
Advanced Micro Devices, Inc.
Point-to-point interrupt messaging within a multiprocessing computer system

US7197589B1
(en)

1999-05-21
2007-03-27
Silicon Graphics, Inc.
System and method for providing access to a bus

US6526514B1
(en)

1999-10-11
2003-02-25
Ati International Srl
Method and apparatus for power management interrupt processing in a computing system

US6813665B2
(en)

2001-09-21
2004-11-02
Intel Corporation
Interrupt method, system and medium

US20040111549A1
(en)

2002-12-10
2004-06-10
Intel Corporation
Method, system, and program for improved interrupt processing

US7849297B2
(en)

2003-08-28
2010-12-07
Mips Technologies, Inc.
Software emulation of directed exceptions in a multithreading processor

US9032404B2
(en)

2003-08-28
2015-05-12
Mips Technologies, Inc.
Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor

US7424599B2
(en)

2003-08-28
2008-09-09
Mips Technologies, Inc.
Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor

US20050050305A1
(en)

2003-08-28
2005-03-03
Kissell Kevin D.
Integrated mechanism for suspension and deallocation of computational threads of execution in a processor

US7870553B2
(en)

2003-08-28
2011-01-11
Mips Technologies, Inc.
Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

US7836450B2
(en)

2003-08-28
2010-11-16
Mips Technologies, Inc.
Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

US7426656B2
(en)

2004-03-30
2008-09-16
Hewlett-Packard Development Company, L.P.
Method and system executing user programs on non-deterministic processors

US20050240806A1
(en)

2004-03-30
2005-10-27
Hewlett-Packard Development Company, L.P.
Diagnostic memory dump method in a redundant processor

US20060020852A1
(en)

2004-03-30
2006-01-26
Bernick David L
Method and system of servicing asynchronous interrupts in multiple processors executing a user program

US20060112208A1
(en)

2004-11-22
2006-05-25
International Business Machines Corporation
Interrupt thresholding for SMT and multi processor systems

US8732368B1
(en)

2005-02-17
2014-05-20
Hewlett-Packard Development Company, L.P.
Control system for resource selection between or among conjoined-cores

US8285893B2
(en)

2006-10-13
2012-10-09
Dell Products L.P.
System and method for adaptively setting connections to input/output hubs within an information handling system

US10802998B2
(en)

2016-03-29
2020-10-13
Intel Corporation
Technologies for processor core soft-offlining

US10423550B2
(en)

2017-10-25
2019-09-24
International Business Machines Corporation
Managing efficient selection of a particular processor thread for handling an interrupt

Family Cites Families (2)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3482264A
(en)

1966-07-07
1969-12-02
Gen Electric
Data processing system including communication priority and priority sharing among subsystems

US3421150A
(en)

1966-08-26
1969-01-07
Sperry Rand Corp
Multiprocessor interrupt directory

1970

1970-04-09
US
US26944A
patent/US3665404A/en
not_active
Expired – Lifetime

1971

1971-02-08
CA
CA104,689,A
patent/CA951829A/en
not_active
Expired

1971-03-29
BE
BE764964A
patent/BE764964A/en
not_active
IP Right Cessation

1971-04-09
JP
JP2184271A
patent/JPS5535743B1/ja
active
Pending

1971-04-09
FR
FR7112735A
patent/FR2085966B1/fr
not_active
Expired

1971-04-19
GB
GB2682971*A
patent/GB1352577A/en
not_active
Expired

1978

1978-03-09
JP
JP2715478A
patent/JPS53149737A/en
active
Granted

Also Published As

Publication number
Publication date

FR2085966B1
(en)

1975-08-01

BE764964A
(en)

1971-08-16

CA951829A
(en)

1974-07-23

DE2113725B2
(en)

1973-10-04

JPS5537032B2
(en)

1980-09-25

US3665404A
(en)

1972-05-23

JPS53149737A
(en)

1978-12-27

JPS5535743B1
(en)

1980-09-16

DE2113725A1
(en)

1971-10-21

FR2085966A1
(en)

1971-12-31

Contact information