GB1353715A - Creation of Inventions and Patents with Artificial Intelligence

GB1353715A – Algebraic summing digital-to-analogue converter
– Google Patents

GB1353715A – Algebraic summing digital-to-analogue converter
– Google Patents
Algebraic summing digital-to-analogue converter

Info

Publication number
GB1353715A

GB1353715A
GB3502272A
GB3502272A
GB1353715A
GB 1353715 A
GB1353715 A
GB 1353715A
GB 3502272 A
GB3502272 A
GB 3502272A
GB 3502272 A
GB3502272 A
GB 3502272A
GB 1353715 A
GB1353715 A
GB 1353715A
Authority
GB
United Kingdom
Prior art keywords
counter
output
input
inputs
digital
Prior art date
1971-12-30
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB3502272A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Woodward Inc

Original Assignee
Woodward Governor Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1971-12-30
Filing date
1972-07-26
Publication date
1974-05-22

1972-07-26
Application filed by Woodward Governor Co
filed
Critical
Woodward Governor Co

1974-05-22
Publication of GB1353715A
publication
Critical
patent/GB1353715A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

238000000034
method
Methods

0.000
abstract
2

244000186140
Asperula odorata
Species

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abstract
1

235000008526
Galium odoratum
Nutrition

0.000
abstract
1

238000001514
detection method
Methods

0.000
abstract
1

Classifications

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06J—HYBRID COMPUTING ARRANGEMENTS

G06J1/00—Hybrid computing arrangements

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled

G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers

G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se

H—ELECTRICITY

H03—ELECTRONIC CIRCUITRY

H03M—CODING; DECODING; CODE CONVERSION IN GENERAL

H03M1/00—Analogue/digital conversion; Digital/analogue conversion

H—ELECTRICITY

H03—ELECTRONIC CIRCUITRY

H03M—CODING; DECODING; CODE CONVERSION IN GENERAL

H03M1/00—Analogue/digital conversion; Digital/analogue conversion

H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters

H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise

Abstract

1353715 Digital to analogue converters WOODWARD GOVERNOR CO 26 July 1972 [30 Dec 1971] 35022/72 Heading G4H A digital to analogue converter either produces an output of instantaneous frequency proportional to the algebraic sum of several digital inputs or a pulse train output of average level proportional to a digital input. Twelve bit binary signals R, Z, Z1 are applied to the respective input terminals C of selectors 200. The output D selects one of the inputs by a two bit number applied to terminals A and B and passes the signals to the stages of a 12 bit binary counter. An addressing device comprising two flip-flops 212, 214 is clocked by pulses on line 220 and provides four addresses (from its R terminals) to select one of the four inputs to selectors 200. The S output of flip-flop 214 (S2) gates clock pulses from source 180 to either the up or down input of counter 248 and is also connected to output 248. The counter has an output CRY when it is full and BRW when it is empty and these are used to clear and reenter inputs into the counter and to clock the addressing device. Positive input numbers are applied to lines R and Z and negative to Z1 (and to T when used). In operation, with inputs as above and all T inputs at logic 1, R 1 and R 2 , the reset states of the address counter are both at 1. Number Z is entered into the counter and, as S 2 is at 0, clock pulses are supplied to the down input of the counter. When the count reaches zero, BRW output changes and provides an output which steps the address circuit and clears the counter. The new address enters R into the counter, the counter again counts down to zero and resets. The new address resulting in address circuit is that of inputs T. All ones are entered into the counter and, as S 2 is now at 1, a clock pulse is applied to the up input. Output CRY immediately operates and clears the counter and steps the address circuit, the process on this input taking so little time compared with the other inputs that it is effectively bypassed. At the last address, number Z1 enters the counter which counts up until it is full and the process then recycles. The output taken from S 2 at point 248 is 0 during the count downs and 1 during the count ups and after detection of the leading edges of the pulses, the output is a pulse train of instantaneous period proportional to the algebraic sum of the input signals. When used as a digital to analogue converter, the input digital number is applied to both the Z and the Z1 terminals and the output is taken at 249, from the R stage of flip-flop 214. The resulting output is 1 during the countdown and 0 during count up and is a pulse train of mean D.C. level proportional to the input signal.

GB3502272A
1971-12-30
1972-07-26
Algebraic summing digital-to-analogue converter

Expired

GB1353715A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

US21416271A

1971-12-30
1971-12-30

Publications (1)

Publication Number
Publication Date

GB1353715A
true

GB1353715A
(en)

1974-05-22

Family
ID=22798008
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB3502272A
Expired

GB1353715A
(en)

1971-12-30
1972-07-26
Algebraic summing digital-to-analogue converter

Country Status (5)

Country
Link

US
(1)

US3786488A
(en)

JP
(1)

JPS4874962A
(en)

DE
(1)

DE2242935B2
(en)

FR
(1)

FR2165850B1
(en)

GB
(1)

GB1353715A
(en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3990000A
(en)

1975-07-10
1976-11-02
Rca Corporation
Alternating current control system

JPS5291638A
(en)

1976-01-29
1977-08-02
Sony Corp
D/a converter

US4053739A
(en)

1976-08-11
1977-10-11
Motorola, Inc.
Dual modulus programmable counter

US4205303A
(en)

1978-03-31
1980-05-27
International Business Machines Corporation
Performing arithmetic using indirect digital-to-analog conversion

US4194186A
(en)

1978-04-20
1980-03-18
The United States Of America As Represented By The Secretary Of The Air Force
Digital hysteresis circuit

GB8414314D0
(en)

1984-06-05
1984-07-11
Motorola Inc
Vertical synchronisation pulse separator

GB2176353B
(en)

1985-06-06
1988-08-24
Motorola Inc
D/a converter

Family Cites Families (6)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3305858A
(en)

1964-03-30
1967-02-21
Sperry Rand Corp
Digital to analog converter simulating a rotary inductor device

US3496562A
(en)

1966-07-29
1970-02-17
Motorola Inc
Range-limited conversion between digital and analog signals

GB1273429A
(en)

1969-08-01
1972-05-10
Standard Telephones Cables Ltd
Improvements in or relating to measuring instruments

US3624649A
(en)

1969-10-10
1971-11-30
Honeywell Inc
Period readout error checking apparatus

US3651414A
(en)

1970-04-30
1972-03-21
Lorain Prod Corp
Variable frequency system

US3646545A
(en)

1970-06-04
1972-02-29
Singer Co
Ladderless digital-to-analog converter

1971

1971-12-30
US
US00214162A
patent/US3786488A/en
not_active
Expired – Lifetime

1972

1972-07-26
GB
GB3502272A
patent/GB1353715A/en
not_active
Expired

1972-08-31
DE
DE19722242935
patent/DE2242935B2/en
active
Granted

1972-09-11
FR
FR7232129A
patent/FR2165850B1/fr
not_active
Expired

1972-12-21
JP
JP47127731A
patent/JPS4874962A/ja
active
Pending

Also Published As

Publication number
Publication date

DE2242935A1
(en)

1973-07-12

US3786488A
(en)

1974-01-15

JPS4874962A
(en)

1973-10-09

FR2165850A1
(en)

1973-08-10

DE2242935B2
(en)

1977-02-24

FR2165850B1
(en)

1976-07-23

Contact information