GB1360130A - Creation of Inventions and Patents with Artificial Intelligence

GB1360130A – Semiconductor devices
– Google Patents

GB1360130A – Semiconductor devices
– Google Patents
Semiconductor devices

Info

Publication number
GB1360130A

GB1360130A
GB2438072A
GB2438072A
GB1360130A
GB 1360130 A
GB1360130 A
GB 1360130A
GB 2438072 A
GB2438072 A
GB 2438072A
GB 2438072 A
GB2438072 A
GB 2438072A
GB 1360130 A
GB1360130 A
GB 1360130A
Authority
GB
United Kingdom
Prior art keywords
layer
region
type
monocrystalline
apertures
Prior art date
1971-06-18
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB2438072A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

International Business Machines Corp

Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1971-06-18
Filing date
1972-05-24
Publication date
1974-07-17

1972-05-24
Application filed by International Business Machines Corp
filed
Critical
International Business Machines Corp

1974-07-17
Publication of GB1360130A
publication
Critical
patent/GB1360130A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

239000004065
semiconductor
Substances

0.000
title
abstract
3

239000010410
layer
Substances

0.000
abstract
30

239000000463
material
Substances

0.000
abstract
17

229910004298
SiO 2
Inorganic materials

0.000
abstract
9

229910052785
arsenic
Inorganic materials

0.000
abstract
6

239000000758
substrate
Substances

0.000
abstract
4

238000004544
sputter deposition
Methods

0.000
abstract
3

238000000151
deposition
Methods

0.000
abstract
2

239000012535
impurity
Substances

0.000
abstract
2

230000001590
oxidative effect
Effects

0.000
abstract
2

238000009792
diffusion process
Methods

0.000
abstract
1

239000002019
doping agent
Substances

0.000
abstract
1

238000005530
etching
Methods

0.000
abstract
1

238000002955
isolation
Methods

0.000
abstract
1

238000004519
manufacturing process
Methods

0.000
abstract
1

239000002184
metal
Substances

0.000
abstract
1

229910052751
metal
Inorganic materials

0.000
abstract
1

238000012986
modification
Methods

0.000
abstract
1

230000004048
modification
Effects

0.000
abstract
1

230000003647
oxidation
Effects

0.000
abstract
1

238000007254
oxidation reaction
Methods

0.000
abstract
1

229910021420
polycrystalline silicon
Inorganic materials

0.000
abstract
1

239000011241
protective layer
Substances

0.000
abstract
1

Classifications

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L23/00—Details of semiconductor or other solid state devices

H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames

H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/02104—Forming layers

H01L21/02365—Forming inorganic semiconducting materials on a substrate

H01L21/02367—Substrates

H01L21/0237—Materials

H01L21/02373—Group 14 semiconducting materials

H01L21/02381—Silicon, silicon germanium, germanium

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/02104—Forming layers

H01L21/02365—Forming inorganic semiconducting materials on a substrate

H01L21/02518—Deposited layers

H01L21/02521—Materials

H01L21/02524—Group 14 semiconducting materials

H01L21/02532—Silicon, silicon germanium, germanium

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/02104—Forming layers

H01L21/02365—Forming inorganic semiconducting materials on a substrate

H01L21/02612—Formation types

H01L21/02617—Deposition types

H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials

H01L21/02639—Preparation of substrate for selective deposition

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof

H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70

H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts

H01L21/743—Making of internal connections, substrate contacts

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70

H01L21/76—Making of isolation regions between components

H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor

H01L29/66007—Multistep manufacturing processes

H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials

H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

H01L29/66234—Bipolar junction transistors [BJT]

H01L29/66272—Silicon vertical transistors

H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/0001—Technical content checked by a classifier

H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC

Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

Y10S148/00—Metal treatment

Y10S148/037—Diffusion-deposition

Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC

Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

Y10S148/00—Metal treatment

Y10S148/043—Dual dielectric

Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC

Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

Y10S148/00—Metal treatment

Y10S148/085—Isolated-integrated

Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC

Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

Y10S148/00—Metal treatment

Y10S148/122—Polycrystalline

Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC

Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

Y10S438/00—Semiconductor device manufacturing: process

Y10S438/969—Simultaneous formation of monocrystalline and polycrystalline regions

Abstract

1360130 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 24 May 1972 [18 June 1971] 24380/72 Heading H1K A method of making a semi-conductor device comprises forming a dielectric layer on a monocrystalline substrate, opening a window in the layer, growing an epitaxial layer in the window and continuing the growth over the dielectric layer surrounding the window thus forming monocrystalline material within and above the window and polycrystalline material above the dielectric, forming a component in the monocrystalline material and applying a contact for the component to the polycrystalline material, the lateral extent of the polycrystalline material being bounded by a second dielectric layer formed on the first layer. In a first embodiment, Figs. 1 to 4, a bi-polar transistor is produced by diffusing P, As or Sb through a mask to form an N+-type subcollector region 24 in a P–type substrate 20, removing the mask and oxidizing to form a thin protective layer on which a first thick SiO 2 layer 23 is applied by sputtering. A thin layer 25 of Si 3 N 4 is deposited and covered with a second thick SiO 2 layer 26. Apertures 28, 30, 32 are selectively etched through the insulating layers and P-type Si is epitaxially deposited in the apertures to the thickness of the first SiO 2 layer 23. These deposits are monocrystalline and in the apertures 30, 32 above the subcollector region the P-type material is converted to N-type due to redistribution of impurities. The part of the top SiO 2 layer surrounding the aperture 32 is removed by selective etching to define the device area 34, the Si 3 N 4 layer 25 preventing removal of the lower SiO 2 layer. P-type Si is then epitaxially deposited to fill the apertures. The material in the device region 34 is monocrystalline above the aperture 32 and is surrounded with polycrystalline material over the exposed Si 3 N 4 layer. The material deposited in the upper part of the aperture 30 is converted to N-type by diffusion to form a collector reach-through and an N+-type emitter region 36 is diffused into the monocrystalline part of the device region which forms the base of the transistor. A layer of metal is deposited and patterned to form contacts, the base connection being made via the polycrystalline material. The device may be modified to produce an inverse transistor so that region 36 forms the collector. In a second embodiment, Figs. 5 to 8 (not shown), a P–type Si wafer (20) with an N+-type sub-collector region (24) is provided with an insulating layer (26) by sputtering a thick layer SiO 2 and covering with a thin layer of Si 3 N 4 . Two apertures (40, 42) are formed above the sub-collector region and one aperture (44) which defines a resistor region is formed above the substrate. Si is epitaxially deposited in the openings and over the top of the insulating layer, the material being undoped or N–type until the apertures are filled and the dopant then being changed to P-type. The deposited material is monocrystalline within and above the apertures (40, 42, 44) but polycrystalline above the insulating layer. The surface is oxidized and unwanted portions of the epitaxial layer are etched away to leave the monocrystalline region surrounded by polycrystalline material over one of the apertures to form the device region and to leave the monocrystalline deposits within the other apertures. The surface is re-oxidized and P or As is selectively diffused into the reach-through and resistor areas, and As, P or Sb is selectively diffused-in to form the N+-type emitter region in the monocrystalline part of the base region and to heavily dope the collector and resistor contact regions. Al electrodes are then applied. In a modification, Fig. 9 (not shown), instead of removing parts of the deposited P-type layer, isolation is achieved by selective thermal oxidation of the polycrystalline Si. In another embodiment, Figs. 10 to 12 (not shown) an N+-type sub-collector region (24) is formed in a P-type substrate (20), the surface is oxidized (62) and covered with Si 3 N 4 (64) and two windows (66, 68) are opened above the sub-collector region. A thick layer (70) of SiO 2 is pyrolytically deposited and windows (72, 74) are opened aligned with those in the underlayers but one being of larger area. An undoped layer (76) is epitaxially grown in the windows, the deposit in the smaller windows being monocrystalline and that in the other window having a monocrystalline cone surrounded by polycrystalline material. P or As is selectively diffused onto the collector reach-through region (80), a P-type impurity is diffused onto the monocrystalline and polycrystalline base region and finally P or As is selectively diffused to form the emitter region (81) in the monocrystalline part of the base region and to form the collector contact region. Contacts are applied as before. In a further embodiment, Figs. 13 to 15 (not shown), an MOS transistor is produced by thermally oxidizing the surface of a P–type layer (82), depositing a layer (86) of Si 3 N 4 , opening a window (88) in the Si 3 N 4 layer, depositing a thick layer (90) of SiO 2 pyrolytically or by sputtering, and opening a larger window (92) in the thick SiO 2 layer. P-type material is epitaxially deposited to fill the windows and forms a monocrystalline core (94) flanked by polycrystalline material. The surface is oxidized and P or As is selectively diffused into the polycrystalline material to form the source and drain regions (98, 100), the edges of the monocrystalline region also being doped to form the active parts of these regions. The device is then completed by conventional processing.

GB2438072A
1971-06-18
1972-05-24
Semiconductor devices

Expired

GB1360130A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

US15445571A

1971-06-18
1971-06-18

Publications (1)

Publication Number
Publication Date

GB1360130A
true

GB1360130A
(en)

1974-07-17

Family
ID=22551425
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB2438072A
Expired

GB1360130A
(en)

1971-06-18
1972-05-24
Semiconductor devices

Country Status (7)

Country
Link

US
(1)

US3796613A
(en)

JP
(1)

JPS5140790B1
(en)

CA
(1)

CA976666A
(en)

DE
(1)

DE2223699A1
(en)

FR
(1)

FR2141938B1
(en)

GB
(1)

GB1360130A
(en)

IT
(1)

IT956495B
(en)

Cited By (2)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

GB2132017A
(en)

1982-12-16
1984-06-27
Secr Defence
Semiconductor device array

GB2253276A
(en)

1991-01-31
1992-09-02
Rolls Royce Plc
Fluid shear stress transducer

Families Citing this family (24)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

NL170901C
(en)

1971-04-03
1983-01-03
Philips Nv

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

NL166156C
(en)

1971-05-22
1981-06-15
Philips Nv

SEMICONDUCTOR DEVICE CONTAINING AT LEAST ONE on a semiconductor substrate BODY MADE SEMICONDUCTOR LAYER WITH AT LEAST ONE ISOLATION ZONE WHICH ONE IN THE SEMICONDUCTOR LAYER COUNTERSUNk INSULATION FROM SHAPED INSULATING MATERIAL BY LOCAL THERMAL OXIDATION OF HALF OF THE SEMICONDUCTOR LAYER GUIDE MATERIALS CONTAIN AND METHOD FOR MANUFACTURING SAME.

US3947299A
(en)

1971-05-22
1976-03-30
U.S. Philips Corporation
Method of manufacturing semiconductor devices

NL161301C
(en)

1972-12-29
1980-01-15
Philips Nv

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURE THEREOF.

US3956033A
(en)

1974-01-03
1976-05-11
Motorola, Inc.
Method of fabricating an integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector

US3913124A
(en)

1974-01-03
1975-10-14
Motorola Inc
Integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector including fabrication method therefor

NL180466C
(en)

1974-03-15
1987-02-16
Philips Nv

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR BODY PROVIDED WITH A PATTERN OF INSULATING MATERIAL RECOGNIZED IN THE SEMICONDUCTOR BODY.

US4074304A
(en)

1974-10-04
1978-02-14
Nippon Electric Company, Ltd.
Semiconductor device having a miniature junction area and process for fabricating same

US3972754A
(en)

1975-05-30
1976-08-03
Ibm Corporation
Method for forming dielectric isolation in integrated circuits

GB2010580B
(en)

1977-11-14
1982-06-30
Tokyo Shibaura Electric Co
Method for manufacturing a semiconductor device

JPS5539677A
(en)

1978-09-14
1980-03-19
Chiyou Lsi Gijutsu Kenkyu Kumiai
Semiconductor device and its manufacturing

US4252581A
(en)

1979-10-01
1981-02-24
International Business Machines Corporation
Selective epitaxy method for making filamentary pedestal transistor

US4333227A
(en)

1979-11-29
1982-06-08
International Business Machines Corporation
Process for fabricating a self-aligned micrometer bipolar transistor device

US4303933A
(en)

1979-11-29
1981-12-01
International Business Machines Corporation
Self-aligned micrometer bipolar transistor device and process

US4269631A
(en)

1980-01-14
1981-05-26
International Business Machines Corporation
Selective epitaxy method using laser annealing for making filamentary transistors

US4338138A
(en)

1980-03-03
1982-07-06
International Business Machines Corporation
Process for fabricating a bipolar transistor

DE3016553A1
(en)

1980-04-29
1981-11-05
Siemens AG, 1000 Berlin und 8000 München

PLANAR TRANSISTOR, ESPECIALLY FOR I (UP ARROW) 2 (UP ARROW) L STRUCTURES

US4487639A
(en)

1980-09-26
1984-12-11
Texas Instruments Incorporated
Localized epitaxy for VLSI devices

JPS5873156A
(en)

1981-10-28
1983-05-02
Hitachi Ltd
Semiconductor device

US4462847A
(en)

1982-06-21
1984-07-31
Texas Instruments Incorporated
Fabrication of dielectrically isolated microelectronic semiconductor circuits utilizing selective growth by low pressure vapor deposition

JPS59161867A
(en)

1983-03-07
1984-09-12
Hitachi Ltd
Semiconductor device

US4568601A
(en)

1984-10-19
1986-02-04
International Business Machines Corporation
Use of radiation sensitive polymerizable oligomers to produce polyimide negative resists and planarized dielectric components for semiconductor structures

US4728624A
(en)

1985-10-31
1988-03-01
International Business Machines Corporation
Selective epitaxial growth structure and isolation

DE19845787A1
(en)

1998-09-21
2000-03-23
Inst Halbleiterphysik Gmbh
Bipolar transistor, especially a high speed vertical bipolar transistor, is produced by single-poly technology with differential epitaxial base production using a nucleation layer to improve nucleation on an insulation region

1971

1971-06-18
US
US00154455A
patent/US3796613A/en
not_active
Expired – Lifetime

1972

1972-04-07
JP
JP47034577A
patent/JPS5140790B1/ja
active
Pending

1972-05-16
DE
DE19722223699
patent/DE2223699A1/en
not_active
Withdrawn

1972-05-24
GB
GB2438072A
patent/GB1360130A/en
not_active
Expired

1972-06-05
FR
FR7221478A
patent/FR2141938B1/fr
not_active
Expired

1972-06-08
CA
CA144,164A
patent/CA976666A/en
not_active
Expired

1972-06-13
IT
IT25585/72A
patent/IT956495B/en
active

Cited By (2)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

GB2132017A
(en)

1982-12-16
1984-06-27
Secr Defence
Semiconductor device array

GB2253276A
(en)

1991-01-31
1992-09-02
Rolls Royce Plc
Fluid shear stress transducer

Also Published As

Publication number
Publication date

CA976666A
(en)

1975-10-21

FR2141938B1
(en)

1978-03-03

US3796613A
(en)

1974-03-12

FR2141938A1
(en)

1973-01-26

DE2223699A1
(en)

1972-12-21

IT956495B
(en)

1973-10-10

JPS5140790B1
(en)

1976-11-05

Contact information