GB1374721A - Creation of Inventions and Patents with Artificial Intelligence

GB1374721A – Information storage
– Google Patents

GB1374721A – Information storage
– Google Patents
Information storage

Info

Publication number
GB1374721A

GB1374721A
GB3101172A
GB3101172A
GB1374721A
GB 1374721 A
GB1374721 A
GB 1374721A
GB 3101172 A
GB3101172 A
GB 3101172A
GB 3101172 A
GB3101172 A
GB 3101172A
GB 1374721 A
GB1374721 A
GB 1374721A
Authority
GB
United Kingdom
Prior art keywords
region
iii
electrode
diffused
storage region
Prior art date
1971-07-06
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB3101172A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

International Business Machines Corp

Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1971-07-06
Filing date
1972-07-03
Publication date
1974-11-20

1972-07-03
Application filed by International Business Machines Corp
filed
Critical
International Business Machines Corp

1974-11-20
Publication of GB1374721A
publication
Critical
patent/GB1374721A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

239000004065
semiconductor
Substances

0.000
abstract
3

238000009413
insulation
Methods

0.000
abstract
2

239000000463
material
Substances

0.000
abstract
1

238000000034
method
Methods

0.000
abstract
1

238000012986
modification
Methods

0.000
abstract
1

230000004048
modification
Effects

0.000
abstract
1

229910021420
polycrystalline silicon
Inorganic materials

0.000
abstract
1

Classifications

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor

H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

H01L29/1025—Channel region of field-effect devices

H01L29/1062—Channel region of field-effect devices of charge coupled devices

G—PHYSICS

G11—INFORMATION STORAGE

G11C—STATIC STORES

G11C16/00—Erasable programmable read-only memories

G11C16/02—Erasable programmable read-only memories electrically programmable

G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L29/40—Electrodes ; Multistep manufacturing processes therefor

H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions

H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

H01L29/42312—Gate electrodes for field effect devices

H01L29/42396—Gate electrodes for field effect devices for charge coupled devices

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor

H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched

H01L29/76—Unipolar devices, e.g. field effect transistors

H01L29/762—Charge transfer devices

H01L29/765—Charge-coupled devices

H01L29/768—Charge-coupled devices with field effect produced by an insulated gate

Abstract

1374721 Semi-conductor memory elements INTERNATIONAL BUSINESS MACHINES CORP 3 July 1972 [6 July 1971 (2)] 31011/72 Addition to 1374009 Heading H1K In a memory element in which binary information is represented by the flow of charge between a storage region III of a semi-conductor body 1 and a diffused region 3 making a PN junction with the body 1, a single electrode 32 is capacitively coupled both to the storage region III and to a gate region II between the regions 3 and III. The threshold voltage required on the electrode 32 to induce an inversion layer in the underlying semi-conductor material is lower for the storage region III than for the gate region II, with the result that the inversion layer in the region III may be selectively connected to or isolated from the diffused region 3 by an inversion channel in the region II. Two alternative modes of operation employing this facility and termed respectively “reach-through” and “clear” modes are described. The difference in inversion threshold between the regions is achieved in the illustrated embodiment by the provision at region II of a diffused or ion implanted zone 25 of the same conductivity type as but higher conductivity than the body 1. In a modification of this embodiment the higher conductivity zone defining the region II completely surrounds the diffused region 3. Other methods of achieving the required threshold difference are by providing a thicker oxide insulation 30 between the electrode 32 and the gate region II than between the electrode 32 and the storage region III, by providing a nitrideon-oxide insulation above the storage region III and oxide alone above the gate region II, or by providing an Al electrode above the gate region II and an Al-on-doped polycrystalline Si above the storage region III.

GB3101172A
1971-07-06
1972-07-03
Information storage

Expired

GB1374721A
(en)

Applications Claiming Priority (2)

Application Number
Priority Date
Filing Date
Title

US15990771A

1971-07-06
1971-07-06

US15986071A

1971-07-06
1971-07-06

Publications (1)

Publication Number
Publication Date

GB1374721A
true

GB1374721A
(en)

1974-11-20

Family
ID=26856384
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB3101172A
Expired

GB1374721A
(en)

1971-07-06
1972-07-03
Information storage

Country Status (3)

Country
Link

GB
(1)

GB1374721A
(en)

NL
(1)

NL7209362A
(en)

SE
(1)

SE384944B
(en)

1972

1972-06-14
SE
SE779672A
patent/SE384944B/en
unknown

1972-07-03
GB
GB3101172A
patent/GB1374721A/en
not_active
Expired

1972-07-04
NL
NL7209362A
patent/NL7209362A/xx
not_active
Application Discontinuation

Also Published As

Publication number
Publication date

NL7209362A
(en)

1973-01-09

SE384944B
(en)

1976-05-24

Contact information