GB1392231A – Switching system
– Google Patents
GB1392231A – Switching system
– Google Patents
Switching system
Info
Publication number
GB1392231A
GB1392231A
GB2153472A
GB2153472A
GB1392231A
GB 1392231 A
GB1392231 A
GB 1392231A
GB 2153472 A
GB2153472 A
GB 2153472A
GB 2153472 A
GB2153472 A
GB 2153472A
GB 1392231 A
GB1392231 A
GB 1392231A
Authority
GB
United Kingdom
Prior art keywords
processor
store
priority
circuit
gates
Prior art date
1971-05-12
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2153472A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1971-05-12
Filing date
1972-05-09
Publication date
1975-04-30
1972-05-09
Application filed by Philips Electronic and Associated Industries Ltd
filed
Critical
Philips Electronic and Associated Industries Ltd
1973-06-08
Priority to DE19732329310
priority
Critical
patent/DE2329310A1/en
1975-04-30
Publication of GB1392231A
publication
Critical
patent/GB1392231A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F13/14—Handling requests for interconnection or transfer
G06F13/16—Handling requests for interconnection or transfer for access to memory bus
G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
Abstract
1392231 Processors PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 9 May 1972 [12 May 1971] 21534/72 Heading G4A To reduce the time for which a common bus is occupied when information is to be transferred between one of a plurality of processors P, Q, R and one of the plurality of stores A, B, C, D a switching unit shown in Figs. 5A, 5B, is included between the processors and the stores, the unit comprising a register PSR-RSR, ASR-DSR for each processor and store and first and second priority circuits 1, 2, in the first of which is determined, for each requested store, the requesting processor having the highest priority and in the second of which is determined the highest priority store request. The latter may be determined by the priority of either the processors or the stores. As described, the registers PSR-RSR include a section Pn-Rn for the number of the associated processor, a section Pr-Rr for the number of the requested store(s) and a section PS-RS for the selection information. If, for example, processor P requests store B, processor Q requests store A and processor R requests stores A and D, priority unit 1 which comprises four sections receives an input from gates 102, 103 to circuit 1A, an input from gate 105 to circuit 1B and an input from gate 112 to circuit 1D which results in “occupied” flip-flops FFA, FFB, FFD being set. If processor P has the highest priority followed by processors Q, R circuits 1A-1D deliver outputs on leads 1AQ, 1BP, 1DR to control a switching unit SWC and to gates 114, 116, 124 respectively so that the numbers of processors Q, P and R are stored in registers XnA, XnB and XnD respectively, counters CCA, CCB and CCD starting cycling at this time. This results in signals CA, CB and CD being applied to priority circuit 2 and if the store A has the highest priority followed by stores B, C and D processor Q is first given access to store A so that counters CCB and CCD are held in their standby state whilst counter CCA continues to circulate. (Alternatively the line having the lowest processor number Pn may have priority in which case processor P is given access to store B). Access to store A is effected by gate 134 being enabled by the output A2 from priority circuit 2 and by signal 1AQ so that gate SB2 in selection bus SB is enabled to feed the information QS from the register QSR to register ASR at an appropriate output pulse from counter CCA. Transfer from a selected store is controlled by priority circuit 4 receiving at its input an output po of the circulating counter to select one of the registers XnA-XnD so that the processor number stored therein selects one of three gates OB5-OB7. The circuit 4 also enables one of four sets of gates OB1-OB4 so that data from the selected store is passed through the appropriate gate OB5-OB7 to the selected processor register PIOR-RIOR. When the information has been transferred a flip-flop FFOB in priority circuit 4 is cleared by the output ceo of the circulating counter to prepare the circuit 4 for the next request. Transfer from a processor is similarly effected by a priority circuit 3 receiving at its inputs an output pi from the circulating counter and selecting one of registers XnA-XnD, the processor number stored therein enabling the associated set of gates IB1-IB3 to transfer data from registers PIOR-RIOR by one set of four gates IB4- IB7, also enabled by the priority circuit 3, to the selected store AIOR-DIOR. When information has been transferred a flip-flop FFIB in the priority circuit 3 is cleared by the output cei of the circulating counter. At the final count of the circulating counter the flip-flop FFA-FFD in priority circuit 1 associated with the effected request is cleared to allow the system to proceed to the next highest priority request.
GB2153472A
1971-05-12
1972-05-09
Switching system
Expired
GB1392231A
(en)
Priority Applications (1)
Application Number
Priority Date
Filing Date
Title
DE19732329310
DE2329310A1
(en)
1972-05-09
1973-06-08
BURNERS FOR LIQUID FUEL
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
NL7106491A
NL7106491A
(en)
1971-05-12
1971-05-12
Publications (1)
Publication Number
Publication Date
GB1392231A
true
GB1392231A
(en)
1975-04-30
Family
ID=19813137
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB2153472A
Expired
GB1392231A
(en)
1971-05-12
1972-05-09
Switching system
Country Status (6)
Country
Link
US
(1)
US3761879A
(en)
JP
(1)
JPS5230095B1
(en)
CA
(1)
CA957779A
(en)
DE
(1)
DE2222855A1
(en)
GB
(1)
GB1392231A
(en)
NL
(1)
NL7106491A
(en)
Cited By (1)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
GB2148563A
(en)
*
1983-10-24
1985-05-30
British Telecomm
Multiprocessor system
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*
1973-08-30
1977-07-19
Burroughs Corporation
Computer-peripheral interface
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1973-09-08
1979-12-24
US3970993A
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*
1974-01-02
1976-07-20
Hughes Aircraft Company
Cooperative-word linear array parallel processor
FR2273317B1
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*
1974-05-28
1976-10-15
Philips Electrologica
US4130865A
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1974-06-05
1978-12-19
Bolt Beranek And Newman Inc.
Multiprocessor computer apparatus employing distributed communications paths and a passive task register
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1974-08-05
1976-05-25
Gte Automatic Electric Laboratories Incorporated
Multiprocessing system implemented with microprocessors
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1974-10-01
1979-01-23
Nippon Telegraph And Telephone Public Corporation
Microprogrammed, multipurpose processor having controllable execution speed
US4150428A
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1974-11-18
1979-04-17
Northern Electric Company Limited
Method for providing a substitute memory in a data processing system
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1975-04-14
1977-03-29
The Charles Stark Draper Laboratory, Inc.
Synchronous fault tolerant multi-processor system
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1975-08-08
1977-07-05
Bell Telephone Laboratories, Incorporated
Method and apparatus for controlling a multiprocessor system
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1975-09-30
1983-08-17
株式会社東芝
Keisan Kisouchi
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1976-04-22
1980-07-08
General Electric Company
Shared memory multi-microprocessor computer system
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1976-05-27
1977-12-27
Tokyo Shibaura Electric Co., Ltd.
Multi-processing system for controlling microcomputers and memories
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1977-01-28
1978-08-03
Siemens Ag
COMPUTER SYSTEM
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1978-02-17
1982-01-05
California Institute Of Technology
Step-oriented pipeline data processing system
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1978-10-31
1980-11-25
Honeywell Information Systems Inc.
Intersystem transaction identification logic
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1978-11-13
1980-12-02
Motorola, Inc.
Bus arbiter
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*
1979-01-09
1985-12-12
Sullivan Computer
Shared memory computer apparatus
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1979-01-09
1984-11-20
Sullivan Herbert W
Shared memory computer method and apparatus
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*
1979-06-20
1982-11-25
Siemens AG, 1000 Berlin und 8000 München
Method and arrangement for connecting several central processors to at least one peripheral processor
US4495567A
(en)
*
1981-10-15
1985-01-22
Codex Corporation
Multiprocessor/multimemory control system
GB2170624B
(en)
*
1982-06-05
1987-06-10
British Aerospace
Communication between computers
US4760521A
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*
1985-11-18
1988-07-26
White Consolidated Industries, Inc.
Arbitration system using centralized and decentralized arbitrators to access local memories in a multi-processor controlled machine tool
US4807184A
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*
1986-08-11
1989-02-21
Ltv Aerospace
Modular multiple processor architecture using distributed cross-point switch
AU598101B2
(en)
*
1987-02-27
1990-06-14
Honeywell Bull Inc.
Shared memory controller arrangement
US5088024A
(en)
*
1989-01-31
1992-02-11
Wisconsin Alumni Research Foundation
Round-robin protocol method for arbitrating access to a shared bus arbitration providing preference to lower priority units after bus access by a higher priority unit
US5274774A
(en)
*
1989-01-31
1993-12-28
Wisconsin Alumni Research Foundation
First-come first-serve arbitration protocol
US5142638A
(en)
*
1989-02-07
1992-08-25
Cray Research, Inc.
Apparatus for sharing memory in a multiprocessor system
US5283877A
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*
1990-07-17
1994-02-01
Sun Microsystems, Inc.
Single in-line DRAM memory module including a memory controller and cross bar switches
US5206952A
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*
1990-09-12
1993-04-27
Cray Research, Inc.
Fault tolerant networking architecture
JPH0594409A
(en)
*
1991-10-02
1993-04-16
Nec Eng Ltd
Bus arbitration system
US5576554A
(en)
*
1991-11-05
1996-11-19
Monolithic System Technology, Inc.
Wafer-scale integrated circuit interconnect structure architecture
US5831467A
(en)
*
1991-11-05
1998-11-03
Monolithic System Technology, Inc.
Termination circuit with power-down mode for use in circuit module architecture
EP0541288B1
(en)
*
1991-11-05
1998-07-08
Fu-Chieh Hsu
Circuit module redundacy architecture
US5498990A
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1991-11-05
1996-03-12
Monolithic System Technology, Inc.
Reduced CMOS-swing clamping circuit for bus lines
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*
1992-08-10
1994-03-03
Monolithic System Technology, Inc.
Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration
US5655113A
(en)
1994-07-05
1997-08-05
Monolithic System Technology, Inc.
Resynchronization circuit for a memory system and method of operating same
Family Cites Families (6)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3274554A
(en)
*
1961-02-15
1966-09-20
Burroughs Corp
Computer system
US3200380A
(en)
*
1961-02-16
1965-08-10
Burroughs Corp
Data processing system
US3419849A
(en)
*
1962-11-30
1968-12-31
Burroughs Corp
Modular computer system
US3274561A
(en)
*
1962-11-30
1966-09-20
Burroughs Corp
Data processor input/output control system
US3544965A
(en)
*
1966-03-25
1970-12-01
Burroughs Corp
Data processing system
US3593302A
(en)
*
1967-03-31
1971-07-13
Nippon Electric Co
Periphery-control-units switching device
1971
1971-05-12
NL
NL7106491A
patent/NL7106491A/xx
unknown
1972
1972-05-08
US
US00250990A
patent/US3761879A/en
not_active
Expired – Lifetime
1972-05-09
GB
GB2153472A
patent/GB1392231A/en
not_active
Expired
1972-05-09
CA
CA141,650A
patent/CA957779A/en
not_active
Expired
1972-05-10
DE
DE19722222855
patent/DE2222855A1/en
active
Pending
1972-05-12
JP
JP47046575A
patent/JPS5230095B1/ja
active
Pending
Cited By (2)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
GB2148563A
(en)
*
1983-10-24
1985-05-30
British Telecomm
Multiprocessor system
US4674033A
(en)
*
1983-10-24
1987-06-16
British Telecommunications Public Limited Company
Multiprocessor system having a shared memory for enhanced interprocessor communication
Also Published As
Publication number
Publication date
JPS5230095B1
(en)
1977-08-05
CA957779A
(en)
1974-11-12
DE2222855A1
(en)
1972-11-23
US3761879A
(en)
1973-09-25
NL7106491A
(en)
1972-11-14
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Legal Events
Date
Code
Title
Description
1975-09-10
PS
Patent sealed [section 19, patents act 1949]
1986-01-15
PCNP
Patent ceased through non-payment of renewal fee
