GB1402320A

GB1402320A – Decoder for use in 4-2-4 matrix playback system
– Google Patents

GB1402320A – Decoder for use in 4-2-4 matrix playback system
– Google Patents
Decoder for use in 4-2-4 matrix playback system

Info

Publication number
GB1402320A

GB1402320A
GB4793072A
GB4793072A
GB1402320A
GB 1402320 A
GB1402320 A
GB 1402320A
GB 4793072 A
GB4793072 A
GB 4793072A
GB 4793072 A
GB4793072 A
GB 4793072A
GB 1402320 A
GB1402320 A
GB 1402320A
Authority
GB
United Kingdom
Prior art keywords
signals
control
output
circuit
signal
Prior art date
1971-10-25
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB4793072A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Sansui Electric Co Ltd

Original Assignee
Sansui Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1971-10-25
Filing date
1972-10-18
Publication date
1975-08-06

1971-10-25
Priority claimed from JP46084484A
external-priority
patent/JPS5127363B2/ja

1971-10-30
Priority claimed from JP46086521A
external-priority
patent/JPS5127364B2/ja

1971-11-04
Priority claimed from JP46087832A
external-priority
patent/JPS5127366B2/ja

1971-11-10
Priority claimed from JP46089678A
external-priority
patent/JPS5127367B2/ja

1971-12-29
Priority claimed from JP722145A
external-priority
patent/JPS5213404B2/ja

1972-03-23
Priority claimed from JP47029332A
external-priority
patent/JPS5249721B2/ja

1972-04-17
Priority claimed from JP47038407A
external-priority
patent/JPS5249723B2/ja

1972-10-18
Application filed by Sansui Electric Co Ltd
filed
Critical
Sansui Electric Co Ltd

1975-08-06
Publication of GB1402320A
publication
Critical
patent/GB1402320A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

Classifications

H—ELECTRICITY

H04—ELECTRIC COMMUNICATION TECHNIQUE

H04S—STEREOPHONIC SYSTEMS

H04S3/00—Systems employing more than two channels, e.g. quadraphonic

H04S3/02—Systems employing more than two channels, e.g. quadraphonic of the matrix type, i.e. in which input signals are combined algebraically, e.g. after having been phase shifted with respect to each other

Abstract

1402320 Quadraphonic decoders SANSUI ELECTRIC CO Ltd 18 Oct 1972 [25 Oct 1971 30 Oct 1971 4 Nov 1971 10 Nov 1971 29 Dec 1971 23 March 1972 17 April 1972] 47930/72 Heading H4R A decoder for use in a 4-2-4 quadraphonic playback system has at least one control unit responsive to the instantaneous amplitude relationships of the directional audio input signals in the first and second channel signals. A first variable matrix means, controlled by one of the control signals, produces two audio output signals corresponding to two directional audio input signals. A second variable matrix means, controlled by the other control signal produces two audio output signals corresponding to two remaining directional audio input signals. One embodiment (Fig. 4) has encoded L and R signals applied at terminals 23, 24. A first variable matrix circuit includes resistors 35, 36, 37 and a second variable matrix-circuit includes resistors 39, 40, 41 and an inverter 42. Resistors 36 and 40 comprise photosensitive CdS elements illuminated by incandescent lamps 44, 45 respectively. The control unit 32 (see Fig. 5) is a phase discriminator and has limiters 50, 53 to transform signals L,R into rectangular wave signals. Output signals of opposite polarities produced by the limiter 53 are amplified by amplifiers 56 and 58 respectivelyand their outputs are applied to switching circuits 60 and 61 thereby causing these switching circuits to be ON and OFF alternately. The output from limiter 50 is coupled to the common input of switching circuits 60, 61. Their output terminals are grounded through capacitors 62, 63. Slidable arms of potentiometers 64, 65 supply control outputs EC1, EC2. The control circuit 32 operates to switch signal L by alternatively rendering ON and OFF switching circuits 60, 61 in response to signal R, thereby discriminating the phase difference between signals R and L. Returning to Fig. 4, where the phase difference between signals L and R is about zero, a loud sound is present at the front and a small sound at the rear. The first control output EC1 from control unit 32 is large, whereas the second control output is small. As a result, lamp control circuits 46, 47 operate to pass a large current through lamp 45 but a small current through lamp 44. Consequently resistor 40 has a small resistance value whereas element 36 has a large resistance value. Accordingly the level of signal L in decoder output FL1 is increased but the level of signal R contributing to cross-talk is decreased. The level of signal R in decoder output FR1 is increased whereas the level of signal L contributing to cross-talk is decreased. On the other hand the level of signal R in output RR1 is decreased while the level of the signal L contributing to cross-talk is increased. This means a separation between rear channels. However, as the level of front channel signals is increased and the level of rear channel signals is decreased the separation between front and rear channels is improved. Where the phase difference between signals L and R is about 180 degrees the separation between the front channels is improved and that between rear channels is improved. Where the phase difference between signals L and R is about 90 degrees (i.e. where sounds at the same level are present at front and rear) the control outputs EC1 and EC2 have the same level and the circuit (Fig. 4) operates as a fixed matrix circuit. In an alternative circuit (Fig. 8) sum and difference signals (L + R) and (L – R) are applied to logarithmic amplifiers 70 and 72 respectively. A boot-strap circuit 74 applies signals proportional to log (L + R) of opposite phases across a rectifier 78. Similarly a bootstrap circuit 76 applies signals proportional to log (L-R) of opposite phases across a rectifier circuit 79. The output of rectifier 78, proportional to log |L+R|, and the output of rectifier circuit 79, proportional to log |L-R|, are applied to transistors 80, 81 constituting a differential amplifier 82. A first control output EC1 corresponds to log A second control output EC2 corresponds to log Another embodiment (Fig. 9) has a first matrix circuit 90 for the front channels comprising a differential amplifier 91 including two transistors 92, 93. Signal L is coupled to the base of transistor 92 while signal R is coupled to the base of transistor 93 through an emitter 94. The collector of transistor 92 provides the first output while the collector of transistor 93 provides the second output. A first control circuit 99 includes a F.E.T. 100 connected to a control input terminal so that it acts as a variable resistor. The control circuit 99 operates to vary the A.C. impedance of the emitter circuits of transistors 92, 93 in accordance with the magnitude of the control input so as to control the gain of the differential amplifier 91. A similar matrix circuit 105 for the rear channels is provided but has no inverter. A further embodiment has, for the front channels, matrix circuits 120, 121 (Fig. 10) for producing signals (L+R)and (L-R). (The signal (L-R) is applied to a third matrix circuit 123 via a variable gain amplifier 122 to be added to the outputs from matrix circuit 120. Circuit 123 functions to produce an output expressed by (1+f)L and (1-f)R, and an output -(1-f)L, -(1+f)R which is coupled to terminal 28-2 through an inverter 124. The rear channel signals are obtained by matrix circuits 125, 126, 128 and a variable gain amplifier 127. The gains of variable gain amplifiers 122, 127 are varied in opposite directions by control outputs EC1 and EC2 for control unit 32. Phase chargers 29, 30 are provided. A detailed circuit is given (Fig. 11, not shown). With the circuit described, reproduced high frequency sound may be wrongly positioned at the front or rear by the over-riding influence of low frequency sounds, or vice versa. This may be eliminated by using variable gain amplifiers 122, 127 having a low gain for frequencies below 200 Hz, a high gain for signals higher than 5 kHz and gain control in the frequency band of 200 Hz to 5 kHz. Filter circuits to achieve this are described (Figs. 11, 12, not shown). Two elaborations of the decoder of Fig. 10 are described (Fig. 13, 25, not shown) for independent control of front-left and -right channels and the rear-left and -right channels. This includes various phase shifters, matrix circuits and either phase discriminators (Fig. 13) or comparators (Fig. 25). In a further elaboration (not shown) the two channel signals are divided into a plurality of frequency bands and control signals are produced for the respective frequency bands.

GB4793072A
1971-10-25
1972-10-18
Decoder for use in 4-2-4 matrix playback system

Expired

GB1402320A
(en)

Applications Claiming Priority (7)

Application Number
Priority Date
Filing Date
Title

JP46084484A

JPS5127363B2
(en)

1971-10-25
1971-10-25

JP46086521A

JPS5127364B2
(en)

1971-10-30
1971-10-30

JP46087832A

JPS5127366B2
(en)

1971-11-04
1971-11-04

JP46089678A

JPS5127367B2
(en)

1971-11-10
1971-11-10

JP722145A

JPS5213404B2
(en)

1971-12-29
1971-12-29

JP47029332A

JPS5249721B2
(en)

1972-03-23
1972-03-23

JP47038407A

JPS5249723B2
(en)

1972-04-17
1972-04-17

Publications (1)

Publication Number
Publication Date

GB1402320A
true

GB1402320A
(en)

1975-08-06

Family
ID=27563172
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB4793072A
Expired

GB1402320A
(en)

1971-10-25
1972-10-18
Decoder for use in 4-2-4 matrix playback system

Country Status (3)

Country
Link

US
(1)

US3825684A
(en)

GB
(1)

GB1402320A
(en)

NL
(1)

NL159558B
(en)

Cited By (1)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

GB2502618A
(en)

*

2012-06-01
2013-12-04
British Sky Broadcasting Ltd
Surround Sound Speaker System with Wireless Rear Speakers

Families Citing this family (31)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3967063A
(en)

*

1971-06-23
1976-06-29
Cbs Inc.
Logic for matrix systems for reproducing quadraphonic sound

JPS5317283B2
(en)

*

1973-03-07
1978-06-07

JPS5248001B2
(en)

*

1973-08-20
1977-12-07

JPS5323161B2
(en)

*

1973-08-27
1978-07-13

JPS5248002B2
(en)

*

1973-09-18
1977-12-07

DE2445123C3
(en)

*

1973-09-26
1980-03-06
Hitachi, Ltd.

Analog signal processing circuit

GB1514162A
(en)

*

1974-03-25
1978-06-14
Ruggles W
Directional enhancement system for quadraphonic decoders

US3943287A
(en)

*

1974-06-03
1976-03-09
Cbs Inc.
Apparatus and method for decoding four channel sound

US3937885A
(en)

*

1974-09-06
1976-02-10
Motorola, Inc.
Control circuit for a matrixed four channel audio reproducing system

JPS5154401A
(en)

*

1974-11-07
1976-05-13
Sansui Electric Co
Matorikusu 4 channeruyodekooda

US4799260A
(en)

*

1985-03-07
1989-01-17
Dolby Laboratories Licensing Corporation
Variable matrix decoder

US5046098A
(en)

*

1985-03-07
1991-09-03
Dolby Laboratories Licensing Corporation
Variable matrix decoder with three output channels

US4862502A
(en)

*

1988-01-06
1989-08-29
Lexicon, Inc.
Sound reproduction

US5172415A
(en)

*

1990-06-08
1992-12-15
Fosgate James W
Surround processor

US5136650A
(en)

*

1991-01-09
1992-08-04
Lexicon, Inc.
Sound reproduction

US5727068A
(en)

*

1996-03-01
1998-03-10
Cinema Group, Ltd.
Matrix decoding method and apparatus

US5796844A
(en)

*

1996-07-19
1998-08-18
Lexicon
Multichannel active matrix sound reproduction with maximum lateral separation

US5870480A
(en)

*

1996-07-19
1999-02-09
Lexicon
Multichannel active matrix encoder and decoder with maximum lateral separation

US7280664B2
(en)

2000-08-31
2007-10-09
Dolby Laboratories Licensing Corporation
Method for apparatus for audio matrix decoding

US7283634B2
(en)

*

2004-08-31
2007-10-16
Dts, Inc.
Method of mixing audio channels using correlated outputs

JP4558792B2
(en)

*

2005-06-30
2010-10-06
富士通株式会社

DC / DC converter and power amplifier using the same

JP4602204B2
(en)

*

2005-08-31
2010-12-22
ソニー株式会社

Audio signal processing apparatus and audio signal processing method

JP4479644B2
(en)

*

2005-11-02
2010-06-09
ソニー株式会社

Signal processing apparatus and signal processing method

JP4637725B2
(en)

*

2005-11-11
2011-02-23
ソニー株式会社

Audio signal processing apparatus, audio signal processing method, and program

JP4940671B2
(en)

*

2006-01-26
2012-05-30
ソニー株式会社

Audio signal processing apparatus, audio signal processing method, and audio signal processing program

JP4894386B2
(en)

*

2006-07-21
2012-03-14
ソニー株式会社

Audio signal processing apparatus, audio signal processing method, and audio signal processing program

JP4835298B2
(en)

*

2006-07-21
2011-12-14
ソニー株式会社

Audio signal processing apparatus, audio signal processing method and program

JP5082327B2
(en)

*

2006-08-09
2012-11-28
ソニー株式会社

Audio signal processing apparatus, audio signal processing method, and audio signal processing program

CN101502131B
(en)

*

2006-08-10
2014-06-25
皇家飞利浦电子股份有限公司
A device for and a method of processing an audio signal

AU2015275309B2
(en)

*

2011-06-06
2017-10-12
Reality Ip Pty Ltd
Matrix encoder with improved channel separation

US8693697B2
(en)

2011-06-06
2014-04-08
Reality Ip Pty Ltd
Matrix encoder with improved channel separation

Family Cites Families (1)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

JPS5213082B1
(en)

*

1971-07-19
1977-04-12

1972

1972-10-18
GB
GB4793072A
patent/GB1402320A/en
not_active
Expired

1972-10-19
US
US00298933A
patent/US3825684A/en
not_active
Expired – Lifetime

1972-10-24
NL
NL7214354.A
patent/NL159558B/en
not_active
IP Right Cessation

Cited By (1)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

GB2502618A
(en)

*

2012-06-01
2013-12-04
British Sky Broadcasting Ltd
Surround Sound Speaker System with Wireless Rear Speakers

Also Published As

Publication number
Publication date

NL159558B
(en)

1979-02-15

US3825684A
(en)

1974-07-23

NL7214354A
(en)

1973-04-27

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Legal Events

Date
Code
Title
Description

1975-12-17
PS
Patent sealed [section 19, patents act 1949]

1990-06-13
PCNP
Patent ceased through non-payment of renewal fee

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