GB1466478A – Regeneration of dynamic monolithic memories
– Google Patents
GB1466478A – Regeneration of dynamic monolithic memories
– Google Patents
Regeneration of dynamic monolithic memories
Info
Publication number
GB1466478A
GB1466478A
GB2172474A
GB2172474A
GB1466478A
GB 1466478 A
GB1466478 A
GB 1466478A
GB 2172474 A
GB2172474 A
GB 2172474A
GB 2172474 A
GB2172474 A
GB 2172474A
GB 1466478 A
GB1466478 A
GB 1466478A
Authority
GB
United Kingdom
Prior art keywords
bit line
transistor
latch
pulse
transistors
Prior art date
1973-06-29
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2172474A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1973-06-29
Filing date
1974-05-16
Publication date
1977-03-09
1974-05-16
Application filed by International Business Machines Corp
filed
Critical
International Business Machines Corp
1977-03-09
Publication of GB1466478A
publication
Critical
patent/GB1466478A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
G—PHYSICS
G11—INFORMATION STORAGE
G11C—STATIC STORES
G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
G11C11/409—Read-write [R-W] circuits
G11C11/4094—Bit-line management or control circuits
G—PHYSICS
G11—INFORMATION STORAGE
G11C—STATIC STORES
G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
G—PHYSICS
G11—INFORMATION STORAGE
G11C—STATIC STORES
G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Abstract
1466478 Data store INTERNATIONAL BUSINESS MACHINES CORP 16 May 1974 [29 June 1973] 21724/74 Heading G4C [Also in Division H3] A monolithic data store has an array of dynamic storage cells requiring periodic refreshing, and refresh circuits. Four rows of cells are shown, each cell comprising a transistor, e.g. 101, gated by signals on column word lines WL1, and connected in series with a capacitor CL1 between the substrate SS and the left or right half of a bit line B/L1, B/L2. The bit line halves are connected through a latch L1 and to a bit drive and sense circuit through isolation transistor 10 whose gate is biased at a constant level V L equal to the nominal up level of the bit line. To read and restore a selected cell a pulse R turns on transistors 12 and 22 in the refresh circuits and transistors 36, 38 in the latch to bring the bit line halves to their nominal “up” level V L and to charge the gate capacitance of transistors 14, 24. Since transistor 10 has its gate biased at V L it isolates the bit line from any voltage fluctuations at node A. A word line pulse then occurs to select one of the cells in the row. If the storage capacitor of the selected cell was charged the appropriate bit line half has its voltage raised and conversely if it was not charged its voltage is lowered. The resulting voltages on the bit line halves at the latch causes one of latch transistors to conduct when subsequently an LP pulse grounds the sources of the latch transistors 32, 34 and the right hand bit line half is grounded or maintained close to its nominal potential V L accordingly. The conventions adopted for binary 1 and binary zero, i.e. charged or uncharged, in the two halves of a row are opposite due to the inversion imposed by the latch. The bit line voltage appearing at isolation transistor 10 is sensed at node A by the sense circuits since transistor 10 will conduct or not depending on the voltage on B/L2. Subsequently a chip select pulse CSX is applied to the refresh circuit in the accessed half of the row and switches transistor 26 on to refresh the data in the accessed cell if the charge V H stored at the gate capacitance of transistor 24 has not been discharged due to bit line B/L1 being grounded during the read access, transistor 26 remaining off if the bit line was discharged during the read access since the discharged bit line prevents transistor 24 from switching on. A write operation is similar to a read operation except that node A is set at the appropriate potential to charge or otherwise the selected cell prior to the occurrence of the LP pulse.
GB2172474A
1973-06-29
1974-05-16
Regeneration of dynamic monolithic memories
Expired
GB1466478A
(en)
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
US00375273A
US3806898A
(en)
1973-06-29
1973-06-29
Regeneration of dynamic monolithic memories
Publications (1)
Publication Number
Publication Date
GB1466478A
true
GB1466478A
(en)
1977-03-09
Family
ID=23480223
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB2172474A
Expired
GB1466478A
(en)
1973-06-29
1974-05-16
Regeneration of dynamic monolithic memories
Country Status (7)
Country
Link
US
(1)
US3806898A
(en)
JP
(1)
JPS5518989B2
(en)
CA
(1)
CA1033841A
(en)
DE
(1)
DE2430690C3
(en)
FR
(1)
FR2235455B1
(en)
GB
(1)
GB1466478A
(en)
IT
(1)
IT1010160B
(en)
Families Citing this family (30)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3882326A
(en)
*
1973-12-26
1975-05-06
Ibm
Differential amplifier for sensing small signals
US3979603A
(en)
*
1974-08-22
1976-09-07
Texas Instruments Incorporated
Regenerative charge detector for charged coupled devices
US3967252A
(en)
*
1974-10-03
1976-06-29
Mostek Corporation
Sense AMP for random access memory
US3949385A
(en)
*
1974-12-23
1976-04-06
Ibm Corporation
D.C. Stable semiconductor memory cell
FR2304991A1
(en)
*
1975-03-15
1976-10-15
Ibm
ARRANGEMENT OF CIRCUITS FOR SEMICONDUCTOR MEMORY AND ITS OPERATING PROCEDURE
US3953839A
(en)
*
1975-04-10
1976-04-27
International Business Machines Corporation
Bit circuitry for enhance-deplete ram
US4007381A
(en)
*
1975-04-18
1977-02-08
Bell Telephone Laboratories, Incorporated
Balanced regenerative charge detection circuit for semiconductor charge transfer devices
US3978459A
(en)
*
1975-04-21
1976-08-31
Intel Corporation
High density mos memory array
US4003035A
(en)
*
1975-07-03
1977-01-11
Motorola, Inc.
Complementary field effect transistor sense amplifier for one transistor per bit ram cell
US4031522A
(en)
*
1975-07-10
1977-06-21
Burroughs Corporation
Ultra high sensitivity sense amplifier for memories employing single transistor cells
US4158891A
(en)
*
1975-08-18
1979-06-19
Honeywell Information Systems Inc.
Transparent tri state latch
US4010453A
(en)
*
1975-12-03
1977-03-01
International Business Machines Corporation
Stored charge differential sense amplifier
US4050061A
(en)
*
1976-05-03
1977-09-20
Texas Instruments Incorporated
Partitioning of MOS random access memory array
US4028557A
(en)
*
1976-05-21
1977-06-07
Bell Telephone Laboratories, Incorporated
Dynamic sense-refresh detector amplifier
US4081701A
(en)
*
1976-06-01
1978-03-28
Texas Instruments Incorporated
High speed sense amplifier for MOS random access memory
US4174541A
(en)
*
1976-12-01
1979-11-13
Raytheon Company
Bipolar monolithic integrated circuit memory with standby power enable
DE2712735B1
(en)
*
1977-03-23
1978-09-14
Ibm Deutschland
Read / write access circuit to memory cells of a memory and method for their operation
JPS53120238A
(en)
*
1977-03-29
1978-10-20
Mitsubishi Electric Corp
Semiconductor amplifier
JPS53120237A
(en)
*
1977-03-29
1978-10-20
Mitsubishi Electric Corp
Semiconductor amplifier circuit
US4162416A
(en)
*
1978-01-16
1979-07-24
Bell Telephone Laboratories, Incorporated
Dynamic sense-refresh detector amplifier
DE2803226C2
(en)
*
1978-01-25
1983-01-20
Siemens AG, 1000 Berlin und 8000 München
Dynamic evaluation circuit for semiconductor memories
JPS54158828A
(en)
*
1978-06-06
1979-12-15
Toshiba Corp
Dynamic type semiconductor memory device
FR2442488A1
(en)
*
1978-11-22
1980-06-20
Cii Honeywell Bull
DEVICE FOR EXTRACTING AND REWRITING INFORMATION FOR A COOLING MEMORY
JPS5570990A
(en)
*
1978-11-22
1980-05-28
Fujitsu Ltd
Sense amplifier circuit
US4262342A
(en)
*
1979-06-28
1981-04-14
Burroughs Corporation
Charge restore circuit for semiconductor memories
US4296480A
(en)
*
1979-08-13
1981-10-20
Mostek Corporation
Refresh counter
US4291392A
(en)
*
1980-02-06
1981-09-22
Mostek Corporation
Timing of active pullup for dynamic semiconductor memory
US4291393A
(en)
*
1980-02-11
1981-09-22
Mostek Corporation
Active refresh circuit for dynamic MOS circuits
JPS5956292A
(en)
*
1982-09-24
1984-03-31
Hitachi Ltd
Semiconductor storage device
US5339274A
(en)
*
1992-10-30
1994-08-16
International Business Machines Corporation
Variable bitline precharge voltage sensing technique for DRAM structures
Family Cites Families (4)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
GB1296067A
(en)
*
1969-03-21
1972-11-15
US3646525A
(en)
*
1970-01-12
1972-02-29
Ibm
Data regeneration scheme without using memory sense amplifiers
US3678473A
(en)
*
1970-06-04
1972-07-18
Shell Oil Co
Read-write circuit for capacitive memory arrays
DE2309192C3
(en)
*
1973-02-23
1975-08-14
Siemens Ag, 1000 Berlin Und 8000 Muenchen
Regenerating circuit in the manner of a keyed flip-flop and method for operating such a regenerating circuit
1973
1973-06-29
US
US00375273A
patent/US3806898A/en
not_active
Expired – Lifetime
1974
1974-04-29
IT
IT21991/74A
patent/IT1010160B/en
active
1974-05-07
FR
FR7416722A
patent/FR2235455B1/fr
not_active
Expired
1974-05-16
GB
GB2172474A
patent/GB1466478A/en
not_active
Expired
1974-05-28
JP
JP5941574A
patent/JPS5518989B2/ja
not_active
Expired
1974-06-12
CA
CA202,286A
patent/CA1033841A/en
not_active
Expired
1974-06-26
DE
DE2430690A
patent/DE2430690C3/en
not_active
Expired
Also Published As
Publication number
Publication date
FR2235455A1
(en)
1975-01-24
DE2430690C3
(en)
1981-10-15
DE2430690B2
(en)
1981-02-12
IT1010160B
(en)
1977-01-10
JPS5024039A
(en)
1975-03-14
US3806898A
(en)
1974-04-23
DE2430690A1
(en)
1975-01-16
FR2235455B1
(en)
1978-01-20
JPS5518989B2
(en)
1980-05-22
CA1033841A
(en)
1978-06-27
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Legal Events
Date
Code
Title
Description
1977-07-20
PS
Patent sealed [section 19, patents act 1949]
1994-01-12
PCNP
Patent ceased through non-payment of renewal fee
Effective date:
19930516
