GB1481609A - Creation of Inventions and Patents with Artificial Intelligence

GB1481609A – Apparatus arranged to process a plurality of discrete computing tasks
– Google Patents

GB1481609A – Apparatus arranged to process a plurality of discrete computing tasks
– Google Patents
Apparatus arranged to process a plurality of discrete computing tasks

Info

Publication number
GB1481609A

GB1481609A
GB56060/74A
GB5606074A
GB1481609A
GB 1481609 A
GB1481609 A
GB 1481609A
GB 56060/74 A
GB56060/74 A
GB 56060/74A
GB 5606074 A
GB5606074 A
GB 5606074A
GB 1481609 A
GB1481609 A
GB 1481609A
Authority
GB
United Kingdom
Prior art keywords
task
flag
processor
entry
tasks
Prior art date
1974-01-21
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB56060/74A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Control Data Corp

Original Assignee
Control Data Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1974-01-21
Filing date
1974-12-30
Publication date
1977-08-03

1974-12-30
Application filed by Control Data Corp
filed
Critical
Control Data Corp

1977-08-03
Publication of GB1481609A
publication
Critical
patent/GB1481609A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

Classifications

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F9/00—Arrangements for program control, e.g. control units

G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs

G06F9/46—Multiprogramming arrangements

G06F9/48—Program initiating; Program switching, e.g. by interrupt

G06F9/4806—Task transfer initiation or dispatching

G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system

G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

1481609 Data processing system CONTROL DATA CORP 30 Dec 1974 [21 Jan 1974] 56060/74 Heading G4A In a multiprocessor data processing system including a main memory storing a plurality of tasks and a task description table containing, for each task, an entry specifying data necessary for the execution of that task status flag, each processor is arranged during the execution of a task and in response to a “call task instruction” to store in the description table a corresponding task entry including a status flag indicating “ready”, and in response to an “end task instruction”, terminating the current task, to search the task description table for an entry whose status flag indicates ready and in response to the location of such an entry to change the corresponding status flag to “execute” and to load the corresponding task from the main memory into its local memory from where it is executed. As described eight processors are provided each being generally similar to the others except that one has certain overall control functions, e.g. monitoring for faults. Initially a start-up program, which may be hard wired in the control processor or read in from a peripheral, is executed to load common executive routines (shown in Fig. 5) in specified areas of the local memory of each processor. The executive routine starts at point A and causes the processor to search the task description table in the main store, interlocks being provided to ensure that only one processor at a time has access to the table. Each processor is coupled by a pair of data channels to a main store access unit which includes three buffer stores and other interface equipment, each buffer acting to accumulate 480 bit words for the main memory from 12 bit words supplied by the processors and vice versa. The processor words include address signals and read/write function codes &c. When a table entry showing “ready” status and indicating that the corresponding task is suitable for execution by the searching processor is located the status flag is changed from “ready” to “execute” and the task is copied from main memory into the processor local store for execution, there being suitable routines for acquiring the appropriate data, specified by the table entry, to allow the task to be executed. To allow tasks to co-operate certain tasks include “call task”, “set flag”, and “test flag” instructions. In response to a “call task” instruction the processor establishes an appropriate task entry with its status flag at “ready” and stores it in the main memory from where it is subsequently accessed by any one of the processors. When one task requires data collected by another, the first task performs a “test flag” routine to test a flag which is stored in a flag table by the other task when the data is available. If the “test flag” routine detects that the flag is not set the requesting task status in the description table is changed to “wait” and a search is instituted through the table entries for another task to execute. When a task is suspended, e.g. after a “test flag” routine, a save procedure enables data relating to the task to be stored and subsequently retrieved when the task is resumed. The “set flag” routine establishes a flag in the appropriate entry and sets the flag to the appropriate state or merely sets the flag if it already exists. The “set flag instruction” also changes the status of all tasks waiting for the flag, determined by corresponding references in the flag table, from “wait” to “ready”. In response to an “end task” instruction indicating that the current task is complete the status flag in the appropriate description table entry is set to “terminate” and a procedure is followed to examine the the entries of all related tasks, i.e. tasks called by the terminated task and tasks which called the terminated task. The appropirate entries in the description table are then deleted if appropriate, e.g. the entry of the terminated task is deleted if no other active tasks were called by it. The system is described in some detail with each processor having up to eight associated peripherals, e.g. card readers, punches, magnetic tape devices, CRT, &c.

GB56060/74A
1974-01-21
1974-12-30
Apparatus arranged to process a plurality of discrete computing tasks

Expired

GB1481609A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

US05/435,356

US4073005A
(en)

1974-01-21
1974-01-21
Multi-processor computer system

Publications (1)

Publication Number
Publication Date

GB1481609A
true

GB1481609A
(en)

1977-08-03

Family
ID=23728063
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB56060/74A
Expired

GB1481609A
(en)

1974-01-21
1974-12-30
Apparatus arranged to process a plurality of discrete computing tasks

Country Status (8)

Country
Link

US
(1)

US4073005A
(en)

JP
(1)

JPS50105040A
(en)

CA
(1)

CA1012652A
(en)

DE
(1)

DE2449547A1
(en)

ES
(1)

ES434009A1
(en)

FR
(1)

FR2258667B1
(en)

GB
(1)

GB1481609A
(en)

NL
(1)

NL7500498A
(en)

Cited By (3)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

GB2199966A
(en)

1986-12-19
1988-07-20
Nippon Telegraph & Telephone
Load balancing in multi-processor system

US5241677A
(en)

1986-12-19
1993-08-31
Nippon Telepgraph and Telehone Corporation
Multiprocessor system and a method of load balancing thereof

GB2273378A
(en)

1992-12-09
1994-06-15
Mitsubishi Electric Corp
Task allocation in a network.

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1974-04-17
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Nat Res Dev
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Telecommunications network central control system – has several interchangeable arithmetic units generated by mass memory for individual communication forms

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Method for the configuration and functioning of the computer system of a two-way cable television center

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multiplex information processing system

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Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and method for performing the same

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Shared synchronous memory multiprocessing arrangement

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Bell Telephone Laboratories, Incorporated
Multiprocessor system with demand assignable program paging stores

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Hardware scheduler/dispatcher for data processing system

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Fanuc Ltd
Control system for plural microprocessors

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Hitachi Ltd
Bus control system

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Shared storage for multiple processor systems

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Fixed resource allocation method and apparatus for multiprocessor systems having complementarily phased cycles

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1981-12-15
Nippon Electric Co., Ltd.
Data processing system with a plurality of processors

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Operations controller for a fault-tolerant multiple computer system

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1980-02-05
1982-03-02
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Scheduler for a multiple computer system

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1980-02-05
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Task communicator for multiple computer system

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1980-02-28
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Independent handling of I/O interrupt requests and associated status information transfers

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1981-03-05
1984-02-07
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Microprogrammed digital data processing system employing multi-phase subroutine control for concurrently executing tasks

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1981-05-04
1983-07-19
International Business Machines Corporation
Multi-processor task dispatching apparatus

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Toshiba Corp
Mutual exclusion system

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Co-processor combination

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Memory access method and apparatus in multiple processor systems

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1984-06-22
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American Telephone And Telegraph Company, At&T Bell Laboratories
Reconfigurable dual processor system

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1985-01-30
1987-01-13
International Business Machines Corporation
Method for controlling execution of application programs written in high level program language

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1985-02-05
1993-04-15
Digital Equipment Corp

APPARATUS AND METHOD FOR ACCESS CONTROL IN A MULTI-MEMORY DATA PROCESSING ARRANGEMENT.

US4754398A
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1985-06-28
1988-06-28
Cray Research, Inc.
System for multiprocessor communication using local and common semaphore and information registers

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1986-09-10
1995-06-05
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I / O device address method

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Controlled dynamic load balancing for a multiprocessor system

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1986-12-29
1994-01-18
Nec Corporation
Multiprocessor system sharing expandable virtual memory and common operating system

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1987-02-06
1988-08-10
Canon Inc
Instrument control equipment

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1988-02-29
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Convex Computer Corporation
Multi-processor computer system having self-allocating processors

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1988-02-29
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Multi-processor computer system having process-independent communication register addressing

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1988-09-07
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International Business Machines Corp.
Sharing of workspaces in interactive processing using workspace name tables for linking of workspaces

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1989-02-07
1992-08-25
Cray Research, Inc.
Apparatus for sharing memory in a multiprocessor system

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International Business Machines Corporation
Multiprocessor with relatively atomic instructions

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1998-12-16
株式会社東芝

Instruction assignment device and instruction assignment method

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1989-12-29
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Supercomputer Systems Limited Partnership
System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling

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R. J. Reynolds Tobacco Company
Intelligent computer integrated maintenance system and method

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COMMUNICATION SYSTEM WITH A MULTIPROCESSOR SYSTEM THAT SERVES FOR CENTRAL CONTROL.

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Contention handling apparatus for generating user busy signal by logically summing wait output of next higher priority user and access requests of higher priority users

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Method and apparatus for controlling the deferred execution of user requests in a data processing system

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1974

1974-01-21
US
US05/435,356
patent/US4073005A/en
not_active
Expired – Lifetime

1974-09-12
CA
CA209,124A
patent/CA1012652A/en
not_active
Expired

1974-10-17
DE
DE19742449547
patent/DE2449547A1/en
not_active
Withdrawn

1974-10-29
JP
JP49124834A
patent/JPS50105040A/ja
active
Pending

1974-12-30
GB
GB56060/74A
patent/GB1481609A/en
not_active
Expired

1975

1975-01-16
NL
NL7500498A
patent/NL7500498A/en
not_active
Application Discontinuation

1975-01-21
ES
ES434009A
patent/ES434009A1/en
not_active
Expired

1975-01-21
FR
FR7501828A
patent/FR2258667B1/fr
not_active
Expired

Cited By (7)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

GB2199966A
(en)

1986-12-19
1988-07-20
Nippon Telegraph & Telephone
Load balancing in multi-processor system

GB2199966B
(en)

1986-12-19
1991-08-07
Nippon Telegraph & Telephone
Multiprocessor system and a method of load balancing thereof

US5053950A
(en)

1986-12-19
1991-10-01
Nippon Telegraph And Telephone Corporation
Multiprocessor system and a method of load balancing thereof

US5241677A
(en)

1986-12-19
1993-08-31
Nippon Telepgraph and Telehone Corporation
Multiprocessor system and a method of load balancing thereof

GB2273378A
(en)

1992-12-09
1994-06-15
Mitsubishi Electric Corp
Task allocation in a network.

GB2273378B
(en)

1992-12-09
1996-11-06
Mitsubishi Electric Corp
Client server system and control method thereof

US6169991B1
(en)

1992-12-09
2001-01-02
Mitsubishi Denki Kabushiki Kaisha
Client server system and control method thereof

Also Published As

Publication number
Publication date

FR2258667B1
(en)

1980-09-12

AU7721375A
(en)

1976-07-15

NL7500498A
(en)

1975-07-23

CA1012652A
(en)

1977-06-21

JPS50105040A
(en)

1975-08-19

FR2258667A1
(en)

1975-08-18

US4073005A
(en)

1978-02-07

ES434009A1
(en)

1977-02-16

DE2449547A1
(en)

1975-07-24

Contact information