GB1565400A

GB1565400A – High resolution and wide range shaft position transducer systems
– Google Patents

GB1565400A – High resolution and wide range shaft position transducer systems
– Google Patents
High resolution and wide range shaft position transducer systems

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Publication number
GB1565400A

GB1565400A
GB47734/76A
GB4773476A
GB1565400A
GB 1565400 A
GB1565400 A
GB 1565400A
GB 47734/76 A
GB47734/76 A
GB 47734/76A
GB 4773476 A
GB4773476 A
GB 4773476A
GB 1565400 A
GB1565400 A
GB 1565400A
Authority
GB
United Kingdom
Prior art keywords
signals
transducer
counter
signal
shaft
Prior art date
1975-12-18
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB47734/76A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Otis Elevator Co

Original Assignee
Otis Elevator Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1975-12-18
Filing date
1976-11-16
Publication date
1980-04-23

1976-11-16
Application filed by Otis Elevator Co
filed
Critical
Otis Elevator Co

1980-04-23
Publication of GB1565400A
publication
Critical
patent/GB1565400A/en

Status
Expired
legal-status
Critical
Current

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Classifications

H—ELECTRICITY

H03—ELECTRONIC CIRCUITRY

H03M—CODING; DECODING; CODE CONVERSION IN GENERAL

H03M1/00—Analogue/digital conversion; Digital/analogue conversion

H03M1/12—Analogue/digital converters

H03M1/22—Analogue/digital converters pattern-reading type

H03M1/24—Analogue/digital converters pattern-reading type using relatively movable reader and disc or strip

H03M1/28—Analogue/digital converters pattern-reading type using relatively movable reader and disc or strip with non-weighted coding

H03M1/30—Analogue/digital converters pattern-reading type using relatively movable reader and disc or strip with non-weighted coding incremental

H03M1/308—Analogue/digital converters pattern-reading type using relatively movable reader and disc or strip with non-weighted coding incremental with additional pattern means for determining the absolute position, e.g. reference marks

Description

(54) HIGH RESOLUTION AND WIDE RANGE SHAFT
POSITION TRANSDUCER SYSTEMS
(71) We, OTIS ELEVATOR COMPANY, a corporation organized and existing under the laws of the State of New Jersey, United
States of America, of 750 Third Avenue,
New York, New York, 10017, United States of America do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following state ment : – This invention relates to apparatus for generating signals signifying the angular position of a shaft which rotates a plurality of times.
In the past when it has been desired to produce a signal indicative of the angular position of a shaft which rotates a plurality of times, it has been standard practice where high resolution and wide range are to be obtained to employ a gear reduction unit with two rotary position transducers.
One transducer is driven directly from the shaft to give accurate resolution signals. The other transducer is driven from the gear reduction unit and produces the range signals. Early arrangements of this type required extremely accurate and costly gear reduction units.
An arrangement for reducing the complexity of a gear reduction unit for use with two rotary position transducers is taught in U. S. Patent No. 2,944,159. This simplified gear arrangement is employed in U. S. Patent No. 3,885,209 in combination with two synchros or resolvers which are electrically coupled to cascade to provide analog position signals. When synchros or resolvers of the type employed in this latter patent are employed and a digital output signal signifying the position of a shaft is desired, analog to digital conversion equipment is required. Conversion to digital signals is difficult where both high resolution and wide range are provided by the analog equipment and consequently, such apparatus is expensive.
It is an object of this invention to provide apparatus which produces digital signals signifying the angular position of a shaft and is simpler than previous apparatus.
One of the features of the invention is the employment of two rotary position transducers, both of which rotate a plurality of times and produce signals which are ambiguous, in that the same signals are generated for each revolution of the respective transducer.
In carrying out the invention, there is provided apparatus for generating electrical signals signifying the angular position of a shaft which rotates in use through a plurality of revolutions, comprising a first rotary position transducer arranged to be driven by the shaft and to generate the same first signals during each revolution of the transducer, the first signals signifying the angular position of a first reference point of the first transducer during each revolution of the transducer, a second rotary position transducer arranged to be driven by the shaft so that when the first transducer is driven through a first plurality of revolutions the second transducer is driven through a second plurality of revolutions differing from said first plurality by one revolution and to generate the same second signals on each revolution of the second transducer, the second signals signifying at least when a second reference point of the second transducer reaches a reference position, and logic circuitry arranged to be responsive to the first and second signals and to provide signals signifying both the angular position of the first reference point and the number of revolutions of the shaft, said logic circuitry including a difference circuit arranged to determine the number of revolutions by deter mining the difference in the angular positions of the first and second transducers, which difference changes by a constant amount on each revolution of tbe shaft.
Three separate embodiments of the invention are described. In the first disclosed, the first and second rotational signal general tors are absolute encoding devices. Consequently upon the restoration of power after a loss thereof each immediately produces its respective output signal whereupon the logic circuitry immediately produces the rotary position signal signifying both the correct angular position Of the first reference point – and the correct number of rotations of the first shaft.
In the second and third disclosed embodiments, incremental signal producing devices are employed as the first and second rotational signal generators. Both of the embodiments are arranged however to overcome a shortcoming of previous position transducers employing incremental devices. Upon the restoration of power following a loss thereof previous incremental type transducers required the return to an initial condition or reliance upon an external reference in order to reproduce the correct angular position of the first reference point and the correct number of rotations of the first shaft.
The arrangements of the second and third embodiments disclosed herein have the advantage of not requiring either of the restoratives needed by previous incremental type transducers. As a result, they combine tbe simplicity of incremental devices with the advantage of absolute devices in this regard. In the second embodiment, restoration of the correct angular position of the first reference point and the correct number of rotations of the first shaft is accomplished within two revolutions of the first shaft after the return of power following a power loss. In the third embodiment such restoration is accomplished within one such revolution. From these embodiments, those skilled in the art will also understand how more rapid restora tives can be accomplished by obvious modifications of the embodiments.
Other objects, features and advantages of the invention will be apparent from the following description of exemplary embodiments of the invention when considered in conjunction with the accompanying drawings, in whichh:
Figure 1 is a generalized configuration of some of the mechanical elements of an embodiment of the invention;
Figure 2 is a block diagram of one embodiment of the invention;
Figures 3 and 4 taken together show the circuit elements employed in the embodiment shown in Figure 2;
Figure 5 is a block diagram of another embodiment of the invention;
Figure 6 shows an arrangement of the circuit elements employed in the embodiment shown in Figure 5;
Figure 7 is a block diagram of a third embodiment of the invention; and
Figures 8A and 8B show an arrangement of the circuit elements employed in the embodiment shown in Figure 7.
Referring now to the drawing, shown in
Figure 1 is input shaft 101 upon which is mounted first gear 102 and rotary position transducer 103 Intermeshing with gear 102 is another gear 104 which together with second rotary position transducer 105 is mounted on shaft 106.
In the first of the three embodiments to be hereinafter described, transducers 103 and 105 are digital encoding devices, each of which for each rotation Of its associated transducer produces 2,048 separate output signals, each comprising 11 signal bits. In this first embodiment first gear 102 has one less tooth than second gear 104. In particular in the arrangement described, gear 102 has 255 teeth and gear 104 has 236 teeth.
In the second two embodiments to be hereinafter described, transducers 103 and
105 are each a rotary signal generator. In each of these embodiments first transducer
103 produces 1,024 cycles of an electrical signal in each of two channels during each rotation. In addition, it produces index signals which will be described more fully hereinafter with respect to each embodiment separately. Second transducer 105 in each embodiment produces only index signals to be described hereinafter with respect to each embodiment separately. In these embodiments, first gear 102 has one
tooth less than second gear 104 also. In particular In the arrangements described.
first gear 102 has 256 teeth and second gear 104 has 257 teeth.
Shown in the block diagram of Figure 2 is the resolution portion – and range portion of apparatus constructed in accordance with the first to be described embodiment of the invention. Reference charac
ters have been shown with respect to various input and output lines on this Figure to show the correspondence between the blocks of this Figure and the circuit elements of Figures 3 and 4.
The resolution portion of this apparatus includes a first register AREG which is connected to receive the multiple bit output signal from a first encoder of the Baldwin cyclic encoder series 5V200 variety or the equivalent corresponding to transducer 103 but not shown in detail. The encoder selected for this embodiment produces 11-bit gray code output signals along lines EAOA1O and consequently the output of register ARIiG is connected to the
input of gray to binary code converter
ACON to derive binary coded output sig
nals. The binary coded output signals are
applied to gate circuits GAA and selection switch SSA to provide a hereinafter des
cribed function. the output signals of con
verter ACON are also applied to a storage
register 19TO.
The range portion of the embodiment shown in Figure 2 includes selection switch
SWB which receives the ll-bit gray code output signals of a second encoder also of
the Baldwin cyclic encoder series 5V200 variety or the equivalent corresponding to transducer 105 but not shown in detail.
These signals are applied along lines EBO EBlO. Switch SWB also receives input signals along lines SO-S10 from a unit described hereinafter. The output of switch
SWB is connected to a register BREG whose output in turn is connected to gray to binary code converter BCON.
The outputs of converter BCON, gates
GAA and selection switch SWA are fed into subtracter circuit SUBT which produees signals indicative of the number of rotations of shaft 101 (Figure 1) in this embodiment. These signals are applied to second storage device 2STû and to switch
SWB. Also shown in Figure 2 is timing signal generating device TSIG which produces output pulses along lines CLOA, MA, MB and CLOB.
Figure 3 shows that register AREG comprises 11 type D flip-flops of the Motorola
MC14013 variety or the equivalent. Each of these receives a clock pulse from signal generator TS1G along line CLOB. As is well known when a clock pulse appears along line CLOB each of these flip-flops can produce an output along its respective output line AGO AG1D in accordance with the input on its respective input line
EA0-EA10. Also two of these flip-flops which receive input signals along lines EA3 and ERA10 produce second outputs along lines AG3 and AGlO which are the inverse of the outputs along lines AG3 and At 10.
The inverted output signal AG3 together with the first output signals along lines
AG0-AG2 and AG4-AGlO are applied to
ten exclusive OR gates as shown which comprise the gray to binary code converter ACON. These exclusive OR gates are of the Motorola MC14507 variety or the equivalent.
The outputs from converter ACON along lines CA0-CA3 are the inverted four least
significant bits of each binary coded number corresponding to each gray code num
ber applied to register AREG along lines iAQ-EAlÛ. The seven most significant bits of the binary coded numbers corresponding to the gray code numbers applied to register AREG are produced along lines AGlo and CA9 through CA4. The signals on lines CA8 and CA9 are applied to the inputs of inverters T8 and I9 of the
Motorola MCl4049 variety or the equivalent which produce output signals along lines CA8 and CA9.
Selection switch SWA comprising a 4bit AND/OR selector circuit of the
Motorola P4C14519 variety of the equivalent, receives the inverted four least significant bits of each binary number generated along lines CA0-CAS together with the signals appearing along lines AGlO, CA9,
CA8 and Eel +. The signal applied along line El + Is a constant positive d.c. potential equivalent to the potential representing a binary one in the disclosed apparatus and is derived from any suitable source (not shown).Switch 5WA generates output signals along output lines A0-A3 corresponding to the inputs along lines CAO-CA3 or along lines Eel +, AGlO, CA9 and CA8 depending upon whether a pulse is applied to the switch along lines MA or MB, respectively. Gates GAA comprising seven
NAND units of the Motorola MC14011 variety or its equivalent receive inputs along lines CA4-CA9 and AG10 and produce signals along output lines A4-A1D when a pulse appears along line MA. The signals along lines CAQ-CA3, CA4-CA9 and
AGlO are also applied to a first storage unit 1STO comprising 11 type D flip-flops, of the Motorola MC14013 variety or the equivalent.Upon the reception of a clock pulse along line CLOR each of these flipflops produces an output signal along lines RO-R10 in accordance with the input signal applied to it.
Timing signal generator TSIG of Figure 3 includes two NAND gates N1 and
N2 of the Motorola MC14011 variety or the equivalent, which together with resistors Ri and R2 and condenser C1 comprise a free-running multivibrator which generates pluses at a frequency of 222 Hz.
101) These pulses are employed by a type D flip-flop D1 (MCl4Oi3 or equivalent) and
NAND gates N3 and N4 (MC14011 or equivalent) to produce pulses along lines
MA, MB, CLOA and CLOB. As shown in the timing diagram adjacent generator
TSIG, the pulses along line CLOA have a frequency corresponding to that of the
free-running multivibrator with a pulse
width equal to one-half a cycle. This fre
quency is selected to be rapid enough so
that at least four complete cycles of pulses
are produced along line CLOA during each
output of transducer 101 along lines EA0 ERA10 at the highest rotational speed of
the transducer.The pulses along lines MA
and MB are complements of each other
and have a frequency equal to one-half
that of the free-running multivibrator also
with pulse widths equal to one-half a cycle.
The pulses along line CLOB also have a
frequency equal to one half that of the
free-running multivibrator but have a pulse
width equal to three-quarters of a cycle.
Shown in Figure 4 is the range portion
of the first described embodiment. Selec;- tion switch SWB comprising three 4bit
AND/OR selector circuits of the Motorola
MC14519 variety or the equivalent receives
input signals in gray code from the second
ll-bit encoder along lines EB0-El0. It also receives inputs along lines SO-S 10 and
produces outputs along lines BGO-BGl0 corresponding to one or the other set of
inputs depending upon whether a pulse is
applied to its selector circuits along line
MB or MA.
The outputs of switch SWB along lines BG0-BG10 are applied to register BREG
comprising eleven type D flip-flops of the
Motorola MC14013 variety or the equivalent. These flip-flops provide outputs along lines SB0-SB10 in accordance with the inputs they receive along lines BG0-BG10 when
ever a clock pulse appears on line CLOA.
The output signals from register BREG
along lines SB0-SB10 are applied to one set of inputs of gray to binary converter
BCON. This unit comprises three 4-bit
AND/OR selector circuits of the Motorola MC14519 variety or the equivalent, and serves two functions.When signals appear along lines Eel + and MA it converts the signals along lines SB0-SB10 applied to its one set of inputs from gray code to the equivalent binary code and applies the binary code signals along its output lines BO-BlO. During that half of each cycle of the signal applied along line MA when no pulse is present, converter BCON operates in response to the voltage applied constantly along line El + as a selection switch and transfers the inputs applied to it along lines SB0-SB10 to its output lines BO-B10.
The output signals from converter BCON along lines BO-B10 are applied to one set of inputs of subtracter SUBT which comprises three 4-bit Full Adder circuits of the Motorola MC14008 variety or the equivalent. As previously mentioned, the other set of inputs of subtracter SUBT receives the signals applied along lines
A0-A10 by switch SWA and gates GAA of the resolution portion of the apparatus.
When no pulse appears along line MB at the input of subtracter SUBT it operates to produce signals along its output lines SO-SlO signifying the sum of the input signals on its two sets of inputs. During the half of each cycle of the signal applied along line MB when a pulse is present subtracter SUBT operates to produce signals along its output lines signifying the sum of the input signals on its two sets of inputs plus a binary one as indicated by the pulse along line MB. The carry outputs K01 and
K02 of the first two adder stages are con
nected to the carry inputs KI2 and KI3 of the second and third adder stages as is shown in the well-known manner.
The eight most significant outputs of subtracter SUBT are applied along lines
S3-S10 to second register 2STO. All of the outputs from subtracter SUBT are applied as previously mentioned to selection switch
SWB. Second register 2STO comprises eight type D flip-flops of the Motorola
MC14013 variety or the equivalent, each of which operates in response to the reception of a pulse along line CLOB to transfer the signals on lines S3-S10 to lines Rl 1- R18.
Shown in the block diagram of Figure 5 is the second to be described embodiment of the invention. This embodiment comprises two signal generators PG1 and PG2 of the TRU-Rota type DC-1024-D-ll-M
SD-12V or equivalent which correspond to transducers 103 and 105 respectively. Signal generator PG1 produces similar pulsed output signals in two channels. The signal in one channel is applied along output line X and the signal in the other channel along output line Y. Depending upon the direction of rotation the signal along line Y either leads or lags the signal along line X by 90″ or a quarter of a period of the respective signals. In accordance with earlier explanation 1,024 cycles of each signal are provided along each of lines X and Y, respectively for each revolution of signal generator PG1. In addition, signal generator PG1 produces a first index pulse along line IM1 each time the first reference point of shaft 101 is in a first angular position.
The output signals of signal generator
PG1 produced along lines X and Y are applied to signal conditioner circuit
COND1 which operates to produce signals along lines UD, 4DN and 4U which cause bi-directional counter CN1 to produce out put signals along lines PP0-PP11 signifying the angular position of the first reference point of shaft 101.
Counter CNl also produces a signal along line CO whenever it is restored to an initial condition as a result of the reception of a predetermined number of signals from conditioner CONDi, enough to fill the counter. The signals along line CO are applied to counter CN2 and cause it to produce signals along lines PP12-PP19 signifying the number of times the first reference point of shaft 101 passes through the previously mentioned first angular position.
Signal generator PG2 produces a second
index pulse along line IM2 each time a second reference point of shaft 106 passes
through a second angular position. A pulse signal along line IM2 applied to counter
CN2 causes it to apply the signals it re
eives along lines PP4-PP11 from counter CN1 to lines PP12-PP19 so that if corres
ponding signals are not already existing on these latter lines they will then appear therealong.
Shown in Figure 6 are the circuit elements which comprise signal conditioner COND1 and counters CNl and CN2 of
Figure 5. Signal conditioner COND1 includes an oscillator OSC which produces pulses along line CLO and complementary
pulses along line CLO at a frequency of
122.9 KHZ with a pulse width of one-half the period. Also included in the signal conditioner are a plurality of type “D” flipflops Motorola MC14013 variety or equivalent, which receive the signals from signal generator PG1 along lines X and
Y. These units are employed for producing signals along lines X1 and X2 and Y1 and Y2 in response to signals generated along lines X and Y.The signals along lines X1, X2, Y1 and Y2 are applied to three exclusive OR gates NO1, NO2 and
NO3 (Motorola MC14507 variety or the equivalent) whose outputs are applied to a binary coded decimal or decimal decoder
BCD (Motorola MC14028 variety or the equivalent). Decoder BCD together with a pair of NOR and inverter gates, U1, U2, D1 and D2 (Motorola My 14001 and MC14049 variety, respectively or the equivalent) produces signals along lines 4U, 4DN and 4DN. Depending upon the direction of rotation four pulses are produced along line 4U or 4DN for each cycle of the signals produced along lines X and Y by signal generator PG1. The signals along line 4DN are the complements of the signals along line 4DN.The signals along line 4U and 4DN in conjunction with two NOR gates NAl and NA2 (Motorola MC14001 variety or the equivalent) produce signals along line UD.
Bi-directional counter CNl comprises three 4-bit binary up-down counters BC1,
BC2 and BC3 connected in series. Bidirectional counter CN2 comprises two such 4-bit binary up-down counters BC4 and BC5. Each of counters BC1-BC5 is a Motorola MC14516 variety or the equivalent. As shown each of the four data lines Pl-P4 of each counter BC1-BC3 are connected to ground potential and those signals are applied to the output lines of counter CNl whenever a signal is applied to that counter along line IM1. The eight most significant output lines PP4-PP 11 of counter CN1 are shown connected to the data lines P1-P4 of each of the counters
BC4-BC5 comprising bi-directional counter
CN2.The signals applied along those latter lines are applied to the output lines of counter CN2 whenever a signal is applied to that counter along line IM2. Each of the counters BCl-BC5 are also shown connected in series in the well-known manner.
Figure 7 illustrates a block diagram of another embodiment of the invention. This embodiment comprises signal generators
PG3 and PG4 which correspond to transducers 103 and 105, respectively. Signal generator PG3 produces output signals on two channels which are applied along output lines X3 and Y3. These signals are similar to the signals applied along output lines X and Y of pulse generator PG1 previously described with regard to Figure 5. In addition signal generator PG3 produces an index signal along line IM3 which transfers from a first level to a second level each time the first reference point of shaft 101 is in the first angular position and then transfers from the second level to the first level each time the first reference point of shaft 101 is rotated 1800 from the first angular position.This index signal is applied along line IM3 to signal conditioner COND2 along with the signals applied along lines X3 and Y3.
Signal generator PG4 produces an index signal along line IM4 which transfers from a first level to a second level each time the second reference point of shaft 106 is in the second angular position and transfers from the second level to the first level each time the second reference point of shaft 106 is rotated 1800 from the second angular position. This index signal is applied along line IM4 to signal conditioner
COND2.
The output signals of signal generator
PG3 produced along lines X3, Y3 and 1M3 and of signal generator PG4 produced along line IM4 are applied to the circuits of signal conditioner COND2 to produce signals which are applied along lines 3Qll,
IM3BSTB, U10 and 4XUD to bi-directional counter CN3. In addition signal conditioner COND2 also produces signals which are applied along lines BE, BE, and
IM4BSTB to gates XOR8 and NOG4 and to bi-directional counter CN4. The signal along line U10 is also applied to bi-directional counter CN4.
The output signals of counter CN3 representing the angular position of the first reference point of shaft 101 are applied along lines 3PO-3Pll. Counter CN3 also produces a carry signal which is applied along line C030 to counter CN4 whenever counter CN3 is restored to its initial condition in response to the reception of a predetermined number of pulses. This restoration is accomplished in the same manner as previously described with respect to counter CNl of Figures 5 and 6. The signal on line 3Pll is also applied to gate
NOG4 and cooperates with the signal applied along line BE to produce an output signal from gate NOG4 which is applied along line C040 to full adder ADD1. Full adder ADD1 operates to produce signals which are applied along lines 4P4-4P10 to bi-directional counter CN4.In addition full adder ADD1 produces a signal which is applied along line 4PllA to gate
XOR8. Gate XOR8 operates in response to the signals applied to it along lines 4PllA and BE to produce an output signal which is applied along line 4Pll to bidirectional counter CN4.
Bi-directional counter CN4 responds to the carry signals applied to it along line
C030 to produce output signals along lines 3P12-3P19 representing the number of carry signals received. In addition the signal applied to counter CN4 along line
IM4BSTB causes it to apply the signals it receives along lines 4P4-4P1 1 from full adder
ADD1 and gate XOR8 to lines 3P12-3P19 so that if corresponding signals are not already existing at these latters lines they will thereupon appear there along.
Shown in Figure 8A are the circuit ele
ments which comprise signal conditioner
COND2. Signal conditioner COND2 in
cludes a plurality of buffer amplifiers B1,
B2, B3, B4 of the Fairchild “Dual Dif
ferential Line Receivers”, type AM9615 or equivalent which receive the signals
from pulse generators PG3 and PG4 ap
plied along lines X3, Y3, IM3 and IM4
respectively. Amplifier B1 and B2 pro
duce a pulse along line X3B and Y3B.
respectively for each cycle of the signal
applied along line X3 and Y3 in the well
known manner. Amplifier B3 and B4 pro
duce a pulse along line IM3B and IM4B
for each signal applied along line IM3 and IM4 respectively. Also included in signal conditioner COND2 are a plurality of “COS/MOS 4-bit D Type Registers”
DIC1 and DIC2 of the RCA type
CD4076BE or equivalent. Units DIC1 and
DIC2 are employed for producing signals along lines X3B1, X3B2, Y3B1, Y3B2 and lines IM3B1, IM3B2, IM4B1, IM4B2 in response to signals applied along lines X3B,
Y3B and lines IM3B, IM4B respectively.
Also illustrated in Figures 8A and 8B are a plurality of exclusive OR gates XOR1
XOR8 of the Motorola “Quad Exclusive
OR Gate” type MC14507 or equivalent; a plurality of NAND gates NND2-NND3 of the Motorola “Quad Two Input Nand
Gate” type MC14011 or equivalent; a plurality of NOR gates NOG1-NOG4 of the Motorola “Quad Two Input NOR
Gate” type My 14001 or equivalent and inverting amplifiers IA3-IA5 of the Motorola “Hex Inverter” type MC14049 or equivalent.
The signals on lines IM3B1 and IM3B2 from register DIC2 are applied to exlusive OR gate XOR1 (Figure 8A) which has its output signal applied to counter BUDl-BUD3 (Figure 8B).
Ocillator OSC2, is a free running type which produces pulses at a frequency of
131k Hz. which are applied to lines CLO1 and CLOY. The pulses on line CLOl are the complement of those on line CLO1.
Line CLO1 is connected to counter BUD 1- BUDS (Figure 8B). Line CLO1 is connected to register DIC1. At least four pulses are produced along line CLO1 during each quarter cycle of the signals along lines X3 and Y3 at the highest speed of signal generator PG3 in order that later to be described equipment can produce four pulses as a result of each such cycle.
Also shown in Figure 8A is exclusive
OR gate XOR3 which receives signals
applied to it along lines X3B1 and Y3B2 from register DIC1 to produce signals which are applied to input B of binary coded decimal to decimal decoder BCD3
of the Motorola type MC14028 or equivalent. In addition unit BCD3 receives sig
nals applied to inputs A and C along lines
Y3B1 and X3B2 respectively from unit
DIC1. As shown signals from the number
1 and 4 output lines of unit BCD3 are
applied to the input of NOR gate NOG1
and signals from the number 2 and 7 out
put lines of unit BCD3 are applied to the
input of NOR gate NOG2. The signals
produced by NOR gate NOG1 and NOG2
are applied along lines 4XU and 4XD to inverting amplifiers IA3 and IA4 res
pectively to produce signals along lines
4XU and 4XD which are quadruple multi pies of the signals applied along the lines
X3B and Y3B.The signal on line 4XU is also applied to one of the inputs of NAND gate NND2 which has its other input connected to line D10 to produce a binary signal which is applied along line U10 to counters CN3 and CN4. Similarly NAND gate NND3 has signals applied to it along lines 4XD and U10 to produce signals on lines D10.
NOR gate NOG3 combines the signals applied to it along lines 4XU and 4XD and applies signals along line 4XUD to the input of the first of the three binary
UP/DOWN counters BUD1, BUD2 and
BUD3 (Figure 8B) each of the Motorola type MC14516 or equivalent which comprise counter CN3. As shown in Figure 8A exclusive OR gate XOR5 receives signals applied to it along lines IM3B2 and
D10 and generates a signal on its output line which is applied to one input of exclusive OR gate XOR6, the other input of which is connected to ground. Exclusive OR gate XOR6 has its output line 3Qll connected to counter CN3 (Figures 7 and 8B). The remaining input lines 3Q03Q10 of counter CN3 (Figure 8B) are each connected to ground.
Bi-directional counter CN3 is connected in series by means of line C030 to counter
CN4 comprising a pair of series connected
UP/DOWN counters BUD4 and BUDS.
Each of the UP/DOWN counters BUD4 and BUDS is also a Motorola type MC14516 or equivalent. In addition to producing signals on lines 3P0-3P1 1 signifying the angular position of the first reference point of shaft 101, counter CN3 applies the eight most significant bits along lines 3P4-3Pll to binary full adder ADD1.
Binary full adder ADD1 comprises two series connected “Four Bit Full Adders”
ADDA and ADDB of the Motorola type MC14008 or equivalent. As shown in Figure 8B data inputs A1-A8 of full adder
ADD1 are connected to ground. Full adder
ADD1 has a carry signal applied to it along line C040 from the output of NOR gate
NOG4. NOR gate NOG4 receives signals applied to it along lines 3Pll and BE. The signal applied along line BE is produced by inverter IA5 and is the complement of the signal generated by exclusive OR gate
XOR7 (Figure 8A) in response to the signals applied that gate along lines IM4B2 and D10.
In response to a pulse signal applied to it along line IM4BSTB counter CN4 operates to apply the signals it receives along lines 4P4-4Pll to lines 3P12-3P19 if corresponding signals are not already existing on these latter lines. The signal on line 4P1 1 produced by exclusive OR gate XOR8 in response to the signals applied to it along lines BE and 4PllA and the remaining signals on lines 4P0-4P10 obtained directly from full adder ADD1 represent in binary form the number of revolutions of the first reference point of shaft 101.
In order to understand the operation of all embodiments of the invention, a description of operation of each will be provided. Accordingly, assume that when the first and second reference points of shafts 101 and 106 of an arrangement built in accordance with the first embodiment shown in Figures 2, 3 and 4 are in first and second angular positions respectively, the binary encoders corresponding to transducers 103 and 105 each produces a gray code output equivalent to zero. From the foregoing it will be understood that the encoder of shaft 101 produces 2,048 separate 11-bit signals for each rotation of its associated gear 102 through 255 teeth or 360 degrees. The encoder on shaft 106 also produces 2,048 separate output signals for rotation of its gear 104 through 360 degrees.This gear contains 256 teeth however and for each revolution of gear 102 through 255 teeth gear 104 rotates 255 teeth also which is one tooth less than 360 degrees for gear 104. As a result the encoder of shaft 106 produces eight less output signals than the encoder on shaft 101 for every revolution of that latter shaft.
From the foregoing it is also to be understood that because of the discrete character of the output signals from the encoders on shafts 101 and 106, the signals from the encoder are produced out of synchronism with each other except each time the first reference point of shaft 101 is in the first angular position. This asynchronism between the production of the signals of the encoders is compensated for in order that correct indications of the angular position of the reference point of shaft 101 are produced at every position of that shaft in each of its revolutions.
The following description of operation will be explained as taking place at one particular position of shaft 101 in order that it might be understood how the embodiment provides accurate indications of angular position of the first reference point of shaft 101.
Since gear 104 travels one tooth less than gear 102 for every rotation of gear 102, it should also be understood that on each successive rotation of shaft 101 the angular position of the second reference point on shaft 106 increasingly lags the angular position of the first reference point on shaft 101 if the shafts are started in rotation with the first and second reference points in the first and second angular positions, respectively. This lag angle increases the same amount for each rotation and thus it is indicative of the number of rotations of shaft 101.
In order to understand how the embodiment of Figures 3 and 4 operates to indicate the angular position of the first reference point of shaft 101, assume shafts 101 and 106 are started in rotation with the first and second reference points in the first and second angular positions respectively. Also assume that shaft 101 is on a particular rotation and that the first reference point has travelled more than seveneighths of the way through that rotation from the first angular position.
Under these circumstances signals are applied to lines EA0-EA10 to register
AREG which signify in gray code the angular position of the first reference point of shaft 101 in that particular rotation.
Simultaneously signals are applied to lines
EBO-EB10 to selection switch SWB which signify in gray code the position of the second reference point of shaft 106. Also assume that timing signal generator TSIG has just generated a new pulse along line
CLOA and that the corresponding pulse along line MA has not yet been generated.
As a result a pulse magnitude still appears along line MB and switch SWB applies the signals along lines EBO-EB10 to lines BG0 BG10. Accordingly when the pulse along line CLOA was generated and the type
D flip-flops of register BREG caused the signals along lines BG0-BG10 to be produced along line SB0-SB10, signals indicative of the angular position of the second reference point of shaft 106 are applied to one set of inputs of gray to binary code converter BCON. Consequently when sufficient time elapses that timing signal generator TSIG generates a pulse along line MA converter BCON generates signals along lines BO1B10 which in binary code signify the angular position of the second reference point of shaft 106.
Upon the generation of the pulse along line MA timing signal generator
TSIG also generates a pulse along line
CLOB. In response to a pulse applied along line CLOB the type D flip-flops of register
AREG cause the 11 gray code signal bits applied to them along lines EA0-EAl0 to be produced on lines AG0-AG10. In addition the complements of the signals applied along line EA3 and EA10 are produced along line AG3 and AG10.The three least significant bits of the signal which in gray code signifies the angular position of the first reference point of shaft 101 are applied along lines AGO
AG2 to gray to binary converter ACON.
These signal bits together with the complement of the fourth least significant bit applied along line AG3 to converter ACON provide along lines CA0-CA3 the complements of the four least significant bits in binary code corresponding to the four least significant bits in gray code. The seven most significant gray code bits generated by the encoder on shaft 101 are applied along lines
AG4-AG10 to converter ACON to produce along lines CA4-CA9 the fifth through tenth most significant bits in binary code corresponding to the similar bits of the gray code position signal. The eleventh or most significant bit need not be converted from gray to binary code since it always is the same in both.This most significant bit along line AG10 together with the next six most significant bits along lines CA4-CA9 are applied to gates G AA which in the presence of a pulse along line MA produce along lines A4-A10 the complements of the seven most significant bits of the signals in binary code indicative of the position of the first reference point of shaft 101.
Simultaneously the signals along lines
CA0-CA3 are applied to selection switch
SWA which in the absence of a pulse along line MB and the presence of a pulse along line MA transfers these four signals signifying the complements of the four least significant bits of the binary code signal indicative of the position of the first reference point of the shaft 101 to the output lines A0-A3. The complements of the eleven binary code signal bits indicative of the first reference point of shaft 101 are applied along lines A0-A10 to the second set of inputs of subtracter SUBT. As previously explained subtracter SUBT is at that time also receiving binary coded signals along lines B0-B10 on its other set of inputs. These latter signals are indicative of the angular position of the second reference point of shaft 106. In the absence of a pulse along line MB subtracter
SUBT operates as a humming circuit to add the signals along lines B0-B10 to the signals along lines A0-A10. As explained, the signals along lines A0-A10 are the complements of the binary signals representing the angular position of the first reference point of shaft 101. Accordingly, subtracter SUBT produces on lines SO-SlO a binary signal indicative of the difference between the signals representing the angular position of the second reference point of shaft 106 and the signals representing the angular position of the first ref erence point of shaft 101, or the angle by which the angular position of the second
reference point of shaft 106 lags that of the
first reference point of shaft 101.
With shaft 101 within the last eighth
portion of any rotation, as is the assumed condition, the asynchronisms between the
production of signals by the two encoders causes the difference signals along lines
SO-S10 to indicate an erroneous number of rotations of shaft 101. This occurs because in this position when the encoder on shaft 101 produces a signal before the production of the corresponding signal by the encoder on shaft 106 the former encoder has produced eight more signals on this rotation of shaft
101 than the latter encoder has. From earlier explanation it should be understood that
eight signals are equivalent to one tooth of gear 104. Consequently these eight signals signify that the second reference point on shaft 106 lags the first reference point on shaft 101 by an angle equivalent to another full rotation.Since this occurs before the completion of the rotation it has to be prevented from causing the difference between the two signals applied to subtracter SUBT from causing inaccurate indications of the number of rotations of the first reference point of shaft 101 past the first angular position. Switch
SWB, register BREG, converter BCON, subtracter SUBT and switch SWA operate as a compensating circuit during the presence of pulses along line MB in order that accurate indications are produced during such times.
To accomplish this compensation function, the output signals from subtracter
SUBT along lines S0-S10 are applied to the second set of inputs of switch SWB.
Consequently, before the reception of a pulse along line MB and while a pulse continues to be applied along line MA, the output lines BG0-BG10 of switch SWB have applied along them the lag angle signals from subtracter SUBT. When a pulse is generated along line CLOA at the end of the pulse along line MA the eleven type
D flip-flops of register BREG cause complements of the lag angle signals to be applied along lines SB0-SB10. These signals are applied to converter BCON which in the absence of a pulse along line MA operates as a selection switch and transfers these complement signals to lines BO
B10.
Since the pulse along line MA has ceased and that along line MB has begun, gates GAA are inhibited and thus each of lines A4-A10 has a binary one applied along it. In addition, in response to the pulse along line MB switch SWA selects the input signals on lines E1 +, AG10,
CA9 and CA8 and transfers those signals to its output lines A0-A3. The signals along lines CA8, CA9 and AG10 represent the complements of the three most significant bits of the binary number indicative of the position of the first reference point of shaft 101.During each revolution of shaft 101 when its first reference point is traveling through the last eighth of a rotation toward the first angular position the signals signifying these three most significant bits comprise a compensating signal which is of sufficient magnitude that when subtracted from the lag angle signal generated during the MA pulse the asyncronisms between the generation of signals from the two encoders are prevented from producing a lag angle signal which produces inaccurate indications of position.This subtraction is accomplished by applying the binary signals along line A10-A4 and that along line A3 resulting from the binary one signal on line El + together with the signals along lines A0-A2 indicative of the complements of the three most significant bits of the binary code signal representing the position of the first reference point to the associated set of inputs of subtracter
SUBT. With these signals applied to one set of inputs and the complement of the lag angle signal applied to the other set of inputs along lines B0-B10 subtracter SUBT during the presence of a pulse along line
MB, produces along lines SO-S 10 the difference between the lag angle signal and the compensating signal. The eight most significant bits along lines S3-S10 are applied to the eight type D flip-flops of register 2STO.Upon the next generation of the pulse along lines CLOB, these produce output signals along lines Ri 1-R18 which are accurate indications of the integral number of teeth of gear 104 by which the angular position of the second reference point of shaft 106 lags the angular position of the first reference point of shaft 101. As stated previously, this indicates the number of rotations the first reference point of shaft 101 has rotated past the first angular position since the assumed initial condition in which the first reference point and the second reference point were simultaneously in the first and second angular position respectively.When the binary number represented by the eight bits on lines Rll-R18 are combined with the eleven bits on line
R0-R10 a digital number is produced signifying the angular position of the first reference point of shaft 101 and the number of rotations of shaft 101.
It is to be understood that although the pulse along line MB ceases and that along line MA starts substantially simultaneously with the generation of the pulse along line
CLOB, the operation time of subtracter
SUBT is sufficiently slower in switching its output from the compensated lag angle signal to the uncompensated signal in response to the cessation of the pulse along line MB that the compensated signal is produced along lines R11-R18 as outputs by the eight type D flip”flops or register 2STO.
In order to understand how the embodiment of Figures 5 and 6 operates to indicate the angular position of the first reference point of shaft 101 assume that the first and second reference points of shafts 101 and 106 are in their first and second angular positions and that pulse generator PGl and pulse generator PG2 are simultaneously producing their index pulses along lines IM1 and IM2. Also assume that shafts 101 and 106 are turning in a direction in which binary counters CNl and CN2 will increase their count as the angular rotation of shaft 101 increases.
From what has been explained previously, it will be understood that pulse generator PGl produces 1,024 electrical pulses along each of lines X and Y for each revolution of shaft 101. Also, with the rotation of shaft 101 such as to increase the count in counters CNl and CN2 the pulses along line Y lead those along line X as previously mentioned.
It is to be understood that the pulses produced by oscillator OSC along lines
CLO and CLO are such in relationship to the fastest speed at which pulse generator
PG1 rotates that at least four pulses appear on each of lines CLO and CLO between each pulse generated along line X and each pulse generated along line Y.
As a result for each pulse along lines X and Y type D flip-flops 1X, 2X and 1Y, and 2Y produce output signals along each of lines X1, X2, Y1 and Y2. These output signals are applied to the exclusive OR gates NO1, NO2 and N03 whose outputs are applied in turn to three inputs of decoder BCD. With the production of pulses in the Y channel 90 degrees in advance of pulses in the X channel signals are applied along lines Y1, Y2, X1 and X2 in that order. The production of a pulse along line Y1 causes exclusive OR gate NOl to apply a signal to the A input of decoder BCD. As a result a corresponding signal appears at output 1 of the decoder.
This is transmitted to the associated NOR and inverter gates U1 and U2 and causes the production of a pulse along line 4U.
Similarly the production of a pulse along line Y2 causes exclusive OR gate N02 to apply a signal to input B of decoder
BCD without effect at this time since 9ut- put 3 of decoder BCD which produces an output signal when input signals are applied to the A and B inputs of the decoder is not connected in the circuit. The production of a pulse along line X1 causes exclusive OR gate NO3 to provide a signal to the C input of decoder BCD. With input signals on its A, B and C inputs, decoder
BCD produces an output signal on its 7 output. This is applied to the associated
NOR and inverter gates U1 and U2 and produces a second pulse along line 4U.
When the pulse applied along line X2 is applied to OR gates NO1, NO2 and NO3 each ceases to produce an output signal.
Thereafter, a clock pulse applied along line
CLO causes type D flip-flop 1Y to remove the pulse signal on line Y1. This causes exclusive OR gate NO1 to again apply a signal to input A of decoder BCD. As before, this causes the production of a pulse along line 4U. Similarly the removal of the pulse signals along lines Y2 and X1 will cause the production of a signal from output 7 of decoder BCD and another pulse will be produced along line 4U. In this way each cycle of the signals produced along line X and Y results in the production of four pulses along line 4U so that each rotation of signal generator PG1 in the assumed direction results in the production of 4,096 pulses along line 4U, which means that 16 such pulses are produced for each angle of rotation equivalent to one tooth of gear 102.
Each pulse along line 4U causes NOR gates NA1 and NA2 to produce corresponding pulses along line UD. These pulses along line UD, in the well-known manner, enable binary up-down counters BC1-BC5 to increase their count each time a pulse is applied to input CI1 to counter BC1 from exclusive NOR gate N04 as a result of a pulse along line 4U.
Outputs are applied along lines PP0 PP11 in accordance with the number of pulses applied to input CI1 of counter BC1 and the corresponding inputs CI2 and CI3 of counters BC2 and BC3 as a result of the preceding counters BC1 and BC2 being filled. Upon the production of 4,096 pulses along line 4U of the counters BC1 through
BC3 are filled with the result that an output is produced at the C03 output of counter
BC3. This is applied along line CO to input CI4 of counter BC4 which together with counter BC5 produces output signals along lines PP12-PP19 in accordance Wfth the number of inputs applied along line CO to input CI4.
On each return of the first reference point of shaft 101 to the first angular pos:- tion, 4,096 pulses should have been pro duced on line 4U such that counters BCI
BC3 have been restored to their initial condition in which they produce a zero count on lines PP0-PPll. To insure that counters BCl-BC3 are restored to their initial condition upon the return of the first reference point of shaft 101 to the first angular position notwithstanding that one or more pulses have not been counted, an index pulse is produced along line IM1 when the first reference point of shaft 101 is in the first angular position.This index pulse is applied along line IM1 to the PE inputs of each of counters BC1-BC3 and causes the ground potential on lines P1- P4 of each counter to be transferred to the output lines PPO-PP11 restoring the counters to their initial condition if they aren’t already in that condition.
As will be understood, on each rotation of shaft 101 the angular position of its reference point increasingly leads the angular position of the second reference point on shaft 106 because of the one more tooth on gear 104 than on gear 102. Specifically.
each time the second reference point of shaft 106 returns to the second angular position, and signal generator PG2 produces an index pulse along line IM2, the first reference point of shaft 101 is beyond the first angular position by preciselv one more tooth of gear 102. This effect is cumulative and with the arrangement of binary counter BC1-BC3 each providing four output signal bits, together with the fact that 16 pulses are applied along line 4U for each angle of rotation of shaft 101 equivalent to one tooth of gear 102 each time the index pulse of signal generator
PG2 is applied along line IM2 counters
BC2 and BC3 contain a number equivalent to the number of teeth gear 102 has rotated through since the first reference point of shaft 101 was last in the first angular position.This number is equivalent to the number of rotations of shaft 101. It is caused to be transferred to output lines PP12 through PP19 of counters BC4 and
BC5 as a result of the application of the second index pulse along line IM2 to the
PE inputs of counters BC4 and BC5. Since.
as is known, the application of such a pulse operates to transfer the signals on lines PP4 through PP11 to lines PP12 to
PPl9 so that if corresponding signals do not already exist on the latter lines they will thereupon appear therealong.
From the foregoing it can be seen that should counters BC4 and BC5 fail to count the carry signals from counter ENC3 applied along line CO properly the count in counters BC4 and 13C5 will be corrected as soon as signal generator PG2 produces its index pulse in response to the second reference point of shaft 106 returning to its second angular position.Similarly should the source of electrical power be lost on any revolution of shaft 101 a correct indication of the total number of rotations of that shaft from the point at which both the first and second index pulses were generated in synchronism together with a correct indication of the angular position of the first reference point of that shaft will be produced upon the first generation of a second index pulse along line IM2 following the first generation of a first index pulse along line IM1 after the restoration of the source of electrical power.
Operation of this embodiment in response to rotation of shafts 101 and 106 such that the counters reduce the numbers stored therein occurs in response to the generation of pulses along line 4DN which are produced in a manner similar to those applied along line 4U in response to the signal on line X leading that on line
Y. During this operation counters BC1
BC5 reduce their count in response to the absence of pulses along line UD. These operations will be apparent to those skilled in the art in view of the foregoing description and will not be explained in detail herein for purposes of brevity.
In order to understand how the embodiment of Figures 7, 8A and 8B operates to signify the angular position of the first reference point of shaft 101 assume that the first and second reference points of shafts 101 and 106 are in their first and second angular positions respectively. Als assume that as a result of the assumed positions of the reference points of shafts 101 and 106 signal generators PG3 and PG4 produce signals which have simultaneously transferred from a first logic level represented by a binary one to a second logic level represented by a binary zero.In addition it is assumed that the signal applied along line IM3 remains at that binary zero level until the first reference point of of shaft 101 has rotated 1800 from its first angular position in a clockwise direction and the signal applied along line IM4 remains at that binary zero level until the second reference point of shaft 106 has rotated 1800 from its second angular position in a counterclockwise direction at which position of shafts 101 and 106 the signals applied along lines IM3 and IM4 are transferred to a logic level represented by a binary one.It is understood that since gear 102 has one less tooth than gear 104 the second reference point of shaft 105 increasingly lags the first reference point of shaft 101 and that this effect is cumulative with each revolution of shaft 101.
Assume that as shaft 101 rotates through each revolution of 360 , signal generator
PG3 applies 1,024 cycles of an electrical signal along each of lines X3 and Y3 and in addition that as shaft 101 rotates in a clockwise direction the signals applied along line
Y3 lead the signals applied along line X3 by 90 . It is understood that as shaft 101 is rotated through each revolution of 360″ in a counter-clockwise direction, signal generator PG3 also applies 1,024 cycles of the signals along each of lines X3 and
Y3 but that the signals applied along line
Y3 lag the signals applied along lines X3 by 90″. From this phase relationship of the signals applied along lines X3 and Y3 the signal conditioner COND2 determines the direction of rotation of the shaft 101
as it is rotated and in response to the assumed clockwise rotation of shaft 101 produces binary one signal pulses on the output of NAND gate NND2 in a manner to be described. These signals are applied
along line U10 to cause bi-directional coun
ters CN3 and CN4 to increase their count
in response to the pulses applied to counter
CN3 along line 4XUD as the angular posi
tion of shaft 101 is rotated in the clock
wise direction.If the assumed rotation of
shaft 101 had been reversed NAND gate
NND2 would have applied a zero binary
level signal to counters CN3 and CN4 as
a result of the signals applied along line
Y3 lagging the signals applied along line
X3 and the count stored in those counters
would be decreased in response to the
pulses applied to counter CN3 along line
4XUD.
As a result of the initial assumed posi
tion, binary zero level signals are applied
along lines IM3 and IM4 to the input of
inverting differential amplifiers B3 and B4
(Figure 8A) respectively which apply bin
ary one signals along lines IM3B and IM4B
to register DIC2. Before rotation of shaft
101 from its initial assumed position no
signals were present on lines 4XU and
4XD and consequently the output of exclu
sive OR gate XOR4 was a binary zero and
and the signals on lines IM3B and IM4B
were not clocked into register DIC2. As a
result binary zeros were applied along lines IM3B 1, IM3B2, IM4B1 and IM4B2 to ex
clusive OR gates XOR1 and XOR2 each
of which produces a binary zero signal.
Before shaft 101 begins to rotate in a
clockwise direction, signal generator PG3
is applying the negative half of the first
cycle of the signal along line Y3 to the
input of inverting differential amplifier B2.
This causes the amplifier to apply a binary
one signal along data line Y3B to register DIC1. Register DIC1 responds to this sig
nal on line Y3B and a clock pulse along
line CLO1 to generate a signal along line
Y3B1 which is applied to binary to decimal
converter BCD3. This signal causes a binary one output signal to be produced from the 1 output of the converter which is applied to the associated input of NOR gate NOG1. This gate in turn produces a binary zero along line 4XU which is applied to inverter IA3 and causes it to produce a binary one signal on line 4XU. Each binary one signal along line 4XU is applied to NAND gate NND2 causing it to apply a binary one signal along line U10. Each binary one signal along line 4XU is also applied to exclusive OR gate XOR4.The first of these, applied to register DIC2 to cause it to produce a binary one signal on line IM3B1 and IM4B1 in response to the binary one signal on lines IM3B and
IM4B. These binary one signals on line
IM3B1 and IM4B1 are applied to exclusive
OR gates XOR1 and XOR2 which pro
duce binary one signals on lines IM3BSTB
and IM4BSTB, respectively.
The binary one signal along line 4XU was also applied to NOR gate NOG3 to
cause the production of a binary one sig
nal along line 4XUD which is applied to input COIN1 of counter BUD1. This signal
is without effect at this time however be
cause the binary one signal applied along
line IM3BSTB to the PE inputs of
counters BUD1-BUD3 cause the ground
or binary zero signal applied to each of lines 3Q0-3Q10 to be applied to lines 3P0 3P10. At the same time a binary zero sig
nal is also applied along line 3Qll as a
result of binary zero signals applied along
line IM3B2 and D10 to exclusive OR gates
XOR5. This signal along line 3Qll is trans
ferred to line 3Pll by counter BUD3 in
response to the binary one signal applied
along line IM3BSTB.
Lines 4P44Pl lA receive the signals
applied along lines 3P4-3Pll from adders
ADDA and ADDB as a result of the input
signal along line C040 being in the binary
zero state. This state exists as a result of
the binary zero signal on line 3P1 1 to
NOR gate NOG4 and the binary one sig
nal applied thereto along line BE. This
latter signal is in the binary one state as
a result of the application of binary zero
signals along lines IM4B2 and D10 to ex
clusive OR gate XOR7. As a consequence.
the signal along line BE is in the binary zero state. This signal and the binary zero
signal along line 4PllA are both applied to exclusive OR gate XOR8 (Figure 8B)
and cause the production of a binary zero
signal along line 4Pll. The existence of
a binary one signal along line IMB4STB, as previously mentioned, under these conditions causes counters BUD4 and BUDS to produce binary zero signals on lines 3P12-3Pl9. With binary zero signals on all lines 3P0-3Pl9 counters BUD1-BUDS are all in their initial condition. Additional pulses along line CLO1 are without significant effect while shaft 101 remains stationary. The first additional one of these pulses applied along line CLO1 causes register DIC1 to produce a binary one output on line Y3B2 in response to the binary one signal on line Y3B1.This is applied through exclusive OR gate XOR3 to the B input of converter BCD3 which causes the binary one signal at the 1 input to return to binary zero. This causes
NOR gate NOG1 to produce a binary one signal along line 4XU and a binary zero signal through inverter IA3 on line 4XU.
This binary zero signal cause exclusive OR gate XOR4 to produce a binary zero signal without effect.
Assume now that shaft 101 starts to rotate in the clockwise direction. As mentioned, under this condition the signals on line Y3 lead those on line X3 by 90″. In order to understand how the signals from generators PG3 and PG4 cause counters
BUD1-BUDS to produce outputs indicative of the rotation of shaft 101, a brief description of the manner of generation of pulses along line 4XUD follows.
The next significant clock pulse applied along line CLO1 to register DICI occurs when a binary one signal is applied to that register along line X3B. This clock pulse causes register DIC1 to apply a binary one signal along line X3B1 to the second input of exclusive OR gate XOR3. As a result exclusive OR gate XOR3 applies a binary zero signal to the B input of converter
BCD3. It is understood that the binary one signal is still applied along line Y3B1 to the A input of converter BCD3. As a result converter BCD3 produces a binary one signal on its output line 1 which is applied to NOR gate Nt)Gl causing a binary one signal on line 4XU and a binary zero signal on line 4XU.This binary one signal along line 4XU is applied to exclusive OR gate XOR4 to cause register
DIC2 to apply the binary one signals on lines IM3B1 and IM4B1 to lines IM3B2 and IM4B2. These latter two signals cause the binary one signals on lines IM3BSTB and IM4BSTB to be transferred to binary zero signals in order to permit counters
CN3 and CN4 to count pulses applied on line 4XUD.
The next clock pulse applied to register DICI causes it to apply a binary one signal along line X3B2 to input C of converter
BCD3. In response to the binary one signal on its input C converter BCD3 produces binary zero signals on each of its output lines 1, 2, 4 and 7. As a result the binary zero signal applied along line 4XU is transferred to a binary one and the binary one signal applied along line 4XU is transferred to a binary zero.
Because the signals applied along line
Y3 lead the signals applied along line X3 as a result of the assumed direction of rotation it is understood that at the end of the first half cycle of the signal applied along line Y3 to amplifier B2, that amply fier applies a binary zero signal along line
Y3B to register DICI. The first clock pulse applied to register DIC1 after the binary zero signal is applied along line Y3B to that register causes it to apply the binary zero signal on line Y3B along line Y3B1 to converter BCD3 on input 1. At this time, it is understood, binary one signals are applied to each input of exclusive OR gate XOR3 along lines Y3B2 and X3B1 and in addition a binary one signal is applied along line X3B2 to input C of converter BCD3.In response to the signals applied to it converter BCD3 applies a binary one signal from its output line 4 to NOR gate NOG1 which causes a binary one signal to appear on line 4XU. The next clock pulse causes register DIC1 to apply the binary zero signal on line Y3B1 to line
Y3B2. As a result exclusive OR gate XOR3 applies a binary one signal to the B input of converter BCD3 which in response applies a binary zero signal to each of its output lines 1, 2, 4 and 7.
It is further understood that as a result of continued clockwise rotation a binary zero signal is applied along line X3B to register DIC1 from amplifier B1. The next clock pulse applied to register DIC1 causes it to apply the binary zero signal on line X3B along line X3Bl to one input of exclusive OR gate XOR3. At this time it is understood the binary zero signals are applied along line Y3B2 to the second input of gate XOR3 and along line Y3B1 to converter BCD3. At the same time a binary one signal is still applied along line
X3B2 to the C input of converter BCD3 which as a result applies a binary one signal from its output 4 to one input of NOR gate NOG1. As a result a binary one signal is applied along line 4XU.When the next clock pulse is applied to register DIC1 it causes the register to apply the binary zero signal on line X3B1 along line X3B2 to the C input of converter BCD3. As a result of the binary zero signals applied to each of its inputs A, B, C and D, converter BCD3 applies a binary zero signal along each of its output lines to NOR gates
NOG1 and NOG2.
From the foregoing, it is to be understood that in response to each binary one signal applied to NOR gate NOG1 a corresponding binary one signal is applied along line 4XU. Consequently when the signals on line Y3 lead the signals on line
X3 four pulses are applied along line 4XU for each cycle of the signal along line Y3 to amplifier B2. Similarly when the signals applied along line X3 lead the signals applied along Y3 four pulses are applied along line 4XD for each cycle of the signal applied along line X3 to amplifier B1.
As shown in Figure 8A, the signals on lines 4XU and 4XD are applied to the input of NOR gate NOG3. As a result of what has been explained it is understood the NOR gate NOG3 applies 4,096 pulses per revolution of shaft 101 along line 4XUD to the input of counter CN3 regardless of the direction of rotation of shaft 101.
It is to be understood that the output of counter CN3 signifies the position of the first reference point of shaft 101 and counter CN4 signifies the number of revolutions of that shaft. As shaft 101 is rotated in the assumed direction counter
CN3 responds to the signals applied it on line 4XUD while counter CN4 responds to the carry signals applied to it on line
C030 in the ordinary manner of pulse accumulators such as explained with respect to counters CN1 and CN2 of the embodiment of Figures 5 and 6. However as will be shown should either counter signify incorrectly the position of the first reference point of shaft 101 corrections are applied to each of the counters during each revolution of shaft 101.
To illustrate the occurrence of the application of the correction signals assume that the first reference point of shaft 101 is rotated through an angle of 1800 from the assumed initial position in which it was in the first angular position.
It is understood therefore, that 2,048 pulses have been applied along line 4XUD to the input of counter CN3. As a result of counting each of those 2,048 pulses counter CN3 produces signals on lines 3P0-3Pll representing in binary form the equivalent of the decimal number 2,048.
If for some reason the signals on lines 3P0-3Pll representing the number of pulses received by counter CN3 are in error, these signals will be corrected when the reference position of shaft 101 is 1800 from its first angular position in the following manner.
Whenever shaft 101 is rotated 1800 in a clockwise direction from its first angular position the pulse corresponding thereto is applied along line 4XUD to the input of counter CN3 almost simultaneously with the signal on line IM3 from pulse generator
PG3, as previously explained, being transferred from the binary zero to the binary one level. As a result differential amplifier
B3 (Figure 8A) applies a zero level signal to the data line IM3B of register DIC2.
The binary one signal along line 4XU at this time applied to exclusive OR gate
XOR4 causes register DIC2 to transfer the zero level signal on line IM3B to its output line Ism381. As will be understood from prior description, a binary one signal will be present on line IM3B2 at this time as a result of the continued presence of a binary one signal on line IM3B during the 1800 rotation of shaft 101. The binary one level signal on line IM3B2 and the binary zero level signal on IM3B1 cause exclusive OR gate XOR1 to generate a signal which is applied along line IM3BSTB to counter CN3 to cause the ground or binary zero signal on lines 3Q0-3Q10 to be applied to lines 3P0-3P10.At this time the binary one signal on line IM3B2 is also applied to exclusive OR gate XOR5 which together with gate XOR6 generates a binary one signal along line 3Qll to counter CN3. This binary one signal along line 3Q1 1 together with the binary zero signals along lines 3Q0-3Q10 are caused to be transferred to the output lines of counter CN3 by the signal applied to CN3 along line IM3BSTB so that if corresponding signals are not already existing on those output lines they will thereupon appear therealong. As a result the counter correctly represents in binary form the number of pulses applied to its input along line 4XUD during the 1800 rotation.Counter
CN3 is enabled to continue counting by the next pulse along line 4XU which transfers the binary one on line IM3B2 to a binary zero signal which causes a binary zero to appear along line IM3BSTB. This latter signal restores counter CN3 to a condition in which it can count pulses received along line 4XUD.
Similarly each time the first reference point of shaft 101 returns to the first angular position counter CN3 is also corrected to indicate the initial zero count. Under these circumstances, the signal on line
IM3 changes from a binary one to a binary zero. This is clocked into register DIC2 in response to the simultaneous entrance of a pulse along line 4XU and causes the production of a binary one on line IM3B1 and IM3BSTB. The signal on this latter line enables the transfer of the ground or binary zero signal on lines 3Q0-3Q10 to appear on lines 3P0-3P10. A binary zero also appears on line 3Qll in response to both line IM3B2 and line D10 having binary zero signals along these at this time.
Consequently all lines 3P0-3Pl l carry binary zero signals indicating the initial zero count.
Counter CN4 is arranged to have its
count corrected if necessary each time the
second reference point of shaft 106 is in
the second angular position and 1800 away from that position. The first of these
corrective measures is similar to that pro
vided on the embodiment of Figures 5 and
6. However in order to provide the cor
rection for the 1800 position additional
equipment is included whose operation will
be explained with regard to both corrective
steps.
Whenever the second reference point of
shaft 106 is in the second angular position the signal along line IM4 is transferred
from a binary one to a binary zero. This
causes the production of a binary one along
line IM4Bl as a result of the simultaneous
pulse along line 4XU. This binary one sig
nal on line IM4B1 causes the production
of a similar binary one signal along line
IM4BSTB. As previously mentioned this
causes the signals on lines 4P4-4P1 1 to
appear on lines 3P12-3P19 of counter CN4,
so that the former signals will appear
thereon if similar such signals do not already.From the description of the
arrangement of Figures 5 and 6 it will be
evident that when the second reference
point of shaft 106 is in the second angular
position the count in counter CN3 repre
sented by output lines 3P4-3Pll is indicative of the number of times the first refer
ence point of shaft 101 has passed the
first angular position. This number is the
correct number for the output of counter
CN4 during each particular revolution of
shaft 101 and is transmitted to counter
CN4 in response to the binary one signal
along line IM4BSTB if it is not already
producing that number. This occurs be
cause adder ADD1 receives a binary zero
signal from NOR gate NOG4 and exclusive
OR gate XOR8 receives a binary zero sig
nal along line BE.Consequently, the sig
nals along lines 3P4-3P1 1 are simply
transferred to lines 4P44P1 1 for further
transfer by counter CN4 to lines 3P12 3Pl9. The signal along line BE is a binary
zero when the second reference point of
shaft 106 is in the second angular position
because the signals along lines IM4B2 and
line D10 are zero at that time for the
assumed direction of rotation. With signals
on lines 3P4-3Pl l transferred to lines 3Pl2-3P19 the count is corrected.
The next pulse along line 4XU causes
the production of a binary one along line ÍM4B2 and the transfer of the signal along
line IM4BSTB to a binary zero. Conse
quently, the count on counter CN4 is re
tained until the receipt of the next carry
signal along line C030 as a result of
counter CN3 completing a count of 4,096 pulses or until the receipt of the next corrective pulse along line IM4BSTB.
To understand how counter CN4 is corrected each time the second reference point of shaft 106 passes through an angular position 1800 away from the second angular position, assume the rotation of shaft 101 has caused shaft 106 to be in this position. When this occurs, the signal generated by pulse generator PG4 and applied along line IM4 to amplifier B4 is changed from a binary zero to a binary one. As a result the next simultaneous pulse along line 4XU applied to register
DIC2 (Figure 8A) causes it to apply the binary zero signal from amplifier B4 on line IM4B to its output line IM4B1. As will be understood from previous discussion the presence of a binary one signal on line
IM4B until this time has caused a binary one signal to be applied on line IM4B2.
The binary zero signal on line IM4B1 is applied to one input of exclusive OR gate
XOR2 where it is combined with the binary one signal applied along line IM4B2 to the second input of that gate to produce a pulse signal which is applied along line
IM4BSTB to counter CN4.
It is to be understood that whenever the second reference point of shaft 106 is 1800 away from the second angular position the count in counter CN3 indicated by the signals along line 31P4-3Pll is representative of the number of times the first reefer ence point of shaft 101 has passed through the first angular position from the initial assumed condition plus a number indicative of the angle shaft 101 has rotated equivalent to the 1800 shaft 106 has rotated since its second reference point was last in the second angular position.
This equivalent angle causes the signal on line 3Pll to be the complement of the number desired to be transferred to counter CN4 when the second reference point of shaft 106 is 1800 from the second angular position. Exclusive OR gate XOR8 compensates for this by causing the signal on line 4Pll to be a binary one when the signal on line 3Pll is a binary zero and vice versa. This is accomplished because the signal along line BE is a binary one when the second reference point of shaft 106 is 1800 away from the second angular position as a result of the continued presence of the binary one signal along line IM4B2 during rotation of the second reference point of shaft 106 from the second angular position to the position 1800 removed therefrom for the assumed direction of rotation.
With a binary one along line BE, a binary one on line 3Pll and consequently 4PllA exclusive OR gate XOR8 produces a binary zero on line 4Pll. Conversely, a binary zero on line 3Pll and 4P11A en ables gate XOR8 to produce a binary one signal on line 4Pll. As a result during the production of the signal along line
IM4BSTB the number transferred to counter CN4 is not rendered incorrect by the presence of the complement on line 3P1 1 of the proper signal to be transferred to line 4P11.
From what has been explained it should be understood that the signal generated by pulse generator PG4 and applied along line IM4 to signal conditioner COND2 increasingly lags the signal generated by pulse generator PG3 and applied along line IM3 to signal conditioner COND2 with further rotation of shaft 101. As a result of this increasing lag when the reference point of shaft 101 has been angularly displaced from its initial position by 128-1/2 turns the logic level of the signals applied along lines IM3 changes from a binary zero signal to a binary one signal and simultaneously the signal applied along line IM4 changes from a binary one to a binary zero.As will be explained, when the first reference point of shaft 101 is rotated in excess of 129 rotations through its initial angular position the signals on data lines 4P4-4P1 1 when applied to counter CN4 as described would incorrectly represent the number of rotations of the first reference point. Consequently full adder ADD1, gates XOR7, XOR8 and inverter IA5 act as a signal translator to provide that the signals on line 4P44P1 1 correctly represent the number of rotations of the first reference point of shaft 101 whenever those signals are to be applied to the output lines 3P12-3P19 of counter
CN4.
Because of the increasing lag between shaft 101 and shaft 106 the first reference point of shaft 101 moves closer and closer to the first angular position for each additional positioning of the second reference point of shaft 106 at the position 1800 from the second angular position. Nevertheless, the signals applied from counter
CN3 along lines 3P4-3P10 and that applied to line 4PllA by OR gate XOR8 when the second reference point of shaft 106 is in the 1800 position correctly signifies the number of revolutions of the first reference point of shaft 101 past the first angular position. This continues until the 127th revolution of shaft 101 when its first reference point is 1/2 a tooth from the first angular position and the second reference point of shaft 106 is 1800 from the second angular position.During the next revolution of shaft 106 through 257 teeth of gear 104, the first reference point of shaft 101 therefore will pass through the first angular position twice because its gear 102 with its 256 teeth has to rotate through 257 teeth also. This brings the first reference point 1/2 a tooth past the first angular position. Accordingly, when the second reference point of shaft 106 arrives at the position 1800 from the second annular position as a result of this rctation the count in counter CN3 representing the number of times the first reference point has passed the first angular position should be equivalent to two more than was in it on the next preceding arrival of the second reference point of shaft 106 at the position 1800 away from the second angular position.The count in counter
CN3, however, appears to indicate that only one such revolution of shaft 101 past the first angular position has occurred. In order to provide for the additional count
NOR gate NOG4 applies a binary one to adder ADD1 during this and each subsequent arrival of the second reference point of shaft 106 at its 1800 position.
At each such arrival the signal along line IM4B2 is a binary one, producing a binary zero signal on line BE. Also because of the position of the first reference point of shaft 101 with respect to the first angular position during this and each sebsequent arrival of the second reference point of shaft 106 at the 1800 position the signal along line 3Pll at each such time is also a binary zero. This produces a binary one signal along line C040 which added to the signals along lines 3P4-3P10 and together with the signal along line 4P11 transfers to lines 3P12-3P19 during such revolutions signals signifying the number of times the first reference point has passed the first angular position tn correct the output of counter CN4 should it be in error at such times.
From the foregoing it can be seen that should counters CN3 or CN4 fail to represent correctly the signals signifying the position of the first reference point of shaft 101 and the number of times the first reference point of shaft 101 has passed through its first angular position, the output signals from those counters
CN3 and CN4 will be corrected each time the logic level of the signals generated by signal generators PG3 and PG4 is changed from a first level to a second level or from the second level to a first level. The level changes which cause the correction of counter CN3 during each revolution of shaft 101 have been chosen to occur when the first reference point of shaft 101 is at its first angular position and again when the first reference point is angularly displaced from its first angular position by 1800. The level changes which cause the correction of counter CN4 during each revolution of shaft 101 have been chosen to occur when the second reference point of shaft 106 is at its second angular position and again when that second reference point is displaced from its second position by 1800.
Operation of this embodiment in response to rotation of shafts 101 and 106 such that the counters reduce the numbers stored therein in response to the signals applied along line 4XUD occurs in the absence of a signal on line U10. This absence occurs as a result of the signals on line X3 leading the signals on line Y3.
This operation will be apparent to those of ordinary skill in the art in view of the foregoing and will not be explained herein for purpose of brevity. It should be mentioned, however, that because of the reversal of rotation of the shafts the signals along line IM3B2 and 1M4B2 are in the wrong state to produce the functions desired of exclusive OR gate XOR8 and
NOR gate NOG4 as previously described.
To resolve this input signals are applied along line D10 to exclusive OR gates
XOR5 and XOR7 which signals provide the operation provided by the signals along lines IM3B2 and IM4B2 for the opposite direction ofsrotation.
WHAT WE CLAIM IS:- 1. Apparatus for generating electrical signals signifying the angular position of a shaft which rotates in use through a plurality of revolutions, comprising a first rotary position transducer arranged to be driven by the shaft and to generate the same first signals during each revolution of the transducer, the first signals signifying the angular position of a first reference point of the first transducer during each revolution of the transducer, a second rotary position transducer arranged to be driven by the shaft so that when the first transducer is driven through a first plurality of revolutions the second transducer is driven through a second plurality of revolutions differing from said first plurality by one revolution and to generate the same second signals on each revolution of the second transducer, the second signals signifying at least when a second reference point of the second transducer reaches a reference position, and logic circuitry arranged to be responsive to the first and second signals and to provide signals signifying both the angular position of the first reference point and the number of revolutions of the shaft, said logic circuitry including a difference circuit arranged to determine the number of revolutions by determining the difference in the angular positions of the first and second transducers, which difference changes by a constant amount on each revolution of the shaft.
2. Apparatus as claimed in claim 1 wherein said first and second transducers are absolute position encoders arranged to produce code signals representative of their current angular positions and said difference circuit comprises means for subtracting the code signal of one transducer from the code signal of the other transducer.
3. Apparatus according to claim 1, characterized in that said second transducer is arranged to rotate at a speed slower than said first transducer whereby in each successive rotation of said transducers the angular position of said second reference point increasingly lags the angular position of said first reference point and said difference circuit operates in response to said first and second signals and generates difference signals signifying the angle by which the angular position of said second reference point lags the angular position of said first reference point.
4. Apparatus according to claim 3, characterized in that said logic circuitry includes a combining circuit which operates in response to said first signals and said difference signals and produces said angular position signals.
5. Apparatus according to claim 4, characterized in that said first and second transducers include a first encoder and a second encoder each producing discrete output signals at angular positions of said first and second shafts, respectively, each discrete output signal including a plurality of signal bits, said first encoder and said second encoder at particular angular positions of said first and second shafts producing their respective output signals out of synchronism, and wherein said difference circuit generates said difference signals in response to the differences between said first and second signals, said difference circuit including a compensating circuit enabling said angular position signals to signify correctly the angular position of said first reference point and the number of revolutions of said shaft.
6. Apparatus according to claim 5, including a gear reduction unit connecting said shaft to a second shaft, said gear reduction unit including a first gear mounted on the first-mentioned shaft and a second gear intermeshing with said first gear and mounted on said second shaft, each of said first and second encoders producing a plurality of output signals for each tooth of its associated gear.
7. Apparatus according to claim 1, characterized in that said second transducer rotates at a speed slower than said first transducer, whereby in each successive rotation of said transducers the angular position of said second reference point in creasinEsly lags the angular position of said
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (21)

**WARNING** start of CLMS field may overlap end of DESC **. to occur when the second reference point of shaft 106 is at its second angular position and again when that second reference point is displaced from its second position by 1800. Operation of this embodiment in response to rotation of shafts 101 and 106 such that the counters reduce the numbers stored therein in response to the signals applied along line 4XUD occurs in the absence of a signal on line U10. This absence occurs as a result of the signals on line X3 leading the signals on line Y3. This operation will be apparent to those of ordinary skill in the art in view of the foregoing and will not be explained herein for purpose of brevity. It should be mentioned, however, that because of the reversal of rotation of the shafts the signals along line IM3B2 and 1M4B2 are in the wrong state to produce the functions desired of exclusive OR gate XOR8 and NOR gate NOG4 as previously described. To resolve this input signals are applied along line D10 to exclusive OR gates XOR5 and XOR7 which signals provide the operation provided by the signals along lines IM3B2 and IM4B2 for the opposite direction ofsrotation. WHAT WE CLAIM IS:-

1. Apparatus for generating electrical signals signifying the angular position of a shaft which rotates in use through a plurality of revolutions, comprising a first rotary position transducer arranged to be driven by the shaft and to generate the same first signals during each revolution of the transducer, the first signals signifying the angular position of a first reference point of the first transducer during each revolution of the transducer, a second rotary position transducer arranged to be driven by the shaft so that when the first transducer is driven through a first plurality of revolutions the second transducer is driven through a second plurality of revolutions differing from said first plurality by one revolution and to generate the same second signals on each revolution of the second transducer, the second signals signifying at least when a second reference point of the second transducer reaches a reference position, and logic circuitry arranged to be responsive to the first and second signals and to provide signals signifying both the angular position of the first reference point and the number of revolutions of the shaft, said logic circuitry including a difference circuit arranged to determine the number of revolutions by determining the difference in the angular positions of the first and second transducers, which difference changes by a constant amount on each revolution of the shaft.

2. Apparatus as claimed in claim 1 wherein said first and second transducers are absolute position encoders arranged to produce code signals representative of their current angular positions and said difference circuit comprises means for subtracting the code signal of one transducer from the code signal of the other transducer.

3. Apparatus according to claim 1, characterized in that said second transducer is arranged to rotate at a speed slower than said first transducer whereby in each successive rotation of said transducers the angular position of said second reference point increasingly lags the angular position of said first reference point and said difference circuit operates in response to said first and second signals and generates difference signals signifying the angle by which the angular position of said second reference point lags the angular position of said first reference point.

4. Apparatus according to claim 3, characterized in that said logic circuitry includes a combining circuit which operates in response to said first signals and said difference signals and produces said angular position signals.

5. Apparatus according to claim 4, characterized in that said first and second transducers include a first encoder and a second encoder each producing discrete output signals at angular positions of said first and second shafts, respectively, each discrete output signal including a plurality of signal bits, said first encoder and said second encoder at particular angular positions of said first and second shafts producing their respective output signals out of synchronism, and wherein said difference circuit generates said difference signals in response to the differences between said first and second signals, said difference circuit including a compensating circuit enabling said angular position signals to signify correctly the angular position of said first reference point and the number of revolutions of said shaft.

6. Apparatus according to claim 5, including a gear reduction unit connecting said shaft to a second shaft, said gear reduction unit including a first gear mounted on the first-mentioned shaft and a second gear intermeshing with said first gear and mounted on said second shaft, each of said first and second encoders producing a plurality of output signals for each tooth of its associated gear.

7. Apparatus according to claim 1, characterized in that said second transducer rotates at a speed slower than said first transducer, whereby in each successive rotation of said transducers the angular position of said second reference point in creasinEsly lags the angular position of said
first reference point, said first transducer generates a plurality of electrical signals for each revolution, each electrical signal being generated in response to a rotation through a predetermined angle, said second transducer generates a second index signal each time said second reference point is in a second angular position, and said logic circuitry includes a first counter connected to said first transducer and a second counter connected to said first counter and said second transducer, said first counter receiving said electrical signals and producing an output signal signifying the number received, said first counter generating a carry signal each time it receives a predetermined number of electrical signals, said second counter receiving said carry signals and producing output signals signifying the number of carry signals received, each said second index signal being applied to said second counter and operable to cause sai;d first counter to apply the number signal it is then producing to said second counter.

8. Apparatus according to claim 7 including a gear reduction unit connecting said shaft to a second shaft, said gear reduction unit including a first gear mounted on the first-mentioned shaft and a second gear mounted on said second shaft and intermeshing with said first gear and having more teeth than said first gear, and said first transducer also generates a first index signal each time said first reference point is in a first angular position, said first and second index signals being generated in synchronism when said first and second reference points are simultaneously in said first and second angular positions.
respectively, and each said first index signal is applied to said first counter causing it to be restored to an initial condition.

9. Apparatus according to claim 8, characterized in that said first shaft can rotate in either of two directions, said first transducer generates separate electrical signals for each direction of rotation and said first counter is bi-directional whereby the electrical signals associated with one direction of rotation cause said first counter to produce an output signal signifying the accumulated number of said signals and the electrical signals associated with the other direction cause said first counter to reduce its output signal by the accumulated number of said latter signals.

10. Apparatus according to claim 1, characterized in that said second transducer is arranged to rotate at a speed slower than said first transducer, whereby in each successive rotation of said transducers the angular position of said second reference point increasingly lags the angular position of said first reference point, said first transducer generating a plurality of electrical signals for each revolution, each electrical signal being generated in response to a rotation through a prede- termined angle, said second transducer generating a second index signal which transfers from a first level to a second level each time said second reference point isin a second angular position and from said second level to said first level each time said second reference point is in a position 1800 from said second angular position, and said logic circuitry includes a first counter connected to said first transducer and a second counter connected to said first counter and said second transducer, said first counter receiving said electrical signals and producing an output signal signifying the number received, said first counter generating a carry signal each time it receives a predetermined number of electrical signals, said second counter receiving said carry signals and producing output signals signifying the number of carry signals received, each transfer in level of said second index signal enabling said second counter to respond to the instantaneous output signal of said first counter to signify correctly the number of carry signals received.

11. Apparatus according to claim 10, characterized in that said first transducer also generates a first index signal which transfers from a first level to a second level each time said first reference point is in a first angular position and from said second level to said first level each time said second reference point is in a position 1800 from said second angular position, said first and second index signals being generated in synchronism when said first and second reference points are simultaneously in said first and second angular positions respectively and wherein each transfer in level of said first index signal applied to said first counter causes it to register a predetermined number.

12. Apparatus according to claim 1, characterized in that when said first reference point is initially at a first angular position said second reference point is initially at a predetermined second angular position with respect to said first reference point and said second transducer rotates at a speed slower than said first transducer, whereby in each successive rotation of said transducers the angular position of said second reference point increasingly lags the angular position of said first reference point;
said first transducer generates a plurality of electrical signals during each revolution, each electrical signal being generated in response to a rotation through a predetermined angle and signifying that angular rotation;
said second transducer generates a second index signal each time said second reference point is in said second angular position; and
said logic circuitry includes counting means connected to said second transducer for receiving said second index signals, each said second index signal being applied to said counting means and operable to cause said first transducer to apply the number signal it is then producing to said counting means.

13. Apparatus as claimed in claim 1 wherein said first transducer is arranged to produce one of said first signals when said first reference point is in a reference position, said second transducer is arranged to produce a second signal when said second reference point is in a reference position, and said first signals include a plurality of third signals produced during each revolution of the first transducer, said logic circuitry including counting means including a high order portion and a low order portion, each having a plurality of parallel data inputs and a parallel entry command input, connected to said first transducer for counting said third signals and providing output signals, of which the low order portion is indicative of the rotational position of one of said transducers,
and of which the high order portion is indicative of the relative rotational position of said first and second reference points, which thereby provides an indication of the number of revolutions rotated by said transducers, said parallel entry command input of the low order portion of said counting means being connected to said first transducer and responsive to said first signals to enter therein through said parallel data inputs, in response to said first signal, a count indicative of the rotational position of said first transducer being k half-revolutions, where k=O or an integer; said parallel data entry command input of the high order portion of said counting means being connected to said second transducer and said parallel data inputs of the high order portion of said counting means being interconnected with the outputs of the low order portion of said counting means for entering into said high order portion, in response to said second signals, a count indicative of the relative rotational positions of said transducers, whereby said counting means outputs provide both an indication of the rotational position of one of said transducers and a sub-revolution indication of the relative rotation between said first and second transducers, which in turn is an indication of the number of revolutions which one of said transducers has rotated, and said indications are volatility corrected by said first and second signals.

14. A shaft position transducer according to claim 13 wherein k=O.

15. A shaft position transducer according to claim 13 wherein k=l.

16. Apparatus as claimed in claim 13 wherein said shaft and first and second transducers are arranged for mutually related rotation by said shaft so that a first one of said transducers is driven a first binary number of, or 2″, revolutions as said second one of said transducers is driven one less than said first binary number of, or 2″- 1, revolutions, said first transducer is arranged to produce a second binary number of, or 2run, said third signals per revolution, where m and n are any integers greater than one and may be the same; said counting means comprises a first binary counter, having a plurality of parallel data inputs and a parallel entry command input, connected ta said first transducer for counting said third signals and providing said low order outputs indicative of the rotational position of said first transducer and providing a carry signal in response to each counting of a number of said third signals indicative of a full revolution of said first transducer, and a second binary counter, having a plurality of parallel data inputs and a parallel data entry command input, connected to said first counter for counting the carry signals from said first counter and providing said high order outputs indicative of the relative rotational positions of said transducers, said parallel data inputs of said second counter being interconnected with outputs of said first counter for entering into said second counter, in response to said second signals, a count indicative of the rotational position of said first transducer, whereby said first counter outputs provide both a binary indication of the rotational position of said first transducer and a sub-revolution indication of the relative rotation of said first and second transducers, and said second counter outputs provide a binary indication of the number of revolutions of said first transducer.

17. Apparatus as claimed in claim 16 wherein k=l and said first transducer is arranged to produce said first signals indicative of a first reference position of said first reference point and of a reference position 1800 from said first reference position, said first signals thereby delineating half-revolutions of said first transducer, said second transducer is arranged to produce said second signals indicative of a second reference position of said second reference point and of a reference position 1800 from said second reference position, said second signals thereby delineating half-revolutions of said second transducer, and further comprising means responsive to said first, second and third signals for providing control signals indicative of the direction of rotation and relative position of said transducers, for providing an input to the highest-ordered parallel data input of said first counter in response to said control signals and zeros to the remaining parallel data inputs of said first counter, and for selectively (1) adding to the count represented by said high order portion of the outputs of said first counter and/or (2) reversing the binary significance of the highest-ordered output of said first counter, as applied to the parallel data inputs of said second counter in response to said control signals, whereby said counters are volatility-corrected within a single revolution of said first coded transducer.

18. Apparatus as claimed in claim 16 wherein k=0, and said parallel data inputs of said first counter are disposed to enter a count of zero in response to said first signal, and said parallel data inputs of said second counter are all directly responsive to corresponding outputs of said first counter, whereby said counters are volatility-corrected within two revolutions of said first transducer.

19. Apparatus for generating electrical signals signifying the angular position of a shaft, substantially as hereinbefore described with reference to Figs. 2, 31 and 4 of the accompanying drawings.

20. Apparatus for generating electrical signals signifying the angular position of a shaft, substantially as hereinbefore described with reference to Figs 5 and 6 of the accompanying drawings.

21. Apparatus for generating electrical signals signifying the angular position of a shaft, substantially as hereinbefore described with reference to Figs. 7, 8A and 8B of the accompanying drawings.

GB47734/76A
1975-12-18
1976-11-16
High resolution and wide range shaft position transducer systems

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1975-12-18
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High resolution and wide range shaft position transducer systems

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Publication number
Priority date
Publication date
Assignee
Title

FR2608756A1
(en)

*

1986-12-19
1988-06-24
Staubli Sa Ets
Displacement sensor for automatic machines

US4841297A
(en)

*

1986-12-19
1989-06-20
S.A. Des Etablissements Staubli
Displacement coder

EP0327777A1
(en)

*

1988-02-12
1989-08-16
S.A. DES ETABLISSEMENTS STAUBLI (France)
Displacement sensor for automatic machines

Families Citing this family (9)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

NL7803912A
(en)

*

1977-04-25
1978-10-27
Schlatter Ag

CORNER CODING DEVICE.

JPS58106691A
(en)

*

1981-12-21
1983-06-25
株式会社エスジ−
Multi-rotation type rotary encoder

JPS5979114A
(en)

*

1982-10-27
1984-05-08
S G:Kk
Detector for absolute line position

JPS59188518A
(en)

*

1983-04-11
1984-10-25
Fanuc Ltd
Detection system for absolute position of servocontrol system

JPS59188517A
(en)

*

1983-04-11
1984-10-25
Fanuc Ltd
Detection system for absolute position of servocontrol system

JPS59204708A
(en)

*

1983-05-09
1984-11-20
Fanuc Ltd
Absolute-position detecting device

JPS603099A
(en)

*

1983-06-20
1985-01-09
株式会社エスジ−
Absolute position detector

EP0201106A3
(en)

*

1985-05-10
1990-01-17
Hewlett-Packard Company
Absolute position encoder

WO2016068302A1
(en)

*

2014-10-30
2016-05-06
株式会社ニコン
Encoder apparatus, drive apparatus, stage apparatus, robot apparatus, and multi-rotation information calculation method

Family Cites Families (6)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US2944159A
(en)

*

1959-09-22
1960-07-05
Sperry Rand Corp
Differential action synchro transducer

GB999972A
(en)

*

1961-02-16
1965-07-28
Data Technology Inc
Position encoding apparatus

NL11261C
(en)

*

1965-05-04

US3660830A
(en)

*

1969-08-18
1972-05-02
Lear Siegler Inc
Multi-element shaft encoder incorporating a geneva drive

US3885209A
(en)

*

1973-12-27
1975-05-20
Astrosyst Inc
Two speed control systems

DE2553815C3
(en)

*

1975-11-29
1983-03-17
G. Zscherpel Elektronik, 7060 Schorndorf

Graycode transducer

1976

1976-10-28
CA
CA264,409A
patent/CA1080326A/en
not_active
Expired

1976-11-01
SE
SE7612109A
patent/SE432020B/en
not_active
IP Right Cessation

1976-11-01
IN
IN1988/CAL/76A
patent/IN147783B/en
unknown

1976-11-05
ZA
ZA766650A
patent/ZA766650B/en
unknown

1976-11-16
GB
GB47734/76A
patent/GB1565400A/en
not_active
Expired

1976-11-25
IT
IT52351/76A
patent/IT1073581B/en
active

1976-12-02
MX
MX167244A
patent/MX147090A/en
unknown

1976-12-07
JP
JP51147625A
patent/JPS5276952A/en
active
Granted

1976-12-07
DE
DE2655413A
patent/DE2655413C3/en
not_active
Expired

1976-12-09
AU
AU20413/76A
patent/AU504153B2/en
not_active
Expired

1976-12-09
AT
AT909076A
patent/AT362685B/en
active

1976-12-10
BR
BR7608286A
patent/BR7608286A/en
unknown

1976-12-16
NO
NO764268A
patent/NO146037C/en
unknown

1976-12-17
FI
FI763637A
patent/FI64998C/en
not_active
IP Right Cessation

1976-12-17
BE
BE173387A
patent/BE849545A/en
not_active
IP Right Cessation

1976-12-17
FR
FR7638232A
patent/FR2335823A1/en
active
Granted

1976-12-17
DK
DK572276A
patent/DK150863C/en
not_active
IP Right Cessation

1976-12-17
ES
ES454369A
patent/ES454369A1/en
not_active
Expired

1976-12-17
NL
NL7614088A
patent/NL7614088A/en
not_active
Application Discontinuation

1976-12-18
EG
EG776/76A
patent/EG13211A/en
active

Cited By (3)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

FR2608756A1
(en)

*

1986-12-19
1988-06-24
Staubli Sa Ets
Displacement sensor for automatic machines

US4841297A
(en)

*

1986-12-19
1989-06-20
S.A. Des Etablissements Staubli
Displacement coder

EP0327777A1
(en)

*

1988-02-12
1989-08-16
S.A. DES ETABLISSEMENTS STAUBLI (France)
Displacement sensor for automatic machines

Also Published As

Publication number
Publication date

AU2041376A
(en)

1978-06-15

IN147783B
(en)

1980-06-28

MX147090A
(en)

1982-10-05

ZA766650B
(en)

1977-08-31

CA1080326A
(en)

1980-06-24

JPS6213602B2
(en)

1987-03-27

FI64998B
(en)

1983-10-31

DE2655413C3
(en)

1981-11-19

IT1073581B
(en)

1985-04-17

FI64998C
(en)

1984-02-10

DE2655413A1
(en)

1977-06-23

ES454369A1
(en)

1978-05-16

SE432020B
(en)

1984-03-12

DK150863B
(en)

1987-07-06

SE7612109L
(en)

1977-06-19

DK572276A
(en)

1977-06-19

FI763637A
(en)

1977-06-19

AT362685B
(en)

1981-06-10

DE2655413B2
(en)

1980-12-18

NL7614088A
(en)

1977-06-21

ATA909076A
(en)

1980-10-15

FR2335823B1
(en)

1982-11-19

BR7608286A
(en)

1977-11-29

BE849545A
(en)

1977-04-15

NO146037B
(en)

1982-04-05

FR2335823A1
(en)

1977-07-15

NO146037C
(en)

1982-07-21

NO764268L
(en)

1977-06-21

JPS5276952A
(en)

1977-06-28

DK150863C
(en)

1988-06-06

EG13211A
(en)

1980-12-31

AU504153B2
(en)

1979-10-04

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Legal Events

Date
Code
Title
Description

1980-07-09
PS
Patent sealed [section 19, patents act 1949]

1991-07-10
PCNP
Patent ceased through non-payment of renewal fee

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