GB1565421A - Creation of Inventions and Patents with Artificial Intelligence

GB1565421A – Manufacture of electrical devices
– Google Patents

GB1565421A – Manufacture of electrical devices
– Google Patents
Manufacture of electrical devices

Download PDF
Info

Publication number
GB1565421A

GB1565421A
GB805/77A
GB80577A
GB1565421A
GB 1565421 A
GB1565421 A
GB 1565421A
GB 805/77 A
GB805/77 A
GB 805/77A
GB 80577 A
GB80577 A
GB 80577A
GB 1565421 A
GB1565421 A
GB 1565421A
Authority
GB
United Kingdom
Prior art keywords
ceramic
paste
metal
powdered
oxide
Prior art date
1976-02-03
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB805/77A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

International Business Machines Corp

Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1976-02-03
Filing date
1977-01-10
Publication date
1980-04-23

1977-01-10
Application filed by International Business Machines Corp
filed
Critical
International Business Machines Corp

1980-04-23
Publication of GB1565421A
publication
Critical
patent/GB1565421A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

Classifications

C—CHEMISTRY; METALLURGY

C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES

C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE

C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone

C04B41/009—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone characterised by the material treated

C—CHEMISTRY; METALLURGY

C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES

C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE

C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone

C04B41/45—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements

C04B41/50—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements with inorganic materials

C04B41/51—Metallising, e.g. infiltration of sintered ceramic preforms with molten metal

C04B41/5122—Pd or Pt

C—CHEMISTRY; METALLURGY

C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES

C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE

C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone

C04B41/45—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements

C04B41/51—Metallising, e.g. infiltration of sintered ceramic preforms with molten metal

C04B41/5133—Metallising, e.g. infiltration of sintered ceramic preforms with molten metal with a composition mainly composed of one or more of the refractory metals

C—CHEMISTRY; METALLURGY

C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES

C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE

C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone

C04B41/80—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone of only ceramics

C04B41/81—Coating or impregnation

C04B41/85—Coating or impregnation with inorganic materials

C04B41/88—Metals

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer

H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 – H01L21/326

H01L21/4814—Conductive parts

H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation

H01L21/4857—Multilayer substrates

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L23/00—Details of semiconductor or other solid state devices

H01L23/12—Mountings, e.g. non-detachable insulating substrates

H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties

H01L23/15—Ceramic or glass substrates

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L23/00—Details of semiconductor or other solid state devices

H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames

H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

H01L23/5383—Multilayer substrates

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/0001—Technical content checked by a classifier

H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 – H01L2924/0715

H01L2924/097—Glass-ceramics, e.g. devitrified glass

H01L2924/09701—Low temperature co-fired ceramic [LTCC]

H—ELECTRICITY

H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

H05K1/00—Printed circuits

H05K1/02—Details

H05K1/09—Use of materials for the conductive, e.g. metallic pattern

H05K1/092—Dispersed materials, e.g. conductive pastes or inks

H—ELECTRICITY

H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

H05K3/00—Apparatus or processes for manufacturing printed circuits

H05K3/46—Manufacturing multilayer circuits

H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards

H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials

H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC

Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

Y10T29/00—Metal working

Y10T29/49—Method of mechanical manufacture

Y10T29/49002—Electrical device making

Y10T29/49117—Conductor or circuit manufacturing

Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

Y10T29/49128—Assembling formed circuit to base

Description

PATENT SPECIFICATION ( 11) 1 565 421
_ 1 ( 21) Application No 805/77 ( 22) Filed 10 Jan 1977 t ( 31) Convention Application No 654686 ( 32) Filed 3 Feb1976 in Q ( 33) United States of America (US) 2 ( 44) Complete Specification published 23 April 1980 ( 51) INT CL 3 H 05 K 3/00 Y-4 ( 52) Index at acceptance HIR 10 17 AF ( 72) Inventors LINDA ANN BLAZICK and LEWIS FRANKLIN MILLER ( 54) MANUFACTURE OF ELECTRICAL DEVICES ( 71) We, INTERNATIONAL BUSINESS MACHINES CORPORATION, a Corporation organized and existing under the laws of the State of New York in the United States of America, of Armonk, New York 10504, United States of America do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in 5
and by the following statement:-
The invention relates to the manufacture of electrical devices and more particularly, but not exclusively, concerned with the manufacture of ceramic multilayer circuit boards.
The sintering of a ceramic body is a function of many parameters including 10 green or unfired ceramic sheet density, binder content and type, ceramic composition and particle distribution, firing conditions including ambient and actual temperature A predictable shrinkage rate and final shrinkage percentage is attainable by a controlled set of these variables It is, of course, essential to have a reproducible manufacturing process so that these variables can be controlled 15 Similar considerations apply to the conductive materials applied to the ceramic bodies Composites of conductive materials and ceramics such as used in electronic modules show modified sintering behaviour as a result of the constraints that the combination of ceramic materials and conductive materials put on each other during the firing process For a relatively stress free, unwarped, strong composite, 20 the shrinkage rates of contiguous regions of conductive and ceramic materials must be properly matched For example, should the conductive material attain final shrinkage considerably before the ceramic material, the remaining ceramic material shrinkage will add stress and probably produce undesirable cracks in the product It is most desirable to have the shrinkage of the conductive material and 25 the ceramic material to be matched for the full time of firing.
The publication “Metal-Ceramic Constraints for Multilayer Electronic Packaging” by D A Chance and D L Wilcox in the Proceedings of the IEEE Volume 59, No 10, October 1971, pages 1455-1462 considers the chemical and physical compatibility between the ceramic and metal parts which are cofired or 30 sintered at elevated temperatures It suggests that improper shrinkage design leads to cracks, camber of the sintered part, residual stresses and loss of metal-ceramic adhesion.
The invention provides a method of manufacturing an electrical device by applying a paste to the surface of an unfired or incompletely fired ceramic 35 substrate in a predetermined pattern, causing or allowing the paste to dry off, and thereafter firing the ceramic substrate and paste to form a conductor from the paste, said method comprising fabricating the paste as a mix of a powdered high conductivity metal and a powdered metallic oxide of the metal in a liquid vehicle and selecting the relative proportions of powdered metal and powdered metallic 40 oxide in the paste so that the percentage shrinkage of the paste that occurs during firing closely matches that of the ceramic substrate and more closely matches the percentage shrinkage of the ceramic substrate than that of a paste comprising only the powdered metal and not containing the metallic oxide.
The invention also provides a method of manufacturing a ceramic, multilayer 45 circuit board for carrying semiconductor chips comprising applying a paste comprising a particular mixture of a metal and a metallic oxide of the metal in the ratio of between 1:1 and 9:1 in a pattern onto an unfired ceramic layer; said metal having a high conductivity and a thermal expansion coefficient similar to that of the ceramic layer; drying said pattern; stacking said coated ceramic layer with one or more other similar unfired ceramic layers to form the board structure: subjecting the stacked layers of ceramic to a pressure greater than about 2500 pounds per square inch; firing the ceramic stack to form a unitary board: and cooling the board 5 to room temperature.
We have found that the use of a paste comprising a selected proportion of metal oxide powder as well as the metal powder, permits a measure of control of the shrinkage of the conductor pattern during the formation of multilayer modules comprising ceramic substrates Commonly used ceramics, such as aluminas, 10 mullite, beryllias, titanates and steatites are usable as the ceramic component.
Metallizing compositions which are useful in practicing the invention in that they have a high conductivity and a thermal coefficient of linear expansion similar to that of ceramics, include molybdenum, tungsten, and noble metals that can form oxides such as silver, and palladium The metallization composition is adjusted by 15 ratios of the metal oxide to the metal in the range of 1: 1 to 1:9 depending upon the shrinkage condition of the ceramic to be cofired with the conductive composition.
The powder or particulate mixture containing the metal and metal oxide is deposited in a suitable pattern on one or more of the unfired or green ceramic layers or substrates which will make up the multilayer level ceramic substrate The 20 patterns are dried The plurality of layers of ceramic are then laminated by stacking together and then applying a substantial pressure thereto for example a pressure greater than 2500 pounds per square inch The laminate is then fired at a suitably elevated temperature and then cooled The result is a multilayer ceramic substrate which is substantially free of stresses, cracks and warpage The fired metallurgy is 25 dense and conductive.
The invention will now be further described by way of example with reference to the accompanying drawings, in which:Figure 1 is a flow chart illustrating a method embodying the present invention; Figure 2 illustrates an expanded stack of ceramic layers having metallization 30 patterns in a multilayer ceramic structure; Figures 3 A, 3 B and 3 C illustrate the steps involved in the lamination and firing of a multilayer ceramic substrate; Figures 4 A and 4 B show via structures in a multilayer ceramic structure; Figure 5 shows a semiconductor chip site in a multilayer ceramic module; 35 Figure 6 A and 6 B illustrates the problem of cracking between vias in multilayer ceramic substrates.
Description of the Preferred Embodiments
A multilayer ceramic fabrication process involves the formation of the green or unfired ceramic layers or sheets, the formation of the conductive paste, the 40 screening of the conductive paste onto the green ceramic sheets and the stacking, laminating and firing of the ceramic sheets into the final multilayer ceramic structure These general processes are known in the art and are described in the publication entitled “A Fabrication Technique for Multilayer Ceramic Module”, H A Kaiser et al, Solid State Technology, May 1972, pp 35-40 and the Park U S 45 Patent No 2,966,719.
The ceramic green sheet is formed by weighing out the proper portions of the ceramic powder and glass frit, and blending the particles by ball or other milling techniques The organic binder comprising the thermoplastic resin, plasticizer and solvents is then mixed and blended with the ceramic and glass powders on a ball 50 mill A slurry or slip is cast into a tape form by extruding or doctor blading The cast sheet is then allowed to be dried of the solvent constituent in the binder system After the tape is completely dried, it is then cut into working blanks or sheets, registration holes are formed in the blanks together with the via holes which are selectively punched in the working blanks The via holes will eventually be 55 filled with conductive composition to allow for electrical connections from layer to layer in the multilayer ceramics structure.
The preparation of conductive paste and the remaining steps in the formation of a multilayer ceramic module or substrate may be understood with reference to Figures 1 and 2 The Figure 1 flow chart shows the preferred metal and metal oxide 60 embodiment wherein the molybdenum powder and molybdenum trioxide powder are mixed dry in the ratio of 1:1 to 9:1 molybdenum to molybdenum trioxide The average preferred particle size for molybdenum is about 1 5 to 3 5 microns and molybdenum trioxide 2 to 5 microns A suitable vehicle or solvent is mixed with the 1,565 421 dry powder and then milled in a suitable mill such as a three-roll mill into a paste.
The vehicle chosen must be one which may be given off at or below the firing or sintering temperature of the ceramic being utilized so that only the residual metallization remains after the process is completed The conductive paste is then screened onto the green sheet to form the desired circuit patterns by the 5 conventional silk screening techniques Where it is desired to have electrical connections between the layers it is necessary to punch holes in the sheet prior to silk screening, and a second silk screening operation may be done to fill the via holes Alternatively, one silk screening can be used to simultaneously coat the surface and force the paste into the via holes Thereafter the paste is dried by 10 placing the sheets in an oven and baking them at a rather low temperature, for example, 60 -1000 C for 15-60 minutes, or the paste may be simply air dried.
Figure 2 illustrates a plurality of layers of the ceramic having a variety of conductive patterns thereon which are being stacked in the proper sequence The stack may be carefully registered using registration pins (not shown) so that all 15 conductive lines from layer to layer are properly registered and aligned The top or surface layer 10 is provided in the Figure 2 example with two patterns 12 that are suitable for joining semiconductor chips 14 thereto These particular chips are of the flip-chip or contacts down variety The next level 16 has two conductive patterns 18 which connect through conductive via holes through the layer 1 U to the 20 conductive lines 18 Other via holes through the layer 16 make circuit connections to the succeeding layers 20, 22 and the remaining group of layers 24 so as to provide the required circuit connections for the input and output of signals to the semiconductor chips 14 These vias are between about 5 to 7 thousandths of an inch punched diameter and on centers about 10 to 12 thousandths of an inch 25 The registered stack of green ceramic layers is placed in a laminating press.
Moderate heat and pressure is applied The preferred pressure for alumina ceramic is greater than 2500 psi and a temperature of about 80-1000 C In this step, the thermoplastic binder in the green ceramic sheets softens and the layers fuse together, deforming around the metallized pattern to completely enclose the lines 30 The result is that the unfired stack will show no signs of individual layers The stack of green sheets is then sawed or punched to the size of the finished module plus an allowance for shrinkage The green module is fired in a suitable furnace wherein the module is raised from room temperature to a temperature greater than 14500 C at a rate of 1400 C per hour and the furnace is then maintained at 150016000 C for 35 1-5 hours for the firing of green ceramic The firing ambient is wet hydrogen The temperature is then reduced to room temperature at a rate of about 2000 C/hr.
The effect of laminating and firing of a multilayer structure can better be appreciated with reference to Figures 3 A, 3 B and 3 C Three green, unfired ceramic layers 30, 32 and 34 are shown in Figure 3 A having conductive paste layers 36, 38 40 and 40 thereon Also shown are via holes 42, 44 and 46 which are filled with conductive paste The composite of Figure 3 A is laminated under pressure and temperature by which the thermoplastic nature of the green sheets causes the various layers to adhere to one another and produce a unitary body Portions of the ceramic and the conductive paste are compressed where they come together 45 Figure 3 C illustrates the resulting multilayer ceramic structure following the firing step This multilayer structure 50 has shrunk typically for alumina 16-18 %, The resulting metallurgy 52 has most desirably also shrunk exactly that percentage so as to reduce stresses and cracks in the ceramic to the very minimum.
Figures 4 A, 4 B, 5, 6 A, and 6 B illustrate some of the failure modes for via 50 conductive structures in multilayer ceramic modules.
Figure 4 A shows an unfired laminated stack of ceramic layers 60 with via 62.
Figure 4 B shows the fired structure wherein the unitary ceramic structure 64 contains three vias 66, 68 and 70 Via 66 is a negative via since the surface of the ceramic is above the top surface of the conductive via 66 The via 68 is a flush via 55 since the top surface of the conductive via is at the same level as the top surface of the ceramic 64 The via 70 is a bulged or raised via since the conductive via top surface is slightly above the surface of the ceramic The preferred via is 70 wherein a semiconductor chip 72 such as shown in Figure 5 having conductive metal projections 74 extending therefrom is to be attached to the via on a multilayer 60 ceramic module Via 66 and 68 would not have the ability to make a good connection to the conductive projections of the semiconductor chip as the via 70 or to make good contact with electrical test probes To obtain the structure such as via 70 the loading of the conductive paste with metal and metal oxide must be optimized 65 1,565,421 Figure 5 illustrates the joining of a semiconductor chip to the surface of a multi-layer ceramic module 76 wherein the surface 78 of the module is warped.
This effect is caused by too much pressure from conductive layers within the multilayer ceramic module during the firing step The resulting structure as can be seen from Figure 5 will not satisfactorily join with the semiconductor metal pads 5 74 To alleviate this problem a substantial amount of metal oxide is incorporated into the metallized paste, as suggested in the above processing.
6 A and 6 B illustrate a multi-layer ceramic module 80 having a multiplicity of vias 82 therein In this example, cracks 84 are shown between the vias which are caused by pressure between the metallurgy and the enclosing ceramic The 10 pressure is a function of the relative shrinkages during sintering, the expansion coefficients upon cooling, and material strength properties Again, the solution for this problem is the incorporation of the substantial amount of metal oxide as described above.
It is known that various types of conductors are useful in multi-layer ceramic 15 structures It is most useful to have the metal having the greatest conductivity as the conductor within the multi-layer ceramic However, some of the most conductive of the metals including copper and silver have relatively low melting points and this precludes their use when co-firing the ceramics that require higher sintering temperatures For compatibility with high temperature ceramic materials 20 commonly used in manufacture of multi-layer ceramics, metals with melting points in excess of 14500 C are required Typically, the multilayer ceramic structures described are fired at temperatures sufficiently high to require the use of refractory conductive materials However, as described in German Offenlegungsschrift No.
2460931 2 lower firing bodies can be used which permit the similar use of silver and 25 copper, with their oxides Table I gives some of the properties of principal metals useful in multi-layer ceramic structures.
TABLE I
Melting Boiling Electrical Thermal Approx.
Point Point Density Resistivity Expansion Cost Metal (OC) (OC) (g/cm 3) (,iohm cm) ( 10-6/OC) (S/cm 3) Rhodium 1966 4500 12 4 4 7 8 5 55 40 Molybdenum 2620 4507 10 2 5 7 5 0 0 10 Tungsten 3410 5900 19 35 5 5 4 5 0 23 Nickel 1453 2730 8 90 6 84 13 3 Ruthenium 2450 4150 12 30 9 5 9 6 49 20 Platinum 1774 4300 21 45 10 6 9 0 123 00 Palladium 1549 2200 11 97 10 8 11 0 13 20 Table II gives the properties of certain ceramic materials which are usable as a ceramic in multi-layer ceramic materials The Table gives some of the more 40 significant dielectric properties of these inorganic insulators It is important to as closely as possible match the thermal expansion co-efficient of the metal with the ceramic expansion co-efficient, particularly to further avoid the aforementioned cracks between the vias.
TABLE II 45
Resistivity Melting Expansion at 250 C Dielectric t JI Point Coefficient Material (ohm cm) Constant 10-9 s/in (OC) ( 250 C)x 10-60 C A 1203 10 ‘4 9 6 0 260 2072 7 3 Be O 1104 6 5 0 230 2565 8 0 Zr Si O 4 1014 8 7 0 250 1775 4 0 Mg AI 204 1012 8 5 0 246 2135 8 8 3 A 1203 Si O 2 11014 6 0 0 207 1840 5 3 t D W -= ( 1) I C and represents a signal transmission delay per unit length of the material 55 In equation (I) l=length of signal transmission path E=dielectric constant t O =signal delay C=speed of light 1.565 421 A 1,565,421 5 The use of metal oxides together with the metal, for example, molybdenumtrioxide with molybdenum in a range of 1:1 to 9:1 molybdenum:
molybdenumtrioxide is helpful in matching ceramic shrinkage The use of molybdenumtrioxide produces greater shrinkage in the metallurgy This gives improved shrinkage control and prevents warping of the ceramic and reduces 5 residual stresses in the ceramic which causes cracking and bulges within the multilayer ceramic structure During firing the metal oxide, such as molybdenumtrioxide, is reduced to molybdenum and the oxygen is evolved through the ceramic and to the ambient.
The following Examples are included merely to aid in the understanding of the 10 invention.
Example 1
Four multilayer ceramic modules were formed having thirty ceramic layers approximately 4 inches square Of these layers, eight layers were substantially covered with metallizing to simulate ground or voltage distribution planes such as 15 shown in Figure 2 layer 20 The remaining layers consisted of line circuitry patterns The substantially covered eight layers dominate the metal/ceramic interaction and most directly affect shrinkage The punched vias within the structure were 6 mils in diameter The vias were simultaneously filled during the surface conductor screening process Some of the vias went down directly through 20 28 layers The ceramic utilized in the layers was a high purity alumina containing 400 grams of 89 , alumina and 11 % glass frit, with 25 4 grams of polyvinyl butyral binder plasticized with 9 4 grams of a high molecular weight ester type plasticizer (dioctyl phthalate) The ceramic was made according to the process described in the aforesaid Kaiser et al publication Etched metal masks having cavities of 25 to 25 microns and a total thickness of 2 5 to 3 mils were utilized to extrude the conductive paste by means of a squeegee A molybdenum paste was utilized with an average molybdenum particle size of 2 5 microns.
The first thirty ceramic layer module was used as a control or dummy and had no molybdenum paste on any of the layers whereas the second, third, and fourth 30 modules had their eight substantially covered layers respectively coated with pastes comprising 86 %: 80 %: and 75 , molybdenum solid particles in a vehicle The percentages herein are by weight.
Shrinkage Dummy (no paste on any layer) 17 7 % 35 86 % Solid Mo particles 16 6-16 7 ,, % Solid Mo particles 17 0 % % Solid Mo particles 17 16 % The results indicate that a high percentage of pure molybdenum powder in the paste distinctly retards shrinkage of the module Lower molybdenum content have 40 less effect For this series, each percentage of molybdenum between 75 % and 86 % retarded shrinkage about 0 05 %.
Example 2
The procedure of Example 1 was followed with the exception that the paste composition was varied in certain cases by the substitution of molybdenum trioxide 45 for some of the pure molybdenum powder The average particle size of the molybdenum powder was 2 5 microns and for the molybdenum trioxide it was 3 5 microns The following Table shows the variations in the shrinkage results obtained:
Shrinkage 50 Dummy (no paste) 17 7 % 86/,, Solid Mo particles 16 5-16 7 % o% Mo O 3, 85 % Solids 17 05 % % Mo O 3, 80 % Solids 17 51 % In the above table the third line viz -10 % Mo O 3, 85 % solids” means that the 55 coating paste was a solid particulate and liquid vehicle mixture in which the solid content is 85 % of which 10 % is molybdenum trioxide.
Molybdenum trioxide has a significant effect on shrinkage of the module when substituted for some of the molybdenum metal powder as seen from the above results 60 Example 3
The procedure of Example I was again followed with the exception that both the molybdenum trioxide content and the pressure during lamination were varied as indicated in the following Table:
Shrinkage 5 2500 Psi 3000 Psi Dummy (no paste) 17 56 % 17 4 % % , Mo O 3, 80 % Solids 17 54 % 17 39 % As seen from the results above, the 25 % Mo O 3 content paste substantially matches the shrinkage of the dummy 10 Example 4
The procedure of Example 1 was followed with the exception of the modification of the particle size of the molybdenum metal powder and the molybdenum trioxide The modification is shown in the following Table together with the shrinkage results: 15 Shrinkage Dummy (no paste) 1774 % 1/n 85/15 ( 2 8/1 8) 17 31-17 36 % 75/25 ( 2 8/1 8) 17 22 % 50/50 ( 2 8/1 8) 17 29 % 20 In the above table, the second line viz 85/15 ( 2 8/1 8) means that the coating paste was a solid particulate and liquid vehicle mixture in which the solid content is %’ of which 15 % is molydbenum powder having an average size of 1 8 microns, the average size of the molybdenum metal powder being 2 8 microns.
Example 5 25
The procedures of Example 1 were followed with the exception that a form of silk screen was utilized This consisted of a pattern formed in a photosensitive emulsion which was coated on a 325 mesh stainless steel mesh This mask is used for similar pattern forming purposes as etched metal or electroformed metal masks or stencils 30 The following is a tabulation of the results depending upon the thickness of the emulsion screen utilized:
Shrinkage Dummy (no paste) 1774 % Original Screen ( 2 8 mil) 17 0-17 25 % 35 Thin Screen ( 1 4 mil) 17 0-17 16 % There was no effect on shrinkage in using the various thicknesses of emulsion screens.
Example 1-5 show that the unmetallized dummy shrinkage was best matched by the use of precise percentages by weight of Mo O 3 with molybdenum metal 40 powder.
Examples 6-14
A four ceramic layer test specimen was utilized wherein the two middle layers had the above mentioned dense, substantially covering metallurgy pattern and the outside layers were two ceramic blanks The procedure of Example I was utilized 45 with the variations in vehicle type and percent of molybdenum trioxide as indicated in Table 111.
1,565,421 TABLE III
Percent Percent Mo O 3 in Solid solid Fired Vehicle Content content Paste Wt, Shrinkage 5 Example Type of paste of paste Grams Percent 6 18 6 7 1 80 0 1 5 17 7 8 1 80 15 1 6 18 1 9 1 80 25 1 6 18 3 10 1 80 33 1 5 18 4 11 1 80 50 1 5 18 3 12 2 80 0 1 4 17 8 13 2 80 10 1 4 18 2-18 3 14 2 80 20 1 1 18 2-18 3 15 The compositions of the two vehicles utilized are given as follows:
Vehicle Type 135, gelled linseed compound 2.5 % oleoyl sarkosine 10 % hydrogenated castor oil 20 28.9 %o inkovar AB 180 hydrocarbon resin 18.3 % Amsco 550 ink oil 5.3 % butyl carbitolacetate Percentages are by weight “Amsco” is a registered trade mark.
Vehicle Type 2 25 % N-50 ethyl cellulose % butyl carbitol acetate This series again shows that the unmetallized part shrinkage (Example 6) is approached as more Mo O 3 is used Example 11 did not shown the expected shrinkage increase compared to Example 10, and this is attributed to experimental 30 error Depending on the format, such a usage might be optimum at 20-33 % Mo O 3.
This effect occurs whether polar vehicle type 2, or non-polar vehicle type I was used.
Example 15
The shrinkage of the paste by itself was obtained by screening a dense pattern 35 on paper, drying it, and then measuring specific fiducials on the pattern The pattern was then fired in the same way as the multilayer ceramic, and the fired fiducials were remeasured The shrinkage was the difference between the dried and fired dimensions.
Paste Type Percentage Shrinkage 40 Pure Mo 13 5-14 % % Mo O 3 17 % % Mo O 3 21 % This confirms that the Mo O 3 addition substantially increases paste shrinkage, 45 without the presence of ceramic.
Example 16
The procedure of Example I was followed except that the dew point of the hydrogen gas in the sintering furnace was varied from 45 C to 55 C The modules comprising metallization patterns containing 25 % Mo O 3 was less effected by the 50 change in the firing ambient.
Paste Type Change in Shrinkage Pure Mo 1 % % Mo O 3 0 2 % Example 17 55
The procedure of Example I was followed except that the paste in the vias in the layers 2-5 were varied to examine the effect on the top surface via bulge, and 1,565,421 the presence of cracks between the top vias The vias were 0055 ” diameter on 010 ” centers.
Top Surface X-ray Paste in Layers 2-5 Cracks Stress Via Bulge Mo ( 85 % Solids) Many 40-60,000 psi 0010 ” 5 % Mo O 3 ( 80 % Solids) Very few 25,000 psi 0006 ” This shows that the presence of the Mo O 3 in the upper layers reduces surface cracks and bulging The stress in the upper vias is substantially reduced by the presence of Mo O 3.

Claims (8)

WHAT WE CLAIM IS: 10

1 A method of manufacturing an electrical device by applying a paste to the surface of an unfired or incompletely fired ceramic substrate in a predetermined pattern, causing or allowing the paste to dry off, and thereafter firing the ceramic substrate and paste to form a conductor from the paste, said method comprising fabricating the paste as a mix of a powdered, high conductivity metal and a 15 powdered metallic oxide of the metal in a liquid vehicle and selecting the relative proportions of powdered metal and powdered metallic oxide in the paste so that the percentage shrinkage of the paste that occurs during firing closely matches that of the ceramic substrate and more closely matches the percentage shrinkage of the ceramic substrate than that of a paste comprising only the powdered metal and not 20 containing the metallic oxide.

2 A method as claimed in claim 1, in which the relative proportion of metal to metallic oxide is in the ratio of between 1:1 and 9:1.

3 A method as claimed in claim 1 or claim 2, in which the metal is molybdenum, tungsten or palladium and the metallic oxide is respectively 25 molybdenum trioxide, tungsten oxide, or palladium oxide.

4 A method of manufacturing a ceramic multilayer circuit board comprising fabricating a metallic paste comprising a mix of a powdered metal and a powdered metallic oxide of the metal in a liquid vehicle and selecting the relative proportions of powdered metal and powdered metallic oxide in the paste so that the percentage 30 shrinkage of the paste that occurs during firing of the board closely matches that of a component ceramic layer of the board and more closely matches the percentage shrinkage of the ceramic layer than that of a paste comprising only the powdered metal and not containing the metallic oxide; forming a metallization pattern of the paste on the surface of a multiplicity of ceramic substrate layers; stacking the 35 ceramic layers; laminating the stack at a temperature and pressure sufficiently high to form a monolithic structure; firing the structure; and allowing or causing the fired structure to cool.

A method as claimed in claim 4, in which the stack is laminated at a temperature of from 800 C to 1000 C and at a pressure of more than 2500 pounds per 40 square inch.

6 A method as claimed in claim 4 or 5, in which the metallization pattern formed on the surface of at least one ceramic layer forming an intermediate layer in the stack comprises substantially the whole of the area of that surface to thereby form an internal conducting plane 45

7 A method of manufacturing a ceramic, multilayer circuit board for carrying semiconductor chips comprising applying a paste comprising a particulate mixture of a metal and a metallic oxide of the metal in the ratio of between 1:1 and 9:1 in a pattern onto an unfired ceramic layer; said metal having a high conductivity and a thermal expansion coefficient similar to that of the ceramic layer; drying said 50 pattern; stacking said coated ceramic layer with one or more other similar unfired ceramic layers to form the board structure: subjecting the stacked layers of ceramic to a pressure greater than about 2500 pounds per square inch; firing the ceramic stack to form a unitary board: and cooling the board to room temperature.

8 A method of claim 7, in which the metal is molybdenum, tungsten or 55 palladium and said metal oxide is molybdenum trioxide, tungsten oxide or palladium oxide.
I 1,565,421 9 1,565,421 9 9 A method of manufacturing a ceramic multilayer circuit board or module, which method is substantially as hereinbefore described with reference to Figure 1 of the accompanying drawings.
A ceramic multilayer circuit board or module or electrical device manufactured according to the method claimed in any one of claims I to 9 5 ALAN J LEWIS Chartered Patent Agent Agent for the Applicants Printed for Her Majesty’s Stationery Office, by the Courier Press, Leamington Spa, 1980 Published by The Patent Office, 25 Southampton Buildings, London WC 2 A IAY, from which copies may be obtained.

GB805/77A
1976-02-03
1977-01-10
Manufacture of electrical devices

Expired

GB1565421A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

US05/654,686

US4109377A
(en)

1976-02-03
1976-02-03
Method for preparing a multilayer ceramic

Publications (1)

Publication Number
Publication Date

GB1565421A
true

GB1565421A
(en)

1980-04-23

Family
ID=24625850
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB805/77A
Expired

GB1565421A
(en)

1976-02-03
1977-01-10
Manufacture of electrical devices

Country Status (6)

Country
Link

US
(1)

US4109377A
(en)

JP
(1)

JPS5295058A
(en)

CA
(1)

CA1078079A
(en)

DE
(1)

DE2703956C2
(en)

FR
(1)

FR2340288A1
(en)

GB
(1)

GB1565421A
(en)

Cited By (1)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

GB2233497A
(en)

1989-05-25
1991-01-09
American Tech Ceramics
Process for applying conductive terminations to ceramic components.

Families Citing this family (84)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US4388131A
(en)

1977-05-02
1983-06-14
Burroughs Corporation
Method of fabricating magnets

US4243710A
(en)

1978-12-06
1981-01-06
Ferro Corporation
Thermoplastic electrode ink for the manufacture of ceramic multi-layer capacitor

US4221047A
(en)

1979-03-23
1980-09-09
International Business Machines Corporation
Multilayered glass-ceramic substrate for mounting of semiconductor device

US4313262A
(en)

1979-12-17
1982-02-02
General Electric Company
Molybdenum substrate thick film circuit

US4355055A
(en)

1980-02-25
1982-10-19
E. I. Du Pont De Nemours And Company
Use of prolonged tack toners for the preparation of multilayer electric circuits

US4364100A
(en)

1980-04-24
1982-12-14
International Business Machines Corporation
Multi-layered metallized silicon matrix substrate

JPS5922385B2
(en)

1980-04-25
1984-05-26
日産自動車株式会社

Conductive paste for filling through holes in ceramic substrates

JPS6127242Y2
(en)

1980-04-30
1986-08-14

US4320438A
(en)

1980-05-15
1982-03-16
Cts Corporation
Multi-layer ceramic package

JPS5824037B2
(en)

1980-05-26
1983-05-18
富士通株式会社

Conductor ball arrangement method

US4302625A
(en)

1980-06-30
1981-11-24
International Business Machines Corp.
Multi-layer ceramic substrate

US4336088A
(en)

1980-06-30
1982-06-22
International Business Machines Corp.
Method of fabricating an improved multi-layer ceramic substrate

US4349862A
(en)

1980-08-11
1982-09-14
International Business Machines Corporation
Capacitive chip carrier and multilayer ceramic capacitors

FR2496341A1
(en)

1980-12-12
1982-06-18
Thomson Csf
Compact topological interconnection device – localises nodes and crossovers of complex circuit formed on single layer support with connections formed by metal strips

US4340618A
(en)

1981-03-20
1982-07-20
International Business Machines Corporation
Process for forming refractory metal layers on ceramic substrate

JPS57182971U
(en)

1981-05-14
1982-11-19

DE3147789A1
(en)

1981-12-03
1983-06-09
Brown, Boveri & Cie Ag, 6800 Mannheim
Power module and method of producing it

DE3147790A1
(en)

1981-12-03
1983-06-09
Brown, Boveri & Cie Ag, 6800 Mannheim
Power module and method of producing it

US4461077A
(en)

1982-10-04
1984-07-24
General Electric Ceramics, Inc.
Method for preparing ceramic articles having raised, selectively metallized electrical contact points

JPS5987893A
(en)

1982-11-12
1984-05-21
株式会社日立製作所
Circuit board, method of producing same and semiconductor device using same

DE3305687A1
(en)

1983-02-18
1984-08-23
Raymond E. San Diego Calif. Wiech jun.
Method for producing complex micro-circuit boards, micro-circuit substrates and micro-circuits, and substrates and micro-circuits produced according to the method

JPS6028296A
(en)

1983-07-27
1985-02-13
株式会社日立製作所
Ceramic multilayer printed circuit board

US4540621A
(en)

1983-07-29
1985-09-10
Eggerding Carl L
Dielectric substrates comprising cordierite and method of forming the same

US4546065A
(en)

1983-08-08
1985-10-08
International Business Machines Corporation
Process for forming a pattern of metallurgy on the top of a ceramic substrate

FR2556503B1
(en)

1983-12-08
1986-12-12
Eurofarad

ALUMINA INTERCONNECTION SUBSTRATE FOR ELECTRONIC COMPONENT

US4671928A
(en)

1984-04-26
1987-06-09
International Business Machines Corporation
Method of controlling the sintering of metal particles

US4562513A
(en)

1984-05-21
1985-12-31
International Business Machines Corporation
Process for forming a high density metallurgy system on a substrate and structure thereof

US4572754A
(en)

1984-05-21
1986-02-25
Ctx Corporation
Method of making an electrically insulative substrate

US4521449A
(en)

1984-05-21
1985-06-04
International Business Machines Corporation
Process for forming a high density metallurgy system on a substrate and structure thereof

JPS60250686A
(en)

1984-05-25
1985-12-11
日本碍子株式会社
Methd of producing ceramic circuit board

US4598107A
(en)

1984-06-25
1986-07-01
International Business Machines Corporation
Stepwise/ultimate density milling

US4657778A
(en)

1984-08-01
1987-04-14
Moran Peter L
Multilayer systems and their method of production

FR2571545B1
(en)

1984-10-05
1987-11-27
Thomson Csf

METHOD FOR MANUFACTURING A SUBSTRATE OF HYBRID CIRCUIT OF NON-PLANAR SHAPE, AND HYBRID NON-PLANAR CIRCUIT OBTAINED BY THIS PROCESS

US4581098A
(en)

1984-10-19
1986-04-08
International Business Machines Corporation
MLC green sheet process

US4645552A
(en)

1984-11-19
1987-02-24
Hughes Aircraft Company
Process for fabricating dimensionally stable interconnect boards

JPH0610927B2
(en)

1985-04-05
1994-02-09
株式会社日立製作所

Ceramic substrate manufacturing method

US4628406A
(en)

1985-05-20
1986-12-09
Tektronix, Inc.
Method of packaging integrated circuit chips, and integrated circuit package

JPH0714105B2
(en)

1986-05-19
1995-02-15
日本電装株式会社

Hybrid integrated circuit board and manufacturing method thereof

JPS62287658A
(en)

1986-06-06
1987-12-14
Hitachi Ltd
Ceramic multilayered circuit board and semiconductor module

US4763403A
(en)

1986-12-16
1988-08-16
Eastman Kodak Company
Method of making an electronic component

WO1988005959A1
(en)

1987-02-04
1988-08-11
Coors Porcelain Company
Ceramic substrate with conductively-filled vias and method for producing

JPS63240096A
(en)

1987-03-27
1988-10-05
富士通株式会社
Method of forming multilayer green sheet

US4837408A
(en)

1987-05-21
1989-06-06
Ngk Spark Plug Co., Ltd.
High density multilayer wiring board and the manufacturing thereof

US4970122A
(en)

1987-08-21
1990-11-13
Delco Electronics Corporation
Moisture sensor and method of fabrication thereof

US4846869A
(en)

1987-08-21
1989-07-11
Delco Electronics Corporation
Method of fabrication a curved glass sheet with a conductive oxide coating

US4797605A
(en)

1987-08-21
1989-01-10
Delco Electronics Corporation
Moisture sensor and method of fabrication thereof

DE3809350A1
(en)

1988-03-19
1989-09-28
Hoechst Ceram Tec Ag

METHOD FOR INCREASING THE COMBUSTION CONSTRUCTION OF CERAMIC FILM POWERS

DE68909665T2
(en)

1988-04-26
1994-02-10
Toto Ltd

Method of manufacturing dielectric ceramics for electrostatic chucks.

US5502889A
(en)

1988-06-10
1996-04-02
Sheldahl, Inc.
Method for electrically and mechanically connecting at least two conductive layers

US5170245A
(en)

1988-06-15
1992-12-08
International Business Machines Corp.
Semiconductor device having metallic interconnects formed by grit blasting

US4896464A
(en)

1988-06-15
1990-01-30
International Business Machines Corporation
Formation of metallic interconnects by grit blasting

US5224017A
(en)

1989-05-17
1993-06-29
The Charles Stark Draper Laboratory, Inc.
Composite heat transfer device

DE3923533A1
(en)

1989-07-15
1991-01-24
Diehl Gmbh & Co

ARRANGEMENT OF AN INTEGRATED CIRCUIT ON A CIRCUIT BOARD

JPH03125443A
(en)

1989-10-09
1991-05-28
Sharp Corp
Electrode of mounting board and liquid crystal display having the electrode of this mounting board

CA2023713A1
(en)

1989-10-23
1991-04-24
Mark S. O’brien
Gaseous isostatic lamination process

KR920002589B1
(en)

1990-03-30
1992-03-30
삼성코닝 주식회사
Manufacturing process for metal printer ceramic package

US5316989A
(en)

1991-05-08
1994-05-31
Gilbert James
Method for making a smooth-surface ceramic

DE4240812A1
(en)

1992-12-04
1994-06-09
Bosch Gmbh Robert

Heater arrangement for a sensor for determining components in gases

JP2858073B2
(en)

1992-12-28
1999-02-17
ティーディーケイ株式会社

Multilayer ceramic parts

US5727310A
(en)

1993-01-08
1998-03-17
Sheldahl, Inc.
Method of manufacturing a multilayer electronic circuit

JPH06296084A
(en)

1993-02-12
1994-10-21
Ngk Spark Plug Co Ltd
Thermal conductor of high conductivity, wiring board provided therewith and manufacture thereof

US5384681A
(en)

1993-03-01
1995-01-24
Toto Ltd.
Electrostatic chuck

US5428190A
(en)

1993-07-02
1995-06-27
Sheldahl, Inc.
Rigid-flex board with anisotropic interconnect and method of manufacture

US5459923A
(en)

1993-07-28
1995-10-24
E-Systems, Inc.
Method of marking hermetic packages for electrical device

DE4328353C2
(en)

1993-08-17
1996-06-05
Schulz Harder Juergen

Multi-layer substrate

DE4338706A1
(en)

1993-08-24
1995-05-04
Schulz Harder Juergen
Multilayer substrate

US5527998A
(en)

1993-10-22
1996-06-18
Sheldahl, Inc.
Flexible multilayer printed circuit boards and methods of manufacture

DE69530651T2
(en)

1994-10-31
2004-03-25
Tdk Corp.

Manufacturing process of ceramic electronic components and device for manufacturing

US5819652A
(en)

1994-12-14
1998-10-13
International Business Machines Corporation
Reduced cavity depth screening stencil

KR100244965B1
(en)

1997-08-12
2000-02-15
윤종용
Method for manufacturing printed circuit board(PCB) and ball grid array(BGA) package

US6016005A
(en)

1998-02-09
2000-01-18
Cellarosi; Mario J.
Multilayer, high density micro circuit module and method of manufacturing same

JP3669255B2
(en)

2000-09-19
2005-07-06
株式会社村田製作所

Method for producing ceramic multilayer substrate and green ceramic laminate

JP3807257B2
(en)

2001-06-25
2006-08-09
松下電器産業株式会社

Manufacturing method of ceramic parts

US7222419B2
(en)

2001-12-19
2007-05-29
Chung-Shan Institute Of Science And Technology
Method of fabricating a ceramic substrate with a thermal conductive plug of a multi-chip package

WO2003101166A1
(en)

2002-05-28
2003-12-04
Sumitomo Electric Industries, Ltd.
Aluminum nitride sintered compact having metallized layer and method for preparation thereof

KR20030074582A
(en)

2003-09-03
2003-09-19
학교법인 한국정보통신학원
Method for manufacturing multi chip module and multi chip module structure

SG157362A1
(en)

2004-11-04
2009-12-29
Microchips Inc
Compression and cold weld sealing methods and devices

US7649730B2
(en)

2007-03-20
2010-01-19
Avx Corporation
Wet electrolytic capacitor containing a plurality of thin powder-formed anodes

US7554792B2
(en)

2007-03-20
2009-06-30
Avx Corporation
Cathode coating for a wet electrolytic capacitor

US7460356B2
(en)

2007-03-20
2008-12-02
Avx Corporation
Neutral electrolyte for a wet electrolytic capacitor

DE102013012731A1
(en)

2013-08-01
2015-02-05
Krohne Messtechnik Gmbh

Process for the preparation of a gas converter and corresponding gas converter

CN106507603A
(en)

2016-12-30
2017-03-15
桂林电子科技大学
A kind of paster operation servicing unit of the rapid positioning operation for meeting ergonomics

US20210055253A1
(en)

2019-08-21
2021-02-25
Endress+Hauser Conducta Gmbh+Co. Kg
Method of manufacturing a sensor element and ion-selective electrode

CN110981549A
(en)

2019-12-09
2020-04-10
浙江安力能源有限公司
Production process of alumina ceramic

Family Cites Families (5)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3093490A
(en)

1960-04-08
1963-06-11
Eitel Mccullough Inc
Ceramic metalizing mixture and method of compounding it

US3838204A
(en)

1966-03-30
1974-09-24
Ibm
Multilayer circuits

US3561110A
(en)

1967-08-31
1971-02-09
Ibm
Method of making connections and conductive paths

US3815187A
(en)

1972-07-12
1974-06-11
Union Carbide Corp
Process for making ceramic capacitors

US3798762A
(en)

1972-08-14
1974-03-26
Us Army
Circuit board processing

1976

1976-02-03
US
US05/654,686
patent/US4109377A/en
not_active
Expired – Lifetime

1976-12-23
FR
FR7639690A
patent/FR2340288A1/en
active
Granted

1977

1977-01-10
GB
GB805/77A
patent/GB1565421A/en
not_active
Expired

1977-02-01
DE
DE2703956A
patent/DE2703956C2/en
not_active
Expired

1977-02-03
CA
CA271,025A
patent/CA1078079A/en
not_active
Expired

1977-02-03
JP
JP1032077A
patent/JPS5295058A/en
active
Granted

Cited By (1)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

GB2233497A
(en)

1989-05-25
1991-01-09
American Tech Ceramics
Process for applying conductive terminations to ceramic components.

Also Published As

Publication number
Publication date

FR2340288A1
(en)

1977-09-02

DE2703956C2
(en)

1986-01-02

JPS5615159B2
(en)

1981-04-08

JPS5295058A
(en)

1977-08-10

US4109377A
(en)

1978-08-29

FR2340288B1
(en)

1979-09-21

DE2703956A1
(en)

1977-08-04

CA1078079A
(en)

1980-05-20

Contact information