GB1566629A - Creation of Inventions and Patents with Artificial Intelligence

GB1566629A – Function generators
– Google Patents

GB1566629A – Function generators
– Google Patents
Function generators

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Publication number
GB1566629A

GB1566629A
GB3838677A
GB3838677A
GB1566629A
GB 1566629 A
GB1566629 A
GB 1566629A
GB 3838677 A
GB3838677 A
GB 3838677A
GB 3838677 A
GB3838677 A
GB 3838677A
GB 1566629 A
GB1566629 A
GB 1566629A
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United Kingdom
Prior art keywords
input
coupled
output
switch
signals
Prior art date
1976-09-14
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GB3838677A
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ILC Data Device Corp

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ILC Data Device Corp
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1976-09-14
Filing date
1977-09-14
Publication date
1980-05-08

1977-09-14
Application filed by ILC Data Device Corp
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ILC Data Device Corp

1980-05-08
Publication of GB1566629A
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patent/GB1566629A/en

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Classifications

H—ELECTRICITY

H03—ELECTRONIC CIRCUITRY

H03M—CODING; DECODING; CODE CONVERSION IN GENERAL

H03M1/00—Analogue/digital conversion; Digital/analogue conversion

H03M1/66—Digital/analogue converters

H03M1/665—Digital/analogue converters with intermediate conversion to phase of sinusoidal or similar periodical signals

Description

(54) IMPROVEMENTS IN OR RELATING TO
FUNCTION GENERATORS
(71) We, ILC-DATA DEVICE
CORPORATION, of Airport International
Plaza Bohemia, Long Island, New York 11716, United States of America, a corporation organized and existing under the laws of the State of Delaware, United
States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The present invention relates to function generators, which may be used with synchro to digital and digital to synchro converters.
A preferred generator includes a novel single ladder network or binary weighted ladder network utilized in a multiplexed fashion to combine sine and cosine functions or to generate sine and cosine functions respectively.
In digital to synchro converters a digital input, usually comprised of an bit binary word representing the angle 0, is converted to three analog outputs sin 0, sin (o+120 ) and sin (0+2400). Typically this is carried out by first converting from the digital input (8) into analog signals sin 0 and cos 0, conventionally referred to as a resolver outputs (hence digital to resolver) and then converting from sin o, cos 0 to sin 0, sin (8+120″) and sin (0+2400) hence (resolver to synchro).Since the present invention is concerned with the function generator for converting from digital (H) to resolver (sin 0, cos 0) the ensuing description, will for purposes of simplicity ignore the discussion of resolver (sin 0, cos 0) to synchro (sin 0, sin 0+1200), sin (0+2400) which techniques are also well known in the art.
The conventional approach for digital to resolver (D to R) conversion is to provide a pair of function generators for each conversion i.e. sin 0 and cos 0 each comprising two ladder networks and accompanying solid state switches for converting the digital inputs (0) and its complement 0 into sin 0 and cos 0, respectively. Each ladder network comprises a group of resistance elements weighted in accordance with the function to be generated. The number of resistance elements in each ladder network is a function of the desired resolution and accuracy of the function being generated.
The sin 0 and cos 0 functions are generated simultaneously and each function is created by switching selected ones of the weighted resistors into conduction to yield a resultant current whose magnitude represents sin 0 (or cos 0). Application of the current signal to an amplifier yields a voltage signal representing sin 0 (or cos 0). The nature of the relative networks is such that each resistance element represents a portion of the value of the function over the range of interest. By switching in the appropriate resistance elements it is thus possible to generate the proper current signal whose magnitude represents sin 0.
Although the above technique is satisfactory for present day applications, one very significant ever present objective in all such apparatus is the progressive capability towards miniaturization and increased accuracy of the device.
Since the functions sin 0 and cos 0 are complementary, and presuming identical ladder networks are provided for each function generator it should be noted that for each resistance element which is switched on in one of the function generators, the corresponding weighted resistance of the complementary ladder network is switched off.
It is thus possible to utilize a single resistor function generator network for generating both complementary functions, which, it is important to note, is capable of being used in both D to S (i.e. D to R and R to S) and S to D (i.e. S to R and R to D) converters.
However, it is important to provide switching means which, in addition to providing the desired switch function, does not degrade the accuracy of the generated signal. Thus the single ladder network utilizes a voltage controlled switching means which introduces virtually zero current (or at most negligible current) into the current path to prevent the introduction of error into the signal representing the generated function.
The preferred voltage controlled switches are complementary MOS (CMOS) integrated circuits. The switches are preferably pairs of switches whose inputs can be steered to a common terminal of their associated weighted resistor and whose outputs are respectively coupled to the “warping resistors” of the sin n and cos 0 outputs. The switches may be coupled in push-pull fashion. The digital data is presented to each switch with true outputs being coupled to one switch of each pair and the complement being coupled to the other switch of the pair.
The function generator may be used with equal success in S to D (i.e. S to R and R to
D) converters by coupling the signals representing sin A, cos A to the input of the function generator through appropriate “warping” resistors. The control signals to the switching circuits represent an angle B to select the binary weighted resistors whose outputs are connected in common. The digital input representing angle B modifies the analog signal sin A by the signal cos B and modifies the signal cos A by sin B forming the products sin A cos B and cos A sin B. These signals are summed to form a signal representing sin A cos B-cos A sin B which, in turn, equals, after amplification, an error signal E=sin (A-B). The signal E is converted into an analog voltage V proportional to (A-B), i.e.V (A-B). A voltage controlled oscillator generates a pulse output at a pulse rate which is a function of V, ie. Fvco (V). The pulses are accumulated by a binary up/down counter whose output stages are representative of the digital control signals for setting the function generator switches. When E=O, the count in the counter represents the angle A in digital (binary) form resulting in the desired S to D (ie. S to R and R to D) conversion.
The function generator may be a hybrid type wherein only selected binary stages of the single function generator are multiplexed to obtain the desired conversion (S to D or D to S). Typically the most significant binary positions of a function generator are represented by weighted resistance elements of low ohmic magnitude. In applications where extremely high accuracy is a very important objective, to avoid the small resistance which may be introduced into the ladder circuit by the voltage controlled switches, selected ones of the most significant bits may be implemented as two separate ladder networks for sin 0 and cos 0. The remaining digit positions which are of greater ohmic magnitude may then be implemented in the single function generator.It should be noted that the need for the hybrid approach is dictated by the short comings of state-ofthe-art voltage controlled switches (when great accuracy is mandated) since ideally a voltage controlled switch should not introduce any resistance into the ladder circuit.
It is therefore one object of the present invention to provide a novel function generator for use in both S to D and D to S converters and which is utilized in a multiplexed manner to significantly reduce the number of components required in the converter without reducing accuracy and/or functional capabilities.
Still another object of the invention is to provide a converter (S to D or D to S) of the type described and which employs voltage controlled switch means capable of providing the desired multiplexed operation without introducing an error into the output signal developed by the function generator.
The above, as well as the other objects of the invention, will become apparent when reading the accompanying description and drawings, in which:
Figure 1 is a block diagram showing a function generator designed in accordance with the principles of the present invention and utilized in a D to S (ie. D to R) converter.
Figure la shows a CMOS type switch which may be utilized in the circuitry of
Figures 1 and 2.
Figure 2 shows a block diagram of the single function generator of the present invention employed in an S to D (ie. R to D) converter.
Figure 3 is a block diagram showing a hybrid function generator which may be employed in D to S or S to D converters.
Figure 1 shows a D to R converter 10 comprising an operational amplifier 11. A reference carrier signal is coupled to input Il a as is conventional in such converters.
The output 1 lb is coupled to function generator 12 contained within the dotted rectangle as shown and is comprised of a plurality of binary weighted resistors R, 2R.
4R, 2″R, where n represents the number of digit positions in the binary representation angle 0 and may be comprised of ten binary bits, for example. Although techniques in which only a quadrant or an octant of a function sin 0 (or cos 0) may be employed to greatly improve synchro accuracy, these techniques will not be considered in describing the principles of the present invention, it being understood that the present invention may be employed with equal success in converters using the implementation required for example, in quadrant or octant switched converters.
The left-hand terminal of each resistor R–2″R is coupled in common to output 11 b while each right-hand terminal is coupled to the input of an associated switching circuit 13-I to 13-n. Each switch is comprised of an input, for example 13-la, and two outputs 13–lb and 13-lc and a control input 13-ld which receives the digital binary signal associated with the weighted resistor coupled to the input of the switch 13.
The outputs 13-lb through 13-nb are coupled in common to “warping” resistor
14 while outputs l3-lc through 13-nc are coupled in common to “warping” resistor
15. The outputs at the right-hand ends of 14 and 15 are current signals whose magnitudes represent sin 0 and cos S. By coupling the outputs of resistors 14 and 15 to operational amplifiers 16 and 17, the signals developed at 16a and 17a are voltage signals representing sin o and cos 0.
The switches 13 are of the voltage controlled type and, as shown in schematic fashion, are comprised of a switch arm, for example 13-le movable between outputs 13–lb and 13-Ic dependent upon the binary digital signal applied to the control input 13–ld. It should be noted that the digital control signal, when binary “ONE” controls switch arm 13-le for example,
couples output 13–lb to resistor R leaving output 13-Ic unconnected. Conversely, when the digital control input is binary
“ZERO”, arm 13-le connects input 13
la to output 13–le leaving output 13–lb unconnected.As a result the current signals through resistors 14 and 15 provide an output whose magnitudes respectively represent sin 0 and cos 0 through the use of only one function generator.
The switch pairs are preferably implemented by CMOS circuitry providing voltage controlled switching to establish the desired circuit connections between input (13-la) and a selected one of the outputs (13-lb or 13–lc). Some preferred circuits which may be employed are the CMOS multiplexors manufactured by RCA and identified by model MOS CD4053A and
CD4053B. As shown in Figure la, the digital inputs 17-I through 17-3 receive the digital control signals for three stages. These inputs are applied to level converting circuits 18, 19 and 20.The outputs of circuits 18-20 respectively are connected to an associated binary-to-one-of-two decoders 21, 22 and 23, whose outputs 21a and 21b for example, are each high exclusive of the another and dependent upon the binary state of the input signal from circuit 18.
Outputs 21a and 21b are respectively coupled to the control inputs 24a and 25a, for example, of transistor gates 24 and 25. In the case of a D to S converter the digital inputs are coupled to inputs 17-1 through 17-3. The weighted resistors of the ladder network are coupled to input terminals 2628. Terminals 29, 31 and 33 are coupled in common to the “warping” resistor 14 while terminals 30, 32 and 34 are coupled in common to “warping” resistor 15.
When employed in an S to D converter (to be more fully described) the terminals 26-28 are coupled in common to a reference input, the terminals 29, 31 and 33 are coupled to the input sin 0 and the terminals 30, 32 and 34 receive the input cos 0, while the desired digital output is developed across the control inputs 17-1 through 17-3.
The number of integrated circuit chips employed is dependent upon the number of digital bits. Although Figure la shows one preferred type of voltage controlled switch, it should be understood that any solid state switch having similar operating characteristics may be used. The voltage controlled input terminal permits use of the switch of the type described without the introduction of control signal currents into the main signal current branches of the
switch. For example, in a conventional
current controlled transistor device, the
application of a current control signal upon the base, creates either a base-to-emitter or base to collector current path which alters the emitter-to-collector (or collector-to
emitter) current thereby affecting the
current for that branch of the ladder
network coupled to the switching transistor.
Use of the CMOS transistor switching
circuitry described introduces zero (or at
most negligible) current into the emitter
collector circuit path from the base when a
voltage control signal is applied to the base.
Figure 2 shows the circuitry for a S to D
converter 40 in which the signals sin A and
cos A are respectively applied through
“warping” resistors 41 and 42 respectively.
The opposite terminals of resistors 41 and 42
are connected in common to the respective
inputs 43-la through 43-na and 43–lb through 43-nb respectively of the voltage
controlled switching circuits 43-1 through 43-n. Each of these switching circuits is
provided with a digital controlled input 43 ld through 43-nd, each of which is
respectively adapted to receive one of the
binary digital input control signals.
The outputs of the switching circuits such as, for example the outputs 43-lc, 432c,…, 43-nc, are respectively coupled to a weighted resistor Rl, R2,…, Rn, each of which has predetermined “weighted” value as was described herein above in order to create the function generator ladder network.
The opposite terminals of the weighted resistors are all connected in common to the input of operational amplifier 45. The signal created in the common line leading to the input of operational amplifier 45 develops a signal whose current magnitude is a function of sin A cosin B minus cosin A sin
B formed as a result of the fact that the input signal sin A is modified by the digital input and weighted resistors by cosin B to form the product thereof and similarly wherein cosin A applied through warping resistor 142 is modified in accordance with the digital input by sin B to form the product cosin A sin B.
The current signal is applied to operational amplifier 45 to form a voltage signal at output 45a. As is well known, the trigonometric expression sin A cosin B minus cosin A sin B is equal to sin (A-B).
This signal is created in voltage form, at output 45a and, as will be more clearly understood hereinbelow, is commonly defined as the error signal E.
In the instance where the S to D converter utilizes an AC carrier signal, the output 45a is coupled through a demodulator circuit 46 to remove the carrier signal. The error signal E is then applied to an error processing circuit 47 which generates a DC voltage level V proportional to the difference between angle A and angle B. This DC voltage is applied to voltage controlled oscillator 48 which functions to generate output pulses at a pulse rate which is dependent upon the magnitude of the DC signal applied to input 48a. The output pulses are applied to input 49a of digital binary counter 50 having a plurality of stages equal at least to the number of bits in the digital representation of the angle data.The operation of the circuitry of Figure 2 is as follows:
Let it be assumed that there is no signal developed at this point in time for the angle
B and therefore the angle B would be assumed to be 00. In this instance, the error signal E would be quite large, causing the voltage control oscillator 48 to develop a large number of pulses representative of the error signal. These pulses are accumulated in counter 50 which in turn develops a digital binary output applied to the controls 43–ld through 43-nd to establish the modifying values cosin B and sin B to form the products as was described hereinabove.
In this respect, the angle B increases significantly to create a smaller error voltage value which reduces the number of pulses developed by voltage controlled oscillator 48 until ultimately the error control signal drops to 0 in which case the voltage controlled oscillator 48 ceases developing pulses and the processing operation is thereby complete, the desired digital representation of the angle A appearing at the output terminals of counter 50 (it being understood that this digital representation is the angle B and that B is now equal to A).
The warping resistors 41 and 42 (Figure 3) of the S to D converter and the warping resistors 14 and 15 shown in Figure 1 for the
D to S converter are utilized to modify an otherwise linear representation of sin and cosin into a non-linear function to thereby more closely simulate the sin and cosin waveforms and thus provide output signals which are much close in wave shape to the ideal sin and cosin waveforms.
In certain applications wherein a very high degree of accuracy is required, it has been found that, for the most significant bits of the binary weighted network (which correspondingly have the smaller weighted resistance values) the bipolar CMOS transistor switches described above introduce a very small but never-the-less finite resistance into the particular branch of the ladder circuit in which they are connected. In order to greatly improve the accuracy of such converters, and in the event that it is not possible to provide a switching transistor which ideally introduces “0” resistance into its associated ladder network branch, the hybrid circuit 60 of Figure 3 may be employed.As shown therein, circuit 60 is comprised of a single function generator circuit 61 of the type described herein above and including a weighted binary network with accompanying solid state switching as was described previously.
In addition thereto, the circuitry scheme of Figure 3 further comprises first and second weighted resistor networks 62 and 63 each of which cooperate with transistorized switching arrays 64 and 65 respectively, controlled by input signals from the most significant bit positions of the binary data word to control the conduction or nonconduction of the transistors coupled thereto for the purpose of selectively including or/and excluding those weighted resistors of the ladder network which are required to form the current signal whose magnitude is a function of sin 0 or cosin 0.
Each transistor switch is of the type shown as switch 66 which is an NPN type transistor having the characteristics of low ON resistance and is of the bi-polar transistor switch type. The value of using such transistor switches resides in the fact that the ohmic values of the resistor elements in the ladder network for forming the most significant bit contributions are relatively small in magnitude and hence any resistance added to that particular branch of the ladder network will affect the desired accuracy of the converter.
Thus the circuit paths forming the most significant bit positions of the ladder network are separate and independent as shown in Figure 3 and are coupled with appropriate reference inputs REFI and
REF2 and provide the contribution to the current signals forming sin 0 and cosin 0 for the most significant bit positions. The remaining or least significant bit positions are handled by the single function generator network which is of the type described for example in connection with Figure 1 and which develops at output 61 a those contributions of the lesser significant bits which are summed with the current signals of the more significant bits in common output 67 to provide a resultant current signal whose magnitude represents sin 0.
Similarly, output 61 b provides a current magnitude which combines with the current magnitude of the most significant bits in output line 68 to similarly provide a current signal whose magnitude is representative of cosin 0.
Although not shown for purpose of simplicity, it should be understood that the same hybrid techniques of Figure 3 employed in a D to S converter may be used with equal success in S to D converters.
WHAT WE CLAIM IS:
1. Function generator means for converting a value represented by a binary word into a pair of complementary analog signals functionally related to said value and complementary to one another comprising:
a binary weighted ladder network comprised of a plurality of branches each having a resistance element of a predetermined weighted value;
a first end terminal of each branch being coupled in common to an input line;
a reference signal source being coupled to said input line;
first and second output lines; the generator means being characterized by having a plurality of switch means each having an input, first and second outputs and a control terminal adapted to couple said switch input to one of said switch outputs when a first binary signal level is coupled to said control terminal and adapted to couple said input to the remaining one of said switch outputs when the opposite binary signal level is applied to said control terminal;
each of said switch inputs being associated with one of said branches and being coupled to the remaining end terminal of its associated branch;
the first and second outputs of each switch being respectively connected to said first and second output lines whereby the outputs of said first and second output lines generate signals whose current magnitude is a function of the input value and wherein said signals are complementary to one another.
2. The generator means of Claim 1 characterized by having the signals S and S on said first and second output lines related to said input value A such that S1=f, (A) and S2=f2 (A) and whereby d[f2(A)i
fa(A)= dt
3. The generator means of claim 2 wherein S,=sin A and S2=cos A.
4. The function generator means of Claim
I further characterized in that each switch means further comprises a pair of transistor switch means having low ON impedance and high input impedance so that a voltage control level selectively applied to the control electrode introduces negligible current into the collector-emitter circuit.
5. The generator means of claim 4 characterized in that said pair of transistors are coupled in a single-pole double throw configuration for selectively coupling the branch resistor coupled to the switch input (the single-pole to one of the first and second switch outputs (double-throw).
6. The generator means of claim 1 characterized in that said analog signals are non-linear and further comprising a warping resistor series coupled in each of said first and second output lines for more closely simulating the non-linear functions.
7. Function generator means for converting first and second input signal values related to one another in a complementary fashion into a binary digital output level which level is a function of both said first and second signals;
a binary weighted ladder network comprised of a plurality of branches each having a resistance element of a predetermined weighted value;
a first end terminal of each branch being
coupled in common to an output line;
first and second input lines each being
respectively coupled to receive said first and
second input signals; ;
said function generator being
characterized by a plurality of switch means
each having first and second inputs, an
output, and a control terminal and being
adapted to couple one of said switch means
inputs to said switch means output when a first binary signal level is coupled to said
control terminal and adapted to couple the
other one of said switch means inputs to said
switch means output when the opposite
binary signal level is applied to said control terminal;
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (9)

**WARNING** start of CLMS field may overlap end of DESC **. ladder network will affect the desired accuracy of the converter. Thus the circuit paths forming the most significant bit positions of the ladder network are separate and independent as shown in Figure 3 and are coupled with appropriate reference inputs REFI and REF2 and provide the contribution to the current signals forming sin 0 and cosin 0 for the most significant bit positions. The remaining or least significant bit positions are handled by the single function generator network which is of the type described for example in connection with Figure 1 and which develops at output 61 a those contributions of the lesser significant bits which are summed with the current signals of the more significant bits in common output 67 to provide a resultant current signal whose magnitude represents sin 0. Similarly, output 61 b provides a current magnitude which combines with the current magnitude of the most significant bits in output line 68 to similarly provide a current signal whose magnitude is representative of cosin 0. Although not shown for purpose of simplicity, it should be understood that the same hybrid techniques of Figure 3 employed in a D to S converter may be used with equal success in S to D converters. WHAT WE CLAIM IS:

1. Function generator means for converting a value represented by a binary word into a pair of complementary analog signals functionally related to said value and complementary to one another comprising:
a binary weighted ladder network comprised of a plurality of branches each having a resistance element of a predetermined weighted value;
a first end terminal of each branch being coupled in common to an input line;
a reference signal source being coupled to said input line;
first and second output lines; the generator means being characterized by having a plurality of switch means each having an input, first and second outputs and a control terminal adapted to couple said switch input to one of said switch outputs when a first binary signal level is coupled to said control terminal and adapted to couple said input to the remaining one of said switch outputs when the opposite binary signal level is applied to said control terminal;
each of said switch inputs being associated with one of said branches and being coupled to the remaining end terminal of its associated branch;
the first and second outputs of each switch being respectively connected to said first and second output lines whereby the outputs of said first and second output lines generate signals whose current magnitude is a function of the input value and wherein said signals are complementary to one another.

2. The generator means of Claim 1 characterized by having the signals S and S on said first and second output lines related to said input value A such that S1=f, (A) and S2=f2 (A) and whereby d[f2(A)i
fa(A)= dt

3. The generator means of claim 2 wherein S,=sin A and S2=cos A.

4. The function generator means of Claim
I further characterized in that each switch means further comprises a pair of transistor switch means having low ON impedance and high input impedance so that a voltage control level selectively applied to the control electrode introduces negligible current into the collector-emitter circuit.

5. The generator means of claim 4 characterized in that said pair of transistors are coupled in a single-pole double throw configuration for selectively coupling the branch resistor coupled to the switch input (the single-pole to one of the first and second switch outputs (double-throw).

6. The generator means of claim 1 characterized in that said analog signals are non-linear and further comprising a warping resistor series coupled in each of said first and second output lines for more closely simulating the non-linear functions.

7. Function generator means for converting first and second input signal values related to one another in a complementary fashion into a binary digital output level which level is a function of both said first and second signals;
a binary weighted ladder network comprised of a plurality of branches each having a resistance element of a predetermined weighted value;
a first end terminal of each branch being
coupled in common to an output line;
first and second input lines each being
respectively coupled to receive said first and
second input signals;;
said function generator being
characterized by a plurality of switch means
each having first and second inputs, an
output, and a control terminal and being
adapted to couple one of said switch means
inputs to said switch means output when a first binary signal level is coupled to said
control terminal and adapted to couple the
other one of said switch means inputs to said
switch means output when the opposite
binary signal level is applied to said control terminal;
each of said switch means outputs being associated with one of said branches and being coupled to the remaining end terminal of its associated branch;
the first and second inputs of each switch means being respectively connected to receive said first and second input signals; said control terminals being adapted to receive the bits of a binary word representing the desired output value whereby the switch means connect selective ones of said branches in said ladder network to operate upon said input signals so that the branch currents coupled to said output line collectively generate an error signal in said output line whose magnitude is zero when a predetermined binary word value is applied to said control terminals.

8. The generator means of claim 7 further characterized in that input signals are represented by S, and S2 where said binary digital word represents a value A such that S1=f1 (A); S2=f2 (A) and d(f2(A))
f,(A)=
dt

9. A function generator substantially as hereinbefore described with reference to any one of the embodiments illustrated in the accompanying drawings.

GB3838677A
1976-09-14
1977-09-14
Function generators

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GB1566629A
(en)

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US72311276A

1976-09-14
1976-09-14

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GB1566629A
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1980-05-08

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1976-09-14
1977-09-14
Function generators

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JPS5359449A
(en)

DE
(1)

DE2741454A1
(en)

FR
(1)

FR2364508A1
(en)

GB
(1)

GB1566629A
(en)

NL
(1)

NL7710071A
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1977

1977-09-14
GB
GB3838677A
patent/GB1566629A/en
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1977-09-14
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NL7710071A
patent/NL7710071A/en
not_active
Application Discontinuation

1977-09-14
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patent/JPS5359449A/en
active
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1977-09-14
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patent/DE2741454A1/en
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1977-09-15
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1978-04-20

FR2364508B3
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1978-03-16

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1978-05-29

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1978-04-07

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