GB1566947A - Creation of Inventions and Patents with Artificial Intelligence

GB1566947A – Signal subtraction systems
– Google Patents

GB1566947A – Signal subtraction systems
– Google Patents
Signal subtraction systems

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Publication number
GB1566947A

GB1566947A
GB38588/77A
GB3858877A
GB1566947A
GB 1566947 A
GB1566947 A
GB 1566947A
GB 38588/77 A
GB38588/77 A
GB 38588/77A
GB 3858877 A
GB3858877 A
GB 3858877A
GB 1566947 A
GB1566947 A
GB 1566947A
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United Kingdom
Prior art keywords
charge
electrode
potential
electrodes
signal
Prior art date
1976-09-15
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB38588/77A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Raytheon Co

Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1976-09-15
Filing date
1977-09-15
Publication date
1980-05-08

1977-09-15
Application filed by Hughes Aircraft Co
filed
Critical
Hughes Aircraft Co

1980-05-08
Publication of GB1566947A
publication
Critical
patent/GB1566947A/en

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Expired
legal-status
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238000002955
isolation
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claims
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Classifications

G—PHYSICS

G11—INFORMATION STORAGE

G11C—STATIC STORES

G11C27/00—Electric analogue stores, e.g. for storing instantaneous values

G11C27/04—Shift registers

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06G—ANALOGUE COMPUTERS

G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities

G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers

G06G7/14—Arrangements for performing computing operations, e.g. operational amplifiers for addition or subtraction

Description

(54) IMPROVEMENTS RELATING TO SIGNAL SUBTRACTION
SYSTEMS
(71) We, HUGHES AIRCRAFT
COMPANY, a corporation organized and existing under the laws of the State of
Delaware, United States of America, of
Centinela and Teale Street, Culver City,
State of California, United States of
America, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed to be particularly described in and by the following statement:- This invention concerns improvements relating to signal subtraction systems and particularly to signal subtraction systems utilizing charge transfer devices.
Conventionally, in order to provide a difference or subtraction output function by use of charge transfer devices such as a charge coupled device (CCD), an operational amplifier and a sample and hold circuit were required. However, the latter has typically 60 db common mode error for precision large size and high power operational amplifiers and requires considerable space and heat dissipation. A system utilizing charge transfer device techniques that would provide a difference or subtraction from charges without requiring external circuitry would be a substantial advantage to the art.
According to the invention there is provided a signal subtraction system comprising: a charge transfer device having a substrate provided with a charge transfer channel, electrodes for defining potential wells in said channel, means for transferring charge between said potential wells; means operable selectively to clamp or to float the potential of one of said potential-well defining electrodes; and charge storage means associated with said one electrode, such as to be decremented and incremented when the potential well associated with said one electrode is decremented and incremented respectively by charge transfer therefrom and thereto; the arrangement being such that, in operation, with a charge
Qn-1 in the potential well associated with said one electrode and with a charge Qn in the preceding potential well, clamping of said one electrode to a predetermined potential and subsequent floating thereof sets a predetermined charge in said storage means, and subsequent transfer of the charge Qn 1 out of the potential well associated with said one electrode followed by transfer of the charge Qn in to the same potential well, results in the charge in said storage means being representative of the difference between Qn and Qn 1 As is explained hereinafter, the invention provides in one embodiment a nondestructive charge subtraction system for charge coupled devices (CCD) in which a floating electrode is clamped in the presence of a first charge so that when the first charge leaves the potential well and a second charge enters, the signal sensed is representative of the difference between the first and second charges with excellent common mode rejection, high bandwidth and low power. The floating electrode, which is utilized as the output device, is electrically clamped to a reference voltage and then unclamped when a first charge Q-1 is beneath it in a storage well. After Q-1 is clocked out of this well, a voltage equal to its native value is stored (preferably in the nodal capacitance provided by the electrodes and other structure of the CCD) and when the subsequent charge Qn is clocked into the potential well, the voltage output sensed is a function of (QnQn 1) This embodiment of a subtraction system in accordance with the invention allows not only subtraction of adjacent charges along a channel but subtraction of charges separated by one or more isolation bit or bits and subtraction of selected charges along a stream of charges passing along a
CCD channel. Thus, by properly controlling the clocking of the reset clamp on selected
CCD clock periods and observing on intermediate periods, selective difference signals may be obtained.
By virtue of its ability to compare signal values with excellent common mode rejection, the invention finds particularly useful application in moving target indication systems where the need arises to sense moving targets in a scene having a substantially fixed or non-moving background.
In order that the invention might be clearly understood, a number of exemplary embodiments thereof will hereinafter be described with reference to the accompanying drawings wherein like reference numerals indicate like or corresponding parts throughout the various figures. In the drawings: Figure 1 is a schematic cross-section view of a portion of a p-channel CCD signal subtractor in accordance with the invention:
Figure la is a schematic plan view showing the electrodes of the CCD of
Figure 1;
Figure 2 is a schematic diagram of waveforms of voltage or signal charge as a function of time for explaining the operation of the system of Figure 1;
Figures 3a to 3c are schematic diagrams showing the potential configuration established in the system of Figure 1 for three time conditions and showing the movement of the charge packets from wellto-well;
Figure 4a is a schematic diagram of a portion of a CCD in accordance with the invention for three operating times and
Figure 4b is a schematic diagram showing the surface potential profiles for the three time conditions and the movement of the charge packets from well-to-well;
Figure 5 is a schematic circuit diagram for explaining the capacitances present in the
CCD of Figure 1 and their function during the subtraction process;
Figure 6 is a schematic diagram of waveforms of voltage and locations of charge as a function of time for further explaining continuous subtraction or differencing in the system of Figure 1;
Figure 7 is a schematic diagram of waveforms of voltage as a function of time for explaining the selective differencing in the system of Figure 1; Figure 8 is a schematic diagram of waveforms of voltage as a function of time for explaining the operation of the system of
Figure 1 in which an isolation bit is provided between signal charges;
Figure 9 is a schematic block diagram showing an illustrative arrangement for providing the 6 and fSET pulses required for operation of the system of Figure 1;
Figure 10 is a schematic diagram showing charge subtraction in a three phase CCD structure;
Figure 10a is a schematic diagram showing the surface potential profile for three time conditions in the structure of
Figure 10; and
Figure 11 is a schematic diagram of waveforms of voltage as a function of time for explaining the operation of the three phase arrangement of Figure 10.
Referring first to Figure 1, a CCD (charge coupled device) channel is shown in crosssection, it being understood that the electrodes may have a width for example of approximately five times the length of each electrode in the direction along the channel as can be seen in Figure la. A substrate 10, may for example be of an n type semiconductor and the substrate material for illustrative purposes has a +5v reference voltage from a source 12 applied to a conductor plate 14 at the bottom thereof. A thin oxide material 16 is deposited on top of the substrate 10 and includes both buried and surface electrodes through which potentials are applied to move charges from left to right from one potential well to another. It is to be understood that the principles of the invention are equally applicable to any suitable charge transfer electrode structures and are not limited to the illustrated buried structure. The charges are entered into the channel by any suitable circuitry as well known in the art at the input to the channel and a p+ diffusion region is shown in Fig. la as the input structure 17 to form a p channel CCD.
Suitable n+ channel stops 19 and 21 are provided at the edge of the substrate 10 as shown in Fig. Ia to retain the charges within the channel. This example of the invention is illustrated with a single phase driving system using a four phase structure but it is to be understood that it is equally applicable to other types of suitable driving arrangements that move the charge along the channel. A , signal from a suitable source 20 is applied through a lead 22 to electrodes such as 25, 37, 27, 38 and a 02 DC signal is applied from a suitable source 30 through a lead 32 to electrodes 24, 36, 26, 28, and 39. A resettable floating electrode 42 which is utilized for read-out is coupled through a lead 44 to a source follower circuit 46 indicated as a FET 48 with the lead 44 coupled to the control electrode and with the other electrodes coupled between suitable sources of potential and current to provide a signal Vout to an output lead 50. A clamp voltage -V is applied from a source 54 through a FET 56 to the lead 44 to establish the reference potential and to allow the subtraction circuit to operate. The timing of the FET 56 is controlled from a XSET source 60 which clamps the floating electrode 42 in the presence of the first charge of the subtraction process in a well at that position. The capacitance associated with the lead 44 is shown by a dotted capacitor Ct which includes the capacitance of the amplifier stage 46 and stray capacitances Ca, the series capacitance of the oxide Cox and the voltage dependant depletion capacitance Cd. It is to be noted that the surface electrodes may in some arrangements be less in width as shown in
Figure 1 such as approximately threefourths of the width of the buried electrodes.
Referring now also to Figure L, #, is shown by a waveform 64 and operates in conjunction with XSET of waveform 66 and the )2 DC signal to move the charges along the channel. At a time t, a signal charge Qn-1 shown along a line of charges 68 is in the sense well under the electrode 42 as shown in Figure 3a, and the XSET pulse of the waveform 66 is applied to the gate of
MOSFET switch 56 to establish the surface potential of the charge Qn-1 in addition to establishing the well. When the SET pulse of the waveform 66 returns to its OFF potential prior to the pulse of the waveform 64, the lead 44 is in a floating condition and the capacitance Ct assumes the charge VC,.
At a time t2 the j1 pulse of the waveform 64 is applied to surface electrodes 25 and 27 and to buried electrodes 37 and 38 and the charge Q-1 is transferred to a subsequent well as shown in Figure 3b.
Since Q-1 charge is transferred from beneath the floating electrode 42, a corresponding charge must be removed from Ct for charge equalization. Thus, at time t2 the voltage on lead 44 indicated as
V44 in Figure 2 is V(Qn~1)/Ct When the f, pulse of the waveform 64 is terminated, charge Qn is shifted into the well under the electrode 42. At time t3 as shown in Figure 3c the voltage on the capacitance Ct is therefore Qn-1 Qn
V- + Ct Ct which is a difference signal and may be read out during the period bracketed in Figure 2.
Thus, by storing the voltage -Qn-iict of the previous charge on the electrode capacitance, when the charge Qn enters the well under floating electrode 42 a difference signal is provided with a very small common mode rejection since for Qn=Qn-1 the output is substantially independent of Qn.
Similarly, at time t4 with the charge Qn in the wel under the electrode 42, the SET pulse of the waveform 66 is applied to establish the surface potential in the presence of the charge qn under electrode 42 and in response thereto a voltage
Qn
Ct is effectively stored in the capacitance Ct. In response to 0, of the waveform 64 at time t5 the charge Qn is removed from the well under the electrode 42 and at time t6 the charge Qn+iict is transferred to the well under the electrode 42 with the readout voltage being Qn.+1 Qn
V+
Ct Ct Thus, it can be seen that signal subtraction of adjacent signals is provided with the CCd channel structure and without the requirement of a differential amplifier.
For further explaining the operation, reference is now made to Figs. 4a and 4b as well as to Figs. 1 and 2 with a condition at time t1 showing the charge Qn-1 in the sense well formed under the electrode 42 with the voltage V from the SET pulse of the waveform 66 establishing the surface potential of the charge. At time t2 the
charge Q-1 is removed from beneath the
electrode 42 and the voltage
Qn-1
V
Ct
is stored in the capacitance Ct and
maintained on the lead 44. At time t3 the
next charge Qn enters the potential well
under the electrode 42 and the difference voltage on the lead 44 is Qn-1 Qn
V – + Ct Ct
The effective bottom of a CCD potential well is defined by the voltage on the electrode. Since the electrode voltage changes on a floating electrode as charge is added or removed from the potential well, the bottom of the well also changes in response thereto. This change of the bottom of the potential well has a small affect on dynamic range because normally the capacitance Ca is relatively large compared to the capacitance Cd. In the illustrated example of Figs. 4a and 4b, the carriers are holes so that at time t2 the bottom of the well 120 is slightly lower than the level 110 at time t, since the electrode potential itself has changed by Qn-1/ct. At time t3 since Qn is assumed to be greater than Qn-1 the bottom of the well 130 is slightly above the level 110 at time t1.
Referring also to Fig. 5, when the switch 56 is closed, current establishes -10 volts on the common node 44 of C a and COX. When this switch 56 is opened and the node 44 is floating, current flows through Ca and COX to store a voltage change representative of -Qn-1 during the time that the charge is leaving the well under the electrode 42.
When the charge Qn enters the well at times between t2 and t3, current flows through Ca and Ccx to store a voltage change representative of +Qn thus providing the difference voltage on the lead 44.
Referring now to Fig. 6, the 01 pulses of waveform 80 are shown relative to the #SET pulses of waveform 82 to provide a difference voltage Vout as shown by a waveform 84. It can be seen that the #SET pulse always precedes the 01 pulse and a difference voltage may be read after each 6, pulse such as difference voltages
Qn-Qn-1 Ct and Qn+1 Qn Ct
assuming that V which is substantially a bias
voltage is at 0 volts. For V to be equal to 0 volts the substrate may be at-15 volts and
the clock pulses vary from +10 volts to -10 volts. During the period of the pulses 0, of
the waveform 80, no charge is present under
the electrode 42 since there is no potential
minimum. Thus, it can be seen that, if
desired, continous differences can be
obtained of a sequence of signal charges, in
accordance with the system of the
invention.
Referring now to Fig. 7, a timing arrangement is shown in which a first charge is subtracted from a selected charge or selected charges along a sequence of charges passing along the channel. The #, pulses of a waveform 88 are shown with the voltage from the charge that is present under the electrode 42 being indicated and the fSET pulse of a waveform 90 is illustrated with a first pulse only occurring prior to the first sX, pulse when the charge Q-1 is in the well under the electrode 42. The second fret pulse of the waveform 90 occurs when the charge Qn-4 is in the well under the electrode 42 to establish a new potential reference in the capacitance Ct. During each of the reading periods between the two
SET pulses, the charge on Ct has the charge subtracted therefrom with this operation continuing until the second #SET pulse of the waveform 90. Thus, any value may be selected to be subtracted from a sequence of signal charges being propagated along the channel. It has been noted that reading occurs between the negative pulses of the waveform 88.
Referring now to Fig. 8, an arrangement
is shown in accordance with the invention
where an isolation bit is provided between
each subtraction operation so that for
example when charges have been
transferred through many cycles along the
channel with some charge transfer
inefficiency, the lost charge in the preceding
channel substantially does not affect the
difference value since lost charges appear in
isolation bits. The isolation bit may be a fat
zero. It will be understood that any desired
number of isolation bits can be included
between the charges that are to be
subtracted. The 0, pulse of a waveform 100
has two pulses after each fret pulse of a
waveform 102 so that at times t, and t3 the
voltage under the electrode 42 is QnA
V
Ct At a time t2 the voltage in the well is Qnl QnA Ct
and at the time t4 the voltage that may be
read out is QnBQnA Ct
QNA is a signal A, QN, is a fixed isolation bit
which may be fat zero plus some transfer
inefficiency charge and QNB iS a signal B. At
a time t5 the #SET pulse of the waveform 102
is applied, at time t6 in response to the first
pulse of the waveform 100 the voltage
stored in the capacitance Ct is V Q{n+ A Ct and at time t7 the voltage is Q(n4l)IQ(n+l)A Ct
At time t8 the pulse of the waveform 100 results in the voltage Qln+1 IA Ct on the capacitance Ct. The readout available then at time t9 is (Q(n. 11B Q(n+1}A) Ct
Thus the use of a single isolation bit allows greater subtraction accuracy and if further accuracy is required additional isolation bits may be utilized. The repetition rate of, the seT pulse of the waveform 102 is equal to the pulse repetition rate of SET of the waveform 100 divided by (1 plus number of isolation bits).
Referring now to Fig. 9 an example of pulse sources to provide the different subtractions is shown as an illustrative example. An oscillator 110 applies signals to a delay monostable circuit 112 which in turn applies signals to a pulse width monostable circuit 114. A clock driver for providing amplitude adjustment responds to the circuit 114 to develop the C, pulses that may be utilized in the arrangements of Figs. 2, 6 and 7. For the isolation arrangement of Fig.
8 a second delay monostable circuit may be
coupled to the output of the delay
monostable circuit 112 and applies signals through a serial path of a monostable circuit
120, an AND gate 122 and a clock driver
124. The AND gate 122 also receives the signal from the pulse width moristable circuit 114. The 5ESET pulses for all the
arrangements that utilize a continuous
repetitive pulse (all except for Fig. 8) may be formed from a series path of delay monostable circuit 126, a pulse width monostable circuit 128 and a clock driver
130, circuit 126 being coupled to the oscillator 110. The SET pulse of Fig. 8 which occurs when a difference is desired may include a series path of a divide by n counter
138 being adjustable and responding to the
oscillator 110, a delay monostable circuit
140, a pulse width monostable circuit 142 and a clock driver 144. It is to be understood that the arrangement of Fig. 9 is only an illustrative example, and any suitable
arrangement for providing the pulses may be utilized all within the scope of the invention.
Referring now to Fig. 10, 10a and 11 a three phase cancellation arrangement is shown for illustrating that the principles of the invention are equally applicable to any suitable CCD structure and to any number of phases, or to any combination of phase pulses and DC signals utilized for driving the charge packets and for CCD operation.
Positioned on a substrate 180 having a plate
182 coupled to a suitable voltage source V, are electrodes 183 to 190 respectively, coupled to receive signals tb3 # ),, #3, 1, DC(9,), #3 and s, suitable sources. The electrode 188 which is the floating electrode is coupled to a lead 192 which in turn is coupled through a FET 194 to a Doc(02) source 196. The lead 192 is also coupled through a source follower 196 to provide an output signal VOUT. In the illustrated arrangement the charge values are transferred along the channel and a difference signal is read at the electrode 188. As shown in Fig. 10a, a time t, which is reset time, the charge packets are under electrodes 184 and 188 as shown by a potential profile 198. At time t2 in response to the sb3 pulse the charge packets are transferred to under electrodes 186 and 189 as shown by a potential profile 199. At time t3 in response to the 8, pulse the charge packets are transferred under electrodes 184, 189 and 190 as shown by a potential profile, 200. At time t4 the charge packets are transferred to under electrodes 185 and 188 as shown by a potential profile 201, so that the difference value can be read from the floating electrode 188. This operation continues in a similar and repetitive manner in response to the clock pulses.
As shown in principally in Fig. 11, which shows the charge being transferred under floating electrode 188 by a line 204, at time t, in response to the FSET pulse of a waveform 206 the voltage V of a waveform 205 is stored on the floating electrode nodal capacitance as shown by a waveform 208.
The sb3 pulse of a waveform 210 establishes the well of the voltage profile at time t2 and the #, pulse of a waveform 214 establishes the well of the voltage profile at time t3. At time t3 the charge on the floating electrode node is
Qn-1
V
Ct
At time t4 when the charge packet Qn is transferred to under the floating electrode
188 the floating electrode node voltage is Qn Qn 1 V+
Ct which is the difference voltage as explained previously relative to the two phase operation. At time t1 in response to the 5BESET pulse of the waveform 206 the voltage V is again established on the floating electrode node, and the subsequent differencing operation continues in a similar manner to provide the next difference V+{Qn+1Qn)
t at time t4. Thus the principles of the invention are applicable to other structures
and driving arrangements such as the three phase structure of Fig. 10.
Thus, there has been provided a CCD signal subtraction system in which an
electrode is clamped in the presence of a first charge and then when that charge leaves the potential well under the floating electrode and a second charge enters, the signal sensed is the difference signals with ideal common mode rejection. By clocking the reset clamp on selected CCD clock periods and observing on intermediate periods, a difference signal may be provided between selected charges. Also, for operation when charge transfer efficiency is a problem any number of isolation bits may be utilized by controlling the number of pulses of the s, signal relative to the FSET pulses. The principles of the invention may be utilized for example in the detection of minimum signal charge superimposed on a large background charge for determining moving targets or for MTI. The charge subtraction principles in accordance with the invention are not to be limited to any particular system or to any electrode structure or number of operating driving phases but may be utilized wherever a difference between two signals is required. The concepts of the invention are equally applicable to bucket brigade structures as to CCD structures.
WHAT WE CLAIM IS:
1. A signal subtraction system comprising:
a charge transfer device having a substrate provided with a charge transfer channel, electrodes for defining potential wells in said channel, means for transferring charge between said potential wells; means operable selectively to clamp or to float the potential of one of said potential-well defining electrodes; and charge storage means associated with said one electrode, such as to be decremented and incremented when the potential well associated with said one electrode is decremented and incremented respectively by charge transfer therefrom and thereto; the arrangement being such that, in operation, with a charge Qn 1 in the potential well associated with
said one electrode and with a charge Qn in
the preceding potential well, clamping of
said one electrode to a predetermined
potential and subsequent floating thereof
sets a predetermined charge in said storage
means, and subsequent transfer of the
charge Qn-1 out of the potential well
associated with said one electrode followed
by transfer of the charge Qn in to the same
potential well, results in the charge in said
storage means being representative of the
difference between Qn and Qn-1- 2. A system as claimed in claim 1 including output means coupled to said one electrode arranged to provide an output voltage indicative of the charge in said storage means.
3. A system as claimed in claim 1 or 2 including a source of clock pulses for sequentially applying pulses to said electrodes, and a source of clamping pulses coupled to said one electrode for clamping said one electrode prior to selected clock pulses.
4. A system as claimed in any preceding claim including charge transfer electrodes between said electrodes which define said potential wells, said charge transfer electrodes being for establishing conditions for charge transfer between said potential wells.
5. A signal subtraction system substantially as herein described with reference to any of the accompanying drawings.
6. In a moving target indication system, a signal subtraction system as claimed in any of the preceding claims.
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (6)

**WARNING** start of CLMS field may overlap end of DESC **. charge and then when that charge leaves the potential well under the floating electrode and a second charge enters, the signal sensed is the difference signals with ideal common mode rejection. By clocking the reset clamp on selected CCD clock periods and observing on intermediate periods, a difference signal may be provided between selected charges. Also, for operation when charge transfer efficiency is a problem any number of isolation bits may be utilized by controlling the number of pulses of the s, signal relative to the FSET pulses. The principles of the invention may be utilized for example in the detection of minimum signal charge superimposed on a large background charge for determining moving targets or for MTI. The charge subtraction principles in accordance with the invention are not to be limited to any particular system or to any electrode structure or number of operating driving phases but may be utilized wherever a difference between two signals is required. The concepts of the invention are equally applicable to bucket brigade structures as to CCD structures. WHAT WE CLAIM IS:

1. A signal subtraction system comprising:
a charge transfer device having a substrate provided with a charge transfer channel, electrodes for defining potential wells in said channel, means for transferring charge between said potential wells; means operable selectively to clamp or to float the potential of one of said potential-well defining electrodes; and charge storage means associated with said one electrode, such as to be decremented and incremented when the potential well associated with said one electrode is decremented and incremented respectively by charge transfer therefrom and thereto; the arrangement being such that, in operation, with a charge Qn 1 in the potential well associated with
said one electrode and with a charge Qn in
the preceding potential well, clamping of
said one electrode to a predetermined
potential and subsequent floating thereof
sets a predetermined charge in said storage
means, and subsequent transfer of the
charge Qn-1 out of the potential well
associated with said one electrode followed
by transfer of the charge Qn in to the same
potential well, results in the charge in said
storage means being representative of the
difference between Qn and Qn-1-

2. A system as claimed in claim 1 including output means coupled to said one electrode arranged to provide an output voltage indicative of the charge in said storage means.

3. A system as claimed in claim 1 or 2 including a source of clock pulses for sequentially applying pulses to said electrodes, and a source of clamping pulses coupled to said one electrode for clamping said one electrode prior to selected clock pulses.

4. A system as claimed in any preceding claim including charge transfer electrodes between said electrodes which define said potential wells, said charge transfer electrodes being for establishing conditions for charge transfer between said potential wells.

5. A signal subtraction system substantially as herein described with reference to any of the accompanying drawings.

6. In a moving target indication system, a signal subtraction system as claimed in any of the preceding claims.

GB38588/77A
1976-09-15
1977-09-15
Signal subtraction systems

Expired

GB1566947A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

US72335676A

1976-09-15
1976-09-15

Publications (1)

Publication Number
Publication Date

GB1566947A
true

GB1566947A
(en)

1980-05-08

Family
ID=24905876
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB38588/77A
Expired

GB1566947A
(en)

1976-09-15
1977-09-15
Signal subtraction systems

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JP
(1)

JPS5362962A
(en)

AU
(1)

AU502883B2
(en)

DE
(1)

DE2736326C3
(en)

FR
(1)

FR2365245A1
(en)

GB
(1)

GB1566947A
(en)

IL
(1)

IL52589A
(en)

IT
(1)

IT1089841B
(en)

NL
(1)

NL7710157A
(en)

SE
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(en)

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Publication number
Priority date
Publication date
Assignee
Title

US4800579A
(en)

1986-03-31
1989-01-24
Kabushiki Kaisha Toshiba
Charge transfer device provided with charge detection circuit of a floating gate system

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* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

CA1099409A
(en)

1977-04-07
1981-04-14
Lawrence G. Heller
Charge transfer device differencing circuit

US4239983A
(en)

1979-03-09
1980-12-16
International Business Machines Corporation
Non-destructive charge transfer device differencing circuit

FR2455772B1
(en)

1979-05-04
1986-01-17
Thomson Csf

DEVICE FOR TRANSFERRING SUBTRACTION LOADS AND GENERATING QUANTITIES OF LOADS AND SYSTEM PROVIDED WITH SUCH A DEVICE

FR2458947A1
(en)

1979-06-12
1981-01-02
Thomson Csf

CHARGE TRANSFER PHASE INVERTER DEVICE AND DIFFERENTIAL AMPLIFIER COMPRISING SUCH A DEVICE

DE2936731A1
(en)

1979-09-11
1981-04-02
Siemens AG, 1000 Berlin und 8000 München

INTEGRATED CIRCUIT WITH TWO CTD ARRANGEMENTS

DE2936728A1
(en)

1979-09-11
1981-04-02
Siemens AG, 1000 Berlin und 8000 München

INTEGRATED CIRCUIT FOR DIFFERENTIALIZATION BETWEEN TWO CHARGES

JPS5919297A
(en)

1982-07-23
1984-01-31
Toshiba Corp
Output circuit of charge coupled device

US4639678A
(en)

1983-12-30
1987-01-27
International Business Machines Corporation
Absolute charge difference detection method and structure for a charge coupled device

FR2655736B1
(en)

1989-12-07
1992-01-24
Alsthom Gec

VOLTAGE MEASURING DEVICE.

1977

1977-07-25
IL
IL52589A
patent/IL52589A/en
not_active
IP Right Cessation

1977-07-28
AU
AU27405/77A
patent/AU502883B2/en
not_active
Expired

1977-08-12
DE
DE2736326A
patent/DE2736326C3/en
not_active
Expired

1977-09-12
IT
IT50962/77A
patent/IT1089841B/en
active

1977-09-13
SE
SE7710259A
patent/SE7710259L/en
unknown

1977-09-14
FR
FR7727749A
patent/FR2365245A1/en
not_active
Withdrawn

1977-09-14
JP
JP11002377A
patent/JPS5362962A/en
active
Granted

1977-09-15
NL
NL7710157A
patent/NL7710157A/en
not_active
Application Discontinuation

1977-09-15
GB
GB38588/77A
patent/GB1566947A/en
not_active
Expired

Cited By (1)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US4800579A
(en)

1986-03-31
1989-01-24
Kabushiki Kaisha Toshiba
Charge transfer device provided with charge detection circuit of a floating gate system

Also Published As

Publication number
Publication date

AU502883B2
(en)

1979-08-09

JPS5727494B2
(en)

1982-06-10

AU2740577A
(en)

1979-02-15

IT1089841B
(en)

1985-06-18

DE2736326C3
(en)

1979-10-25

DE2736326A1
(en)

1978-03-16

DE2736326B2
(en)

1979-03-08

IL52589A
(en)

1979-09-30

FR2365245A1
(en)

1978-04-14

SE7710259L
(en)

1978-03-16

JPS5362962A
(en)

1978-06-05

IL52589A0
(en)

1977-10-31

NL7710157A
(en)

1978-03-17

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