GB1570344A

GB1570344A – Information storage and retrieval system
– Google Patents

GB1570344A – Information storage and retrieval system
– Google Patents
Information storage and retrieval system

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Publication number
GB1570344A

GB1570344A
GB36755/78A
GB3675578A
GB1570344A
GB 1570344 A
GB1570344 A
GB 1570344A
GB 36755/78 A
GB36755/78 A
GB 36755/78A
GB 3675578 A
GB3675578 A
GB 3675578A
GB 1570344 A
GB1570344 A
GB 1570344A
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United Kingdom
Prior art keywords
event
entry
layer
signal
events
Prior art date
1975-12-03
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

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GB36755/78A
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System Development Corp

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System Development Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1975-12-03
Filing date
1976-12-01
Publication date
1980-07-02

1976-12-01
Application filed by System Development Corp
filed
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System Development Corp

1980-07-02
Publication of GB1570344A
publication
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patent/GB1570344A/en

Status
Expired
legal-status
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Classifications

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F16/00—Information retrieval; Database structures therefor; File system structures therefor

G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data

G06F16/22—Indexing; Data structures therefor; Storage structures

G06F16/221—Column-oriented storage; Management thereof

Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC

Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

Y10S707/00—Data processing: database and file management or data structures

Y10S707/99931—Database or file accessing

Y10S707/99933—Query processing, i.e. searching

Description

PATENT SPECIFICATION (ii) 1570344
do ( 21) Application No 36755/78 ( 22) Filed 1 Dec 1976 + 4 ( 62) Divided out of No1 570 341 ( 19) C<\ ( 31) Convention Application No 637 511 ( 19) K 0 ( 32) Filed 3 Dec1975 in C' ( 33) United States of America (US) ( 44) Complete Specification published 2 July 1980 ( 51) INT CL 3 G 06 F 15/40 ( 52) Index at acceptance G 4 A 13 E 13 M 2 C 5 A 8 C 9 C JR ( 72) Inventors THOMAS EDWARD DECHANT, EDWARD LEWIS GLASER, PAUL ELDRED PITT and FREDERICK WAY III ( 54) INFORMATION STORAGE AND RETRIEVAL SYSTEM ( 71) We, SYSTEM DEVELOPMENT CORPORATION, a corporation organised and existing under the laws of the state of Delaware, United states of America, of 2500 Colorado Avenue, Santa Monica, California 90406, United States of America, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly 5 described in any by the following statement:- This invention relates to information storage and retrieval systems. Distinguishing the present invention from the prior art there are certain characteristics that are generally applicable to prior art information storage and retrieval systems in existence today These features are as follows: to 1 As the size of a stored data base increases, the average time required to retrieve data therefrom increases. 2 Data compresed in a storage and retrieval system must be expanded before it can be operated on. 3 If another element is added to a data base (for example, a record is added to is a file), the amount of space required to store the updated base always increases. 4 Some inquiries will be rejected by a retrieval system because they are not stated or formated correctly. As the size of a random access data base increases, the efficiency of storage decreases (due to the requirements for indexing tables, pointers, etc) 20 An embodiment of the present invention does not have any of the above features. A preferred embodiment of the present invention involves a method and apparatus of restructuring digital information to produce isoentropicgrams and seeds Iso-entropicgrams and seeds are explained hereinafter To be explained in 25 more detail, a seed is an optimum way of representing a particular piece of information with minimum storage Stored information is retrieved, not by searching the data base, but by a generation process During the generation process a data request, along with stored iso-entropicgram seeds, are fed as parameters to an output generator 30 In summary, some of the advantages gained from using the techniques according to the present invention may be achieved as follows: ( 1) less physical storage is required, ( 2) fast retrieval time, ( 3) ease of restructuring and updating a data base, ( 4) ease of specifying new retrieval criteria, and ( 5) ease of specifying and carrying out a process 35 The information storage and retrieval system described in the present patent application is a new class of machine, based on entirely new concepts and techniques Since it is based on new concepts, a new word has been coined to describe these concepts and techniques, the word being "holotropic". The holotropic information storage and retrieval system is not based upon a 40 new component nor merely upon a rearrangement of existing components, but instead is based upon new methods and apparatus for building a whole new class of information processing machines. Some superficial similarities will be found between presently available techniques and the class of new machines disclosed herein However, the 45 2 1,570,344 2 differences are much more significant then the similarities, making it awkward to describe the new class of machines in existing terms For example, one aspect of the invention resembles holography in the sense that information pertaining to an item is not stored in one place However, to use the word "holographic" to describe this new class of machines would convey the totally incorrect impression 5 that it is optical in nature and, at the same time, the term fails to refer to these machines' other characteristics By way of further example, this aspect of the invention may behave in some respects like an associative memory However, here again, the differences outweigh the similarities and the use of a descriptor like "associative" generates more confusion that it does clarification For this reason, 10 the term holotropic is used to identify the new machines, concepts and techniques involved. One application of the holotropic method and apparatus is for information storage and retrieval However, in describing the functioning of a holotropic memory system, care must be taken in using the terms used for previous 15 techniques The mechanisms by which holotropic memory systems store and retrieve information are totally different from the mechanisms associated with terms like "search", "scan", "match", "point", "link", or "thread" Thus, according to an embodiment of the present invention, instead of searching for the presence of stored data on the basis of matching an inquiry, the holotropic memory 20 system uses the inquiry to invoke parameters which define both the applicable pieces and any relations between these pieces and the rest of the information. Those parameters then produce the information requested in the inquiry, not by reading it out of storage, but by recomposing it In a holotropic memory system, the information itself is not found, it is generated 25 From the user's point of view, there are two characteristics of holotropic techniques which profoundly change conventional modes of dealing with an information storage and retrieval system One characteristic concerns the absence of the need for descriptors, and another concerns file compression. Attention will now be directed to descriptors and exactness as it applies to an 30 embodiment of the present invention The data which is to be entered into the holotropic system for later retrieval need not be categorized, indexed, described, -or even formated for the purpose of retrieval Should the user wish to set up a structure of categories containing descriptors or indices because it makes it easier for him, he may of course do so An important distinction here is that a holotropic 35 memory system never imposes such structures upon the process Even though the holotropic memory system can accommodate such structures, it does not require them. The same flexibilities characterize the making of inquiries of a holotropic memory system The inquirer can simply ask questions in whatever form, using 40 whatever words occur to him Usually the person attempting to use an information storage and retrieval system has no trouble stating his inquiry in such a way that he understands it, and such a way that other people understand it The difficulty arises when he tries to translate his inquiry into an equivalent question which meets the acceptance requirements imposed by conventional information storage and 45 retrieval systems. With prior information storage and retrieval systems, limits have to be set on the inquiry process Since a holotropic memory system does not impose any requirements on the inquiry process, necessary control is vested where it belongs, so namely, with the user The most important control the user exercises concerns the 50 degree of exactness of the match between his inquiry and the contents of the data base The maximum setting on his "degree of exactness" control would be that for an exact match Should an exact match not be found, the holotropic memory system enables it to tell the user that the situation exists and indicates that change must be made in the exactness setting so that the inquiry will retrieve at least one 55 relevant item. The exactness control setting has no effect whatsoever on the search time of the holotropic memory system However, since it indirectly controls the amount of data retrieved, it does effect the total response time in the sense that more retrieved data will take longer to display in print 60 Because of the differences in the techniques of the inquiry process in traditional and in holotropic information storage and retrieval systems, the structure of the latter may be vastly different In traditional retrieval information storage and retrieval systems, an inquiry can be rejected because it contains an unallowable descriptor, or because something is misspelled, or because the parts 65 are ordered improperly, or because the inquiry is not framed according to the specifications Thus, an inquiry can be rejected regardless of whether the information it asked for is actually in the data base In a holotropic data storage and retrieval system, no inquiry need ever be rejected for such reasons The only sense in which an inquiry needs to be "rejected" at all by a holotropic information 5 storage and retrieval system is that it fails to retrieve In other words, the data base does not contain anything which matches the inquiry at the specified level of exactness If this happens, the user is told whether or not a change in exactness will retrieve an item, and if so, the setting. Another consideration for holotropic information storage and retrieval method 10 and apparatus is file compression The nature of the holotropic system is such that the stored data is compressed into less space than would be used to store the data with presently available techniques This is true even if it were entered as a linear string, that is, as a single record The degree to which any particular data sample is compressed in a holotropic system is a function fo two independent processes is The first process is fairly easily described, and its effects are relatively predictable The holotropic storage and retrieval system compresses input data by automatically taking advantage of any redundancy In one test, a 10,000word sample of ordinary English prose was compressed to approximately one-half the space which would have been required had the sample (without any index tables, 20 pointers, or other artifacts) been stored as a single record in a traditional information storage and retrieval system The exploitation of these redundances occurs at all levels Once a character, a word, a sentence, a paragraph, or any other arbitrarily specified input element has been encountered, no subsequent occurrences of that same element need be stored in their original form Instead, the 25 holotropic system notes that a previously encountered element has occurred again, in a manner which perits reconstitution of any or every one of the multiple input elements in its original context. The second process contributing to data compression in a holotropic memory system is more difficult to predict It is more difficult to predict as it is a function of 30 the relatedness of elements which are part of a data base. As each new input element is added to the data base, it is automatically correlated with every other appropriate element already stored Since the process operates on the data base in its compressed form, it does not adversely affect storage time One possible result of this correlation is that the content and structure 35 of a new input element may reveal a relationship between itself and a number of already stored elements which permits all of the related elements to be treated as a' single entity and stored together Thus, a number of elements which at one time were stored separately, can be collapsed on the basis of their relationship with a subsequent input element, with results that the updated file can require less total 40 storage space than it did prior to the addition of the new input element. Another characteristic which is also very different in a holotropic system from traditional information storage and retrieval systems is that in a holotropic system both the degree of compression and the relative speed of retrieval may increase as the size of the data base increases 45 A derivative feature of compression in a holotropic system is that certain processing or manipulation of the stored data is done in its compressed form, this permitting higher processing speeds than systems which must first expand the data. Although the above discussion has been directed primarily to holotropic information storage and retrieval systems, specific holotropic method and 50 apparatus techniques may be applied in other areas. One area is in digital communications, where band width limitations place an upper bound on speed of transmission Here, a holotropic system can be used to encode the digitized data, and the speed of transmission of any message will be increased as a function of the degree of compression as discussed with respect to 55 information storage and retrieval applications It is important to remember that the information thus compressed and transmitted can represent anything whatsoever, from a payroll file to a digitized pictorial image Significantly, other systems can be used to efficiently compress and transmit data However, one thing which makes the holotropic approach unique is that, since holotropic compression is a function 60 of the redundancy of the message, compression and error correction are one and the same mechanism. Significantly, holotropic techniques can be implemented in software, but some or all are much more efficient when implemented in microcode, and are maximally efficient when implemented directly in hardware However, even where holotropic 65 I 1,570,344 techniques are implemented in software or microcode, holotropic memory systems can perform more efficiently in terms of storage, speed, etc than presently known techniques At the hardware level, holotropic technology can take full advantage of the unique properties of the latest components, such as, charge couple devices, S magnetic-bubble logic, and memory, etc 5 The technology described herein is applicable alike to large computers (for example, information storage and retrieval systems), to subsystems (for example, intelligent disk storage devices), or to very small stand-alone machines (for example, battery-driven calculators). The present invention provides a method using a data processor for identifying 10 a portion of a stored data base, the data base being represented by digital coded signals which represent the order of occurrence of plural events within each of plural entries, the method comprising the steps of: a) forming, as a request, a series of digital coded event signals representing events of an entry; 15 b) forming digital coded signals representing the order of occurrence of events within the entry of the request; c) utilizing the stored data base to form digital coded signals representing the data base order of occurrence for those events which are present in the request; and 20 d) utilizing he digital coded signals formed in the last two steps for identifying a data base entry which has a predetermined degree of match in order of occurrence of events with events of the request. The present invention further provides a data processing method of retrieving, from a memory system, data which is contained in a multiple layered data base, 25 each layer representing an ordered sequence of entries and events in which one or more events represent each entry, in each layer some events being the same and at least one being different and some entries being the same and at least one being different, each layer comprising a plurality of separately retrievable vector signals, one for each different event for such layer, each said retrievable vector signal rep 30 resenting an event-time value for each occurrence of the corresponding event and identifying the order of occurrence of the corresponding events, said data base comprising at least first and second layers, each of a plurality of events in said second layer having a corresponding entry in said first layer, the method comprising the steps of: 35 a) forming a request comprising plural entries, each entry being represented by at least one coded event signal, the entries and events being ordered in order of occurrence, b) interrogating the first layer and locating, for each of a plurality of the request entries, at least one first layer entry having event-time values which 40 represent events bearing at least a predetermined degree of match to the order of occurrence of events represented by the corresponding request events; c) interrogating those second layer event vector signals which correspond to the located first layer entries to locate at least one second layer entry containing event-time values which represent first layer entries having a predetermined degree 45 of match with the order of occurrence of the request entries; d) generating a first layer entry identification signal representing each first layer entry (second layer event) which, according to second layer eventtime values, are present in the located second layer entry; and e) generating a first layer event signal corresponding to each event-time value 50 contained in each first layer entry which is identified by each said first layer entry identification signal, each such first layer event signal having a value corresponding to the event vector signal which contains the corresponding event-time value. The present invention provides in addition a data processor for identifying a portion of a stored data base, the data base being represented by digital coded 55 signals which represent the order of occurrence of plural events within each of plural entries, the processor comprising means arranged in operation to a) form, as a request, a series of digital coded event signals representing events of an entry; b) form digital coded signals representing the order of occurrence of events 60 within the entry of the request; c) utilize the stored data base to form digital coded signals representing the data base order of occurrence for those events which are present in the request; and d) utilize the digital coded signals formed in the last two means for identifying 1,570,344 a data base entry which has a predetermined degree of match in order of occurrence of events with events of the request. The present invention provides moreover a data processor for retrieving, from a memory system, data which is contained in a multiple layered data base, each layer representing an ordered sequence of entries and events in which one or more 5 events represent each entry, in each layer some events being the same and at least one being different and some entries being the same and at least one being different, each layer comprising a plurality of separately retrievable vector signals one for each different event for such layer, each said retrievable vector signal representing an event-time value for each occurrence of the corresponding event 10 and identifying the order of occurrence of the corresponding events, said data base comprising at least first and second layers, each of a plurality of events in said second layer having a corresponding entry in said first layer, the processor comprising means arranged in operation to a) form a request comprising plural entries, each entry being represented by at 15 least one coded event signal, the entries and events being ordered in order of occurrence: b) interrogate the first layer and locate, for each of a plurality of the request entries, at least one first layer entry having event-time values which represent events bearing at least a predetermined degree of match to the order of occurrence 20 of events represented by the corresponding request events; c) interrogate those second layer event vector signals which correspond to the located first layer entries to locate at least one second layer entry containing eventtime values which represent first layer entries having a predetermined degree of match with the order of occurrence of the request entries: 25 d) generate a first layer entry identification signal representing each first layer entry (second layer event) which according to second layer event-time values, are present in the located second layer entry; and e) generate a first layer event signal corresponding to each event-time value contained in each first layer entry which is identified by each said first layer entry 30 identification signal, each such first layer event signal having a yalue corresponding to the event vector signal which contains the corresponding event-time value. Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:Brief Description of the Drawings 35 Fig 1 is general block diagram of the data processing machine (DPM); Figs 2, 3 and 4 form a schematic and block diagram of the ENCODE MODULE; Fig 5 is a diagram showing the relationship of Figs 2, 3 and 4; Fig 6 is a schematic and block diagram of the ALU used in various modules in 40 the DPM SYSTEM, Figs 7 and 8 form a flow diagram illustrating the sequence of operation of the ENCODE MODULE; Figs 9 and 10 form a schematic and block diagram of the DECODE I MODULE; 45 Fig 11 is a flow diagram illustrating the sequence of operation of the DECODE I MODULE; Figs 12, 13 and 14 form a schematic and block diagram of the DECODE II MODULE; Fig 15 is a schematic and block diagram of the DELTA MODULE; 50 Fig 16 is a flow diagram illustrating the sequence of operation of the DELTA MODULE; Fig 17 is a schematic and block diagram of the REVOLVE MODULE; Figs 18 A and 18 B form a flow diagram illustrating the sequence of operation of the REVOLVE MODULE; 55 Fig 19 is a block diagram of an iso-entropicgram revolver employing the REVOLVE MODULE; Figs 20 and 21 form a schematic and block diagram of the SEED MODULE; Fig 22 is a flow diagram illustrating the sequence of operation of the SEED MODULE; 60 Fig 23 is a block diagram of a seed finder and employing the SEED MODULE; Fig 24 is a schematic and block diagram of the CHANGE MODULE; 1,570,344 Fig 25 is a flow diagram illustrating the sequence of operation of the CHANGE MODULE; Fig 26 is a block diagram of a seed line changer employing the CHANGE MODULE; Fig 27 is a schematic and block diagram of a generalized clock contol unit for 5 use in designated modules; Figs 28,29,30 and 31 form a schematic and block diagram of the OUTPUT MODULE; Figs 32 and 33 form a flow diagram illustrating the sequence of operation of the OUTPUT MODULE; 10 Fig 34 is a block diagram of the compaction and retrieval machine employing the OUTPUT MODULE; Figs 35,36,37 and 38 form a flow diagram illustrating the sequence of operation of the PIPE MODULE; Figs 39,40 and 41 form a flow diagram illustrating the sequence of operation 15 of the PIPE MODULE; Figs 42 A-D are graphs used to illustrate functions of the BRIGHTNESS MODULE; Figs 43,44, 45 and 46 are schematic and block diagrams of the BRIGHTNESS MODULE; 20 Figs 47,48,49 and 50 form a flow diagram illustrating the sequence of operation of the BRIGHTNESS MODULE; Figs 51,52 and 53 form a schematic and block diagram of the DPM INTERFACE MODULE which includes the IPRF; Fig 54 shows the I/Q bus 1220 structure; 25 Figs 55 and 56 form timing diagrams representing the sequence of operation of I/O bus output and input operations; Fig 56 A is a schematic and block diagram showing the control for the BDONE flip flop in the DPM INTERFACE MODULE; Fig 57 is a schematic and block diagram of the MEMORY MODULE; 30 Fig 58 is a write enable pulse diagram for the MEMORY MODULE; Fig 59 is a schematic and block diagram of the SWITCH MATRIX; Fig 60 is a schematic and block diagram of the P/B MEMORY; Fig 61 is a block diagram of an alternative data processing machine (DMP 2); Fig 61 A, 61 B and 61 C form a schematic and block diagram of the ENCODE 35 MODULE for the DPM 2 system; Fig 61 D and 61 E form a schematic and block diagram of the DECODE I MODULE for the DPM 2 system; Fig 61 F, 61 G and 61 H form a schematic and block diagram of the DECODE II MODULE for the DPM 2 system; 40 Fig 62 is a schematic and block diagram of the DELTA 2 MODULE for use in the alternative machine of Fig 61; Fig 63 is a flow diagram for the DELTA 2 MODULE; Fig 64 is a schematic diagram of of the implies circuit of Fig 62; Figs 65 and 66 form a schematic and block diagram of the REVOLVE 2 45 MODULE; Fig 67 is a flow diagram for the REVOLVE 2 MODULE; Figs 68 and 69 form a schematic and block diagram of the REVOLVE 3 MODULE; Fig 70 is a flow diagram for the REVOLVE 3 MODULE; 50 Figs 71 and 72 form a schematic and block diagram of the SEED 2 MODULE; Fig 73 is a flow diagram for the SEED 2 MODULE; Figs 74 and 75 form a schematic and block diagram of the OUTPUT 2 MODULE; 55 Figs 76 and 77 form a flow diagram for the OUTPUT 2 MODULE; Fig 77 A is a schematic and block diagram of the CHANGE 2 MODULE: Fig 77 B is a flow diagram for the CHANGE 2 MODULE; Fig 77 C is an example of how information is moved between areas of the MEMORY 2 MODULE during operation of the CHANGE 2 MODULE; 60 Fig 77 D is a schematic and block diagram of the MEMORY 2 MODULE; Fig 77 E is a schematic and block diagram of the SWITCH MATRIX 2: Fig 77 F is a schematic and block diagram of the AUXILIARY MEMORY 2: Fig 77 G is a sketch showing the generalized diagram of the software; Fig 78 is a generalized sketch showing the data structure for each layer; 65 1,570,344 A 7 1,570,344 7 Fig 79 A is a sketch illustrating the generalized data structure for layer 0; Fig 79 B is a sketch illustrating the generalized structure for layer 1, Fig 79 C is a sketch showing an example of the data structure for layer 0; Fig 79 D is a sketch showing an example of the data structure for layer I; Figs 80 and 81 form a PARSER program flow diagram; 5 Figs 82-84 form a PIPE program flow diagram: Fig 85 is a sketch illustrating the address linkage during P 122 et seq of the PIPE program: Fig 86 is a sketch illustrating the address linkage during P 17 of the PIPE program: 10 Fig 87 is a sketch illustrating the address linkage during P Ill of the PIPE program: Figs 88-93 are sketches illustrating the sequence of operation and primary storage areas during the operation of the PARSER, PIPE and BRIGHT programs; Figs 94-96 are BRIGHT program flow diagrams; 15 Fig 97 is an OUTPUT subroutine flow diagram: Fig 98 is a MEMDPM subroutine flow diagram; Fig 99 is a DPMMEM subroutine flow diagram: Fig 100 is a DECODE I subroutine flow diagram; Fig 101 is an INSERT subroutine flow diagram; 20 Fig 102 A is a pictorial flow diagram illustrating the operation of the FORMATER program during a layer 0 request; Fig 102 B is a pictorial flow diagram for the operation of the FORMATER program during a layer I request; Fig 102 C is a FORMATER program flow diagram; 25 Fig 103 is a COMMAND subroutine flow diagram; Fig 104 is a GET INTEGER subroutine flow diagram; Fig 105 is a GET FLOATING POINT subroutine flow diagram; Fig 106 is a REQUEST subroutine flow diagram; Fig 107 is a PROCOUT (Process Output) subroutine flow diagram; 30 Fig 108 is a sketch giving an example and illustrating the correspondence between G 2 TBL table and the OLIST list; Fig 109 is a SETUP subroutine flow diagram; Figs 110 and 111 form a GENERATE subroutine flow diagram: Fig 112 is a SORT subroutine flow diagram; 35 Fig 113 is a PRINTER (Printer) subroutine flow diagram; Fig 114 is a conceptual view of the prior art data base system; Fig 115 is a conceptual view of a layered data base system according to the present invention, Fig 116 is a sketch illustrating layering data base structure of the data base; 40 Fig 117 is a sketch illustrating conversion tables CVRTBL and CVTBL 2; Fig 118 is a sketch illustrating ESTAK, Figs 119 A-E are sketches illustrating available used space management for the seed lines; Fig 120 is a sketch illustrating an example of the layered data structures after 45 initialization; Fig 121 is a DATA BASE program flow diagram; Fig 122 is a layer INITIALIZATION program flow diagram; Fig 123 is a LAYER BUILDING program flow diagram; Fig 124 is a PROCESS ENTRY program flow diagram; so Fig 125 is a PROCESS A LAYER 0 ENTRY subroutine flow diagram; Fig 126 is an ADD N EVENTS subroutine flow diagram; Fig 127 is a PUT NEW SEED IN STORAGE program flow diagram; Fig 128 is a SEARCH FREE SPACE program flow diagram;Fig 129 is a RELEASE SPACE subroutine flow diagram; 55 Fig 130 is a GARBAGE COLLECTION program flow diagram; Fig 131 is an ADJUST SEED HEADER subroutine flow diagram; INDEX Contents Page I GENERAL DESCRIPTION OF DPM SYSTEMS 13 A Data Base Structure 13 B Iso-Entropicgram Techniques 14 5 C Changes 18 D Verifying Presence of an Occurrence Value at Input Line 19 E Hybrid Coding 20 10 F Conventions and Components Used in the Figures 21 IA GENERAL ORGANIZATION OF DPM SYSTEM OF FIGS I-34 23 II ENCODE MODULE 25 15 A General Description 25 B Components 26 C Detailed Description 27 D Example of Operation 34 III DECODE I MODULE 40 20 A General Description 40 B Components 41 C Detailed Description 42 D Example of Operation 46 IV DECODE II MODULE 50 25 V DELTA MODULE 51 A General Description 51 B Components 51 C Detailed Description 52 D Example of Operation 54 30 VI REVOLVE MODULE 55 A General Description 55 B Components 56 C Detailed Description 57 D Example of Operation 65 35 1,570,344 1,570,344 INDEX (Continued). VII. VIII. IX. X. XI. XII. XIII. XIV. XV XVI. XVII. XVIII. XIX. REVOLVER SEED MODULE A General Description B Components C Detailed Description D Example of Operation SEED FINDER CHANGE MODULE A General Description B Components C Detailed Description D Example of Operation SEED LINE CHANGER GENERALIZED CLOCK CONTROL OUTPUT MODULE A General Description B Components C Detailed Description D Example of Operation DATA COMPACTION AND RETRIEVAL MACHINE PIPE MODULE A General Description B Components C Detailed Description BRIGHTNESS MODULE A General Description C Detailed Description DPM INTERFACE MODULE MEMORY MODULE SWITCH MATRIX Page 83' 104 107 107 Ill 112 127 127 132 157 167 169 1,570,344 10 INDEX (Continued). Page XX P/B MEMORY 171 XXI GENERAL ORGANIZATION OF ALTERNATIVE DPM SYSTEM 2 173 5 A General Discussion 173 B Revised ENCODE MODULE 174 C Revised DECODE I MODULE 175 D Revised DECODE II MODU 175 E PIPE and BRIGHTNESS MODULES 175 10 XXII DELTA 2 MODULE 176 A General Description 176 B Components 177 C Detailed Description 178. D Example of Operation 180 ' 15 XXIII REVOLVE 2 MODULE 183 ' A General Description 183 ' B Components 184 C Detailed Description 184 D Example of Operation 191 20 XXIV REVOLVE 3 MODULE 196 A General Description 196 B Components 197 C Detailed Description 198- D Example of Operation 203 25 XXV SEED 2 MODULE 209, A General Description 209 B Components 211 C Detailed Description 211 D Example of Operation 215 30 XXVI OUTPUT 2 MODULE 217A General Description 217 B Components 219 C Detailed Description 219 l l 1,570,344 11 INDEX (Continued). Page D Example of Operation 225 XXVII CHANGE 2 MODULE 228 A General Description 228 5 B Components 228 C Detailed Description 228 D Example of Operation 231 XXVIII MEMORY 2 MODULE 231 XXIX SWITCH MATRIX 2 232 10 XXX AUXILIARY MEMORY MODULE II 232. XXXI COMPUTER, DATA BASE & SOFTWARE ORGANIZATION 234 A MINI COMPUTER 234. B General Description of Data Base Structure 234. C General Description of Software 235 1 Data Base Initialization 235 2 Layer Building 235 XXXII INQUIRY AND RETRIEVEL HARDWARE/ 20 SOFTWARE ORGANIZATION 238 A General Description of Inquiry and Retrieval Software 238 B FORMATER program 250 C PARSER program 251 25 D PIPE program 254 E B RIGHT program 261 F OUTPUT Subroutine 267 G MEMDPM subroutine 268 H DPMMEM Subroutine 269 30 I DECODE I subroutine 269 J INSERT subroutine 270 K COMMAND subroutine 271 L GET INTEGER subroutine 274 M GET FLOATING POINT subroutine 275 35 N REQUEST subroutine 275 12 1,570,344 12 INDEX (Continued). Page 0 PROCOUT (Process Output) subroutine 278 P SETUP subroutine 280 5 Q GENERATE subroutine 282 R SORT subroutine 284 S PRINTR (Printer) subroutine 285 ' T PRNTC (Print a Character) subroutine 285 10 U GETC (Get a Character) subroutine 286 XXXIII HARDWARE/SOFTWARE ORGANIZATION FOR BUILDING LAYERED DATA BASE 286 A LAYERED DATA BASE STRUCTURE 286 15 B DATA BASE program, Level 1 292 C LAYER INITIALIZATION Program level 2 294 D LAYER BUILDING program, 295 20 Level 22920 E PROCESS ENTRY program, Level 3 296 F PROCESS A LAYER O ENTRY subroutine 299 G ADD N EVENTS subroutine, 25 Level 1 301 H PUT NEW SEED IN STORAGE program, Level 2 303 I SEARCH FREE SPACE program, Level 3 305 ' 30 J RELEASE SPACE SUBROUTINE FLOW, Level 3 305 K GARBAGE COLLECTION program, Level 3 306 L ADJUST SEED HEADER subroutine 306APPENDIX A 307 Index of Tables 307 Tables 311 INDEX (Continued). Page APPENDIX B 1002 Index of Program Listings 1002 Program Listings 1004 5 I GENERAL DESCRIPTION OF DPM SYSTEMS A Data Base Structure Fig I depicts a general diagram of an information storage and retrieval system and embodies the present invention The system of Fig 1 is referred to herein as a data base management (DPM) system The DPM system is designed to perform 10 certain general data base management functions, as follows First is the "enter" function which is the ability to enter information into the data base Second is the "update" function which is the ability to change or delete information in the data base Third is the "retrieval" function which is the ability to retrieve information from the data base, and the fourth is the "discrimination" 15 function which enables the user to discriminate upon the information in the data base The discrimination function is referred to herein as the "piping and brightness" function. In order to understand the above four functions, it is imperative that one first understands the structure of the data base and the technique of storage for the data 20 base. All incoming information to the DPM system is restructured by the MINI COMPUTER into a layered data base in its main memory Each layer is a logical entity or a group of entities called "events" Each of these events is separated by a delimiter from a set of delimiters for the layer The group of events between two 25 delimiters is referred to as an "entry" Layering is hierarchical in that the higher level layers encompass the lower level layers For example, if one were to structure contextual data base, the following levels may exist: layer 3 consisting of sentences; layer 2 consisting of phrases; layer 1 consisting of words; and layer 0 consisting of letters Each layer has appropriate and distinct delimiters However for purposes 30 of illustration only a two layer system is specifically disclosed One layer is for words and the second for sentences. Table 1 is an example of the word layer 0 Each occurrence of an event is represented by a 1 whereas an 0 represents the lack of an event As depicted, the layer may be visualized as having two dimensions referred to as lines (or rows) and 35 columns The number of lines is equal to the number of events in the layer The number of columns is equal to the number of possible occurrence values for each event. Entries are viewed as a series of events occurring in time Each column is assigned an event-time, or possible occurrence value, from left to right in 40 increasing monotonical value order Table 1 depicts layer 0 for the sentence "THIS IS A TEST" Line 0 of layer 0 contains the delimiter 1 (representing a textual blank) which actually separates the words of the sentence Line 1 designates the T events Line 2 designates the H events Line 3 designates the I events Line 4 designates the S events Line 5 designates the A events Line 6 designates the E 45 events. Since the events can be considered as a series of chronologically occurring event-times, each event is represented in the layer by a binary 1 in the appropriate line and column Thus, if the event-times can be considered as being represented by so an occurrence clock, each time a I is entered in the layer corresponding to an event 50 the occurrence clock is increased by 1 This is depicted in Table 2 A Thus a delimiter h occurs at event-time 0, the letters T-H-I-S occur at eventtimes 1, 2, 3 and 4 A second delimiter'6 occurs at event-time 5 The letters I-S appear at event-times 6 and 7 Another delimiter 6 appears at event-time 8 The letter A appears at event-time 9 Another delimiter b appear at event-time 10 and the letters 55 T-E-S-T appear at event-times 11, 12, 13 and 14 The ending delimiter '6 appears at event-time 15. All of the events in any one line are represented by an occurrence vector the occurrence vector is represented by the occurrence values of an event shown at any particular line Occurence vectors are shown in Table 2 B, for each line of 60 Table 1, as a series of decimal occurrence values Thus, for example, a "delimiter 1,570,344 occurrence vector" for the delimiter-b event is depicted in the first line of Table 2 B Similarly, the event occurrence vector for the letter T is depicted at the second row of Table 2, etc. Table 3 depicts a sentence layer 1 for the sentence "THIS IS A TEST" The symbol " " is used as the delimiter symbol to delimit phrases The first occurrence 5 of " " is implied, forming the initial leading delimiter for the word layer A number of different types of delimiters may be assigned to each layer (e g, "; ", "; ''"' etc) and can be selected as desired by the user The possible occurrence value at which each delimiter occurs in layer 0 is used as an implied line pointer to layer 1. The line pointer is formed by assigning a value corresponding to the relative 10 position of the events in line 0 of Table 1 and adding thereto a bias The implied pointers of 1, 2, 3, 4 and 5 are depicted at the bottom of Table 3. Consider now an example of the sequence of operation required in layering the phrase' ATHIS wb IS'b A 6 TEST 6 Considering the examples of Tables l and 3, in an actual example of the system, the first delimiter} is implied and not physically 15 present in the input stream A line or event counter is used to keep track of each new event for each different layer In addition, and event-time clock for each layer is provided for identifying event-times, or possible occurrence values. Initially, the line and event-time clocks for each layer are initialized by setting them to 0 The lowest layer, layer 0, is tagged with event names, in this case the 20 binary representation of the character assigned to the line This is not done with higher layers. The implied delimiter 6 is the first possible occurrence value encountered in the input phrase Since this is not present in layer 0, the'6 is assigned to the next available line, line 0, by the line counter The first delimiter occurrence is marked 25 by placing binary 1 in column 0, line 0 corresponding to the state of the event-time clock and the line counter The line counter and the event-time clock are then incremented by 1 The event-time clock now identifies event-time 1, and the line counter identifies line 1. For each event line, zeroes are used to fill in the positions in which a 1 is not 30 entered. The next event to be encountered is the T in the word "THIS" Accordingly, a 1 is entered at line 1, column 1, corresponding to the 1 states of both the event-time clock and the line counter The event-time clock and the line counter are then incremented by 1 This operation continues until the " 6 THIS" has been entered in 35 layer 0 The next event to be encountered is the end delimiter A 5 The line counter is then reset to 0 and at this time the event-time clock is at 5 Accordingly, a 1 is entered at line 0, column 5 The complete word event A 6 THIS F 6 has now been entered on layer 0 and is to be processed on word layer 1 The first occurrence of the " " phrase delimiter is implied and is therefore entered at line 0, column 0, 40 corresponding to the event-time clock and line counter for layer 1 The event-time clock and line counter for layer 1 are incremented by 1 and a 1 is entered at column 1, line 1, corresponding to the word THIS. Next the series of input events "IS '6 "are encountered First, letter layer 0 is checked to see if there is an event line in existence for each of the characters IS/0 45 Since the events, 1, S ' have previously occurred, but not in that order, only the event-time clock is incremented for each of these events and the line counter is appropriately positioned to identify the lines corresponding to each of these events. A new event is not added to layer 1 if the event has already occurred Rather, so only an occurrence mark is added at the appropriate column of the line 50 corresponding to the event A sequence of events between two dilimiters is not added to the same event layer a second time if an implied pointer exists to a higher layer Instead, the series of events between the two delimiters will be represented and entered in the layered system as an occurrence mark on the next higher layer, and nothing needs to be done on the lower layer 55 To be explained in more detail hereinafter, the DPM system of Fig 1 implements the layering concept by representing data, not in lines and columns, but by occurrence vectors which represent event-time by actual occurrence values. B Iso-entropicgram Techniques Information is not stored in the DPM system directly in the event-time form 60 shown on Tables 1 and 3, but is translated into a special compacted form The compaction is referred to herein as iso-entropic compaction Specifically an occurrence vector or word of information is represented by a give line value and a 1.570344 l A given line number Each given line value and line number has a set of equivalent line values and line number values which include the given line value and line number Each equivalent representation has the same information content Each line value represents at least one digitally coded actual occurrence value out of a set of possible ones Each line value is related to another in the same set by an 5 exclusive OR of the values thereof and the values thereof relatively shifted The set of equivalent line values form an iso-entropicgram. The representations in the set are of various lengths when leading O 's are disregarded The shortest one is referred to as the "seed" Most retrieval operation from the DPM system, along with the operations that change or modify the data 10 base, are carried out directly on the seed and therefore are very efficient compared to conventional data base techniques. Table 4-A gives an example of an iso-entropicgram using binary l's and O 's. Each line represents one of the representations of the complete set The input line is depicted at the top of line 0 Referring to the input line, it will be seen that there 15 are actual occurrence values 0, 1, 2, 4 and 6 Each line, moving down in the isoentropicgram, is formed by shifting the binary bits of the preceding line in the isoentropicgram by I bit position to the right and exclusive O Ring the bits (or values) of the unshifted line with the shifted line The "exclusive OR" is referred to herein as an XOR An XOR operation on binary coded information is a bit by bit half-add 20 with a deletion or truncation of those resultant bits which, as a result of the shift, exceed the number of bits in the original unshifted line In this case, the binary bits that are truncated are those to the right of the largest event-time or possible occurrence value 7. Refer now to Table 5 and consider in detail the way in which line 1 is formed 25 from line 0 of Table 4-A The top two lines of Table 5 depict line 0 unshifted and line 0 shifted to the right by 1 binary bit The vertical line indicates the point at which truncation occurs The remaining bits of the shifted and unshifted line 0 are XOR'd resulting in line 1 of the iso-entropicgram This process is repeated, using line 1 to form line 2, and using line 2 to form line 3, etc It will be seen that after a 30 number of lines equal in number to the number of bits in the input line have been generated, the next line to be generated is the input line, also referred to as the output line Note for example that lines 0 through 7 of Table 4-A are each different, whereas line 8 is the same as line 0, the input line The isoentropicgram is closed on itself, lines 0 and 8 being identical 35 The process of going from one line to another in the same isoentropicgram is referred to herein as "revolving". One limitation imposed on the iso-entropicgram is that the number of bit positions, i e, the width, must be an integral power of 2 (e g, 1,2,4,8, 16, etc) It will also be found that in an iso-entropicgram, one can look down through the columns 40 and pick any number of columns which are an integral power of 2 and the bits in these columns will repeat every integral power of 2 lines By way of example, columns 0 and I repeat at line 2; columns 0, 1, 2 and 3 repeat at line 4; columns 0, 1, 2, 3, 4, 5, 6, and 7 repeat at line 8; etc. It will further be seen that as the lines of an iso-entropicgram are formed, past 45 occurrence information appears to progressively sweep across the isoentropicgram, influencing representation of layer information The sweeping in the isoentropicgram of Table 4-A appears to sweep to the right For example, at line 7, the information in line 0, column 0, has interacted with every column to the right so and, in fact, all columns have interacted with columns to their right 50 Table 6 illustrates this point by using, as the input line, the basic isoentropicgram pattern created by a single binary coded bit of occurrence information The basic pattern depicted in Table 6 has been named the "delta" pattern, partly because of its rough similarity to delta modulation and partly because the physical shape outlined by the l's appears like the delta symbol The 55 iso-entropicgram produced in Table 6 is actually a result of the interacting patterns produced by the delta's position at the input line. Another example of the delta interaction is depicted in Table 7 which shows an iso-entropicgram with the O 's left out for clarity Here it will be seen that the deltas go are outlined; therefore their interference occurs at line 4 The interference pattern 60 produced by the interaction of these deltas has similar properties as those of an optical hologram Thus, in an optical hologram, each point is the combined result of a reflected beam whose intensity and path distance is a function of the scene reflecting the beam The recorded intensity at each point is a result of the 1,570,344 combined intensities of the two beams and the phase displacement between them caused by the reflected beam's path length. Similarly, the information at each point in the iso-entropicgram of Tables 6 and 7 is the result of two information intensities (binary 0 and binary 1) and the phasing between them At each point past information is analogous to the optical hologram's refle-cted beam, and the present information to its direct beam. Information stored in the iso-entropicgram is highly redundant Thus each line of the iso-entropicgram forms one representation of a complete set of equivalent representations All lines form the complete set Each line represents a new encoding or transformation of the inj-uf &fine Additionally, it has been found that. large sections of the iso-entropicgram can be eliminated but the entire isoentropicgram can be reconstructed from the remaining bits and pieces, using the interrelations of the lines and columns. As discussed above, line 0 and 8 of the iso-entropicgram of Table 4 are identical in form One can generalize by saying that if line 0 is the input line, line 0 + 2 N is the output line which is identical in form to the input line, where 0 + 2 N is equal to the number of bits in the input line. The purpose of utilizing the iso-entropicgram techniques is to replace the input line with another representation (line) which is equal to but preferably shorter in length than the input line The seed line is the one which can be represented with the minimum number of bits eliminating leading O 's Referring to Table 4-A, it will be seen that the seed is line 2, where only four occurrence values, namely, 0 through 3, are needed to represent the information since the rest of the bits to the right are 0 The seed then represents a minimal encoding for the isoentropicgram In the iso-entropicgram, the seed then is the one with the least number of possible occurrence value positions required to represent all occurrence values. If all binary bit positions in a line are called the possible occurrence values and each I is called an actual occurrence value, it can be said that the isoentropicgramn involves: (I) Grouping strings of actual occurrence values into lines and grouping the lines into a set All lines 'in the set are equivalent and interrelated. According to the preferred embodiment of the present invention, each line in the set is related to another by shifting the occurrence values of the line one place and XO Ring the shifted and unshifted lines, deleting those shifted values which go beyond the width of the iso-entropicgram; ( 2) All lines of the set are unique, that is, no line is repeated; ( 3) The set of lines is closed upon itself in the sense that by manipulating any one line, the entire set of lines can be repeated, and the set size (number ol lines in the set) is predetermined. The set size or number of lines for a given length of lines can be specified as follows: N (number) = number of possible occurrence values per line and the number of lines per set The log 2 N is an integer. General techniques are disclosed herein whereby any line of an isoentropicgram set can be generated from any other line by knowing the line to be used as the reference and, secondly, the number of lines between the line to be used and the input line. Since the transmission of any line of the iso-entropicgram set before so eliminating leading O 's carries the same information and requires the same number of bits, the set is iso-entropic In terms of information theory each line has the same entropy Using seed finding techniques disclosed herein, it is possible to select a line that will represent the input line with fewer occurrence values and hence the entropy is reduced As a result, information representation may be stored or transmitted more efficiently. The lines in an iso-entropicgram can be derived from any other line without resort to a line by line revolve Using for example, the line by line revolve, the seed line is revolved to the input line by revolving the seed through the number of lines of the iso-entropicgram which are necessary to generate the input line For example, in Table 4-B 3, a revolve of 9 lines from the seed line 7 will generate the input line 16. According to one preferred embodiment of the invention means is provided for generating the input line without generating each of the lines in between the seed line and the input line According to the preferred embodiment of the present invention, this is done by determining the number of lines required to generate the i 5 1,570,344 input line and breaking this number down into its component powers of 2, going from the largest possible to the smallest possible component power of 2 One XOR operation is then performed using each of the component powers of 2 to move from the seed line to the input line In each XOR operation a given line is shifted to the right by the number of bit positions (possible occurrence positions) identified by 5 the corresponding component power of 2 the shifted given line is then XOR'd with the unshifted given line. The example of Table 4-B requires a revolve of nine lines to rotate the seed line to the input line Breaking 9 into its component powers of 2, going from the largest to the smallest, the component powers are 8 and 1 Table 4-D top line 10 shows the seed line unshifted The reset line of TABLE 4-D shows the seed line shifted with respect to the first line by 8 bits The third line shows the XOR of the first two lines In this step, then, the seed line has been revolved from line 7 to line 15 (CF line 15 of Table 4-1 D) The remaining component power of 2 is 1 Accordingly, the third line of Table 4-D, line 15 of the iso 15 entropicgram, is right shifted one bit position and XOR'd with itself to generate the input line 16. Another revolve technique is disclosed herein for generating any line of an iso-entropicgram directly from any other line of the same isoentropicgram without generating the intervening lines This may be done by a process of 20 revolving which involves a shift and XOR of the given line of an isoentropicgram. The number of positions of shift is determined by one of the lines of the delta of Table 6 Basically the process involves: 1 Determining the number of lines in the corresponding iso-entropicgram by which the given line is to be revolved; 2 Generating the line of the delta whose number is equal to that of the number of lines to be revolved; 3 For each occurrence value in the selected delta forming at least partially, an individual representation of the given line and aligning the representations of the given line with one end aligned with the 30 corresponding occurrence value of the selected line of the delta; 4 XO Ring the thus aligned occurrence values of the given line eliminating those shifted occurrence values outside of the iso-entropicgram. Tables 46 and 47 depict such an example Referring to Table 47, assume that the given line is line 0 It will be seen that the sixth line in the isoentropicgram from the given line is line 6 Referring to Table 6, delta line 6 contains occurrence values 0, 2, 4 and 6 Taking the given line depicted at line 0 of Table 47 forming a representation of that line for each of the occurrence values of the delta line 6 and aligning the left had end with the corresponding occurrence values of the delta line 6 results in the pattern depicted at 0, 2, 4 and 6 in Table 46 XO Ring the aligned bits 40 together results in line 6 of Table 47 In other words, there are occurrence values at 0, 2, 4, and 6 of delta line 6 The given line is reproduced 4 times and separate ones of the reproduced lines are shifted 0, 2, 4 and 6 possible occurrence values The resulting lines are XOR'd together to generate line 6 of the isoentropicgram, eliminating any shifted occurrence values to the right of the edge of the iso 45 entropicgram. Any line can be used as the given line of the iso-entropicgram The relative distance, i e, number of lines by which the revolve is to take place, is equal to the desired line number minus the given line number This difference determines the line of the delta to be used for the process of shifting and XO Ring If the desired line is lower in number than the given line, for example a given line of 5 and a desired line of 3, the relative distance is negative In that event, the width of the isoentropicgram is added to the negative difference and the result designates the line of the delta to be used For example, using a given line of 5 and a desired line of 3, one would compute the delta line as follows: 55 3 5 = -2; -2 + 8 = 6. This general concept is implemented in the alternative DPM system of Fig 61. However, to facilitate implementation, the process involves a shift and XOR of the delta line rather than the given line which is to be revolved The process implemented in the DELTA 2 MODULE and the DPM system of Fig 61 is as 60 follows: 1 Determining the number of lines in the corresponding iso-entropicgram by which the given line is to be'revolved; 2 Generating the line of the delta whose number is equal to that of the 1,570,344 number of lines to be revolved, one such delta line at least partially being generated for each occurrence value of the given line, and aligning each generated delta line with one end of the delta line in alignment with the corresponding occurrence value of the given line; 3 XO Ring the thus aligned occurrence values of the generated delta line, 5 eliminating those shifted occurrence values outside of the isoentropicgram. A more detailed description of the DELTA 2 MODULE implementation is given in the sections on the DELTA 2 MODULE and the REVOLVE 2 MODULE. To be explained in more detail herein, any line of an iso-entropicgram is 10 completely identified by a line number, a line value and a width (or length) value The line number is the line number in the iso-entropicgram The line value represents the actual occurrence values, excluding O 's to the right of the last 1 The width is the width of the corresponding iso-entropicgram which in turn is the length of any line of the iso-entropicgram including O 's on the right 15 For example, using this form of expression, the seed line of Table 4-A can be represented as line number of 2, line value of 1101 and width of 8 To be explained in more detail, the actual embodiment of this invention operates an actual occurrence value expressed in binary coded decimal rather than lines and columns of l's and O 's Using this form of expression the above line value becomes 0, 1, 3 20 C Changes Changes to a data base consist of insertions, deletions and the addition of new information Deletions remove actual occurrence values from event occurrence vectors An insertion adds an actual occurrence value to one or more event occurrence vectors and, if necessary, actual occurrence values are shifted to allow 25 for insertion New additions to a data base add new actual occurrence values to existing event occurrence vectors or add entire new event occurrence vectors. In accordance with a preferred embodiment of the present invention described hereinafter in connection with the CHANGE MODULE, changes in the event occurrence vectors are made directly to the seed line of an event occurrence 30 vector In other words, it is not necessary to revolve an event occurrence vector back from its seed line to the input line of its iso-entropicgram Tables 9-A and 9-B illustrate the sequence of operation for changing a hypothetical event X Line a of Table 9-A depicts the occurrences of X in absolute decimal coded form. Lines B, b and c respectively, depict deletions and insertions Thus, occurrence 35 values 6 and 12 are to be deleted and occurrence values 1, 3, 8, 9 and 11 are to be added to the event X depicted at line a The change vector incorporating all the insertions and deletions is depicted at line d of Table 9-A. The change vector includes all of the occurrence values for the deletions and insertions sorted in an increasing incremental order from left to right A change 40 operation takes place by XO Ring the change vector and the event occurrence vector to be changed If lines a and d of Table 9-A are XO Red the result is as depicted at line e It will be seen that line e includes all of the actual occurrence values depicted at lines a and d with the common occurrence values 6 and 12 delected It will be recognized that the XOR just described was described with both 45 the event X and the change vector at their 0 or input line for their corresponding iso-entropicgrams. Assume now that the vector X is at its seed line as depicted at g in Table 9-A. The seed of X is at line 6 of its iso-entropicgram According to the preferred embodiment of the present invention, the change vector is revolved through its iso so entropicgram until it is also at line 6 in its iso-entropicgram Line h of Table 9-A depicts the change vector at line 6 of its iso-entropicgram According to the present invention the line values of X and the change vector depicted at g and h are then XO Red providing the result indicated at line i Referring to i of Table 9A, the XOR results in the same line number, namely, line 6, with a line value of 0, 1 Table 55 9-B shows the iso-entropicgram for the input line depicted at e of Table 9-A It will be seen that when the input line (line 0) of Table 9-B has been revolved to its line 6, its actual occurrence values are indeed 0 and 1 which is the same as that depicted at line i in Table 9-A Using the revolve techniques described hereinabove, the resultant value depicted at i, according to the present invention, is 60 then revolved until its seed line is found. With reference to Table 9-B, it will be seen that the seed is at line 5. Accordingly, line 6 depicted at i of Table 9-A and 6 of Table 9-B, is revolved I 1,570,344 189 forward 15 times until it arrives back at line 5 of the same isoentropicgram, as depicted at the bottom of Table 9-B Line 6 plus 15 additional lines is line 21. Subtracting out of 16 (the total lines in the iso-entropicgram) leaves line 5 which is the seed line Thus, the new seed line number 5 has a line value of 0. Significant to the present invention, it should be noted that in the aforegoing 5 example the changes involve five insertions and only two deletions Even though the insertions and hence information content increased, it resulted in a net reduction in the seed In other words, the seed event X contains three occurrence values in its line value whereas the line value for the final seed contains only one occurrence value This occurs because the seed is a representation formed by 10 information interference patterns which are not controlled by the quantity or the number of occurrence values The patterns are only influenced by the relationship between the occurrence values As a result it is possible for a data base to shrink in size with added information. D Verifying Presence of Occurrence Value at Input Line 15 As described above, Table 6 depicts a delta The delta of Table 6 is the same width as the iso-entropicgram of Table 4-A A delta is formed by placing a 1 at possible occurrence value 0 as the input line and revolving it until the original input is formed using the desired iso-entropicgram width. The delta can be used to verify the presence of an occurrence value (i e, a 1) 20 at the input line of an iso-entropicgram without actually generating the input line. The verification process may be accomplished using pencil and paper by physically inverting the delta from top to bottom and from side to side Thus, the delta of Table 6 inverted becomes that depicted in Table 9-C Next, the lower right-hand tip of the delta is positioned over the possible occurrence value column 25 of interest at the output line Next, the line of the inverted delta that coincides with the line of the iso-entropicgram which is going to be used for the test are AN Ded together The resultant line is then XO Red If the result of the XOR is a 1, an actual occurrence value is present at the input line in the possible occurrence value column of interest If the result is 0, an occurrence value is not present 30 Although the foregoing method is accurate and useful using paper and pencil, the present invention embodies concepts similar to the foregoing in a more practical embodiment In the actual embodiment of the invention it is possible to have a seed expressed as a line number, a line value, and an isoentropicgram width to determine whether the input line of the corresponding iso-entropicgram has any 35 particular desired occurrence value and this can be done without revolving the seed back to the input line Usually the line to be used for the checking process is the seed line Therefore, the description of the embodiment of the invention will be described assuming that the line to be used as a basis for the test is the seed line. Referring to the inverted delta, it will be seen that the numbers of positions 40 between adjacent " I's is an integral power of 2 for lines 0, 2, 4 and 6 For example, line 2 has l's separated by two positions, whereas line 4 has l's separated by four positions Because of this characteristic of the delta, it is quite easy to generate occurrence values representing the occurrence values which are present in the lines of the delta which are component powers of 2 To this end, the seed line which 45 is to be used as a basis for a test is first revolved in its isoentropicgram until it is at the line which is an integral power of 2 lines away from the input line Using Table 4-A by way of example, seed line 2 when revolved two lines to line 4 is an integral power of 2 (namely, 4) away from the input line. so Referring to the inverted delta of Table 9-C, it will be seen that line 4 50 contains occurrence values at 3 and 7 Thus it should be evident that the number of possible occurrence values separating the actual occurrence values in the delta (for those lines which are integral powers of 2) is equal to the line number Thus, applying the inverted delta of Table 9-C to the iso-entropicgram of Table 4-A, assume that it is desired to determine whether occurrence value 6 is present in the 55 input line Applying line 4 of the inverted delta of Table 9-C to line 4 of the isoentropicgram of Table 4-A, occurrence value 6 is present in the inverted delta line of Table 9-C, whereas it is absent in the iso-entropicgram line of Table 4-A, whereas four places to the left of the occurrence value 6 (of interest), the inverted delta contains an occurrence value and so does the iso-entropicgram of Table 60 4-A Tables 9-D and 9-E depict these operations. The foregoing method for determining the presence of an occurrence value at the input line using one of the non-input lines of the iso-entropicgram is referred to herein as the DEL function The actual method whereby the embodiment of the I 1,570,344 present invention carries out the DEL function is described in more detail in connection with the section describing the OUTPUT MODULE. E Hybrid Coding The disclosed embodiment of the present invention involves a further compaction technique in which the occurrence vectors are represented in a hybrid 5 encoded form Information is stored in the MEMORY MODULE in hybrid encoded form Thus, considering the iso-entropicgram technique used to represent a particular occurrence vector, the present invention involves a technique which picks the line of the iso-entropicgram which in hybrid coded form is the shortest, not necessarily the one which is shortest in the unencoded form 10 The reason for selecting the shortest hybrid coded iso-entropicgram representation for the seed is to enable the shortest or smallest memory space to be used for storage Referring now to Table 8, the possible occurrence values are depicted, and immediately below, the corresponding binary bits representing an i 5 occurrence vector are depicted at 1 15 Up to this point, the occurrence vectors have been primarily described in what will be termed bit string form In other words, a binary 1 or a binary 0 is used to represent the presence or absence of actual occurrence values This form of representation is depicted at line 1 in Table 8 Line 2 of Table 8 depicts the same information in a binary coded decimal form called absolute code form Thus, bit 20 string form for the information of Table 8 requires 8 digits, each with 1 binary bit, for storage, whereas absolute code form requires fivedigits, each with 3 binary bits, for storage. Each digit in bit string form requires only one binary bit for storage, whereas each of the digits in absolute form requires three binary coded bits 25 However, if the number of blanks or O 's between two binary ones (occurrences) becomes large, it will be seen that a point will be reached where it will be shorter and save memory space to represent the information in absolute form Stating it differently, the distance between the binary l's in the bit string form determines whether bit string encoding or absolute encoding will give the best compaction 30 and hence the shortest length of information to be stored. By way of example, in a very wide iso-entropicgram, the distance between two event-times or occurrences may be great For example, one occurrence value may be 5 and the next 2,673 In this case, absolute encoding should be used since it requires much fewer binary coded bits of information for storage If the distance 35 between event-times is short, and the number of occurrences is therefore frequent, bit string encoding will be better. Accordingly, the present invention involves a technique where a hybrid encoding is used A brief description of the hybrid encoding will now be given since it is an integral part of a preferred embodiment of the seed determination process 40 Table 9 depicts in hybrid code an example of the most significant six words of storage for an occurrence vector containing occurrences at event times 87, 88, 90, 93, 100, 114, 116, 119, 123 and 125 Each word contains a bit or "flag" at the lefthand end which identifies whether it is a bit string word or an absolute word A binary I indicates an absolute word whereas a binary 0 indicates a bit string word 45 Disregarding the bit string/absolute form bit at the left-hand of each word, each binary bit string word contains the largest occurrence value at the righthand end and the smallest at the left hand. Word I is in absolute form and represents 125 with the most significant binary bit at the left and the least significant binary bit at the right (disregarding the bit 50 string/absolute form bit at the left end of the word) Word 2 is in bit string form and has seven binary bit positions representing possible occurrence values 118 through 124 but it only contains actual occurrence values depicted by binary l's for occurrence values 119 and 123. During the process of encoding to hybrid code, an occurrence vector in bit 55 string form is scanned backward from the right-hand end as depicted in Table 4-A to the left-hand end from the latest event time or largest occurrence value to the earliest event time or smallest occurrence value, assigning absolute and bit string form to the words for storage in memory Memories are normally organized so that information is stored in words As the occurrence values are scanned from the 60 largest to the smallest, absolute and binary form words are assigned so as to give the maximum compaction Thus, word I is in absolute coded form and represents the occurrence value 125 Word 2 is in bit string form and has binary l's at the second and sixth position in the word, indicating occurrence values of 123 and 119 Word 3 1,570,344 is in bit string form with binary I bits at the second and fourth positions, representing occurrence values of 116 and 114 Encoding is changed from absolute to binarv coded form when more than seven bits can be saved by switching from bit string form to absolute form The occurrence value 100 is 14 possible occurrence values away from the occurrence value 114 In the encoding procedure, it is 5 necessary to check the efficiency of changing the forms of representation by calculating the number of bits that are saved Since there are three possible occurrence values to the left of occurrence value 114 in word 3, three bits are potentially wasted by switching to absolute form, plus, it will require a full word of seven binary coded bits to represent the information in absolute form Thus a total 10 of 10 ( 7 + 3) bits are required for changing to absolute coded form, producing a saving of four bits Therefore, it is desirable to switch from binary form to absolute form Thus, as depicted in Table 9, word 4 is in absolute form and represents the occurrence value 100. Occurrence value 93 is seven possible occurrence values from the occurrence 15 value 100 Since seven bits are potentially saved (not more than 7) the form of encoding is not changed and the encoding for the next word 4 will remain in absolute form. Occurrence value 90 is only three bits away from occurrence value 93. Accordingly, bit string encoding is more efficient and word 6 is in binary string 20 form. Hybrid encoding is used to store all occurrence vectors in the DPM system. Therefore, although one particular line in an iso-entropicgram may produce the shortest length of occurrences in bit string form, it may be found that another line of the same iso-entropicgram will actually produce the shortest length when 25 converted to hybrid form. Hybrid encoding is used to encode all of the occurrence vectors set back to the auxiliary memory for storage and all occurrence vectors read from the auxiliary for processing by the rest of the DPM SYSTEM. Decoding of the occurrence vectors read from the auxiliary memory and 30 processed in the DPM INTERFACE MODULE is accomplished by entering the hybrid coded string of words largest occurrence value first Information is processed in the DPM SYSTEM in absolute coded form Accordingly, the DECODE I and DECODE II MODULES depicted in Fig 1 translate all hybrid coded information transferred from the auxiliary memory into the MEMORY 35 MODULE into absolute coded form for processing by the DPM SYSTEM. Similarly, the ENCODE MODULE translates all processed information in the DPM SYSTEM from absolute form back to hybrid coded form for storage in the MEMORY MODULE and subsequent transfer back to the auxiliary memory The details for performing encoding and decoding in the ENCODE and DECODE 40 MODULES will be described hereinafter with respect to each of these modules. F Conventions and Components Used in the Figures Each of the modules has control input/output lines (narrow lines) and information input/output lines (heavy lines) By way of example, the ENCODE MODULE shows these lines along the right hand side of Fig 3 The narrow lines 45 used to represent each control input/output line represent a single conductor Each heavy line represents 8 conductors for carrying 8 binary coded bits of information in parallel Arrows to the left indicate incoming signals to the corresponding module whereas arrows to the right indicate outgoing signals. Symbols are shown at the tail of each arrow representing each incoming 50 control input/output line Each of these symbols not only uniquely identifies each line, but identifies the source or module from which the signal for that line originates. The convention employed is to use one or two letters followed by one or more numbers The letters identify the originating module and the number gives a unique 55 identification to the line For example, Fig 3 of the ENCODE MODULE shows the symbol SM 2 for the top line The signal for that line originates in the SEED MODULE Table 10 gives a list of the letter symbols and the corresponding module Some control input/output lines have identifying symbols which do not follow this convention and the originating module is identified 60 Outgoing control input/output lines (arrows to right) are also labeled The symbols on the left (tail of arrow) are logic representing the logical equations for gates used in generating the signal on the outgoing line A symbol is used at the arrowhead to identify the line as it leaves and enters other modules For example, 1,570,344 22 1,570,344 22 in the ENCODE MODULE, the logic P 9 represents a gate used to generate a logic signal on the line EWI. Gating is shown in block diagram in some instances and in others, logical equations are used to represent the gating for simplification Standard symbols are used in the logical equations Thus, a "+" represents an "OR" condition; a " " 5 represents an AND condition; and symbols representing the outputs from flip flops, gates, register, counters, etc are used as the terms in the equations By way of example, logical gating is depicted in the ENCODE MODULE, Fig 4 to reset the flip flop EFRST to 0 The logic is: P 5 G ERFST ULK The gate represented by this logic is true when true signals are formed at each of the outputs indicated in the 10 equation This, of course, illustrates an AND gate with each of the indicated outputs as inputs to an AND gate The logic PIO G + P 7 GE + P 11 Co for flip flop Pl 1 represents three AND gating conditions combined by two OR gating conditions. Flip flops are extensively used througout this patent application One type of 15 flip flop used extensively employs a type SM 7474 positive edge triggered D-type flip flop disclosed at page 121 of the book entitled The TTL Data Bookfor Designi Engineers, published 1973 by The Texas Instruments Co Each of these flip flops such as P 12 of Fig 4 is characterized in that an input exists at the top side and one at the bottom side and two inputs exist at the left hand side Also, each has a pair of 20 complementary outputs at the right hand side, the upper one of which has the same symbol as the flip flop (i e, P 12) and the lower one of which has a line over the top referred to as prime (i e, P 12) These flip flops operate as follows A true signal applied at the top side (without clock) sets the flip flop to a I state, causing true and false signals at the unprimed and primed outputs, respectively (i e, P 12 and P 12) A 25 true signal applied at the bottom side sets the flip flop (without clock) to a 0 state causing false and true signals at the unprimed and primed outputs, respectively (i.e, P 12 and P 12) The lower left side input of these flip flops is for clock, and the upper lift side input is for control of the state into which the flip flop is set responsive to clock at the lower left hand side input A true signal at the upper left 30 side input causes the corresponding flip flop to be set to a true state responsive to a simultaneously applied true clock pulse at the lower left side input, and a false signal at the upper left side input causes the corresponding flip flop to be set to a false state responsive to a simultaneously applied true clock pulse at the lower left side input 35 To simplify the drawings, the outputs on the right side of flip flops are not always shown as they are for flip flop P 12 for example, see flip flop Pl of the ENCODE MODULE However, the unprimed and primed outputs are always implied and will be used at various places in the system For example, the Pl output of flip flop Pl is not shown on the right of flip flop P 1, but it is shown in the logical 40 equation P 1 GE for controlling the upper left side input to flip flop P 1. Similar to the control input/output lines and the information input/output lines, heavy connecting lines are used throughout to designate multiple signal conductors whereas a thin line represents a single conductor. Selection circuits are used throughout the system By way of example, the 45 ENCODE MODULE has selection circuits EDSI-ED 57 The selection circuits each have two or more labeled multi-bit information input circuits, each input circuit for receiving multiple binary coded bits of information, and one multi-bit output for receiving the same number of bits as an information input The information input circuits are labeled directly on the outside of the box such as 50 EDSI-ED 57 of the ENCODE MODULE In some cases, the labels are implied such as for selection circuit DS 1 of the DPM INTERFACE MODULE where the label is implied to be the same as the originating circuit of the information signals. Also, each selection circuit has a control input corresponding to each of the information inputs which is correspondingly labeled inside of the box A true signal 55 at the correspondingly labeled control input causes the selection circuit to couple only those signals at the correspondingly labeled information input to the output circuit By way of example, in the ENCODE MODULE, a true signal at the 1 side control input of selection circuit ED 51 causes the output of register 104 to be coupled through EDSI to the left input of the ALU 60 Various modules also have an arithmetic logic unit ALU of the type SN 74181 disclosed at page 381 of the above TTL book An ALU is shown by way of example in the ENCODE MODULE, Fig 2 The arithmetic unit ALU is characterized in that 8 bit signals coded in the 1, 2, 4, 8 binary coded number system applied at the inputs #1 and #2 enable ALU to form 8 bit signals, coded in the same number 65 system, at an output OP A true signal applied at the ADD input causes a signal at the output OP representing the sum of the two coded signals applied at #1 and #2 Whereas, a control signal applied at the SUB input causes a signal at OP, representing the difference between the signals at #1 and #2 in 2 's complement form 5 The arithmetic unit ALU has additional outputs G, L and E A true signal is formed at the G, L and E outputs, respectively, when the number represented by the coded signal at #1 is -greater than" (>), “less than” (<), and "equal to" (=) than at #2. lo The ALU design shown here is for a 4 bit chip However, it could be 10 generalized into larger groupings In all likelihood, larger capacity ALU's (e g, 24 or 32 bits) would make use of type SN 74182, look ahead carry generators, of the above TTL book However, these are not necessary for an 8 bit wide ALU. It will be obvious to those skilled in the art that minor circuitry peripheral to the SN 74181 is required to receive the true signals and provide the output signals 15 shown and described with reference to the ALU and these circuits are depicted in the block diagram of Fig 6. Some modules have unprimed inputs (i e, EOFI of Fig 17), whereas a primed form (i e, EOFI) is used in the module The primed form (i e, EOFI) merely indicates the logical inverse of the unprimed form which is formed by conventional 20 signal inverter circuits Signal inverter circuits are not always shown but are implied in some instances (as for example, IO Fi in Fig 17). Although specific hardware is disclosed for various modules in the DPM system, it should be noted that the modules might also be implemented using micro programmed mini computers with appropriate firmware programs 25 I-A GENERAL ORGANIZATION OF DPM SYSTEM OF FIGS I-34 Reference should be made to Fig 1 in the following discussion. The DPM SYSTEM has a MINI COMPUTER and a DPM INTERFACE MODULE The MINI COMPUTER may be any one of a number of mini computers well know in the art, a micro-programmed computer or a specially 30 designed computer For purposes of illustration the PDP 11/45 with floating point arithmetic units is disclosed by way of example Included therein is a MAIN MEMORY and an OPERATOR CONSOLE with typewriter and printer input and output The MINI COMPUTER contains a user program which supervises and sequences the operations of the entire DPM SYSTEM The DPM INTERFACE 35 MODULE provides the interface between the MINI COMPUTER, an auxiliary memory for the MINI COMPUTER and the rest of the DPM SYSTEM The DPM contains an IPRF which is a set of registers in which the MINI COMPUTER stores parameters to be used as input by the other modules in the system as discussed more fully in connection with each module The MINI COMPUTER through the DPM 40 INTERFACE MODULE also stores information in the MEMORY MODULE for processing by the rest of the modules The information stored in the MEMORY MODULE is in the form of hybrid coded occurrence vectors The DECODE I and II MODULES decode all hybrid coded signals from the MEMORY MODULE to absolute coded value signals and the ENCODE MODULE encodes all signals 45 being stored in the MEMORY MODULE from absolute coded value signals to hybrid code The exception is with respect to information signals transferred between the MINI COMPUTER or the DPM INTERFACE MODULE and the MEMORY MODULE. The MINI COMPUTER causes an occurrence vector, in the form of a given 50 line value of an iso-entropicgram, to be sent from the MAIN MEMORY to the MEMORY MODULE via the DPM INTERFACE MODULE A REVOLVE MODULE reading from the MEMORY MODULE through the DECODE I and II MODULES writes into the MEMORY MODULE through the ENCODE MODULE and causes the given line value and line number to be revolved through 55 various lines in the corresponding iso-entropicgram The seed is formed using the SEED MODULE Specifically, the REVOLVE MODULE revolves a given line, under control of the SEED MODULE, through its iso-entropicgram The ENCODE MODULE determines the physical length of each encoded line of the iso-entropicgram as it is stored in the MEMORY MODULE The SEED 60 MODULE keeps track of the length of the shortest line and identifies the area in the MEMORY MODULE that stores the shortest line. The SEED MODULE during the seed finding process forms signals representing the number of line revolves which must take place to locate the seed 1,570,344 line This signal, called the total number of lines signal, is set to the DELTA MODULE which forms one or more signals representing the component powers of 2 of the total number of lines signal The component powers of 2 signals areprovided one by one to the REVOLVE MODULE which in turn revolves the given line by that number of lines The input line of an iso-entropicgram is retrieved 5 from the seed line, or any other line, in a reverse sequence of operation More specifically, the REVOLVE MODULE under control of the OUTPUT MODULE revolves the seed line until the input line is formed In this case the OUTPUT MODULE forms a signal representing the total number of lines required to revolve the seed to the input line The DELTA MODULE receives the total number of 10 lines signal and forms one or more signals representing its component powers of 2. The REVOLVE MODULE again revolves the seed line by the amount specified by each component power of 2 signal until the input line is reached. Data is entered in the existing data base by adding, changing or deleting, This is generally referred to as the update function The update function is taken care 15 of by the CHANGE MODULE. When a seed is to be updated, the MINI COMPUTER enters the changes, etc. into a word referred to as the "Change vector" The CHANGE MODULE first gets the occurrence vector in seed form from the data base Using the DECODE I and II and ENCODE MODULES for communication with the MEMORY 20 MODULE, the REVOLVE MODULE revolves the change vector seed back to the same line of its iso-entropicgram as the seed The change vector is then merged with the seed using the XOR operation discussed above. The OUTPUT MODULE is provided primarily for the retrieval process of revolving a seed or other line to the input line of its iso-entropicgram However, the 25 OUTPUT MODULE also causes the DEL function to take place The purpose of the DEL function, as discussed above, is to determine if a particular occurrence value exists at the input line of an iso-entropicgram given the seed line. Significantly, the DEL function allows this to be checked very rapidly without having to revolve the seed line back to the input line 30 The OUTPUT MODULE has a special clipping function which allows the DPM SYSTEM to recall an occurrence vector from the data base and retrieve just a specified portion of the occurrence vector For example, one might want to know how many times the word "help" occurred between occurrence event times 2, 000 and 2,832 To be explained in more detail, the numbers 2,000 and 2,832 would be 35 entered into the OUTPUT MODULE as lower and upper clipping bounds, allowing the event "help" to be retrieved only for those occurrences which lay between 2,000 and 2,832. The PIPE MODULE and BRIGHTNESS MODULE perform a discrimination function in the DPM SYSTEM This does not have anything to do with the data 40 base managing functions Significantly, the PIPE and BRIGHTNESS MODULES allow near miss retrievals In other words, they allow inexact retrieval of information from the data base. Both the piping and brightness functions of the PIPE and BRIGHTNESS MODULES work on a sequence of events between delimiters These delimiters 45 could be any level delimiters The PIPE MODULE is presented with a sequence of events which make up the user request Each event is retrieved from the data base and compared against the others in the request The object is to find if the same sequence of events has occurred between any two delimiters in the layer in question The output of the PIPE MODULE consists of two values for each logical 50 entity in the layer as follows: 1 A starting value, and 2 A numerical value which gives the number of occurrences of events that appeared in the data base from the request. If the sign bit of the numerical value is "I" (true), this indicates that the 55 request occurred exactly somewhere between the specified delimiters The aforegoing is primarily the piping function. The brightness function improves on the piping function For example, the piping function chooses the best candidate for brightness The brightness function then chooses the best possible candidate 60 Essentially, the brightness function takes the starting value within a logical entity which is received from the PIPE MODULE and then takes each event from the input request and finds the closest occurrence of the event to this starting value, if one exists The brightness function then finds this occurrence for each event in 1,570,344 the request and the process is repeated for each logical entity which is to be checked. After all the events in the request have been processed, a calculation is made to find the brightness value for the request. The brightness value can be described considering the following example 5 Picture the logical entity from the data base and immediately to its left the request. The request is then shifted right, one event at a time, over the data base entries and a value is computed for each shift The value indicates how close the request lines up with that of the data base The best value is then passed as an output to the user at the OPERATOR CONSOLE This value is computed for each logical entity 10 which has been requested. The exact way in which the piping and brightness functions work are best understood in connection with each module Accordingly, reference should be made to the sections XV PIPE and XVI BRIGHTNESS MODULE and the software sections XXXII for a more complete description and understanding of is these features. 11 ENCODE MODULE A General Description Section I GENERAL DESCRIPTION OF DPM SYSTEM describes hybrid form of coding of the information, with respect to the example in Table 9 The 20 ENCODE MODULE is provided in the DPM SYSTEM of Fig 1 for the purpose of converting absolute coded occurrence vectors to hybrid coded form and controlling and writing of the hybrid coded occurrence vectors into the MEMORY MODULE. At the outset, it should be kept in mind that occurrence vectors represent a 25 series of occurrence values out of a larger set of incrementally ordered possible occurrence values or event-times Occurrence vectors are stored, retrieved and processed such that the highest numbered occurrence value is first The highest numbered occurrence value identifies the most recent occurrence in the eventtime domain The lowest numbered entry, and hence the entry farthest back in 30 event-time, is stored, retrieved and processed last Examples of delimiter and event occurrence vectors (in absolute coded form) are shown at "b" and "T" of Table 2. This form of information representation is quite important to an understanding of the ENCODE MODULE embodiment about to be described and with respect to each of the other module embodiments about to be described 35 The MEMORY MODULE reads and writes information a word at a time A word has 8 binary bits of information. The ENCODE MODULE, in the encoding process, processes each occurrence vector as folows: The ENCODE MODULE is called each time an absolute occurrence is to be 40 encoded by either the REVOLVE MODULE or the OUTPUT MODULE The module which calls the ENCODE MODULE is hereinafter called the calling module. The ENCODE MODULE receives the absolute occurrence values of an absolute coded occurrence vector in decreasing value order A currently received absolute word 45 and a previously received word in the series are held and compared The difference between the current and previous absolute values represent the number of binary bits of displacement between them If the difference is greater than some "specified number of bits" (in this case, 7 bits), then the previous absolute value is outputted in the hybrid word series as an "absolute" word (see word 0 of Table 9) If the 50 difference is less than this "specified number of bits", the present absolute value is entered as an occurrence into a bit string word (see word 2 of Table 9) of the hybrid series The latter is accomplished by shifting the bit string word under formation the number of bit positions designated by the difference and entering a bit or predetermined value, i e, "I", into the bit string word, and the ENCODE 55 MODULE is "exited" by terminating its operation When a bit string word under formation is complete, it is also outputted It should be noted that binary bit at the most significant end of each word being outputted is reserved as a type or flag bit to indicate the form of the hybrid word A " I " bit flag indicates an absolute word whereas an " O " bit flag indicates a bit string word 60 The hybrid form to which the absolute occurrence values are encoded is a series of absolute and bit string words starting with an absolute word An absolute word in itself represents the value of one occurrence by a combination of binary coded signals A bit string word represents an occurrence value by the number of 1,570,344 possible occurrence values of displacement of an occurrence of predetermined value, i e, " 1 ", from the previous absolute word or from the previous occurrence of predetermined value in the hybrid word series The first word of each hybrid word series is always an absolute word and therefore in itself, identifies the value of the first and largest occurrence However, it should be understood that within the 5 broader concepts of the invention, the invention may be employed in a system which is not bound bv words, in which case the bit string portion of the hybrid form would not be confined to words. * Another purpose of the ENCODE MODULE is to perform "clipping" and "clipping" by "interval" Clipping is the operation of determining if each absolute 10 word occurrence value lies between a top limit (TL) and a bottom limit (BL) This operation is performed by comparing each absolute word with TL and BL If the input entry is < TL and > BL, the absolute word is within desired bounds, and encoding continues and, if not, a corresponding indication is formed.
If “clipping” by “interval” is to be performed, an “interval” value (El) is 15 provided to the ENCODE MODULE If the absolute word is not < TL and > BL, then El is subtracted from TL and BL, and the same absolute word is again compared with the modified TL and BL values This continues until BL goes below 0 at which time a corresponding signal is formed or the absolute word is found within the bounds of the modified TL and BL, according to the above criteria, at which 20 time the absolute word is converted to hybrid form, as discussed above The “clipping” by “interval” function is important under certain conditions when it is needed to know if the input entry is within certain regular intervals, i e, 45-40 or 25-20, 10-5 The values TL, BL and EI are read by the ENCODE MODULE from the corresponding registers of the IPRF 25 B Components The ENCODE MODULE includes registers ET, EIR, El, ER, EO, EHW, ETL, EBL and EOP Each of these registers contains 8 bits of storage With the exception of EOP and ER, each register is of type SN 74100 disclosed at page 259 of the above TTL book and are characterized in that a true signal applied at the L 30 input at the side thereof causes the binary coded signals applied at the upper side input to be applied to the lower output When the signal at the L input goes false, the information is retained in the register even though the information input signals change thereafter.
The EIR register is shown with two special outputs Eo and Eo True signals are 35 formed at these outputs when the content of the EIR register is 0 and not 0, respectively It will be understood that an appropritate circuit (not shown) is connected to the SN 74100 register for forming these signals Preferably, the circuit has the “I” output of each bit position connected to the input of a common “OR” gate The output of the “OR” gate is the Eo output, whereas the output of 40 the “OR” gate is connected through an inverter to the Eo output.
The ER register is a data latch of type SN 74116 of the above TTL book and is similar to the SN 74100, except that it has a “CLEAR” line which provides a one step clearing operation.
Register EOP consists of a flip flop MSB and a seven bit parallelin/parallel 45 out shift register 114 of type SN 74199 as disclosed at page 456 of the above TTL book Register 114 is a 7 bit register and is characterized in that parallel loading is accomplished by applying the 7 bits of data at its upper side and making the shift/load (S/L) control input flow or false when the CLOCK input is not inhibited, i e, receives a true signal A true signal at S/L causes a shift to the right by 50 register 114 responsive to the leading edge of a true pulse at the CLOCK input.
A false signal at S/L causes the 7 bits applied at its upper input to appear at the output of the register 114 and be stored therein responsive to the leading edge of a true pulse at the CLOCK input.
Considering register EOP in more detail, a false signal at P 9 causes register 114 55 to load the input signals applied at the upper side Typically, a true signal is simultaneously formed at P 9 1 SW to the MSB flip flop When CLK goes true, P 9.-BW CLK becomes true and, being applied to the CLOCK input of the MSB flip flop and the register 114, causes the MSB flip flop to be set true and load 7 bits of information from register EO 60 In addition, the ENCODE MODULE has counters MAR 3, MLN 3, CTR and NOC CTR has 8 states, NOC, MAR 3 and MLN 3 each have 256 states and are of type SN 74161 disclosed at page 325 of the above TTL book.
CTR is a 3 bit up/down counter of type SN 74191 disclosed at page 417 of the 1,570,344 above TTL book and is characterized in that a false signal at U/D causes the counter to count up when a true signal is applied to the CT input and a true signal at U/D causes the counter to count down when a true signal is applied to the CT input The counter can be preset to a value corresponding to the signals applied at its input at the upper side while applying a true signal to the L input The block 5 indicating CTR contains a circuit not shown, similar to that described for the ER register for forming true signals at the Co and Co outputs when the state of CTR is 0 and not 0, respectively The counter CTR counts through its prefixed sequence of 8 states and automatically resets to its initial or 0 state.
Each of the MAR 3, MLN 3 and NOC counters are of type SN 74161 of the 10 above TTL book and are controlled to always count upwards Not shown but included within each box is a logical signal inverter to invert the signal at CLR before it reaches the SN 74161 A true signal applied at the CLR (CLEAR) inputs of MAR 3, MLN 3 and NOC causes them to be cleared or reset to a ” O ” state A true signal at the CT input causes the counters MAR 3, MLN 3 and NOC to count up 15 The ENCODE MODULE also has flip flops EFRST, ELAST, BSW, ECE, U/D and MSB In addition, a control counter 113 has flip flops Pl to P 12.
The ENCODE MODULE also has a source of recurring clock pulses 102 The source of clock pulses 102 forms a series of equally spaced (not essential) recurring true clock pulses at its output The output of source 102 is connected to one input 20 of an AND gate 112 which forms clock signals at CLK whenever the other input to gate 112 is true in coincidence with a clock pulse A signal inverter 117 inverts the signal at CLK to form pulses at CLK.
The ENCODE MODULE also has an arithmetic logic unit ALU at #1 and #2 in 2 ‘s complement form Conventional OR gates 108 and 110 are connected to G, L 25 and E so that true signals are formed at a GE output of 108 and a LE output of 110, respectively, when the values of the signals at #1 are “equal to or greater than” (>) that at #2, and “equal to or less than” (<) that at #2. The ENCODE MODULE also has selection circuits EDSI-ED 57 of the type disclosed above The ENCODE MODULE also includes conventional logical OR 30 gates 104-110, 118 and 119 and an AND gate 112. C Detailed Description The ENCODE MODULE can be most readily understood with reference to the description in connection with the block diagram, Figs 2-4, and the corresponding flow diagram, Figs 7-8 As an aid, Table 11 contains symbols used 35 to identify the counters, registers, flip flops, and one-shot multivibrators, together with the mnemonic meaning of the symbols used Also as an aid, the flow diagram contains P numbers adjacent to the various blocks, i e, (P 1), (P 2), etc These P numbers correspond to the outputs of the control counter 113 and thereby indicate the state of the control counter during which the indicated action shown in the flow 40 diagram takes place However, the same P number appears for more than one box. Therefore, for added ease in making reference to the flow diagram, symbols EB I through EB 26 are used to identify each box in the flow. Table 11 shows the principal information inputs and outputs and the input control for the ENCODE MODULE Top clipping limit, bottom clipping limit, 45 interval and iso-entropicgram width are each 8 bits long and are loaded into registers of the ENCODE MODULE by the modules indicated in Table 11. Assume initially that clipping is not to be performed in which case OPSW, ETL, EBL and EIR are all initially 0 Also assume that the ENCODE MODULE is so about to be called for its encoding function for the first time Preliminary to calling 50 the module, the current absolute word is received by the EDS 6 selection circuit either from the D 54 output of the REVOLVE MODULE or from the ORTI register of the OUTPUT MODULE The first current absolute word to be received is the first or largest absolute coded word ( 8 bits in length) of an occurrence vector. After the REVOLVE MODULE supplies the current absolute word, true signals are 55 formed at RM II and RM 6 by the REVOLVE MODULE When the current absolute word is being supplied by the OUTPUT MODULE, true signals are formed at OM 13 and OM 14 by the OUTPUT MODULE A true signal at R Ml I causes the ED 56 selection circuit to couple the current absolute word at D 54 to the information input of register El The true signal at RM 6 enables the OR gate 109 to 60 activate the load (L) input of EI and load the current absolute word into El. Similarly a true signal at OM 13 causes ED 56 to route the information input from the ORTI output to the information input of El and the true signal at O M 14 enables the OR gate 109 to activate the load (L) input of EL and load the current I 1,570,344 absolute word into El It should be noted that all current absolute words for one occurrence vector are supplied in sequence largest to smallest by the same calling module. The iso-entropicgram width (HW) is stored in the input parameter register file IPRF Loading of the iso-entropicgram width into EHW is enabled by true signals 5 at any one of the following outputs: OM I output of the OUTPUT MODULE; SM 3 output of the SEED MODULE; and the CM 3 outlet of the CHANGE MODULE. OPSW is an output circuit of the OPSW flip flop in the OUTPUT MODULE. OPSW is the logical inversion of OPSW Only the OUTPUT MODULE determines if clipping is to take place and, if it is to take place, the OPSW flip flop is in a 1 state, 10 otherwise it is in an 0 state Since it is assumed for the following explanation that no clipping is to take place, a true signal appears at OPSW. The EFRST flip flop is set to a 1 state whenever the present call on the ENCODE MODULE is for converting the first absolute word in a particular occurrence vector EFRST is set by the calling module In the case of the 15 REVOLVE MODULE, a true signal is formed at the RM 2 output, whereas, in the case of the OUTPUT MODULE, a true signal is formed at the OMI output, and enables the OR gate 105 to set the EFRST flip flop to a I state. The ELAST flip flop indicates if the current absolute word is the last one of an occurrence vector A 1 state of ELAST indicates the last one, whereas the 0 state 20 indicates it is not the last one ELAST is set by the calling module In the case of the REVOLVE MODULE, a true signal is formed at RM 9 and in the case of the OUTPUT MODULE, a true signal is formed at O M 18, either of which causes the OR gate 106 to set ELAST to a 1 state. Assume initially that ELAST is in an 0 state Initially the MINI COMPUTER 25 forms a true signal at MINIT which causes gates 118 and 117 to set all of control counters 113 and flip flop ECE to 0 To be explained hereafter, true signals at EMEND thereafter set these elements to 0 The ENCODE MODULE is called by the REVOLVE MODULE by forming a true signal at RM 7 and by the OUTPUT MODULE by forming a true signal at OM 15 Either of these true signals enables 30 the OR gate 107 to trigger the ENGO one-shot multi vibrator which, in turn, causes, a true signal at the ENGO output The true signal at the ENGO output causes the ECE flip flop to be set to a I state The 1 state of the ECE flip flop causes a true signal at the ECE output which, in turn, causes the AND gate 112 to couple the CLK output of the clock 102 to the clock input of each of the control counter 35 113 flip flops PI-P 12 Clock signals now being formed at the output of the AND gate 112 cause the ENCODE MODULE to commence its sequence of operation by virtue of the control action of control counter 113 All flip flops P 1-P 11 being in an 0 state and a true signal being formed at OPSW cause flip flop P 5 to be set to a I state, forming a true signal at the P 5 output 40 One form of clipping is caused by the OPSW flip flop in a I state An alternate form of clipping is automatically done by the ENCODE MODULE Specifically, in the alternate clipping, the absolute words of an occurrence vector are received by the ENCODE MODULE in decreasing order of magnitude The ENCODE MODULE automatically clips or discards all of those absolute words which are 45 larger than the iso-entropicgram width and hence lie outside of the isoentropicgram The alternative form of clipping is very useful in connection with the REVOLVE MODULE where the result of an exclusive OR is clipped to keep only the lower ordered values which are within the iso-entropicgram width The ENCODE MODULE will automatically perform this clipping, using flow chart 50 blocks EB 6 and EB 1. Considering the alternate clipping function in more detail, EFRST is set to I when the ENCODE MODULE is called for the first, time to encode an occurrence vector This is done to insure that the alternate clippin g function is performed. Thus at EB 6, flip flop EFRST being in a 1 state, causes EB 8 to be entered where the 55 iso-entropicgram width in register EHW is compared with the input current absolute word in register El If the content of EHW < El, the operation of the ENCODE MODULE is exited by forming a true signal at EMEND, thereby indicating to the calling module (i e, REVOLVE) that it has processed one absolute word Actually, the absolute word is just discarded by the ENCODE MODULE When the calling 60 module again calls the ENCODE MODULE to cause another absolute word of the same occurrence vector to be processed, flip flop EFRST will still be in a 1 state, causing EB 8 to again be entered If the current absolute word is larger in value than the iso-entropicgram width, an exit is again taken This is repeated until at EB 8 the current absolute word is smaller than the iso-entropicgram width (e g EHW > El) 65 I 1,570,344 29 1,570,344 29 at which time EB 9 is entered to reset flip flop EFRST to 0 Thereafter when called, the ENCODE MODULE does not perform clipping because the ENCODE MODULE goes from EB 6 to EB 7.
Consider now the operation during EB 8 and EB 9 in detail.
Assume EB I and EB 6 of the ENCODE MODULE flow have been traversed, 5 and assume EB 8 is now entered during which the iso-entropicgram width in E 11 W is compared with the current absolute word in El If the current absolute word is larger than the iso-entropicgram width, it is outside of the isoentropicgram and therefore a “don’t care” condition exists To perform the comparison, the true signal at P 5 causes EDSI and ED 52 to couple the contents of EHW and El to the 10 arithmetic unit ALU ALU, together with the OR gates 108 and 110, in turn form true signals at outputs LE and G whenever the content of EHW is, respectively, > than and c than the content of El If the than the content of El (true signal at G), EB 9 is entered Assume during EB 8 the content of EHW is > than that 25 of El and a true signal is formed at G, causing EB 9 to be entered The BSW flip flop states of 0 and 1 indicate the previous absolute word has been entered in the hybrid coded output in bit string form and absolute word form, respectively Since the first hybrid word is always in absolute word form, BSW is to be set to 0, indicating that the corresponding output is in absolute word form and the MAR 3 and Iv LN 3 30 registers are cleared to initial or 0 states, ready for the first hybrid word to be stored in the MEMORY MODULE.
During EB 9, true signals are formed at the following outputs: G, EFRST, and P 5 Hence, at the following pulse at CLK, the counters and registers NOC, MAR 3 and MLN 3 and flip flops EFRST and ELAST are all reset to 0 35 EB 19 is then entered and the same signals cause ER to be reset to 0 and the reset logic resets BSW and MSB of register EOP to 0.
Following EB 19, EB 20 is entered during which the same true signals are also present which causes load logic to load the current absolute word into EO The current absolute word in EO now forms the previous absolute word for the next call 40 on the ENCODE MODULE The same logic also causes NOC to count up one state, indicating that one absolute word has now been provided to the ENCODE MODULE.
At this point, a true signal is formed at the outputs P 5, EFRST Therefore, the next pulse at Crk, the ECE flip flop is reset to 0, thereby disabling the gate 112 45 from applying clock signals to the control counter 113 as described above.
Subsequently, the calling module again calls the ENCODE MODULE and provides the next current absolute word at which time a true signal is applied at either the RM 7 or O M 15 output (of the REVOLVE or OUTPUT MODULES) causing the OR gate 107 to trigger the one shot multi vibrator circuit ENGO, 50 thereby setting the ECE flip flop back to a 1 state and enabling the AND gate 112 to apply clock signals to the control counter 113.
At this point, it is assumed that the next current absolute word is not the last one in the occurrence vector and hence the ELAST flip flop is in an 0 state, forming a true signal at ELAST This causes the next clock pulse from gate 112 to reset flip 55 flop P 5 and set flip flop P 6 to a 1 state, thereby enabling EB 10 to be entered.
During EB 10, a true signal is formed at the P 6 output which causes EDSI and, ED 52 to couple the previous absolute word contained in EO and the current absolute word contained in El to the ALU which forms an output at OP corresponding to the difference This difference is referred to as the previous and 60 current difference signal Additionally, the signal at ED 57 causes the selection circuit ED 57 to gate the previous and current difference signal to the information input of the ET into which the signal is loaded by the subsequent clock signal at C Ek Thus, ET now contains the previous and current difference signal which is the number of bits of displacement (either in event time or in possible occurrence 65 values) between the current absolute word in El and the previous absolute word in EO Additionally, the true signal at P 5 causes the U/D flip flop to be reset to a I state, asserting its true signal at the U/D output, thereby causing CTRto be set so that it counts down The P 6 output of the P 6 flip flop is connected directly to the input of the P 7 flip flop, thus the following clock coming out of the gate 112 causes 5 the P 7 flip flop to be set to a 1 state, thereby entering EB 11.
During EB 11, the previous and current difference signal contained in ET is subtracted from the remaining binary bit signal contained in ER The remaining binary bit signals represent the remaining binary bits to be filled in the bit string word being formed in EOP The subtraction results in a difference signal 10 during EBI 1 which indicates one of two values and these will now be explained If the content of ER is larger than or equal to ET, the difference is > than 0, meaning that the difference represents the remaining available bits in the bit string word (now under formation in EOP) after current absolute word is entered If the content of ER is < than ET, the difference is less than 0 (or -), meaning that the 15 difference represents the number of bits needed in the next bit string word (to be formed) to enter the current absolute word An example of these two conditions is now given: the bit string word has a maximum of 7 available bits (see register 114) in EOP having 8 bits, less 1 flat bit = 7) Assume the remaining available binary bits signal in ER = 5 and the previous and current difference 20 signal in ET = 3, giving a positive difference of 2 The difference of + 2 represents the remaining available bits in the bit string word after the current absolute word If the values are reversed (ER = 3 and ET = 5), then the difference is -2 and represents the number of bits needed in the next bit string word to enter the current absolute word In other words, the current absolute word will require all remaining 25 available bits (ER) in the current bit string word under formation in EOP plus 2 additional bits in the next bit string word to be formed. When on a previous call to the ENCODE MODULE it was found (during EB 18) that the current absolute word was to be outputted in absolute word form, ER was reset to 0 at EB 18 and hence is 0 at the next entry to EB 11 Under these 30 conditions, a difference less than 0 is formed during EB 11 However, the difference is the negative of ET ( 0 ET = -ET). Consider now the details of operation Assume that the ENCODE MODULE is at EB 11, and a true control signal is being formed at the P 7 output This causes EDSI and ED 52 to couple the content of ER and ET to ALU which, in turn, forms 35 an output representing ER ET Assume the result is < 0 A control signal is formed at the L output of ALU, indicating that there are insufficient bits in EOP for the current absolute word EB 12 is entered. During EB 12, the control signal at P 7 and L causes ED 57 and the load logic for ET to store the number of bits needed in the next bit string word signal being 40 formed at EOP into ET at the following pulse at CLK Additionally, the same true signals cause ED 53 and the load logic of CTR to store the content of ER into the counter, setting it to a state corresponding to the content of ER If ER contains 0, as occurs when this is only the second call on the ENCODE MODULE and hence is the second time through the flow, the true signals at P 7 and L also cause the flip 45 flop P 8 to be set into a I state, thereby causing EB 13 to be entered If ER contains 0, CTR is set to 0, causing a true signal at the Co output The true signals at P 8 and Co cause the P 9 flip flop to be set to a 1 state and EB 15 is entered, thereby skipping EB 14. To be explained in more detail, EB 14 causes the bit string word being formed 50 in EOP to be filled out with leading O 's This operation, and hence EB 14, is skipped when ER is 0 since no remaining bits need to be filled in the bit string word under formation. Return now to EB 11 and consider the operation when ER is not 0 and ER ET is < 0 causing a true signal at the L output of ALU Note that ER is not 0 when a 55 bit string word is being formed in EOP and available bits exist in EOP in the bit string word under formation EB 12 and 13 are entered as discussed above and CTR is set to a state corresponding to the number of binary bits remaining to be filled value contained in ER During EB P 4, a true signal exists at P 8 and C (CTR is not 0) and each pulse at= counts CTR down one and causes the EOP shift logic to 60 shift the bit string word one bit position in the direction of the least significant bit thereof until CTR reaches 0, at which time the true signal at a is removed and one is formed at Co This causes CTR and EOP to stop counting and shifting and EB 15 is entered as discussed above. Assume that during EB 15 and BSW flip flop is in an 0 state, having previously 65 1,570,344 been set there during EB 19 thereby indicating that the next event in the hybrid output from the previous event is to be in the form of an absolute word With BSW in an 0 state, EB 16 is entered During EB 16, the false signal atw causes the load logic of register 114 to load the previous absolute word contained in EO into the register 114 of EOP and true signals at P 9 and cause the logic P 9 BSW to set 5 the MSB flip flop to a I state, indicating that the word in EOP is an absolute word. Subsequently, EB 17 is entered. During EB 17, the P 9 output (see right hand of ENCODE MODULE schematic) causes a Write Enable signal (EWI) to be formed in the MEMORY MODULE, causing it to store the absolute word contained in EOP into the storage 10 location designated by the content of MAR 3. The true signals at P 9 and the pulse at CLK cause the content of MAR 3 and MLN 3 to count up one state In this manner, the counter MLN 3 always indicates the number of memory writes and hybrid coded words written in the MEMORY MODULE Thus, an absolute word is outputted by the formation of the true signal 15 at the P 9 output which, in turn, causes the MEMORY MODULE to read the absolute word from EOP. Return now to EB 11 and consider the situation where a prevous absolute word is contained in EO, a current absolute word is contained in El, and ER is > ET Alu forms the difference between ER and ET (i e, ER ET) and ALU and gate 108 20 form a true signal The difference signal at the output OP of ALU represents the remaining available bits in the bit string word now under formation in EOP after entry of the current absolute word in El Under these conditions, the bit string word being formed in EOP is shifted by the number of bit positions indicated by ET and the current absolute word is entered into EOP 25 To this end, EB 22 is entered from EB 11 The true signals formed at P 7 and GE cause the load logic of ER to store the difference signal being formed at the OP output of ALU into ER at the occurrence of the following pulse at CEK Thus, ER now contains the new number of bits remaining to be filled in the bit string word under formation which will exist after the current absolute word is entered 30 Additionally, the same signals cause ED 53 and the load logic to store in CTR the previous and current difference signal in ET The true signals at P 7 and GE cause the Pl 1 flip flop to be set to a 1 state at the next clock signal from gate 112 and thereby enter EB 23.
During EB 23, and the subsequent state EB 24, CTR is enabled to count 35 through a sequence of states corresponding in number to the previous and current difference signal which was set into CTR from ET To this end, the true signal af Pl 1 and at Cli, together with the true signal at U/D, cause CTR to count down 1 state responsive to each true signal at CLK Additionally, in the absence of an 0 state of CTR, a true signal is formed at the a output The true signals at Pl l,o 40 cause the register EOP to be shifted I bit position to the right in the direction of the least significant bit This operation continues until the counter reaches 0 and a true signal is formed at the Co output When a true signal is formed at the Co output, counting and shifting of CTR and EOP is complete and the ENCODE MODULE is ready to enter the value of the current absolute word in El into the shifted bit string 45 word in EOP EB 25 is entered.
During EB 25, a true signal is formed at the Co output and the subsequent true signal at CEK causes the flip flops MSB of EOP and BSW to be set to a 1 state To be explained, the 1 bit stored in MSB is subsequently shifted into register 114 of EOP during EB 26, thereby causing a bit of predetermined value, i e, a 1 bit, the bit so string word being formed in EOP The number of bit positions existing between the currently formed I bit and the previously formed I bit or between the currently formed I bit and the previously absolute word in the series of hybrid word outputs indicates the value of the current absolute word The 1 state of BSW indicates that a bit string word is now being formed in EOP 55 The true signal at Pl 1 and Co cause the flip flop P 12 to be set to a 1 state at the following clock signal from gate 112 and EB 26 is thereby entered.
During EB 26, a true signal is formed at the P 12 output and the subsequent pulse at CEK causes the content of EOP, including the content of MSB and register 114, to be shifted I bit position toward the right toward the least significant end, 60 thereby placing the I bit into the register 114 portion of EOP.
EB 20 is now entered, During EB 20, a control signal is now formed at the P 12 output and the BSW flip flop is in a 1 state The subsequent pulse at CLK causes load logic to store the current absolute word contained in E into EO thereby forming a new previous absolute word and causes NOC to count up one state, 65 1,570,344 3 1 32 1 _5 _,_ J thereby indicating that another absolute word has been encoded into hybrid form.
NOC counts, and thereby indicates, the number of 1 bits processed in any given seed Additionally, the true signal at P 12 causes the ECE flip flop to be set to an 0 state at the pulse at CLK, disabling clock signals at the output of gate 112, causing the EMEND monostable to fire and thereby form a true signal at the EMEND 5 output This causes counter 113 to be reset and the ENCODE MODULE operation to EXIT.
A very important operation in the ENCODE MODULE is depicted at EB 18.
This is the condition under which previous and current difference signal contained in ET is compared with a predetermined threshold value This is the heart of the 10 decision which enables a change, in hybrid output, from bit string word form to absolute word form and the operation is accomplished as follows During EB 18, the P 10 flip flop is in a 1 state, causing a true signal at the P 10 output This causes EDSI and ED 52 to couple the switches 104 and the output of ET to ALU The ALU compares the applied signals and adds the content of ET to the value 7 represented 15 by the switches 104 and forms a result at OP It should be noted that when EB 18 is entered, the content of the ET is always a negative number, the number being stored in 2 ‘s complement form The reason for this situation is that ET at this point in the operation always indicates the number of bits needed in the next bit string word to enter the current absolute word which is a situation where at EB 11, ET was 20 larger than ER resulting in a negative value Thus, at EB 18 when ALU combines the content of ET with the value 7 from 104, a difference signal is formed If the difference signal is > 0, i e, the value 7 is > the absolute value in ET, a control signal is formed at G and EB 21 is entered If the value 7 is < the absolute value in ET, the difference signal will be < 0, causing a control signal at the LE output of OR gate 25110, which in turn causes EB 19 to be entered The result of the comparison of the value 7 and the absolute value in ET is quite important in determining subsequent operations. If the absolute value in Et is < 7 (the value 7 is greater), a control signal is formed at G and the criteria is not met for switching from bit string word to 30 absolute word in the hybrid output because 7 is greater than the absolute value in ET Accordingly, EB 2 I-26 are entered where the current absolute word in El is entered in the bit string word under formation in EOP To this end, EOP is shifted right by the number of bits indicated by the absolute value of the previous and current difference signal contained in ET and then a " 1 " bit entry is made into the 35 bit string word being formed in EOP. If, on the other hand, the absolute value in ET is > than the threshold value 7, it would be a saving in memory space to switch from bit string word form to absolute word form EB 19-20 is entered During EB 19-20, as discussed above, logic resets flip flop BSW to 0, indicating an absolute word form in the hybrid 40 output for the current absolute word.
The operation during EB 19 and EB 26 has already been discussed hereinabove.
Therefore consider EB 21 During EB 21, true signals are formed at the following outputs: P 10, G and at the following pulse at CLK, the U/D flip flop is reset to an 0 state, causing the counter to be set to count up and EB 2 is entered The least 45 significant 4 bits of the 2 ‘s complement value in ET are set in CTR Therefore as CTR is counted up it will return to 0 after the number of counts represented by the absolute value of ET.
During ER 322, the content of ET is tranferred to CTR and subsequently during EB 23 and 24, CTR is counted up until it finally is recycled to an 0 state, causing a 50 control signal at Co For each state of CTR, the content of EOP is shifted right by one When CTR reaches 0, the control signal at Co causes the MSB flip flop of EOP to be set to 1, thereby providing another occurrence in the bit string word output and subsequently during EB 26, the 1 bit is shifted into the register 114 of EOP, all as decribed above 55 Thus, it should now be clearly understood that at EB 18, determining whether -the value in ET (the number of bits needed in the next bit string word to enter the current absolute word) is > 7, also determines whether the ENCODE MODULE switches from bit string word to absoltue string form of output.
There is at least one occurrence held within the ENCODE MODULE that 60 needs to be written out at the end of its operation Therefore, after the calling module has finished using the ENCODE MODULE, the occurrence being held must be outputted The calling module outputs the remaining occurrence by setting flip flop ELAST Flip flop ELAST is set by the REVOLVE MODULE by forming a signal at RM 9 and by the OUTPUT MODULE by forming a signal at 65 1.570344 OM 18, either of which causes the OR gate 106 to set ELAST to a 1 state The 1 state of ELAST causes a true signal at the ELAST output, thereby indicating this is the last call on the ENCODE MODULE for the occurrence vector currently being converted to hybrid form The control signal at the ELAST output occurs when the ENCODE MODULE EXITS during the I state of P 5 After the control signal at 5 the ELAST output is formed, a control signal is formed by the REVOLVE or OUTPUT MODULE at RM 7 or OM 15, thereby causing the OR gate 107 to trigger the ENGO shot multi-vibrator, thereby causing the ECE flip flop to be set to a 1 state and hence the AND gate 112 to start providing clock pulses where EB 27 is entered 10 During EB 27, the true control signals at P 5 and ELAST enable signals being formed at the output of switches 116, representing the 2 ‘s complement of 8, to be gated through the ED 57 selection circuit and allow the following signal at CLK to load the 2 ‘s complement of 8 (i e, a -8) into ET Additionally, the true control signal at P 5 enables the signal in ER, representing the number of binary bits 15 remaining to be filled (in the bit string word under formation in EOP), to be gated through ED 53 to the input of CTR enabling the same pulse at CLK to load this value into CTR The true signals at outputs P 5 and ELAST cause the P 8 flip flop to be set to a 1 state, thereby causing EB 13 to be entered During EB 13 and 14, the bit string word in EOP is filled out with leading O ‘s and right justified by shifting the bit 20 string word in EOP and counting CTR down until CTR = 0 Subsequently, EB 15 and 17 are entered where the resultant bit string word is outputted Of course, should ER be 0 and hence the CTR is set to 0, right shifting is skipped, and outputting is done immediately.
The foregoing description of the ENCODE MODULE was made assuming 25 that no clipping was to take place Only the OUTPUT MODULE enables clipping to take place If clipping is to take place, the OUTPUT MODULE initially forms true signals which enable the bottom limit register EBL, the top limit register ETL, and interval registers EIR to be loaded To this end, the OUTPUT MODULE forms a true signal at OM 16 and then a true signal at OM I The input of selection 30 circuits ED 54 and ED 55 and register EIR are connected to the BL, TL and IR registers of IPRF (Fig 52) Thus, the true signals at O M 16 and OM 1 cause the bottom limit, top limit and inverval value (if an interval value exists) to be strobed from IPRF into EBL, ETL and EIR via the load logic contained in each of these registers The interval value is only used and, hence, an interval value stored in the 35 interval register EIR if the user wishes to ascertain if the output lies in certain intervals For example, if the user were to check the intervals between 35 and 25, and then again between 15 and 5 of an occurrence vector, he specifies an interval value of 10 The clipping function in general forces the output to lie between certain values set by the user Thus, the operation of the ENCODE MODULE is to 40 compare the very first absolute word of an occurrence vector, which of course is the highest one, with the content of ETL and EBL If the interval value is 0, i e, it is not desired to check between different intervals, and if the current entry lies.
outside of either limit, the ENCODE MODULE operation EXITS since the value lies outside of the prescribed limits If, on the other hand, the interval value 45 contained in EIR is other than 0, this means that it is desired to check between different limits and the limits contained in ETL and EBL are reduced to new limits by the interval value in EIR Then the comparison between El and ETL and EBL is repeated using the new reduced limits It should be noted that in the example of the ENCODE MODULE included herewith, it is only desired to check for increments 50 in a downward direction Therefore, if the current absolute word contained in El is above ETL, the ENCODE MODULE operation automatically EXITS without decrementing.
Consider now the actual clipping and interval function in the ENCODE MODULE The OUTPUT MODULE sets OPSW flip flop, contained therein, to a 55 I state When flip flops VP-Pl 1 of the control counter 113 are in an 0 state causing true control signals at the,P 2 Pl l outputs and the OPSW output has a true signal, the next clock causes the Pl flip flop to be set to a 1 state During ER 52, the control signal at the Pl output causes the ED 51 and ED 52 selection circuits to couple the content of ETL and EIR to ALU If the top limit in ETL is < the current 60 absolute word in El, the current absolute word is out of limit and a control signal is formed at the L output of ALU and at the following clock pulse at CLK, the ECE flip flop is reset to 0, disabling the clock to the control counter 113, resetting counter 113 to 0, causing the ENCODE MODULE to EXIT and firing one-shot EMEND 65 1,570,344 34 1,570,344 34 If the top limit in ETL is < the current absolute word in El, a control signal is formed at the GE output of the OR gate 108 A true signal is also being formed at the Pl output and the combination of true signals at Pl and GE causes the P 2 flip flop to be set to a I state, thereby causing EB 3 to be entered. During EB 3, the content of EBL is compared with the content of El To this 5 end, the true signal at P 2 causes ED 51 and ED 52 to couple the content of EBL and EIR to ALU If the bottom limit in EBL is > the current absolute word in El, a control signal is fomed at the G output of ALU and EB 4 is entered If, on the other hand, the bottom limit in EBL is <, the current absolute word in El gate 110 forms a control signal at LE, causing EB 6 to be entered The operation following EB 6 is the 10 same as that described above and need not be reconsidered here. However, assume that the bottom limit in EBL is greater than the current absolute word in El and a control signal is formed at the G output, causing EB 4 to be entered EB 4 is only shown in the ENCODE MODULE flow in order to indicate that a decision is made based on whether the interval value contained in EIR is O or 15 > 0 If, at the time, true signals are formed at P 2 and G, the content of EIR is not 0, a control signal is formed at the Eooutput of EIR The true signal at Eo in coincidence with the control signal at P 2 and G enables the P 3 flip flop to be set to a 1 state at the following clock signal from gate 112, thereby entering EB 5.
During EB 5, the top limit in ETL and bottom limit in EBL are decremented by 20 the interval value contained in EIR To this end, a true signal is now formed at the P 3 output, causing EDS 1 and ED 52 to couple the values contained in EBL and EIR to the input of ALU, thereby causing ALU to form a decremented bottom limit corresponding to the difference (EBL EIR) The true signal at P 3 also causes ED 54 to couple the decremented bottom limit at OP to the input of EBL The 25 subsequent signal at CLK causes the load logic of EBL to store the decremented bottom limit into EBL Thus, EBL now contains the previous bottom limit value decremented by the interval value contained in EIR The true signal at the P 3 output causes the P 4 flip flop to be set to a 1 state at the following clock signal from gate 112 The control signal at P 4 causes EDSI and ED 52 to couple the content of 30 the top limit in ETL and the interval value in EIR to ALU, causing ALU to form a decremented top limit at OP representing the difference (ETL EIR) The control signal at the P 4 output causes ED 55 to couple the decremented top limit from OP to ETL and the following signal at CLK causes the decremented top limit to be stored in ETL Thus, ETL now contains the previous top limit value decremented 35 by the interval value contained in EIR EB 2 and EB 3 are again entered where the input value is again compared, this time with the decremented top and decremented bottom limit values as described hereinabove.
D Example of Operation A better understanding of the operation of the ENCODE MODULE will be 40 had with reference to the following ENCODE MODULE example During this example, it is assumed that the ENCODE MODULE is called six times to convert the following input entries from one occurrence vector and coded in absolute form to hybrid form: 125, 123, 119, 116, 114, 100 To further aid in understanding of the invention, it is assumed that no clipping is to take place Although the clipping 45 function is an important feature in one aspect of the invention Rather than give a complete word description of the following operation, the operation is indicated in symbolic form.
Input on the initial call:
OPSW= O ETL = EBL = EIR = O 50 EFRST= 1; EHW = 128 El = 125 The sequence followed is:
EBI, EB 6, EB 8-EB 9, EBI 9-EB 20 EBI: OPSW = O – control goes to EB 6 55 EB 6: EFRST = I control goes to EB 8 EB 8: El ( 125) < EHW ( 128) The input is less than the iso-entropicgram width. Therefore, control goes to EB 9; EB 9: EFRST = ELAST = 0 NOC= O MAR 3 = MLN 3 = O EB 19:ER= O BSW= O 1,570,344 reset flip flops; clear number of occurrences; clear output memory area address register and length register; indicates there are no remaining bits left in output register EOP Here used to force an absolute ones index form (AOI) output on the next call; indicates we are in absolute ones index form; EB 20: EO( 125) = EI( 125) current input becomes previous input; NOC( 1) = NOC( 0) + 1 up the number of occurrences by one; HALT Output: EOP = 0 MLN 3 = 0 NOC = I Memory area blank Second call: El = 123 EFRST = 0 Other parameters remain as for first cell; Sequence of control: EB 1, EB 6-EB 7, EB 10-EB 13, EB 13-EB 18, EB 21-EB 24, EB 23, EB 25-EB 26, EB 20 EB 1 OPSW = O control to EB 6 EB 6 EFRST = 0 control to EB 7 EB 7 ELAST = 0 control to EBI O EB 10 ET( 2) = EO( 125) EI( 123) bit distance between previous and absolute set U/D = 1 CTR to count down EB 11 ER( 0) ET( 2) < 0 the current absolute word cannot be placed in the remaining number of bits in EOP control to EB 12; EB 12 ET =-2 kept in 2 's complement form; i e, ET= 11111110; CTR ( 0) = ER ( 0) the amount the output register must be shifted if in bit string form, to keep alignment; EB 13 CTR = O control to EB 15 EB 15 BSW = O control to EB 16 EB 16 EOP( 125) = EO( 125) MSB (EOP)= 1 EB 17 Memory write of EOP MAR 3 ( 1) = MAR 3 ( 0) + 1 MLN 3 ( 1) = MLN 3 ( 0) + I EB 18 ET(-2) + 7 > O EB 21 Set counter to count-up U/D= O EB 22 ER( 5) = ET(-2) + 7 CTR( 60 ET(-2) EB 23 CTR( 7) = CTR( 6) + 1 ( 0) EB 24 EOP = O XXXXXXX EB 23 CTR( 0) = CTR( 7) + I (= 0) EB 25 EOP = 10000000 BSW= I EB 26 EOP = 010 XXXXX EB 20 EO( 123) = EI( 123) NOC( 2) = NOC(I) + I set output equal to previous input set sign bit to indicate absolute word form (AOI); pointer to next memory area address; current physical length of output; control to EB 21 since the number to be clocked to CTR is < 0, must count up to reach 0; number of remaining bits that can be used in EOP; the counter is loaded from the rightmost 3 bits of the 2 's complement of-2, i e 11111 1 l 10 control to EB 24 shift EOP right; control to EB 25 since CTR is 3 bit register, adding a I to the 7 causes wraparound to occur; turn on sign bit; indicates bit string form; shift EOP right one since sign bit position is used to indicate type; current absolute word becomes previous number of occurrences is bumped; HALT Memory Area Output EOP= 010 XXXXX MLN 3 = 1 NOC= 2 11111101 X = remaining bits to be used Third Call EI = 119 Sequence of control other paramaters remain the same; EB 1, EB 6-EB 7, EB 10 O-EB 1 I, EB 22-EB 24, EB 23-EB 24, EB 23-24, EB 23, EB 25-EB 26, EB 20 EB I OPSW = O controlto EB 6 EB 6 EFRST = 0 control to EB 7 EB 7 ELAST = 0 control to EBO 10 EB 10 ET( 4) = EO( 123) EI(I 19) ET = bit distance to be considered; EB 11 ER( 5) ET( 4) > 0 control to EB 22 EB 22 ER(I) = ER( 5) ET( 4) ER = number of bits left in EOP after current absolute word process; CTR( 4) = ET( 4) number of positions EOP must be right shifted before the sign bit is set; EB 23 CTR( 3) CTR( 4) 1 ( 0) control to EB 24 EB 24 EOP = 0010 XXXX EB 23 CTR( 2) CTR( 3) 1 ( 4:0) control to EB 24 EB 24 EOP = 00010 XXX EB 23 CTR( 1) = CTR( 2) I ( 0) control to EB 24 EB 24 EOP = 000010 XX EB 23 CTR( 0) = CTR(I) 1 (= 0) control to EB 25 EB 25 EOP = 1100010 XX set on the most significant bit; BSW = 1 indicate bit string; EB 26 EOP = 0100010 X shift EOP right; EB 20 EO( 1 19) = EI( 119) current absolute word becomes previous bump NOC( 3) -NOC( 2) + 1 the number of occurrences; HALT Memory Area OUT EOP = 0100010 X MLN 3 = 1 NOC = 3 11111101 Fourth Call EI = 116 Sequence of control EBI, EB 6, EB 7 EB 10 ET( 3), EO( 119) EI( 116) EB 11 ER(I)-ET( 3) (< 0) control to EB 12 EB 12 ET(-2), ER(I)-ET( 3) CTR(I) ER( 1) All other parametrers remain the same; EB 1, EB 6-EB 7, EB 10 O-EB 14, EB 13, EB 15, EB 17-EB 18, EB 21-EB 24; EB 23 EB 25-EB 26, EB 20; same as before; obtain bit distance; there are not enough bits to process this entry using current information in EOP; ET = 11111110 in 2 's complement form; number of positions that EOP must be shifted to keep alignment: EB 13 CTR(I) O control to EB 14 EBI 4 CTR( 0) = CTR( 1) 1 EOP = 00100010 right shift EOP; EB 13 CTR( 0) = 0 control to EB 15 EB 15 BSW = I control to EB 17 EB 17 write EOP to memory MAR 3 ( 2) MAR 3 ( 1) + I next memory address; MLN 3 ( 2)MLN 3 ( 1) + I physical length of memory area; EB 18 ET(-2) + 7 (> 0) control to EB 21 EB 21 set U/D = 0 CTR to count up EB 22 ER( 5) = ET(-2) + 7 c c CTR( 6) ET(-2) CTR = rightmost 3 bits of 2 ‘s con nplement ET= 11111 1-10 {; EB 23 CTR( 7) = CTR( 6) + 1 ( 0) control to EB 24 EB 24 EOP = 00 XXXXXX shift EOP X = remaining usable bits for EOP; 1.570344 ji 37 EB 23 CTR( 0) = CTR( 7) + 1 (= 0) control of EB 25 EB 25 EOP= 10 XXXXXXBSW= 1 EB 26 EOP = 010 XXXXX EB 20 EO( 116) = EI( 116) NOC( 4) -NOC( 3) + 1 1,570,344 3 bit register therefore wraparound on the add; set sign bit in EOP; indicate bit string form; shift EOP since sign bit indicates type; previous input is replaced by the current; HALT Memory Area Output EOP = 010 XXXXX MLN 2 = 2 NOC = 4 11111101 00100010 Fifth Call EI = 114 sequence of control remaining parameters remain the same; EBI, EB 6, EB 7, EB 10-E Bll, EB 22-EB 24, EB 23 EB 25-EB 26 EB 20; EBI, EB 6, EB 7 same as before; EB 10 ET( 2) EO( 116) EI( 114) bit distance; set the counter to down EBI 1 ER( 5) ET( 2) > 0 ‘ control to EB 22 EB 22 ER( 3) = ER( 5) ET( 2) update the remaining; CTR( 2) ET( 2) number of bits; EB 23 CTR( 1) =CTR( 2) 1 (:0) ‘ control to EB 24 EB 24 EOP = 0010 XXXX shift EOP right; EB 23 CTR( 0), CTR(I) I (= 0) control to EB 25 EB 25 EOP = 1010 XXXX set sign bit for EOP; BSW = 1 indicate bit string form; EB 26 EOP = 01010 XXX shift EOP; EB 20 EO( 114) = EI( 114) NOC( 5) NOC( 4) + 1 HALT Memory Area Output EOP = 01010 XXX MLN 3 = 2 NOC= 5 11111101 00100010 Sixth Call EI = 100 sequence of control all other parameters remain the same; EBI, EB 6-EB 7, E Bl O-EB 14, EB 13-EB 14, EB 13-EB 14, EB 13, EB 15, EB 17-EB 20; EB 1, EB 6, EB 7 same as before; EB 10 ET( 14), EO( 114) EI( 100) set U/D = I CTR to count down EBI 1 ER( 3) ET( 14) (< 0) control to EB 12 EB 12 ET(-11)-ER( 3)-ET( 14) ET in 2 's complement form; CTR( 3) = ER( 3) number of positions EOP must be shifted to keep alignment; EB 13 CTR( 8) O control to EB 14 EB 14 CTR( 2)= CTR( 3) 1 EOP = 001010 XX EB 13 CTR( 2)40 controlto EB 14 EB 14 CTR(I)=CTR( 2) 1 EOP = 0001010 X EB 13 CTR( 1) O controlto EB 14 EB 14 CTR( 0) = CTR(I) I EOP = 00001010 EB 13 CTR( 0) = O ' control to EB 15 EB 15 BSW = 1 control to EB 17 EB 17 write memory EOP MAR 3 ( 3) = MAR 3 ( 2) + 1 MLN 3 ( 3) = MLN 3 ( 3) + I 38 1,570,344 38 EB 18 ET(-11) + 7 < 0 control EBI 9 ER= 0 BSW= O EB 20 EO( 100) = EI( 100) NOC( 6) NOC( 5) + I to EB 19 assure next call will write; current absolute word to be in absolute word form; HALT Memory area Output EOP = 0 MLN = 3 NOC = 6 11111101 00100010 00001010 Seventh call set ELAST= 1 sequence of operation EB 1, EB 6 EB 7 ELAST = 1 control to EB 27 EB 27 CTR( 0) = ER( 0) ET = 8 EB 13 CTR( 0) = O control to EB 15 EB 15 BSW= O controlto EB 16 EB 16 EOP( 100) = EO( 100) set sign bit of EOP EB 17 write EOP MAR 3 ( 4) MAR 3 ( 3) + 1 MLN 3 ( 4) MLN 3 ( 4) + 1 út 18 ET(-8) + 7 < 0 ' control to EBI 9 ER= O BSW= O EB 20 EO( 100) = EI( 100) all other parameters remain the same; EB 1, EB 6-EB 7, EB 27, EB 13, EB 15-EB 20; same as before; in case we are in bit string; assure proper balance at EB 18; prepare the output; indicates absolute word type; next address; length; EB 19 these are meaningless steps on the last time through note that NOC is not incremented this time; HALT EOP = 0 MLN 3 = 4 NOC = 6 Memory area 11111101 00100010 00001010 In summary, what has been disclosed is an encoder for converting to hybrid form a received series of absolute word signals of decreasing value order The hybrid form has a series of at least one absolute word signal and bit string word signal An absolute word signal represents the value of one occurrence by the combination of binary coded bit signals A bit string word signal represents one occurrence by the number of bits of displacement of a bit of predetermined value therein from an absolute word signal in the hybrid word series Means include the ALU, ED 52, ED 51 and control counter 113 operative during EB 18 in response to received previous and current absolute word signals for forming an output signal indicative of the difference in value therebetween The previous and current different signal is formed at the OP output of ALU and is stored in ET. Additionally, there is means including ET and the control counter 113 for retaining the previous and current difference signal This occurs at EB 10. The encoder also includes means for indicating absolute or bit string word form of hybrid output and includes means, including the switches 104, for indicating a preselected minimum permitted difference (e g 7) between successively received word signals Such means includes ALU, EDSI, ED 52 and the control counter 113 for comparing the minimum difference indication and the retained previous and current difference signal and for indicating the first being > than or < to the latter. The encoder also has means for providing absolute form outputs such means including the EOP load and shift logic, the BSW and its set and reset logic and the 1,570,344 39 1,570,344 39 3 control counter 113 operative in response to the S indication for outputting the stored current absolute word and an absolute flag This operation takes place during EB 18-20, 10-17. The encoder also includes means for providing bit string form outputs and has means including the EOP, CTR and its load and control logic, ED 52, ER, EOP shift 5 logic, MSB set logic and the control counter 113 which are responsive to the > indication for forming a set of ordered signals comprising a binary bit of one value (e.g, 1) associated with the number of binary bits of a second value (e g, 0) corresponding to the value of the retained previous and current difference signal It will be seen that the operation is depicted by EB 21-25 The means for providing 10 bit string form outputs also includes means including the clock and the control counter 113 for selectively outputting the set of signals in association with a bit string flag The binary bit of one value in the bit string form output is in a predetermined relation to the outputted absolute word In this regard, the number of bits of displacement between a bit of the one value andd an absolute word 15 indicates the value of the one bit.
A preferred embodiment of the encoder has a current store such as register EI for storing a currently received absolute word Means including ED 56 control logic stores received absolute words into the current register El A previous register EQ is provided for storing a previously received absolute word Means including the 20 EO control logic and the control counter 113 transfers the current absolute word from the current register to the previous register, forming therein the previous absolute word This is accomplished at EB 20.
A further preferred embodiment of the encoder provides hybrid form output in a series of words The means for forming a set of ordered signals includes 25 counter means CTR CTR has output Co for indicating completion of counting A bit string word forming register EOP is provided and means including CTR load and control logic and ED 52 is operative during EB 2 I-24 in response to the > indication for enabling the counter means to count through a sequence of states corresponding in number to the retained current and previous difference signal 30 contained in ET.
The indication at output Co from CTR indicates completion of the lastmentioned counting Additionally included is means including EOP and its shift logic and control counter 113 operative during EB 2 I-25 for shifting the content of the bit string forming register one bit position in the direction of the most 35 significant bit thereof for each of the last-mentioned counter means states.
Additionally included is means including the MSB flip flop and its set logic and the control counter 113 which is operative during EB 25 in response to the lastmentioned completion indication at Co for inserting a binary bit signal of predetermined value (e g, 1) at the least significant end of the content of the bit 40 storing register EO By this means, occurrence is entered in the hybrid form word output The means for outputting additionally comprises means including the P 9 logic and the control counter 113 operative during EB 17 for selectively outputting the content of the bit string word forming register by forming a signal at the P 9 output, indicating that the word in EOP is now ready for output 45 An additional preferred embodiment of the encoder, according to the invention, is a bit string forming means which has means for entering a first occurrence in a new bit string word under formation Included in the lastmentioned means is means (ER) for storing a signal representing the number of binary bits remaining to be filled in the bit string word forming register EOP Also 50 included is combining means including the ALU, ED 51, ED 52 and the control counter 113 operative during EB 11 for forming a signal representing the difference between the values of the remaining number of binary bits to be filled signal and the previous and current difference signal Additionally included is means including the ALU, ED 51, ED 52 and gates 108 and 110, and the control counter 55 113 operative during EB 11 for comparing the values of the previous and current difference signal and the remaining binary bits to be filled signal for indicating that the value of the first signal is 2 (GE) than or < (L) than the latter signal. Additionally included is means including ET, ED 57 and the control counter 113 operative during EB 12 in response to the < than indication at L for retaining the 60 difference signal in ET from the combining means as the number of bits needed in the next bit string word to enter a current absolute word. Means including the CTR load and control logic and ED 52 is operative during EB 11, 22-24 in response to the > than indication at GE for enabling the counter means to count through a sequence of states corresponding in number to the 65 1,570,344 1,570,344 40 retained number of bits needed in the next bit string word signal contained in ET It should be noted that the foregoing operation occurs when, during EB 11, the retained number of bits needed in the next bit string word contained in ER is > than the previous and current difference signal contained in ET Also included is the EOP shift control logic, the control counter 113 for shifting the content of the bit 5 string forming register EOP one bit position in the direction of the most significant bit contained therein for each of the last mentioned counter means states Means including MSB and its set logic and the control counter 113 are operative during EB 25 responsive to the completion signal at Co for inserting bit signal of predetermined value (e g, 1) at the least significant end of the content of the bit 10 string register EOP.
A further preferred embodiment of the encoder has a bit string forming means which includes means for filling out the bits of a bit string word being formed when no further occurrences can be entered therein Included therein is means ER for storing a signal representing the number of binary bits remaining to be filled in the 15 bit string word being formed Combining means including ALU, EDSI, ED 52 and the control counter 113 is operative during EB 11 for forming a signal representing the differences between the value of the remaining number of binary bits to be filled signal, contained in ER, and the previous and current difference signal, contained in ET Additionally, there is means including ALU, ED 51, ED 52, gates 20 108 and 110 and the control counter 113 operative during EB 11 for comparing the value of the previous and current difference signal and the remaining binary bits to be filled signal for indicating that the first is > than or < than the latter. Means including the CTR load and control logic EDS and ED 52 is operative during EB 12-14 in response to the < than indication for enabling the counter 25 means CTR to count through a sequence of states corresponding in number to that indicated by the value of the stored remaining binary bits to be filled signal contained in ER Also included is means including the EOP shift control logic, the control counter 113 operative during EB 13-14 for shifting the content of the bit string forming register EOP one bit position in the direction of the most significant 30 bit thereof for each of the last mentioned counter means states. According to a preferred embodiment of the encoder, clipping means is provided Included therein is means including ETL and EBL for storing an upper limit value and a lower limit value Means including ALU, EDSI, ED 52 and gates 108 and 110 are operative during EB 2-4 for comparing a current absolute word 35 with the upper and lower limit values and for indicating if it is out of the bounds defined by the limit values. According to a further preferred embodiment of the encoder, an interval adjusting means is provided along with the clipping means Included is means EIR for storing an interval value Means including the ALU, EDSI, ED 52, ED 55, gates 40 108 and 110, and control counter 113 is operative during EB 5 in response to the indication that the current absolute word is out of bounds for incrementally changing the stored upper and lower limit values in EBL and ETL by the stored interval value in EIR In the specific example shown, the incremental changing is a decrementing action Also included is means for enabling the comparing means to 45 repeat the comparing, using the incrementally changed upper and lower limit values and current absolute word. III DECODE I MODULE A General Description The DECODE I and II MODULES are internally similar The difference lies 50 mainly in the input and output signals This section is devoded to the DECODE I MODULE The next section will discuss the differences in the DECODE II MODULE. The purpose of the DECODE I MODULE is to convert to absolute word form a series of received occurrences in a hybrid word The occurrences are of 55 decreasing value and are coded in hybrid form Thus, the DECODE I MODULE converts information in the opposite direction from that of the ENCODE MODULE The hybrid coded form comprises a series of binary coded words, including at least one absolute coded word followed by one or more bit string Ywords and/or absolute words Each absolute word represents an occurrence directly 60 in coded form Each bit string word represents an occurrence by the number of bits of displacement of a bit of a predetermined value from either an absolute word or another one of such bits of predetermined value in the series of hybrid words. 41 1,570,344 41 Additionally, each hybrid word has a flag indicating whether it is an absolute or bit string type of word. The DECODE I MODULE operates in response to a call by a calling module. The possible calling modules for the DECODE I MODULE are: PIPE, SEED, REVOLVE, BRIGHTNESS, OUTPUT MODULES and the DPM INTERFACE 5 MODULE In general terms, the DECODE I MODULE decodes a hybrid word by reading it from the MEMORY MODULE and if the flag bit indicates the word is an absolute word, the DECODE I MODULE outputs the word, passing it directly to the calling module The DECODE I MODULE saves the absolute word which has been outputted and then reads another hybrid word from the MEMORY 10 MODULE If the flag bit indicates that the new word is a bit string word, then the bit string word is stored in a shift register and shifted until a "I" bit (bit of predetermined value) is shifted out of the register With every shift, the previous absolute word value is counted down and each time a "I" bit is shifted out of the shift register, the state of the counter is outputted as the absolute word 15 B Components The DECODE I MODULE includes counters MARI, MLNI, D Ol, and BCTRI Counter MARI is a 256 state counter of type SN 74161 in the above TTL book Counter MLN 1 is formed of an SN 74191 type counter disclosed at page 417 of the above TTL book and counts up responsive to each true signal applied at the 20 Ct input The MLNI counter is also set to a state corresponding to the input signals applied at its upper side responsive to a true signal at the L or load input Internal gating (not shown) forms a true signal at Mo when the MLNI counter is at state 0. Counter BCTR is an 8 state counter Counter DOI is an 8 bit 128 state counter. Both counters BCTR and D Ol are formed of an SN 74191 type counter disclosed at 25 page 427 of the above TTL book These counters operate as follows: a true signal at the CLR input resets the counters to state 0, a true signal at the L input causes the counters to be set to a state represented by the information input signals applied at its upper input Each true signal at the Ct input causes the counter to count up one state Counter BCTR has logic (not shown) for forming a true output signal at Bo 30 and Bo when the counter is at state 0 and not at state 0, respectively. Also included in the DECODE I MODULE is an INRI register Contained therein is a shift register 202 The shift register 202 is a 7 binary bit storage register formed of the type SN 74199 disclosed at page 456 of the above TTL book. The DECODE I MODULE also includes flip flops Pl through P 5, forming a 35 control counter 213, and flip flops DIFST, EOFI, DISW, DIEND, MSBI, SIFF and DGE Each of these flip flops is formed of type SN 7474 disclosed herein in section I F, Conventions Used in the Figures. One-shot multi-vibrators DIGO, DIMEND are also provided Each of these one-shot multi-vibrators is characterized whereby a true signal applied at its input 40 causes the indicated output to receive a true signal for a time period equal in length to the time period between the beginning of one clock pulse and the beginning of the next clock pulse at CLK The DECODE I MODULE includes a source of equally spaced recurring clock pulses 240. The DECODE I MODULE also includes the necessary logic to control the 45 various registers, flip flops and counters as indicated by logical equations using the notation indicated hereinabove with respect to the ENCODE MODULE In addition, specific AND gates 216, 218, 220, 222 are shown and OR gates 224, 226, 228, 230, 234 and 235 are shown The AND gates 218, 220, and 222 are actually indicated schematically and comprise eight individual AND gates (not shown) for 50 gating eight bits of information through to the corresponding outputs from the indicated source of information along the heavy line inputs The second input to each of the eight AND gates within AND gates 218, 220 and 222 is connected to the indicated control logic indicated by logical equations The output of the AND gates within each of the AND gates 218, 220 and 222 are OR'd together by the OR gate 55 226 and provided as an eight binary bit information input to the MLNI counter. The rest of the AND and OR gates are also conventional gates well known in the computer art and need no further explanation other than that provided in the following detailed description. The output of AND gate 216 is indicated by the symbol CLK corresponding to 60 clock The output of an inverter 232 is indicated by the symbol CLK corresponding to the logical inverse of the clock signal CLK similar to the ENCODE MODULE. The required input and output control lines to the DECODE I MODULE are indicated along the right hand side of Fig 9; also indicated along the right hand side of Fig 9 are the information input and output circuits using the system of notation described hereinabove. Referring to the right hand side of the DECODE I MODULE figure, the information inputs to the DECODE I MODULE are shown in heavy lines and are LNI from IPRF, MLN 3 from the ENCODE MODULE and ORT 2 from the 5 OUTPUT MODULE The output from the DECODE I MODULE is from the DOI counter (heavy line), the EOFI output of the EOF 1 flip flop, the DIMEND output of the one-shot multi-vibrator D IMEND, and the output of a gate represented by the logical equation P 2 D 1 SW The information output from the DOI counter is the absolute words that have been decoded from hybrid form The 10 signal at DIMEND indicates the completion of each resultant absolute word in the DOI counter, thereby indicating to the calling module that it can read the absolute word from DOL A true signal at the EOFI output indicates that the number of hybrid words, and hence the length of the memory area, indicated by the words stored in the MLN 1 counter, have been converted and therefore the hybrid 15 occurrence vector has been completely decoded. C Detailed Description Table 13 gives the symbols for the important counters, registers and flip flops in the DECODE I MODULE of Figs 9 and 10 and indicates the length thereof and the primary output of the DECODE I MODULE Table 11 shows the primary 20 inputs Fig 11 is a flow chart indicating the sequence of operation of the DECODE I MODULE using similar notation to that described hereinabove with respect to the ENCODE MODULE Reference to the DECODE I MODULE flow diagram should be made in reading the following description to aid in a complete understanding of the present invention 25 Similar to the ENCODE MODULE, the OR gate 234 is responsive to an initial signal applied at MINIT by the MINI COMPUTER to apply a true signal to the resetting input of each of the flip flops P 1-P 5, resetting them to 0 Also, OR gate 235 responds to the MINIT signal for initially resetting the DCE flip flop at 0. The DECODE I MODULE, as mentioned above, is called by any one of the 30 following modules: PIPE, SEED, REVOLVE, BRIGHTNESS, OUTPUT and INTERFACE The MINI COMPUTER, as later described through the DPM INTERFACE MODULE or one of the other modules stores into one area of the MEMORY MODULE a hybrid coded occurrence vector This hybrid coded occurrence vector is to be converted to absolute coded occurrence words using the 35 DECODE I MODULE (and/or DECODE II MODULE) A calling module initializes the DECODE I MODULE by placing the number of words (length) of the hybrid form occurrence vector to be converted into the MLNI counter and by setting the D l FST flip flop to a 1 state, indicating that the first call to the DECODE I MODULE is occurring 40 The length of the occurrence vector is provided to the DECODE I MODULE from different sources according to the calling module as follows: PIPE MODULE LNI from IPRF; SEED MODULE LNI from IPRF; REVOLVE MODULE MLN 3 counter from ENCODE MODULE; BRIGHTNESS MODULE LNI from IPRF; OUTPUT MODULE LNI from IPRF or ORT 2 register in 45 OUTPUT MODULE; CHANGE MODULE LNI from IPRF; INTERFACE MODULE LNI from IPRF Loading MLNI is as follows: a true signal applied by the OUTPUT MODULE at OM 16 or OM 17 causes AND gates 218 and 222 and OR gate 226 to couple the length value from LNI of IPRF and ORT 2, respectively, to the information input of the MLNI counter The CHANGE MODULE loads 50 the MLNI counter and the SEED MODULE calls the DECODE I MODULE To this end, the CHANGE MODULE applies a true signal at the CM 4 output, causing the AND gate 218 and the OR gate 226 to couple the length value from LNI of IPRF to the information input of the MLNI counter The SEED MODULE applies a true signal at the SM 2 output which causes the AND gate 218 and OR gate 226 to 55 couple the length of occurrence value from LNI of IPRF to the information input of the MLNI counter The REVOLVE MODULE applies a true signal at RM 14 to cause gates 220 and 226 to couple the length of occurrence value from counter MLN 3 of the ENCODE MODULE to the information input of counter MLNI. One of the REVOLVE, SEED, OUTPUT, PIPE, BRIGHTNESS, and DPM 60 INTERFACE MODULES then sets the DIFST flip flop to a 1 state via OR gate 228 by applying a true signal, respectively, at the corresponding output Pl 1, RM 2, SM 4, B 3, O M 21, and Dl l which, as indicated above, indicates that the first call of the DECODE I MODULE is occurring. 1,570,344 Subsequently, the calling module triggers the DIGO one-shot multivibrator, causing it to apply a control pulse at its DIGO output Di GO is triggered by the gate 230 which receives its control pulse from one of outputs P 13, SM 6, RM 4, B 5, and D I GO. A true signal at output Dl GO sets the DCE flip flop to a 1 state, causing a true 5 signal at the DCE output which, in turn, enables AND gate 216 to couple clock signals from the clock 240 to the CLK output Similar to the ENCODE MODULE, the inverter 232 forms the logical inverse of the clock formed at CLK at its output at CLK. Since all of the flip flops of the control counter 213 are initially reset to zero, 10 true signals are now formed at the outputs P 1, P 2, P 3, P 4 and P 5 and the clock pulse at CLK causes flip flop Pl to be set to a 1 state and DIBI Iof the DECODE flow is entered. During D l B 1, the state of the D l FST flip flop is checked, assuming that this is the first call on the DECODE I MODULE The DIFST flip flop is in a 1 state, 15 causing a true signal at the DIFST output Additionally, the Pl flip flop is in a 1 state Accordingly, DIB 2 of the DECODE I MODULE flow is entered where the true signals at PI, DIFST and CLK cause the DISW flip flop to be reset to a 0 state The clock pulse at CLK in combination with the true signals at the Pl and Dl FST outputs causes each of the Dl END, Dl FST and EOFI flip flops to be reset 20 to an 0 state and cause the MA Rl and BCTR 1 counters to be reset to an 0 state. Additionally, the clock at CLK in coincidence with the true signal at output Pl causes flip flop P 2 to be set to a 1 state and flip flop Pl is reset to an 0 state. The DIFST, EOF 1, D 1 SW and D 1 END flip flops have been reset at this time for the following reasons The Dl FST flip flop is reset at this time to indicate that 25 the resetting operation during Dl B 2 has been completed This is the only function of the DIFST flip flop EOFI is reset at this time to indicate that the hybrid words in the occurrence vector have not been completely converted The Dl SW flip flip is used to indicate within the DECODE I MODULE that a MEMORY MODULE read is necessary The 0 state of the DISW flip flop indicates that a read from 30 MEMORY MODULE is necessary to obtain a hybrid word This will subsequently take place during Dl B 5 A 1 state of the D 1 SW flip flop is used to indicate that a read is unnecessary and, as will be explained subsequently, DIB 5 is skipped when D I SW is in a I state The D 1 END flip flop is an internal flip flop and, when set into a 1 state, indicates to the DECODE I MODULE that after conversion of a hybrid 35 coded occurrence vector the last absolute word has been outputted or passed to the calling module To be explained in more detail, when the D 1 END flip flop is set to a 1 state, any subsequent call on the DECODE I MODULE by the calling module will force the DECODE I MODULE to form an end of file indication by setting the EOFI flip flop to a 1 state 40 Following DIB 2, DIB 3 is entered During DIB 3, the P 2 flip flop is in a 1 state and the DIEND flip flop is checked If during DIB 3 the D 1 END flip flop is in a 1 state, which, as discussed above, occurs when the calling module provides the last word of a hybrid occurrence vector, DIBI 9 of the DECODE I MODULE flow is entered 45 The action of the clock suspension logic should now be noted The true signals at P 2, D I END and CLK reset the DO 1 counter to 0 and cause the clock suspension logic 222 to form a true signal at the OR gate 235 causing it to reset the DCE flip flop to O and trigger the one-shot D IMEND Resetting of the DCE flip flop to an 0 state removes the true signal at output DCE and causes the AND gate 216 to 50 remove the clock signals at CLK, thereby causing the DECODE I MODULE operation to EXIT and await the next call on the DECODE I MODULE The oneshot DIMEND then forms a true signal at output DIMEND which causes OR gate 234 to reset flip flops P 1-P 5 to 0 The subsequent operation caused by the D 1 END flip flop being in a 1 state will be further described hereinafter 55 The above action of the clock suspension logic 222 is important and should be kept in mind as a similar action is enabled by the clock suspension logic when any one of the other logic conditions indicated for the clock suspension logic 222 becomes true. Assume that during DIB 3 the last word of a hybrid occurrence vector has not 60 been provided, and the D 1 END flip flop is in an 0 state, causing a true signal at the D IEND output Dl B 4 is entered where the state of the D ISW flip flop is checked. It will be recalled that the DISW flip flop in a 1 state indicates that the MEMORY MODULE read operation is to be skipped, whereas if in an 0 state, causes aMEMORY MODULE read Assume that the DISW flip flop is in an 0 state DI BS 65 1,570,344 is entered where the memory read actually takes place. An input to the DECODE I MODULE is the SM 10 output of the SEED MODULE To be explained in more detail, the SEED MODULE uses the DECODE I MODULE when computing the number of lines to be skipped in an iso-entropicgram However, the SEED MODULE when computing the lines to be 5 skipped, does not require the length value in counter ML Nl to be decremented. Accordingly, the SEED MODULE normally forms a true signal at output SM 10 but removes the true signal when computing the number of lines to be skipped, thereby inhibiting counter MLNI from being decremented. However, for the present description, assume that a true signal is formed at 10 SM 10 True signals are also formed at P 2 and D 1 SW Therefore the MLNI counter receives a true signal at its Ct input, causing MLNI to be counted down one state reflecting the fact that one word of the hybrid occurrence vector is being read from the MEMORY MODULE The logic P 2 Dl SW CLK being true causes a true signal at the Ct input of MARI, causing MA Rl to be counted up one state, 15 reflecting the fact that the next word of the hybrid occurrence vector is to be addressed in the MEMORY MODULE The true signals at P 2 and D I SW cause a true signal to be formed at the DM 11 output of the DECODE I MODULE, thereby signalling the MEMORY MODULE, causing it to read out the content of the proper memory area specified by the SWITCH MATRIX at the memory location 20 specified in the MA Rl counter prior to its being counted up. The control signal at P 2 enables the 8 bit word read-out of the MEMORY MODULE to be stored into the INRI register The true signal at P 2 causes the most significant bit ( 8 bit) of the word read from the memory to be stored in the MSB 1 flip flop The true signal at P 2 also goes to the S/L input circuit for the shift 25 register 202 causing the remaining 7 bits of the word from the MEMORY MODULE to be loaded into the register 202 when the clock signal is applied from logic P 2 DISW CLK Accordingly, at the end of D 1 85 of the DECODE I MODULE flow a hybrid word has been read from the MEMORY MODULE from the appropriate memory area and has been stored in the INRI register and the 30 MLNI counter has been decreased by one so that the length of occurrence vector contained therein indicates the remaining words to be read from the MEMORY MODULE. Assume now that the word stored in the INRI register is an absolute hybrid word It will be recalled that the first word of every hybrid occurrence vector 35 string will always be an absolute word When the word stored in INRI is an absolute word, the flag bit, the most significant bit of the hybrid word, is stored in the MSB I flip flop and causes the MSB I flip flop to be in a I state With the MSB 1 flip flop in a 1 state, true signals are formed at the MSB 1 and P 2 outputs. Accordingly, the P 5 flip flop is set to a 1 state and DIB 8 is entered 40 A true signal is formed at the P 5 output and the following pulse at CLK causes a true signal at the L input of the DO 1 counter, causing the 7 bits in the shift register 202 of the INRI register to be loaded into the DOI counter The true signal at P 5 in coincidence with the pulse at CLK enables the clock suspension logic -222 to reset the DCE flip flop to an 0 state, thereby disabling the clock at CLK out of 45 the gate 216 and resetting counter 213 An EXIT is taken to await the next call The next call is initiated by a control signal, as described above at one of the inputs to OR gate 230. If, during the true signal at P 2 the word in the INRI register read from memory is a bit string word, the MSB 1 flip flop is an 0 state and true signals are formed at 50 the MSB 1 and D I SW outputs and the P 3 flip flop is set to a 1 state, thereby causing Dl B Il of the DECODE I MODULE flow to be entered. At the beginning of processing of each bit string word of a hybrid occurrence vector, the BCTRI counter is in an 0 state having been set there at DIB 2. Therefore, during the first entry into Dl B 11 of the DECODE I MODULE flow, 55 the BCTRI counter is in an 0 state Accordingly, a true signal is formed at the Bo output of the BCTRI counter so indicating The true signal at Bo in combination with the true signal at P 3 causes the P 4 flip flop to be set to a 1 state and D l B 13 is entered. During DIB 13, the BCTR 1 counter is loaded with a signal representing the 60 maximum number of bits in a hybrid word to be processsed To this end, true signals are now formed at the P 4 and BO outputs and the following pulse at CLK causes the L input of the BCTRI counter to be energized and the value 7, represented by the setting of the switches 236, is loaded into the BCTRI counter, and DIB 14 is entered 65 1,570,344 During Dl B 14 of the DECODE I MODULE flow a true signal is formed at the P 4 output Accordingly, the shift register 202 is repeatedly shifted one bit to the right until a one bit indicating an occurrence is shifted out of register 202 into the S 1 FF flip flop Each bit shifted out of the least significant end of the register 202 is stored in the sign flip flop S 1 FF During Dl B 15 of the flow a true signal is formed 5 at the P 4 output and the pulse at CLK causes the Ct input of the BCTRI counter to be energized and count the counter down one state The same signals cause the CT input of the DOI counter to be energized and the counter DOI to count down one state For each right bit shift of the register 202, the number of bits left to be processed in the INRI register identified by the state of the BCTRI counter is 10 counted down one and the absolute word value indicated by the DOI counter is counted down one state This operation continues until a 1 bit is shifted out of the shift register 202 into the sign flip flop SIFF thereby causing a true signal at the SIFF output The state of the DOI counter at this time is an absolute word representing the actual value of the occurrence represented by the 1 bit shifted out 15 of register 202 into the S 1 FF flip flop and accordingly, the state of the DO I counter is to be outputted to the calling module. To this end, signals are formed at the P 4 and 51 FF outputs and the following signal at CLK causes the DCE flip flop to be reset to an 0 state and fires the DIMEND one-shot causing a true signal at the DIMEND output signalling the 20 calling module that an absolute word is completed and contained in the DOI counter The D 1 MEND signal resets the control counter 210 to 0 The formation of the signal at D l MEND indicates completion of an absolute word and is referred to herein as outputting the absolute word. Several important special conditions should be noted If, during DIB 15 and 25 the I state of the P 4 flip flop, the content of shift register 202 is not 0, it means that there is a remaining 1 bit (representing an occurrence) yet to be converted to absolute form in a bit string word Accordingly, a true signal is formed by register 202 at 10 causing the Dl SW flip flop to be set to a 1 state at the following pulse at CLK The 1 state of the DISW flip flop is used during the following entry into 30 Dl B 4 of the flow to bypass the reading of another word from the MEMORY MODULE The reason for this action is that with the D 1 SW flip flop in a 1 state, a new hybrid word will not be read from the MEMORY MODULE following DIB 14, as there is still at least a portion of a bit string word remaining in the shift register 202 to be converted to absolute form 35 Referring to DIB 17 of the flow, whenever the bit string word contained in register 202 of the IN Rl register goes to zero by virtue of the fact that all of the 1 bit (or occurrence) of the bit string word has been shifted out thereof, a control signal is formed at the IO output of the shift register 202 When this occurs another hybrid word must be read from the MEMORY MODULE during DIB 5 A true 40 signal is formed at the outputs P 4 and IO causing the D l SW flip flop to be reset to a 1 state at the next pulse at CLK The 0 state of the DI SW flip flop, during the following entry into D IB 4, causes D IB 5 of the flow to be next entered where a new hybrid word is read from MEMORY MODULE into the DECODE I MODULE for conversion When the last word of a hybrid occurrence vector has been read 45 from the MEMORY MODULE, the length of occurrence vector value contained in the MLNI counter will have been counted down to 0, and a control signal is formed at the Mo output of the ML Ni counter A true signal at Mo and a true signal at the P 5, the P 4 and 10 outputs causes the D 1 END flip flop to be set to a 1 state at the next pulse at CLK thereby indicating that the last absoute word has 50 been outputted to the calling module With the DIEND flip flop in a I state, the following call on the DECODE I MODULE flow will cause the EOFI flip flop to be set to a 1 state responsive to true signals at the P 2 and DIEND outputs at the occurrence of the pulse at CLK. One further special situation with respect to the DECODE I MODULE should 55 be noted If, during the I state of the P 3 flip flop, the BCTRI counter is not in an 0 state, then D 1 812 and DB Bl of the flow are utilized to insure that the proper alignment is made from one bit string word to another This is necessary when the last 1 bit of a bit string word has been converted to absolute word form and outputted, and leading 0 bits remain in the bit string word under conversion in the 60 shift register 202 These leading 0 bits must be taken into account in forming the next absolute work for output. Referring to D B 1 and D 1 812 of the flow and the corresponding action, a true signal at the P 3 output in coincidence with a true signal at the Bo output causes the BCTRI counter, as well as the DOI counter, to be counted down one 65 1,570,344 state responsive to each-pufse at LK As a result, the absolute word being formed in DOI is adjustedf downward by the number of leading O 's remaining in shiftregister 202-which are indicated by the state of BCTR 1 Finallly, when the BCTR 1 counter reaches an 0 state a control signal is formed at the Bo output and the true signal is removed at the CO output terminating the counting of the SBCT Rl and DO I counters and causing B 1 B 13 of the flow to be entered as explained above. D Example of Operation Consider now an example of the operation of the DECODE I MODULE. Assume that four words, making up a hybrid occurrence vector, are contained in the memory area 1 of the MEMORY MODULE and are to be converted from hybrid to absolute word form. EXAMPLE Assume the following is in the memory area I of the MEMORY MODULE: 11 00 00 111101 100010 00 1 O 1 O 1 00 ( 125) ( 123, 119) ( 116, 114) ( 100) The physical length in words is 4. Therefore it is the calling program's responsibility to load MLNI v 4 and set the initialize flip flop D 11 FST to 1. First call MLNI = 4 DIFST = 1 sequence of control ' DIBI DIB 9 D 1 BI Dl FST= 1 controlto DIB 2 DIB 2 DIFST=DIEND=EOF 1 =Dl SW= 0 resetthes MA Rl = 0, BCTR 1 = 0 initialize DIB 3 Dl END= O controlto DIB 4 DIB 4 Dl 1 SW = O controlto D 1 B 5 DIB 5 read memory into INR 1 do the rea INRI = 11111101 ( 125) the result; MARI ( 1) = MA Rl ( 0)1 memory MLNI ( 3) = MLN 1 ( 4)1 decrease t DIB 6 MLN 1 ( 3) O ' control to DIB 7; D 1 B 7 MSB(INRI) = 1 ' control to DIB 9 AOI form DIB 9 Dol ( 125)=INR 1 ( 125) D 15 W= O BCTR 1 = O EXIT output Dol = 125 EOF 1 = 1 se flip flops; these registers address to next position; the number of words input becomes the output; assure a read on the next call and set BCTR 1 to zero; Second call initial conditions: DIFST = 0 MLNI is not clocked sequence of control DIBI, D 1 B 3-D 1 87, Dl B 11, Dl B 13-Dl B 16, Dl B 14-DIB 17 Dl Bl Dl FST = O controlto D 1 B 3 D 1 B 3 D 1 END = O ' control to D 1 B 4 DIB 4 D 1 SW = O controlto D 1 B 5 DIB 5 read memory do the read to INRI; INR 1 = 00100010 MA Rl( 2) = MA Rl(I) + 1 increase address pointer; MLNI( 2) = MLNI( 3) 1 decrease length register; DIB 6 MLNI O controlto Dl B 7 D 1 B 7 MSB(INR 1) = O ' control to DIB 1 l D 1 BII BCTRI= O controlto Dl B 13 DI B 13 BCTR 1 = 7 this counter monitors how v much of the input register remains to be processed; 1,570,344 ad; 1,570,344 DIBI 4 INRI 000100001 SIFF= O DIB 15 BCTRI( 6)=BCTR( 7)-1 Dol( 124)=Dol( 125) I D 15 W= I D 1 B 16 51 FF = O controlto DIB 14 D 1 B 14 INRI = 00001000 SIFFF= 1 DIB 15 BCT Ri( 5)=BCTRI( 6)-I 1 Dol( 123) = Dol( 124) -1 Di B 16 SIFF=l ' controlto DIB 17 DIB 17 INRI O HALT Output Dol = 123 EOF 1 = O EXIT reduce the number of bits to be processed and reduce the previous output set D 1 SW to indicate no read is necessary on the next call; shift INRI; SI 1 FF = I because of the shift output from INRI decrement bits remaining; decrement previous output; Third call just assert sequence of control DIBI 1 DIB 3 J DIB 4 DIB 14 same as before DIGO DIBI, D 1 83-D 1 84, D 1 B 14-D 1 B 16, DIB 14-DIB 16, D 1 814-DIB 16, D 1 814-D 1 B 18 DISW= 1 ' control to DIB 14 INR 1 = 00000100 SIFF = O DIB 15 BCTRI( 4)=BCTR 1 ( 5)-1 Dol( 122)= 123) 1 DISW= 1 DI B 16 Sl FF = O controlto D 1 B 14 DI B 14 INRI = 00000010 SIFF= 0 DIBI 5 BCTRI( 3) = BCTRI( 4) 1 Dol( 121)=Dol( 122) 1 DIB 16 Sl FF = O controlto D 1 B 14 DIB 14 INR 1 = 00000001 51 FF = O DIB 15 BCTRI( 2)=BCTRI( 3) 1 Dol( 120) = Dol( 121) I DIB 16 SIFF= 0 controlto DIB 14 Dl B 14 INRI = 00000000 SIFF= 1 DIB 15 BCTRI(I) = BCTRI( 2) 1 Dol( 1 19) = Dol( 120) DIB 16 Sl FF=l controlto D 1 B 17 DIB 17 IN Rl= O controlto D 1 B 18 DIBI 8 DISW= 0 EXIT output shift INR 1 right; S 1 FF = 0 since "shift out" from INRI = O assure a read on the next call; Dol= 119 EOFI= O Fourth call DIGO to 1 sequence of control DIBI, DIB 3-DIB 7, DIBI-D 1 812, D 1 Bll, D 1 B 13-D 1 B 16, D 1 B 14-D 1 B 17 DIBI s D same as above DIB 3 J D 1 SW = O control to DIB 5 read memory INRI = 00001010 MA Rl( 3) MA Rl( 2) + 1 MLNI(I) MLNI( 2) 1 read into INR 1; bump the memory address; decrement the length DIB 4 Dl B 5 1,570,344 48 -DIR 6 MLNI O controlto DIB 7 D 1 B 7 MSB(INRI) = O,control to DIB 11 D 1 Bl L 1 B CYR(U 0 control to D 1 812 DIB 12 BCTRI(O) TRI( 1) 1 the value in BCTRI is ameasure Do 1 ( 1 18) =:Dol(1the unshifted bits from the previo read, Do 11 must be decrement' D 1 811 B CTR 1 ( 0) =OC controltoll DIB 13 BCTRI = 7 bis rcse N this word; DIB 14 INRI = 00000101 Si FF = O DIB 15 13 CTR( 6)=BCTR( 7) 1 Do 1 ( 117) =Do 1 ( 118) 1 D 1 SW = 1 no read necessary next time; DIB 16 S 1 FF = 0 control to Dl B 114 D 1 B 14 INRI 1 = 00000010 SIFF = 1 DIB 15 BCTR 1 ( 5)=BCTR 1 ( 6) 1 Do 1 ( 116) =Do 1 ( 117) 1 D 1 B 16 S 11 FF 1 l control to Dl B 117 DIB 17 INRI O EXIT output of us ed Dol= 116 EO Fl=O Fifth call set DIGO sequence of control Di 111, D 11 83-D 1)14, DIB 14-DIB 16, DIB 14-DIB 18 DB}same as above Dl B 3 J Di B 34 DISW = 1 controlito DI B 114 DIB 14 IN R 11 = 00000001 shift INR I right; SIFF = O DIB 15 BCTRI( 4)=BCTRI( 5 'i-1 Dol(I 15)'=Dol( 116 j- 1 DISW= 1 DI 1 86 S 1 FF = C control to Dl B 114 DIB 14 INR 1 = 00000000 SIFF= 1 Bl D 15 BCTR 1 ( 3)=BCTR 1 ( 4) 1 Dol(I 14)=Dol(I 15) 1 DIBI 6 SIFF= 1 ' controlto Dl B 17 DIB 17 INRI = 0 controlto Dl B 18 DIB 18 D 15 W= 0 EXIT Output read next time; Dol= 114 EOF 71 = 0 Sixth call set DIGO sequence of control DIBI}same as before D 1 B 3 J Di 1 84 DIRB 15 DIB 16 Di RB 10 Dl B 7 DIBI, DIB 3-DIB 6, D 11310, D 11 87-DIB 9 Di 1 SW = O control to Di R 15 Memory read INRI = 1 1100100 MAR 1 ( 4) = MAR 1 ( 3) + 1 MLN 1 (O)=MI-N 1 ( 0) 1 MI-NI= O control to DIB 10 DIEND= 1 MSB(INRI) = 1 control to D 118 D 19 BCTRI 1 = O DISW= 0 Dol = 100 ( 01 100100) EXIT assures an E O F 1 on next call; reset the sign bit; i 5 1,570,344 output Dol = 100 EOFI = O Seventh call set DIGO sequence of control DIBI, DIB 3, DIB 19 DI B 1 same as above DIB 3 Dl END= 1 controlof DIB 19 5 DIB 19 EOFI = l Dol = I EXIT output Dol= 0 EO Fl=I note the output retrieved was 125, 123, 119, 116, 114, 100 -the same as was 10 encoded before. In summary, it will be seen that what has been disclosed is a decoder for converting hybrid coded signals to absolute coded word signals The hybrid signals represent a series of occurrence values of decreasing value The hybrid signals have a series of received binary coded word signals including at least one absolute coded 15 word and a bit string word The bit string word represents an occurrence by the number of bits of displacement of a bit of predetermined value (i e, 1) from an absolute word in the series of hybrid words A hybrid word also includes a flag signal indicating the type of word The decoder includes an absolute word outputting means including the D 1 MEND one-shot multi-vibrator and its logic and 20 the MSB 1 flip flop and a control counter 213 operative during D 1 89 of the flow in response to an absolute word flag signal of a received hybrid word signal for outputting the received word signal In other words, the outputting means is responsive to the absolute word flag signal for directly outputting the corresponding hybrid word since it is already in absolute word form 25 The decoder also includes absolute word signal forming and outputting means. The means includes the INRI register and its shift control logic, the SIFF flip flop, the DOI and BCTR 1 counters and their load and count control logic and the control counter 213 which are operative during DRB 14, 16, 7-9 in response to an absolute word signal and each bit of predetermined value in a subsequently 30 received bit string word for forming an absolute word signal indicative of the actual value of the bit of predetermined value Also included is means such as the D 1 MEND one-shot multi-vibrator and its control logic operative during Di B 16 for outputting each of the absolute word signals formed thereby The true signal at DMEND outputs the absolute word signal represented by the state of the counter 35 D Ol. In a preferred embodiment, the means for forming and outputting the absolute word signal includes the shift register 202 in register INRI for storing a received bit string word signal Also included is means including the INRI register and its shift control logic and the control counter 213 operative during DIB 14 for repeatedly 40 enabling the shifting of the content of the shift register 202, 1 bit position in the direction of the least significant bit of the bit string word Also included is means including the 51 FF flip flop and the control counter 213 operative during Dl B 16 for providing an indication when a bit of predetermined value arrives at the output of the shift register 202 Also included is the counter DOI and means including the 45 D Ol load control logic and the control counter 213 operative during D 1 87-9 responsive to an absolute word flag signal of a hybrid word for setting the counter DO 1 to a state, relative to the reference ( 0) state thereof, which corresponds to the value of the absolute word signal Means including the DOI count control logic and the control counter 213 is operative during Dl B 15 for enabling the counter to 50 count one state towards its reference state for each shift of the shift register 202. Means including the DIMEND one-shot multi-vibrator and its control logic and the control counter 213 is operative during DIB 16 in response to the bit of predetermined value in the Sl FF flip flop for outputting the state of the counter by forming a true signal at DIMEND 55 In a further preferred embodiment there is means for adjusting the counter DOI for bits which are not of the predetermined value (e g, 0) which remain in the shift register 202 after decoding the last bit of predetermined value in a hybrid word Included is an additional counter means such as the BCTRI Means including the switches 236 indicate the maximum number of bits in an absolute 60 word for output Means including the BCTRI load control logic and control 1,570,344 counter 213 is operative during DIBII-13 for selectively setting the additional counter means BCTRI to a state relative to a reference state (e g, 0), which corresponds to the indication of the maximum number of bits in an absolute word signal Means including the BCTRI count control logic and control counter 213 are operative during DIB 15 for enabling the additional counter means BCTRI to 5 count one state, relative to the set state thereof towards the 0 reference state for each shift of the shift register means 202 The Bo output of the BCTRI counter indicates the occurrence of the reference state of BCTRI Means including the count control logic of BCTRI and control conter 213 is operative during DIB 12 in response to the flag signal of a bit string word signal stored in MSB 1 and the 10 indication at Bo indicating the lack of a reference state of BCTR 1 for further enabling the counting of the counter DO 1 and BCTR 1, one count for each shift of the shift register means 202 By this arrangement the high order 0 bits which are not of the predetermined value which are left in the shift register 202, after all bits of predetermined value are shifted out, are reflected into the absolute word signal 15 under formation in shift register 202. IV DECODE II MODULE Fig 12-14 form a schematic and block diagram of the DECODE II MODULE The DECODE II MODULE is basically constructed the same as the DECODE I MODULE except as described below Two decode modules, 20 DECODE I MODULE and DECODE II MODULE, are needed in the system in order to decode the occurrences of an occurrence vector from hybrid to absolute coded words and provide the resultant absolute coded words in two streams at different rates DECODE I MODULE and DECODE II MODULE provide their respective streams of absolute coded words, one word (or occurrence) at a time 25 when called. The DECODE II MODULE is virtually identical to the DECODE I MODULE as mentioned above In keeping with the virtual identical structure, the same symbols are used to denote the various parts of the DECODE II MODULE as are used for the DECODE I MODULE However, in some instances a 1 in a 30 symbol for the DECODE I MODULE is changed to a 2 in the DECODE II MODULE to help simplify the description or distinguish between lines going between modules The components whose identity and symbols have been changed in the DECODE II MODULE by changing a 1 to a 2 are identified below. DECODE I DECODE II 35 BCTRI BCTR 2 DOI D 02 INRI INR 2 MARI MAR 2 MLNI MLN 2 40 D 1 FST D 2 FST EOFI EOF 2 D 1 GO D 2 GO D 1 MEND D 2 MEND A data selector DD 51 similar to that described above replaces the gates 45 218-226 of the DECODE I MODULE for gating the occurrence vector length into counter MLN 2 However, a gating circuit similar to the DECODE I MODULE could be used The occurrence vector length is coupled from the information source indicated along the top of DDS 1 to the MLN 2 counter responsive to true signals at the control lines indicated along the sides of the DDS 1 50 Additionally, the gating conditions indicated for the load or L input of MLN 2 differs from that of the DECODE I MODULE and should be noted. 1,570,344 The input control lines connected to gates 224 ', 228 ', 230 ' and 234 ', and the clock suspension logic 222 ', differ in minor respects from that of gates 224, 228, 230 234 and suspension logic 222 of the DECODE I MODULE and the primes are affixed to these symbols to so indicate. V DELTA MODULE 5 A General Description The DELTA MODULE breaks the number of lines to be revolved (in an isoentropicgram) from a calling module and breaks the number into smaller increments The implementation now to be described breaks the number of lines to be revolved into its largest possible component powers of 2 in decreasing value 10 order which, in turn, corresponds to the number of lines to be revolved This feature is described in the General Description with reference to Table 4C and is of importance because the lines in the iso-entropicgram can be derived with a minimum of XOR operations Also, by revolving from one line to another in an isoentropicgram where the second line is away from the first by a number of lines 15 equal to a component power of 2, the revolve to the second line is accomplished by a single shift and XOR operation. The DELTA MODULE, in operation, receives a binary coded number in the 1, 2, 4, 8 number code (from the calling module) representing the total number of lines to be revolved, and breaks the number into its largest possible component 20 powers of 2 The largest component power of 2 is formed first, followed by the other largest powers of 2 in decreasing order of magnitude Although the invention is not limited thereto, the DELTA MODULE about to be described operates on 8 bit words. The DELTA MODULE converts a number by storing it into a first register 25 and then shifting the number towards the most significant bit position, repeatedly, one bit position at a time A second register with the same number of bits as the first register has a "I" bit that is shifted towards the least significant bit position, one bit position each time the first register is shifted Since the two registers are shifted in opposite directions by the same amount whenever a " 1 " bit arrives at the 30 output of the first register, the " 1 " bit in the second register indicates directly the corresponding power of 2 of the 1 bit shifted out of the first register. Table 14 is a DELTA MODULE example illustrating how the above operation takes place The binary coded number to be converted represents the decimal number 13 and is stored in the first register in binary coded form, whereas the 35 second register is initially set to 0 Eight shifts are depicted, one for each bit of the number to be converted On the first shift, the first register is shifted 1 bit towards the most significant bit, whereas the second register has a 1 bit stored in the most significant end where it represents the binary coded number 128 With each subsequent shift of the first register towards the most significant bit, the second 40 register is shifted towards the least significant bit Following shift 5, a I bit for the first time is shifted out of the first register This indicates that the content of the second register, which now represents 8, can be read as it now contains the largest component power of 2 Also, 1 bits are shifted out following shifts 6 and 8 and the second register at these times represents the numbers 4 and 1, respectively Adding 45 8, 4 and 1 results in 13 which is the binary coded number originally stored in the first register. B Components The DELTA MODULE, Fig 15, contains inputs and output control lines indicated along the right hand side The system of notation described above in 50 section I F, Conventions Used in Figures, is used Additionally, there are information input and output lines These input and output lines carry multiple bits of information and are indicated by heavy lines. Two registers DELI and DELO are provided Register DELI includes an 8 flip flop shift register 302 and the register DELO includes an 8 flip flop shift register 55 304 Both of the registers DELI and DELO include a most significant bit flip flop, DELI containing MSBDELI and DELO containing MSBDELO MSBDELI has its input for setting it to a I state connected to the output SOUT of shift register 302. The output SOUT of register 302 is the umprimed output from the most significant flip flop in register 302 The MSBDELO flip flop in DELO has its MSBDELO (or 60 umprimed) output connected to the "IN" input of register 304 which is the set to I input of the most significant flip flop in register 304 Logic (not shown) in register 302 applies true signals at D Io and D Io when the register is 0 and not 0, 1,570,344 1 respectively The operating characteristics of shift registers 302 and 304 are the same as shift register 114 of the ENCODE MODULE Register 304 also has a CLR input which is responsive to a true signal at CLR to reset register 304 to 0 Shift registers 302 and 304 are of type SN 74198 disclosed at page 456 of the above TTL lock 5 A control counter 313 has two flip flops Pl and P 2 Additionally, control flip flops DELFST, DELEND and DELCE are provided The DELFST flip flop, when in a 1 state, indicates that the first call is occurring to the DELTA MODULE The DELEND flip flop in a 1 state indicates that the word stored in DELI has beencompletely converted into its component powers of 2 Thus, the 1 state of 10 DELEND is an indication that the DELTA MODULE has completed its operation The flip flop DELCE controls the formation of clock pulses at CLK. Each of the flip flops in the DELTA MODULE are of type SN 7474 described in section I F Conventions Used in Figures. One-shot multi-vibrators DELGO and DELMEND are contained in the 15 DELTA MODULE One-shot multi-vibrator DELGO is set to a 1 state pursuant to each call on the DELTA MODULE One-shot multi-vibrator DELMEND indicates each exit from the DELTA MODULE operation by a true signal at the DELMEND output and resets the module The one-shot DELGO and DELMEND have the same characteristics as the one-shot of the ENCODE MODULE 20 A source of clock signals formed by a clock 312 forms a series of regular recurring true pulses as depicted. The DELTA MODULE also includes OR gates 314, 315, 316, 317, 318 and 320, and an AND gate 322 These gates are conventional gating circuits well known in the computer art The output of AND gate 322 is designated CLK The inverter 25 324 is a conventional logical inversion circuit which forms the logical inverse of the signal at CLK, and the inverted signal is designated CLK. A selection circuit DELS is a conventional selection circuit of the same type disclosed in the section I-B above Selector circuit DELS couples 8 bits of information from any one of the designated three 8 bit inputs to a single 8 bit output 30 which is the information input into register 302. C Detailed Description The purpose of the DELTA MODULE is to receive a number representing the number of lines to be revolved and convert the number into its largest possible component powers of 2 in decreasing value order 35 The DELTA MODULE is called by either the REVOLVE MODULE or the OUTPUT MODULE The DELTA MODULE is called by the REVOLVE and OUTPUT MODULES by first setting the DELFST flip flop to a I state The OR gate 316 sets the DELFST flip flop to a 1 state and has inputs RMI and O M 2 from the REVOLVE and OUTPUT MODULES, respectively A control signal at either 40 the RM 1 output of the REVOLVE MODULE or the O M 2 output of the OUTPUT MODULE enables OR gate 316 to trigger the DELFST flip flop to a 1 state. Following the signals at either RMI or O M 2, the REVOLVE and OUTPUT MODULES, respectively, provide signals at the RM 3 and O M 3 outputs A control signal at either the RM 3 or O M 3 output energizes the OR gate 320, causing a true 45 signal to be applied to the one-shot DELGO, causing it to apply a true signal to the input of the DELCE flip flop This causes the flip flop DELCE to be set to a 1 state and causes the flip flops Pl and P 2 to be reset to an 0 state. The 1 state of flip flop of DELCE causes a true signal at the DELCE output which, in turn, enables the AND gate 322 to couple the clock signals from clock 50 312 to the CLK output The resulting true signals at the Pl and P 2 outputs of flip flops Pl and P 2 cause flip flop Pl to be set to a 1 state at the following pulse at CLK As a result, DIBI of the DELTA MODULE flow is entered. The source of the number to be converted is determined by control signals at the O M 2, CM 4 and SM 7 outputs of the OUTPUT, CHANGE and SEED 55 MODULES, respectively A true signal at O M 2, CM 4 or SM 7, respectively, causes the DELS selection circuit to gate the 8 bits of information from D 56 of the OUTPUT MODULE from CLINE of the CHANGE MODULE or from TI of the SEED MODULE, respectively, to the information input of the shift register 302. The signal at P 2 is now false, causing register 302 to be in a load mode of operation 60 and the true signal at SM 8 (SEED MODULE), O M 4 (OUTPUT MODULE), or CM 5 (CHANGE MODULE) enables the OR gate 314 to cause register 302 to store the 8 bit information signal from DELS. During the 1 state of the flip flop P 1, control signals are formed at the Pl and 1,570,344 53 1,570,344 53 DELFST outputs of flip flops Pl and DELFST, causing the MSBDELO flip flop to be set to a 1 state To be explained in more detail, the I state of the MSBDELO flip flop is used to enable a 1 bit to be shifted into the most significant bit position of the shift register 304 during the following shifts of register 302. The true signals at Pl and DELFST additionally cause the OR gate 318 to reset 5 the DELFST flip flop to an 0 state and reset the DELEND flip flop to an 0 state. Register 302 no longer contains all O 's, a number to be converted having been stored therein, therefore a true signal is formed at the D Io output indicating that the register is not 0 This signal, in coincidence with the true signal at P 1, causes the P 2 flip flop to be set to a I state and DB 3 is entered 10 The conversion is made by shifting register 302 containing the number to be converted towards the most significant bit and by shifting the register 304 towards the least significant bit The first shift shifts a 1 bit into the most significant bit position of register 304 from flip flop MSBDELO During DEB 3 of the flow, whenever the register 302 does not contain all O 's, a control signal is formed at the 15 D 1 o output in coincidence with the true signals at P 2 and MSBDELL Coincidence of these true signals cause the register 302 to be shifted one bit towards the most significant bit position, causing the most significant bit in register 302 to be stored in the MSBDELI flip flop and causing the register 304 to be shifted 1 bit position towards the least significant bit position During the first shift, the MSBDELO flip 20 fip is in a 1 state, causing a 1 bit to be stored in the most significant bit position or flip flop of the register 304 It will be noted that the DELTA MODULE flow indicates a "SHIFT DELO rt" and "SHIFT DELO Ift" "SHIFT DELO rt" indicates a shift right towards the least significant bit position of register 304 whereas "SHIFT DELI Ift" indicates a shift left towards the most significant bit 25 position of the register 302. Following DB 4, DB 5 of the flow is entered where the MSBDELI flip flop is checked If the MSBDELI flip flop is not in a 1 state, i e, a 1 bit having been shifted there from register 302, DB 4 of the flow is again entered where the above shift is repeated in the same manner as described above The shifting process 30 continues until a 1 bit is stored into the MSBDELI flip flop When this occurs, DB 6 of the flow is entered. The 1 state of the MSBDELI flip flop causes a true signal at the MSBDELI output The true signals at P 2, MSBDELI and CLK trigger the one-shot DELMEND to a 1 state, causing a true signal at the DELMEND output from the 35 DELTA MODULE and additionally resetting the DELCE flip flop to a 0 state, thereby preventing the AND gate 322 from applying additional clock pulses at CLK and causing the shifting to terminate and operation of the DELTA MODULE flow to EXIT The true signal at the DELMEND output indicates to the calling module that it has finished processing and that the word contained in register 304 of 40 DELO may be read as it now contains one of the component powers of 2 of the input number originally stored in register 302 The true signal at output DELMEND also enables OR gate 315 to reset control counter 313 to 0 (i e PI, P 2 = 0) The true signals at P 2, MSBDELI and CLK reset the MSBDELI flip flop to a 0 state 45 The DELTA MODULE is again called by either the REVOLVE MODULE or the OUTPUT MODULE by applying control signals at either the RM 3 or O M 3 outputs Either of these signals cause the OR gate 320 to again trigger the one-shot DELGO which, in turn, sets the DELCE flip flop to a 1 state, enabling the AND gate 322 to form pulses at the CLK output Both the Pl and P 2 flip flops are in 0 50. states, accordingly, flip flop Pl is set to a 1 state at the folllowing pulse at CLK. After the first call (signal at RM 3 or O M 3), the DELFST flip flop is in a 0 state, accordingly, DB 3 of the flow is entered, followed by DB 4-6, as described above. During each entry into DB 4 and DB 5, the shift registers in DELI and DELO are shifted until another 1 bit is stored in MSBDELI, causing another true signal at the 55 output DELMEND, indicating to the calling module that a new component power of 2 is now in register 304 for output. Finally, when the last I bit of the input number contained in register 302 is shifted into the MSBDELI flip flop, the content of register 302 is 0, causing a true signal at the D Io output If this occurs while the Pl flip flop is in a I state, the 60 following pulse at CLK sets the DELEND flip flop to a 1 state If it occurs while the P 2 flip flop is in a 1 state, the DELEND flip flop is set to a 1 state, irrespective of the clock The I state of the DELEND flip flop and resulting control signal at DELEND signals the calling module that the last and least significant power of 2 of the input number has been formed (e g entire number has been converted) A true 65 signal at the DELEND output or the D Io output in combination with true signals at Pl and CLK cause the DELMEND one-shot to be set to a 1 state and the DELCE flip flop to be reset to a 0 state, inhibiting the gate from providing further pulses at CLK. DELMEND clock circuit becomes PI DELEND CLK + CLK P 2 MSBDELI. These changes permit the DELTA MODULE to convert the number set in DELI to its component powers of 2 After this has been done, D Io will be asserted Then any further call on the DELTA MODULE will cause DELEND to be set during Pl and the module will terminate upon the assertion of the CLK signal during pulse P 1 Note that DELO is cleared in this case. D Example of Operation With the foregoing detailed organization in mind, consider an actual example of the operation of the DELTA MODULE For the example, assume initially that the number 13 which in binary coded form iis 00001101, is to be converted and the DELTA MODULE is called by control signals at RM 1 and RM 3 or OM 2 and OM 3 from the REVOLVE and OUTPUT MODULES, respectively, as described above. The binary coded number 00001101 is loaded into the register 302 as described above The sequence of operation thereafter is as follows. sequence of control DB 1-DB 5, DB 4-DB 5, DB 4-DB 5, DB 4-DB 5, DB 4-DB 6; DB 1 DELFST = 1 ' control to DB 2 DB 2 DELFST =-DELEND = 0 reset these flip flips; set MSBDELO of DELO ( 100000000); DB 3 DELI ( 13) O ' control to DB 4 DB 4 DELI = 00011010 shift DELI left; DELO = 10000000 shift DELO right; DB 5 MSB (DELI) = 0 ' control to DB 4 DB 4 DELI= 001 10100 DELO = 01000000 DB 5 MSB(DELI): O control to DB 4 DB 4 DELI = 01101000 DELO = 00100000 DB 5 MSB (DELI): O control to DB 4 DB 4 DELI= 11010000 DELO = 00010000 DB 5 MSBDELI = 0 control to DB 4 DB 4 DELI= 10100000 DELO = 00001000 DB 5 MSBDELI = 1 'control to DB 6 DB 6 MSBDELI = 0 DELI= 110100000 HALT OUTPUT DELO = 8 (highest component power of 2 in 13) DELEND = O Second call DELI is unaltered DELFST = 0 sequence of control DB 1, DB 3-DB 6 DB 1 DELEST = O control to DB 3 DB 3 DELI 4 O control to DB 4 DB 4 DELI= 01000000 DELO = 00000100 DB 5 MSBDELI = l 'control to DB 6 DELO = 4 next component power to 2 DB 6 MSBDELI = 0 DELI= 01000000 HALT OUTPUT DELO = 4 DELEND = O Third call all parameters are unaltered on input sequence of control D Bl 1 as explained above DB 3 J DBI, DB 3-DB 5, DB 4-DB 6 1,570,344 DB 4 DELI = 10000000 DELO = 00000010 DB 5 MSB(DELI) = 0 - control to DB 4 DB 4 DELI = 0000000 5 DELO = 00000001 DB 5 MSB(DELI) = 1 control to DB 6 DB 6 MSB(DELI) = O DELI = 00000000; HALT OUTPUT DELO = 1 DELEND = 0 Fourth call 10 sequence of control DBI, DB 3, DB 7; DBI as before DB 3 DELI = 0 - control to DB 7 DB 7 DELEND = 1 DELO = O HALT OUTPUT DELO = O DELEND = 1 15 VI REVOLVE MODULE A General Description As disclosed and described herein above with respect to Table 5, a line in an iso-entropicgram represented by l's and O 's can be generated simply by shifting the preceding line 1 bit position to the right and XO Ring the unshifted and shifted 20 preceding line together, truncating above the most significant bit to the right Also, lines of an isoentropicgram can be skipped to generate a second line in an isoentropicgram from a first line This is done by breaking the number of lines, between the first line and the second line, into its component powers of 2, going from largest to smallest power of 2 If the component powers of 2 are used to 25 determine the increment in which revolve takes place from the first to the second line, each increment is a simple shift and XOR operation This has been described above in connection with Table 4-C. However, each occurrence making up a line of an isoentropicgram is represented in absolute coded form rather than by binary l's and O 's, to facilitate 30 implementation As a result, the shift and XOR operation are accomplished according to the embodiment of the invention using absolute coded occurrence values rather than l's and O 's Table 4-E illustrates this process for the revolve operation disclosed and described in connection with Table 4-1 D Thus, the l's only need be represented and are represented by absolute decimal numbers Line 7 35 is shifted by 8 places to the right simply by adding 8 to the absolute decimal value of line 7 XO Ring takes place simply by sorting the unshifted and shifted values in order of magnitude, deleting those absolute occurrence values which are the same and those values which go beyond the end of the iso-entropigram In this manner the result of the first XOR results in Line 15 of the iso-entropicgram of Table 4-B 40 which is a simple sort of the unshifted and shifted values Note, however, that the shift of line 15 by 1 results in a value 16 Since 16 exceeds the width of the isoentropicgram, it is discarded Also during the subsequent XOR the values 3, 7, 8, 11 and 15 are discarded The sort of the remaining numbers results in a sequence of decimal values representing Line 16 45 Turning now to the REVOLVE MODULE, the revolve operation is performed principally under control of the REVOLVE MODULE with assistance of the MEMORY, ENCODE, DECODE I and II, and DELTA MODULES. Fig 18 shows a flow chart which illustrates the sequence of operation of the REVOLVE MODULE The symbol RB followed by a number identifies each box 50 in the flow and the symbol P followed by a number identifies the flip flop(s) of the control counter 413 which is (are) in a 1 state for the corresponding flow blocks. The REVOLVE MODULE serves the following two functions: 1 It revolves a line of an iso-entropicgram down the number of lines which the calling module has set into the DELI register of the DELTA 55 MODULE. 2 It merges two lines (i e, XOR's two lines) of an iso-entropicgram without any revolve This function is accomplished by the calling module's placing an O in the DELI register of the DELTA MODULE. The purpose of the first function is to find the "seed" line or the output line of 60 the iso-entropicgram The second function is used in connection with the CHANGE MODULE where the CHANGE MODULE uses the REVOLVE 1,570,344 MODULE to revolve the changes down to the seed line and then uses the REVOLVE MODULE to merge these changes with the seed line Thereafter, the REVOLVE MODULE performs its first function of revolving the merged line to the seed line. * The REVOLVE MODULE receives as input actual absolute coded 5 occurrence values provided by the DECODE I and II MODULES DECODE I and II MODULES act independently in the sense that they select in order all occurrence values of a common input line from the MEMORY MODULE at different rates The rate at which DECODE I and II MODULES select the occurrence values from a common input line is determined by the REVOLVE 10 MODULE which calls or requests occurrences as required. The REVOLVE MODULE also receives absolute coded values representing the component powers of 2 formed by the DELTA MODULE These values each represent a number of lines in the iso-entropicgram to be revolved Each component power of 2 signal is combined with each occcurrence value provided by 15 the DECODE I MODULE to form the shifted occurrence values The actual received (unshifted) occurrence values provided by the DECODE I MODULE and the shifted values are then XOR'd and the result is the new line in the isoentropicgram. The most important function of the REVOLVE MODULE is the XOR 20 (exclusive OR) function To this end, the REVOLVE MODULE compares all of the shifted values with the unshifted values and sorts these two series of values in decreasing order of magnitude Significantly, when a shifted value and an unshifted occurrence value are found to be equal, the two values are deleted As a result, the exclusive O Ring (XOR) function is provided The resultant series of values are 25 provided from the RD 54 selection circuit as output of the REVOLVE MODULE to the EI register of the ENCODE MODULE The ENCODE MODULE in turn, by use of one of its two clipping functions (described for ENCODE MODULE), clips off those high order occurrence values from the resultant series which are larger than the width of the iso-entropicgram, i e, larger than the width of the 30 original input line. The resultant series of occurrence values provided by the REVOLVE MODULE to the ENCODE MODULE are in absolute coded form and the ENCODE MODULE converts these occurrence values to hybrid form for storage in the MEMORY MODULE as described above 35 B Components The REVOLVE MODULE of Fig 17 includes 8 bit or 8 flip flop registers CRI, CR 2 and DN Each of these registers is formed of register type SN 74100 disclosed at page 259 in the above TTL book Each has load circuitry which, responsive to a control signal at the L input along the side of the registers, causes the 8 bit 40 information signals applied at the upper side to be stored into the corresponding register. Selection circuits RDSI-RD 54 are provided The selection circuits are of the same type disclosed above which, responsive to a control signal at the numbered inputs along the side of the selection circuits, couple the 8 bit inputs indicated 45 along the upper side of each selection circuit through to an 8 bit output circuit. In addition, an arithmetic ALU is provided of the same type disclosed above. Additionally, logical signal inverters 402 and 403 are provided for forming the o logical inversion of the signal at E and CLK, respectively, and for providing corresponding outputs at E and CLK. A clock 412 is a source of regular occurring, equally spaced clock pulses Flip flops RCE, RS and Pl through P 9 are provided, flip flops Pl-P 9 forming the control counter 413 One-shot multi-vibrators REVGO and REVEND are provided One-shot multi-vibrators REVGO and REVEND normally form a false signal at outputs REVGO and REVEND but respond to a control signal applied to 55 their inputs for setting to a 1 state wherein true signals are formed at outputs REVGO and REVEND for a time interval equal to that between the beginnings of two successive clock pulses from the clock 412 REVEND when forming a true signal at output REVEND signals the calling module that the revolve operation is 60 complete. Switches 404 and 406 are provided, each providing at its output a continuous 8 bit binary coded signal, representing the 2 's complement of 1, thereby representing -I. AND gate 416 and OR gates 418 and 420 are conventional AND and OR gates i,, 1,570,34457157,445 well known in the computer art and need no further explanation Boolean logical equations are used to indicate various logical gates in the system as discussed above Clock suspension logic 422 suspends operation of the REVOLVE MODULE by terminating the CLK and CLK pulse while one of the other modules completes its operation 5 Along the right side of the REVOLVE MODULE schematic are shown the input and output control lines for the REVOLVE MODULE, and the information input and output lines using the same system of notation described hereinabove. C Detailed Description The REVOLVE MODULE during its revolve function cooperates with the 10 MEMORY, ENCODE, DECODE I and II, and DELTA MODULES Normally the DELTA MODULE provides the component powers of 2 of the number of lines to be revolved and the DECODE I and II MODULES each read and decode the same event occurrence vector from the MEMORY MODULE The DECODE I and II MODULES provide the absolute coded occurrence values, making up the 15 event occurrence vector, one at a time as requested by the REVOLVE MODULE. Both the DECODE I and II MODULES provide the absolute coded occurrence values in the same order but one decode module may be requested to provide several occurrence values before the other decode module provides an occurrence value To be explained in more detail, this operation is required in carrying out the 20 exclusive XO Ring operation The result formed by the REVOLVE MODULE is a sequence of absolute coded occurrence values which are encoded by the ENCODE MODULE back to hybrid form and written into the MEMORY MODULE. To be explained in more detail, a simple merge of the occurrence values may be effected by the REVOLVE MODULE without XO Ring simply by providing a 25 value of 0 to the DELTA MODULE as the number of lines to be revolved. To obtain a better overall view of the REVOLVE MODULE, refer now to the REVOLVE MODULE flow, Fig 18 and the REVOLVE MODULE schematic and block diagram, Fig 17, and consider in general the sequence of operation As indicated in Table 11, the REVOLVE MODULE does not have a formal set of 30 input and output values However, the inputs and outputs indicated for the ENCODE, DECODE I and II and DELTA MODULES are present The result of the revolve function is a line of an iso-entropicgram which is stored in the MEMORY MODULE During RB I and RB 2 of the REVOLVE MODULE flow, the DELTA MODULE is called by the REVOLVE MODULE, causing the 35 DELTA MODULE to provide its first component power of 2 making up the number of lines to be revolved The first and subsequent component powers of 2 are stored in the register DN in the REVOLVE MODULE During RB 2, the DECODE I and DECODE II MODULES and the ENCODE MODULE (the latter not indicated on flow) are initialized by setting the appropriate initial conditions 40 therein preceding the first call on these modules. During RB 4, flip flop DELEND is checked and if an 0 state, the value of the number of lines to be revolved contained in DELI of the DELTA MODULE has not been completely broken into all of its component powers of 2 and, regardless of the state of flip flop RS, control goes to RB 5 for further processing If, during RB 4 45 and RB 5, flip flops DELEND and RS are in 1 and 0 states, respectively, the flip flop DELEND indicates that the value of the number of lines to be revolved contained in DELI has not been completely broken down into its component powers of 2, and the flip flop RS indicates that a non zero value is stored in DELI and RB 5 is also entered for further processing However, if, during RB 4 and RB 6, flip flops 50 DELEND and RS are both in a 1 state, flip flop RS indicates a simple merge operation and that an 0 value has been stored in DELI by the calling module. DELEND indicates that the two series of occurrences from the DECODE I and II MODULES have already been merged Accordingly, the REVOLVE MODULE operation is EXITED 55 During RB 5 the DECODE I MODULE is called by the REVOLVE MODULE by setting the DIGO multi-vibrator to a 1 state and, the first time in RB 5, the first and highest numbered occurrence from the input line to be revolved is provided by the DECODE I MODULE and stored in the CRI register of the REVOLVE MODULE Typically, the next operation is in RB 8 through RB 9, combining the 60 highest component power of 2 of the number of lines to be revolved contained in the DN register with the occurrence value contained in the CRI register and the result is stored back into the CRI register Since the occurrence value provided by the DECODE I MODULE is in absolute binary coded form, the sum results in a 1,570,344 value simulating the right shift of "DN" places of the occurrence value provided by DECODE I. Overflow is checked during RB 110 If overflow has occurred, this means that the resultant shifted value in CRI is larger than the DPM can handle Thus, the content of CR 1 is larger than the current isoentropicgram width This is so since 5 the width is constrained to lie within the bounds of the machine Therefore, when overflow occurs, control returns to RB 5 and the DECODE I MODULE is again called, so that it reads the next smaller occurrence value which is then combined with the content of DN and stored into CRI Therefore, the result previously formed during RB 9 and stored in CR 1 is ignored On the other hand, if overflow 10 did not occur or if flip flop EOFI (end of file for DECODE I MODULE) is true, control goes to RB 12. During RB 12-15, the DECODE II MODULE is called by setting the D 2 GO multi-vibrator into a 1 state Initially, the DECODE II MODULE provides the largest occurrence value and this value is stored in register CR 2 If there is nothing 15 to read (i e, end of file has been reached for DECODE II MODULE), flip flop EOF 2 is true and RB 15 is entered where CR 2 is loaded with a value of 1. During RB 16, outputs EOFI and EOF 2 are checked to see if both are true and if so, this indicates the end of file for both DECODE I and DECODE II MODULES If end of file has been reached, control goes to RB 17-RB 19 because 20 this portion of the revolve or merge is complete Accordingly, flip flop ELAST is set and the ENCODE MODULE is instructed to write out its final value MLN 3 in the ENCODE MODULE contains the physical length of the line which was just generated This value is clocked into MLNI and MLN 2 of the DECODE I and II MODULES This is done in case another revolve is needed 25 If either or both of the flip flops EOFI or EOF 2 are in a 1 state, the end of one or both of the files being read by DECODE I and II MODULES has been reached and RB 20 is entered following RB 16 During RB 20, the shifted occurrence value in register CRI is compared with the unshifted occurrence value in CR 2 If the shifted value contained in CRI is larger, then it is necessary to write out this value and 30 accordingly, RB 23-24 are entered where the ENCODE MODULE is called by setting the ENGO multi-vibrator to 1, causing the content of register CRI to be sent to the El register of the ENCODE MODULE where it is subsequently encoded and written out in a preselected area of the MEMORY MODULE. During RB 25-RB 28, the DECODE I MODULE is again called by setting DIGO 35 to 1; the next lower occurrence value is read from the same input line; the next lower occurrence value is combined with the same component power of 2 value contained in the DN register; and the result (shifted occurrence value) is stored in the CRI register. Subsequently, RB 20 of the REVOLVE MODULE flow is again entered where the content of registers CR 1 and CR 2 is again compared This operation occurs and is 40 repeated as long as the shifted value stored in register CRI is larger than the unshifted value in register CR 2. If, during the RB 20 of the ENCODE MODULE flow, it is found that the unshifted occurrence value contained in CR 2 is larger than the shifted occurrence value in CRI, RB 21-RB 23 are entered where the ENCODE MODULE is called 45 and the unshifted occurrence value contained in the CR 2 register is sent via the RD 54 selection circuit to the EI register of the ENCODE MODULE for encoding and writing out in the same preselected area of the MEMORY MODULE RB 12 is re-entered where the DECODE II MODULE is again called, causing the next lower occurrence value to be read out by the DECODE II MODULE and stored in 50 register CR 2 This operation also occurs and is repeated until the unshifted occurrence value is stored in CR 2 that is larger than the shifted occurrence value in the CRI register. If during RB 20 of the REVOLVE MODULE flow it is found that the shifted occurrence value contained in CRI is equal to the unshifted occurrence value 55 contained in CR 2, then RB 5-RB 19 of the REVOLVE MODULE flow are again entered where the action of the ENCODE MODULE of storing a value in the iso-entropicgram is skipped, and two new occurrence values are read from thesame input line by the DECODE I and DECODE II MODULES. When the end of file of both the DECODE I and DECODE II MODULES are 60 reached (i e, no further occurrence values remain to be read by either the DECODE I or the DECODE II MODULE), RB 17-19 are entered where the ENCODE MODULE is signaled to write out the last occurrence value being formed in the preselected area of the MEMORY MODULE. It should be noted that during a revolve operation the MARI register of the 65 1,570,344 59 1,570,344 59 5 DECODE I MODULE and the MAR 2 register of the DECODE II MODULE form pointers for the respective modules which indicate which occurrence value of the common input line is next to be read by the corresponding decode module In this manner, the DECODE I and DECODE II MODULES can provide a string of occurrence values from the same input line at different rates, the occurrence values 5 being provided one by one by the respective decode modules, as called by the REVOLVE MODULE During a CHANGE operation the MA Rl register and the MAR 2 register form pointers for the respective modules which indicate occurrence values from different memory areas that are to be read by the corresponding decode module 10 Refer now in more detail to the organization of the REVOLVE MODULE, referring to the schematic diagram of Fig 17 and the flow diagram of Fig 18. Initially, the MINI COMPUTER forms a true signal at the output MINIT causing the circuits to which it is connected, including control counter 413, flip flops PI-P 9, to be reset to 0 The REVOLVE MODULE is called by any one of the 15 following modules: SEED, CHANGE and OUTPUT, by forming a true signal at the respective outputs SM 9, CM 6 and O M 5, any one of which causes the OR gate 418 to trigger the one-shot multi-vibrator REVCO to a 1 state, causing a true signal at the REVGO output The true signal at REVGO causes the RCE flip flop to be set to a 1 state The 1 state of the RCE flip flop enables the AND gate 416 to start 20 coupling the clock pulses from the clock 413 to the output CLK and through the inverter 403 to CLK. The one-shot multi-vibrator REVGO returns to a 0 state Since flip flops Pl P 9 are all 0, the following pulse at CLK causes the flip flop Pl to be set to a 1 state, thereby causing RB 1 of the REVOLVE MODULE flow to be entered The 1 25 state of the Pl flip flop causes a control signal at the output Pl of the Pl flip flop. The control signal at output Pl in turn resets flip flop RS to 0; causes a true signal at the RMI output of the input and output control lines from the REVOLVE MODULE causing the DELFST flip flop in the DELTA MODULE to be set to a 1 state; and also causes a true signal at the RM 3 output from the REVOLVE 30 MODULE, setting the DELGO multi-vibrator in the DELTA MODULE to a 1 state, thereby calling the operation of the DELTA MODULE as described hereinabove. The DELTA MODULE then converts a number representing the number of lines in the iso-entropicgram to be revolved to its component powers of 2 starting 35 with the largest power of 2, all as described in connection with the DELTA MODULE At this point in time, the DELMEND one-shot multi-vibrator in the DELTA MODULE is in an 0 state forming a false signal at the DELMEND output while a true signal is concurrently being formed at the RM 3 output from the REVOLVE MODULE Accordingly, logic RM 3 DELMEND of the clock 40 suspension logic 422 become false, causing a false signal at the input to the AND gate 416, disabling further clock signals from being applied at the CLK and CLK outputs, thereby disabling further operation in the REVOLVE MODULE The DELTA MODULE independently completes the formation of the component power of 2 of the number representing the lines to be revolved and then sets the 45 DELMEND one-shot multi-vibrator to a 1 state, applying a true signal at the DELMEND output The term RM 3 DELMEND then goes true, causing the clock suspension logic 422 to again apply a true signal to the AND gate 416, again causing clock pulses to be formed at the CLK and CLK output The true signal at output Pl at the following pulse at CLK sets the P 2 flip flip to a 1 state, causing a true signal at 50. the P 2 output thereof and resets flip flop Pl to 0 The true signal at the P 2 output causes a true signal at the L input to the DN register, which in turn causes the DN register to store the largest power of 2 signal formed in the DELO register of the DELTA MODULE, and RB 3 of the REVOLVE MODULE flow is entered The true signal at the P 2 output of the P 2 flip flop causes the DECODE I and DECODE 55 II MODULES and the ENCODE MODULE to be initialized Initialization is a process whereby a true signal at the P 2 output of control counter 413 causes a true signal at the RM 2 output of the REVOLVE MODULE, which in turn causes the DIFST flip flop in DECODE I MODULE, the D 2 FST flip flop in the DECODE II MODULE, and the EFRST flip flop in the ENCODE MODULE, all to be set to a 60 I state RB 4 of the REVOLVE MODULE flow is now entered where the state of the DELEND monostable of the DELTA MODULE is checked and if in a I state, control goes to RB 5 If, however, the DELEND is in a 1 state, then control goes to RB 6 Here the RS flip flop of the REVOLVE MODULE is checked If in a I state, flip flop RS signals a merge operation The logic P 2 DELEND is true, resetting flip 65 1,570,344 flop RCE and monostable REVEND to 0, causing the clock signals from gate 416 to be disabled and the operation to EXIT The REVEND monostable applies a true signal to OR gate 420 causing it to reset counter 413 to zero At the same time, the true REVEND signal is applied back to the calling module indicating that the REVOLVE MODULE has completed its function 5 Assume now that during RB 4 the DELEND monostable in the DELTA MODULE is in a 1 state forming a true signal at the DELEND output, this signal, in coincidence with true signals at RS, the P 2 output of control counter 413, and the pulse at CLK, causes a true signal at the RM 8 output which goes to the SWITCH MATRIX, causing the SWITCH MATRIX to be activated to perform its 10 reading and writing operation in the prescribed MEMORY MODULE area in the manner to be described hereinafter The true signals at the P 2 and CLK outputs in the REVOLVE MODULE additionally cause a true signal at the RM 4 output of the REVOLVE MODULE which in turn sets the DIGO monostable of the DECODE MODULE to a 1 state, thereby calling and causing the DECODE I MODULE to 15 provide the next smaller occurrence in the input line from the MEMORY MODULE and provide it as an absolute binary coded occurrence value at the DOI output of the DECODE I MODULE The true signal at the RM 4 output of the REVOLVE MODULE in coincidence with a true signal at the D 1 MEND output from the DECODE I MODULE causes the clock suspension logic 422 to again 20 form a false signal and disable the gate 416, preventing further clock signals from being formed at the CLK and CLK outputs, thereby disabling the operation of the REVOLVE MODULE When the DECODE I MODULE completes its operation, the true signal is removed at the DIMEND output, thereby causing the clock disable logic 422 to again enable the gate 416 and clock pulses to be formed at the 25 CLK and CLK outputs The true signal at the P 2 output of control counter 413 in coincidence with the pulse at CLK causes the P 3 flip flop to be set to a I state, thereby forming a true signal at the P 3 output and the P 2 flip flop is reset to 0 The true signal at the P 3 output of the control counter 413 and at the EOFI output of the ENCODE MODULE (indicating that the end of file has not yet been reached), 30 causes the logic P 3 EOF 1 to be true and the value of the input line provided by the DECODE I MODULE is coupled through the RD 51 selection circuit to the information input of the CRI register The true signals at P 3 and the signal at CLK cause the load circuitry in CR 1 to store the occurrence value from the D Ol output of the DECODE I MODULE into the CRI register 35 During RB 7, if the end of file had been reached and the DECODE I MODULE was forming a true signal at the EOFI output, RD 51 would not have coupled the output DOI from the DECODE I MODULE to register CRI but, instead, would have coupled the signal representing the 2 's complement of 1 (-1) formed by the switches 404 to the information input of CRI causing the 40 corresponding value to be stored in register CR 1 This occurs during RB 1 1 of the flow after the end of file is reached by the DECODE I MODULE where no further occurrences are to be provided by DECODE I MODULE and a -I insures that further occurrences will not be obtained from DECODE I MODULE nor outputted from register CRI All further occurrences, if any, are taken from CR 2 45 The true signals at the P 3 output of control counter 413 and the RS, and CLK outputs also cause a true signal at the RM 12 output of the REVOLVE MODULE, which in turn sets the special flip flop SP in the SWITCH MATRIX To be explained in more detail, the SEED MODULE forms a true signal at SM 5, causing the SP flip flop to be set to a 1 state only if a current output is considered to be the 50 best seed This will be discussed in more detail in connection with the SEED MODULE. The true signal at the P 3 output also causes the P 4 flip flop to be set to a 1 state and flip flop P 3 is reset to an 0 state at the following pulse at CLK, and RB 9, RB 10, RB 12 of the REVOLVE MODULE is entered The true signal at the P 4 output of 55 the P 4 flip flop causes the RS flip flop to be set to a 1 state As explained before, this is done so that after the first pass the REVOLVE MODULE will EXIT when DELEND (DELTA MODULE) is in a 1 state. The true signal at the P 4 output causes the RD 53 selection circuit to couple the power of 2 signal in the DN register to the ALU and causes the ALU to add the 60 content of the registers CRI and DN and form an output signal at OP corresponding to the sum This signal represents the occurrence value shifted towards the most significant position by the number of possible occurrence values indicated by the power of 2 value in register DN This signal is called the shifted occurrence value 65 1,570,344 61,7,346 The ALU forms a true signal at the OVL output, causing the RDSI selection circuit to couple the shifted occurrence value from the OP output back to the information input of the CRI register Additionally, the true signal at P 4 and EOF 1 in coincidence with the pulse at CLK causes the load circuit of the CRI register to store the value back into the CRI register 5 If overflow occurred from the sum of the CR 1 and DN registers, the result is larger than the width of the isoentropicgram and there is formed a true signal at the OVL output which in conjunction with the CLK pulse causes the output RM 4 to be true In addition, the true signals at the P 4 output from counter 413 and the OVL output from the ALU cause the input to flip flop P 3 in counter 413 to be set to a 1 10 state In the flow diagram this is equivalent to going from RB 10 to RB 5 The reason for this flow is that if overflow occurs in the addition of CR 1 and DN, this indicates that the simulated right shift has generated an iso-entropicgram column value which cannot be represented by the DPM If this is the case, we know the number is larger than the current iso-entropicgram width (which obviously is represented in 15 the machine) and thus the above value would have been clipped by the ENCODE MODULE Going from RB 10 to RB 5 eliminates the call to the ENCODE MODULE and nothing is written in the MEMORY MODULE. RM 4 sets the Dl GO monostable in the DECODE I MODULE As a result the next lower occurrence value is provided by the DECODE I MODULE In 20 addition, the logic RM 4 D 1 MEND is true, causing the clock suspension logic 422 to suspend the clock until the DECODE I MODULE is finished When finished, the next lower occurrence value in DO 1 of the DECODE I MODULE is stored into the CRI register and hence over-writes the overflow value previously stored in CRI 25 Assume RB 12 of the REVOLVE MODULE flow is now entered following RB 10 The true signal at the P 4 output of the P 4 flip flop in accordance with the true signals at the CLK output and the OVL output causes a true signal at the RM 5 output of the REVOLVE MODULE which sets the D 2 GO multivibrator in the DECODE II MODULE to a 1 state, thereby calling the DECODE II MODULE so 30 that it too reads an occurrence value from the same input line as the DECODE I MODULE obtained its occurence value If this is a merge operation initiated by the CHANGE MODULE, DECODE II will be reading a line which is different from the line being read by the DECODE I MODULE. The D 2 MEND monostable in the DECODE II MODULE is in state 0 causing 35 a true signal at the D 2 MEND output The true signal at the RM 5 output of the REVOLVE MODULE in coincidence with the true signal at the D 2 MEND output indicates that the decoded occurrence value is not ready in the DECODE II MODULE for the REVOLVE MODULE and causes the clock suspension logic 422 to again apply a false signal to and disable the gate 416 from supplying clock 40 pulses and the operation of the REVOLVE MODULE is suspended After the DECODE II MODULE provides the occurrence value, it returns control to the REVOLVE MODULE by removing the true signal at the D 2 MENI output of the D 2 MEND monostable This enables the gate 416, allowing clock pulses to again be formed at the CLK and CEK output enables the P 5 flip flop to be set to a 1 state, 45 and enables flip flop P 4 to be reset to 0. The true signal at the P 5 output of the P 5 flip flop in coincidence with a true signal at the EOF 2 output of the EOF 2 flip flop in the DECODE II MODULE causes the selection circuit RD 52 to couple the occurrence value from the DECODE II MODULE to the information input of the CR 2 register The true 50 signal at the P 5 output in coincidence with the following pulse at CTK causes the value to be stored into the CR 2 register It should be noted that if this is not a merge operation, the value obtained from DECODE II MODULE is an actual occurrence value in the same input line of the iso-entropicgram and constitutes the unshifted occurrence value which will be compared with the shifted value now 55 contained in the CRI register It should be noted that should the EOF 2 flip flop in the DECODE II MODULE be in a I state, the end of file has been reached by DECODE II MODULE and therefore no occurrence value is being provided by DECODE II MODULE Accordingly, the RD 52 selection circuit, responsive to the true signals at P 5 and EOF 2, couples the output of the switches 406 to the input 60 of the CR 2 register, causing the 2 's complement of -1 to be stored in the CR 2 register. The checking of flip flop EOF 2 and placing a -I in CR 2 if EOF 2 is in a 1 state is necessitated by the following If in a merge operation, the DECODE I and DECODE II MODULES are reading different lines from different MEMORY 65 1,570,344 62 1,570,344 62 MODULE areas In case the DECODE II MODULE finishes reading first, the -1 in CR 2 will force the DECODE I MODULE to pass the remainder of its occurrence value to the ENCODE MODULE via RB 20, RB 23, RB 24. RB 16 of the REVOLVE MODULE flow is now entered where the states of the EOFI and EOF 2 flip flops of the DECODE I and DECODE II MODULES are 5 checked If both flip flops are in a 1 state, indicating that both DECODE I and DECODE II MODULES have reached the end of file (i e, the end of the input line of the iso-entropicgram), RB 17 of the REVOLVE MODULE flow is entered and the true signals at the outputs P 5, EOFI and EOF 2 cause a true signal at the RM 9 output which sets the ELAST flip flop in the ENCODE MODULE to a 1 state 10 Additionally, the following pulse at CLK in coincidence with the-true signals at P 5, EOFI and EOF 2 cause a true signal at the RM 7 output which in turn sets the ENGO one-shot multi-vibrator to a 1 state, thereby calling the operation of the ENCODE MODULE This causes the ENCODE MODULE to encode and store the last of the occurrence values of the new iso-entropicgram line into the 15 MEMORY MODULE. Assuming that either the EOFI or the EOF 2 flip flop in the DECODE I and DECODE II MODULES is 0, thereby indicating that either DECODE I or DECODE II MODULE has reached the end of file, RB 20 of the REVOLVE MODULE flow is entered where the shifted occurrence value in CRI is compared 20 with the unshifted value in CR 2 It should be noted that the registers CRI and CR 2 contain absolute binary coded values, indicating directly the shifted and unshifted occurrence values This comparison operation is an important part of the REVOLVE MODULE operation as it is a key part of the exclusive O Ring process. To this end, the shifted and unshifted occurrence values of the input line must be 25 sorted into descending order of magnitude Those shifted and unshifted occurrence values which are equal are dropped This then exclusive OR's the shifted and unshifted occurrence values and causes a revolve from one line to the next in the iso-entropicgram. Referring to RB 20 of the REVOLVE MODULE flow, the true signal at the P 6 30 output causes the RD 53 selection circuit to couple the CR 2 register to the ALU and causes the ALU to compare the content of the CRI and CR 2 registers If the shifted value contained in CRI is greater, a true signal is formed at the G output. This causes RB 23-RB 30 of the REVOLVE MODULE flow to be entered where the shifted value contained in CRI is encoded and stored into the MEMORY 35 MODULE by the ENCODE MODULE and the DECODE I MODULE reads its next occurrence value from the same input line, the next occurrence value is combined with the content of register DN to form a shifted occurrence value, and the shifted occurrence value is stored in register CRI. Consider in more detail the operation during RB 23 and RB 24 The true signals 40 at the G output of ALU and at the P 6 output causes the RD 54 selection circuit to couple the shifted occurrence value contained in the CRI register to the output thereof, which goes to the input of the El register of the ENCODE MODULE A signal is formed at the E output of the inverter circuit 403 when the values compared are not equal The true signals at outputs P 6 and E cause a true signal at 45 the RMI 1 output of the REVOLVE MODULE which, in turn, causes the ED 56 selection circuit in the ENCODE MODULE to couple the output from RD 54 to the El register The true signals at P 6, E and CLK energize the L input of the El register of the ENCODE MODULE, causing the occurrence value contained in CR 2 of the REVOLVE MODULE to be loaded into the EI register The true signal 50 at the outputs P 6, E and CLK also cause a true signal at the RM 7 output of the REVOLVE MODULE which, in turn, sets the ENGO multi-vibrator to a 1 state, thereby calling the operation of the ENCODE MODULE as described above. Once called, the ENCODE MODULE converts the shifted value obtained from the CRI register to hybrid form and stores it in the MEMORY MODULE 55 If, during the true signal at the P 6 output both the EOFI and EOF 2 flip flops from the DECODE I and DECODE II MODULES are in a 1 state, a true signal is formed at the RM 14 output of the REVOLVE MODULE which, in turn, causes the MLN 1 and MLN 2 registers of the DECODE I and DECODE II MODULES to be loaded with the value contained in the MLN 3 register of the ENCODE MODULE 60 This is done since the complete input lines will have been processed by the REVOLVE MODULE and the new iso-entropicgram line which is now in the area designated by the MLN 3 register of the ENCODE MODULE forms the new input line and is next to be processed by the DECODE I and DECODE II MODULES in order to revolve to the next line of the iso-entropicgram This operation allows 65 subsequent lines in the iso-entropicgram to be formed from the new isoentropiegram line just formed by the REVOLVE MODULE. Continuing with RB 24 of the REVOLVE MODULE flow, the true signal at the RM 7 output in coincidence with the true signal at the EMEND output of the ENCODE MODULE causes suspension logic 422 to suspend the operation of the 5 REVOLVE MODULE similar to that discussed above until the ENCODE MODULE has completed its encode function and removes the true signal at the EMEND output After the suspension has ended and the gate 416 is again enabled by the clock suspension logic 422, the following pulse at CLK causes flip flop P 7 to be set to a I state and flip flop P 6 is reset to 0 The 1 state of the P 7 flip flop is used 10 as a time delay in the system A time delay is needed in order to allow the ENCODE MODULE to complete its operation before the decode modules are called This is needed in this system since all the molecules operate serially. However, this need not necessarily be the case as the system could be designed so that all the modules operate in parallel 15 RB 25-28 are now entered A true signal at the P 7 output again causes the selection circuit RD 53 and the ALU to compare the shifted and unshifted values, respectively, contained in registers CR 1 and CR 2 Since the values have not changed, the shifted value contained in register CRI is the larger and hence a true signal is again formed at the G output of ALU The true signal at the P 7 and G 20 outputs causes the flip flop P 8 to be set to a 1 state at the following pulse at CLK. Additionally, the true signal at the P 7, G and CLK outputs causes a true signal at the RM 4 output, thereby again calling the DECODE I MODULE, causing it to read out the next lower actual occurrence value in the same input line from the MEMORY MODULE As before, the true signal at the RM 4 output in 25 coincidence with the true signal at DIMEND from the DECODE MODULE causes the clock suspension logic 422 to disable the gate 416 and suspend the operation of the REVOLVE MODULE until DECODE II MODULE removes the true signal at DIMEND, indicating that it has now completed its decode operation and is now providing its next lower actual occurrence value of the input line 30 During RB 27 the true signal at the P 8 and EO Fl outputs causes the RDS 1 selection circuit to couple the next lower occurrence value from register D Ol of the DECODE I MODULE to the infbrmation input of CR 1 and the following pulse at CLK causes the CRI load circuit to store the value into the CRI register Similar to that described above, in connection with the true signal at P 3, should the EOF 1 flip 35 flop of the DECODE I MODULE be in a 1 state, providing a true signal at the EO Fl output, the DECODE I MODULE would have reached the end of file, RB 30 would be entered and hence the 2 's complement of a -1 represented by the switches 404 would be stored in register CRI rather than the output from the DECODE I MODULE 40 Continuing with the operation during RB 27-RB 28, the true signal at the P 8 output causes the P 9 flip flop of the control counter 413 to be set to a I state and RB 28 of the REVOLVE MODULE is entered The true signal at the P 9 output causes the RD 53 selectiion circuit to couple the power of 2 value contained in the DN register to the ALU and causes the ALU to add the content of the CR 1 and DN 45 registers and form a new shifted occurrence value at the output OP. As explained with pulse P 4, if overflow occurs during the addition of CRI and DN, a signal is formed at OVL indicating a right shift to an isoentropicgram column value which cannot be represented by the DPM The value is therefore ignored Accordingly, if output OVL is true, the logic P 9 OVL is true, causing flip 50 flop P 8 and P 9 to be set to 1 and O states, respectively, at the following CLK pulse and a signal is to be formed at output RM 4 during the =L Kpulse P 9, and DIGO of the DECODE I MODULE is set The DECODE I MODULE reads the next lower occurrence value as explained above However, if the addition does not produce overflow, OVL is true, causing logic P 9 OVL to become true and the following 55 CLK pulse sets flip flops P 6 and P 9 to I and 0, respectively, and control returns to RB 16. With the new occurrence value from the input line now read from the MEMORY MODULE and the shifted value contained in the CRI register, RB 16 and RB 20 of the REVOLVE MODULE flow are reentered The true state at the P 6 60 output of the P 6 flip flop again causes the content of the registers CR 1 and CR 2 to be compared, as discussed above, to determine which is the larger If the new shifted occurrence value contained in register CR 1 is the larger, RB 23RB 30 are again entered where the larger value contained in CRI is sent to the ENCODE MODULE for conversion to hybrid form and writing in the MEMORY MODULE 65 1,570,344 and DECODE I MODULE is again called, causing the next lower value occurrence value of the same input line to be read from the MEMORY MODULE, combined with the value in DN to form a shifted occurrence value and stored in register CRI. Assume that during RB 20, during the true signal at the P 6 output, the ALU 5 detects that the content of the unshifted occurrence value at CR 2 is larger than that of the shifted occurrence value contained in register CR 1 The ALU now forms a true signal at the L output causing RB 21-RB 22 to be entered. During RB 21-RB 22 the true signal at the P 6 and L outputs causes the RD 54 selection circuit to couple the unshifted occurrence value contained in register 10 CR 2 to the ENCODE MODULE and the true signals at the P 6, E and CLK outputs cause a true signal at the RM 6 and RM 7 outputs which in turn, cause the unshifted occurrence value in CR 2 to be stored into the El register of the ENCODE MODULE and cause the ENCODE MODULE to be called Thus called, the ENCODE MODULE encodes the unshifted occurrence value from register CR 2 to 15 hybrid form and causes it to be stored into the MEMORY MODULE in the new iso-entropicgram line being formed there. As discussed above, the true signal at the RM 7 and EMEND outputs again cause the clock suspension logic 422 to suspend the operation of the REVOLVE MODULE When the ENCODE MODULE indicates that it has ended its 20 operation by removing the true signal at the EMEND output, the suspension ends and the clock causes the P 7 flip flop to again be set to a 1 state, forming a true signal at the P 7 output which again causes the RD 53 selection circuit and the ALU unit to again compare the shifted and unshifted occurrence values contained in the CRI and CR 2 registers Since the value in CRI is still smaller, a true signal is again 25 formed at the L output and RB 12 is entered. During RB 12 the true signals at the P 7, L and CLK outputs cause true signals to be formed at the RM 5 output which, in turn, sets the D 2 GO one-shot to a I state thereby calling the operation of the DECODE II MODULE, causing it to read the next lower occurrence value from that which it originally read from the MEMORY 30 MODULE and provides it for storage into the CR 2 register. The true signal at the D 2 MEND output from the DECODE II MODULE again causes the operation of the REVOLVE MODULE to be suspended until the DECODE II MODULE provides the next occurrence value Once the next occurrence value is provided by the DECODE II MODULE and the true signal is 35 removed at the D 2 MEND output, the clock suspension logic 422 again terminates the suspension of operation of the REVOLVE MODULE and the following pulse at CLK in coincidence with the true signals at P 7 and L cause the P 5 flip flop to again be set to a 1 state where during RB 14 the next lower occurrence value from the DECODE I MODULE is stored into the CR 2 register, as described above 40 Assume now that RB 20 of the REVOLVE MODULE flow occurs and the P 6 flip flop is in a 1 state and the shifted occurrence value contained in CRI is equal to the unshifted occurrence value contained in CR 2, thereby causing the ALU to form a true signal at the E output thereof and inverter 403 forms a false signal at E. According to the exclusive O Ring procedure, it is necessary to delete both the 45 shifted and unshifted occurrence values in the CRI and CR 2 registers from the new iso-entropicgram line being formed Accordingly, the ALU forms a false signal at the E output in coincidence with the true signal at the P 6 output The logic P 6.E CLK is now false and therefore the pulse at CLK does not cause a true signalat RM 7 and hence does not cause the ENGO multi-vibrator in the ENCODE 50 MODULE to be set The true signal at the P 6 output, however, causes the P 7 flip flop to be set to a 1 state where the ALU again compares the content of registers CR 1 and CR 2 as discussed Since the values in CRI and CR 2 are still equal, the ALU forms a true signal at the E output The true signal at the E output in coincidence with the true signal at P 7 sets the P 3 flip flop to a 1 state, thereby 55 causing RB 7 through RB 20 of the REVOLVE MODULE flow to again be entered where both the DECODE I and DECODE II MODULES are called, causing respective new occurrence values of the same input line to be provided to the REVOLVE MODULE. This process continues until during RB 16 it is detected that tboth the EOF 1 60 and EOF 2 flip flops of the DECODE I and DECODE II MODULES are true, indicating that both DECODE I and DECODE II MODULES have reached the end of the input line When this occurs, true signals are formed at the EOFI, EOF 2 and P 5 outputs, causing a true signal to be formed at the RM 9 output which in turn sets the ELAST flip flop in the ENCODE MODULE which, in turn, causes the 65 1,570,344 ENCODE MODULE to store any remaining occurrence values in hybrid form in the MEMORY MODULE as described in connection with the ENCODE MODULE. D Example of Operation Consider now an actual example of operation for the REVOLVE MODULE. Table 4-B herein gives an example of the way in which one revolves from one line to another in an iso-entropicgram Using this same example, consider the way in which the present embodiment of the invention revolves from line 2 to line 7. Before the REVOLVE MODULE is called, the following preliminary steps are taken: 1 The MLN 1 register of the DECODE I MODULE and the MLN 2 register of the DECODE II MODULE are stored with the physical length of line 2 of the example which physical length is normally obtained from the IPRF. 2 Line 2 of the example, namely, event occurrence vector 0, 1, 3, 8, 9, 10, 11, is stored in hybrid coded form in one of the memory areas of the MEMORY MODULE. 3 The number of lines to be revolved, i e, 5, is loaded into the DELI register of the DELTA MODULE as described above. The sequence of operation following these initial conditions is as follows: RBI RB 2 RB 3 RS = O DELFST = O DELGO = 1 DN = DELO = 4 D 1 FST = D 2 FST = 1 ERFST= 1 RB 4-RB 5 DELEND = O = DIGO = 1 RB 7-RB 11 RB 12-RB 14 RB 16 RB 20, RB 23, RB 24 RB 25-RB 29 RB 16 RB 20,RB 23, RB 24 RB 25-RB 29 RB 16 DO 1 = 11 CR 1 =DO 1 = 11 C Rl( 15) = CRI( 11) + DN( 4) OVL = O RB 12 RS= 1 D 2 GO = 1, EOF 2 = O CR 2 = DO 2 = 11 EOFI( 0) EOF 2 ( 0) = O ' RB 20 C Rl( 15) > CR 2 ( 11) ‘ RB 23 EI = CRI = 15 ENGO= 1 D 1 GO= 1 CR 1 = DOI = 10; EOFI = O C Rl( 14) C Rl( 10) + DN( 4) OVL= O ‘ go to RB 16 EOFL EOF 2 = O – RB 20 CRI( 14) > CR 2 ( 11) EI = CRI = 14 call ENCODE DIGO = CR 1 = DOI = 9, EOFI = O C Rl( 13) = CRI( 9) + DN OVL = O RB 16 EOFL EOF 2 = O RB 20 initialize DELTA MODULE get largest component power of 2 initialize DECODE AND ENCODE MODULES get first value from DECODE I MODULE load value from DECODE MODS into CR 1 simulate the right shift set merge indicator call DECODE II MODULE load the output into CR 2 REVOLVE process not finished yet transfer CR 1 to ENCODE MO call the ENCODE MODULE call DECODE I MODULE get next value simulate the right shift write out through 14 call DECODE I MODULE simulate the shift 1,570,344 1,570,344 RB 20,RB 23, RB 24 RB 25-RB 29 RB 16 RB 20,RB 23, RB 24 RB 25-RB 29 RB 16 RB 20 RB 21, RB 22 RB 12-RB 14 RBI 6 RB 20 RB 21, RB 22 RB 12-RB 14 RB 16 RB 20 RB 21, RB 22 RB 12-RB 14 RB 16 RB 20 RB 21, RB 22 RB 12-RB 14 RB 16 RB 20 RB 23, RB 24 RB 25-RB 29 RB 16 RB 20 RB 23, RB 24 RB 25-RB 29 RB 16 RB 20 RB 23, RB 24 RB 25, RB 26, RB 30 C Rl( 13) > CR 2 ( 11) ‘.
EI = CR 1 = 13 call ENCODE (ENGO = 1) set D IGO = 1 CR 1 =DOI = 8, EOFI = O CRI( 12) = CRI( 8) + DN( 4) OVL = O RB 16 EOF 1 EOF 2 = O RB 20 CRI( 12) > CR 2 ( 11) ‘.
EI = CRI = 12 ENGO = I D 1 GO= 1 CR 1 =DOI = 3, EOFI = O CR 1 ( 7) = CRI( 3) + DN( 4) OVL = O RB 16 EOFI EOF 2 = O CR 2 ( 11) > CRI( 7) EI = CR 2 = 11 call ENCODE (ENGO = 1) call DECODE II CR 2 = DO 2 = 10, EOF 2 = O EOFI EOF 2 = O CR 2 ( 10) > CRI( 7) EI =CR 2 = 10 call ENCODE call DECODE II CR 2 = DO 2 = 9, EOF 2 = O EOF 1 EOF 2 = 2 CR 2 ( 9) > CRI( 7) EI= CR 2 = 9 call ENCODE call DECODE II CR 2 = DO 2 = 8, EOF 2 = O EOF 1, EOF 2 = O CR 2 ( 8) > CRI( 7) EI = CR 2 = 8 call ENCODE call DECODE II CR 2 = DO 2 = 3, EOF 2 = O EOFL EOF 2 = O CRI( 7) > CR 2 ( 3) EI = CRI = 7 call ENCODE call DECODE I CR 1 =DOI = 1, EOFI = O CRI( 5) = CRI( 1) + DN( 4) OVL = O EOFL EOF 2 = O CRI( 5) > CR 2 ( 3) EI=CRI = 5 call ENCODE call DECODE I CRI =DOI = 0, EOFI = O CRI( 4) = CRI( 0) + DN( 4) OVL = O EOFI EOF 2 = O CRI( 4) > CR 2 ( 3) EI = CR 1 = 4 call ENCODE call DECODE I CRI =-1, EOFI = I CR 1 sent to ENCODE MODULE call DECODE I MODULE get next value simulate the right shift simulate the XOR CR 1 sent to ENCODE MODULE call ENCODE MODULE call DECODE I MODULE simulate the shift XOR send CR 2 to ENCODE MODULE activate ENCODE MODULE activate DECODE II MODULE store result in CR 2 simulate XOR output CR 2 get next value output CR 2 get next value XOR output CR 2 read next value from DECODE II MODULE simulate XOR output CRI simulate shift simulate XOR output CR 1 read next value simulate shift simulate XOR output CR 1 end of file reached 67 RB 16 RB 20 RB 21, RB 22 RB 12-RB 14 RB 16 RB 20 RB 21, RB 22 RB 12-RB 14 RB 16 RB 20 RB 21, RB 22 RB 12, RB 13, RB 15 RB 16-RB 19 1,570,344 EOFI EOF 2 = O CR 2 ( 3) > CRI(-I) EI =CR 2 = 3 call ENCODE call DECODE II CR 2 = D 02 = 1, EOF 2 = O EOFL EOF 2 = O CR 2 ( 1) > CR(-1) EI = CR 2 = I call ENCODE call DECODE II CR 2 = DO 2 = O EOFL EOF 2 = O CR 2 ( 0) > CRI(-1) EI = CR 2 = O call ENCODE call DECODE II CR 2 = -1; EOF 2 = 1 EOF 1 EOF 2 = 1 ‘.
set ELAST call ENCODE MLNI, MLN 2 = MLN 3 revolve not done XOR output CR 2 get next value keep outputting CR 2 until EOF 2 = 1 read in next value not finished yet output CR 2 end of file reached write out last value to MEMORY MOD length of new line stored in DECODE I and DECODE II MODS At this point the revolve operation is not complete Line 6 in the isoentropicgram has been formed and stored in hybrid coded form in the MEMORY MODULE.
The decimal occurrence values of line 6 are 15, 14, 13, 12, 11, 10, 9, 8, 7, 5, 4, 3, 1, 0.
The line is next revolved down one line to line 7 as follows:
RB 2 RB 5, RB 7RB 10 RB 12-RB 14 RBI 6 RB 20 RB 23, RB 24 RB 25-RB 29 RBI 6 RB 20 RB 5, RB 7RB 10 O RB 12-RB 14 RB 16 RB 20 call DELTA DN = DELO = 1, DELEND= O call DECODEI CR 1 =DOI = 15, EOFI CR 1 ( 16) = C Rl( 15) + 1 OVL = 0 call DECODE II CR 2 = DO 2 = 15, EOF 2 = O EOFI EOF 2 = O ‘.
C Rl( 16) > CR 2 ( 15) EI = CRI = 16 call ENCODE MODULE call DECODE I MODULE CRI =DOI = 14, EOFI = O CRI( 15) = C Rl( 14)+ 1 OVL= O ‘.
EOFI EOF 2 = O ‘.
CR 1 =CR 2 = 15 ‘.
call DECODE I MODULE CRI =DOI = 13, EOFI = O CRI( 14) = CRI( 13) + DN(I) OVL = O call DECODE II MODULE CR 2 = DO 2 = 14, EOF 2 = O EOFI EOF 2 = 0 ‘.
CRI = CR 2 = 14 get next component power of 2 from DELTA MOD read the first value simulate the shift get unshifted version XOR this value ( 16) will be clipped by ENCODE MODULE read next value simulate the shift read another value simulate the shift XOR 1 68 157 68 v RB 5, RB 7RB 10 RB 12-RB 14 RB 16 RB 20 RB 5, RB 7RB 10 RB 12-RB 14 RB 16 RB 20 RB 5, RB 7RB 9 RB 12-RB 14 RB 16 RB 20 RB 5, RB 7RB 9 RB 12-RB 14 RB 16 RB 20 RB 5, RB 7RB 9 RB 12-RB 14 RB 16 RB 20 RB 5, RB 7RB 10 RB 12-RB 14 RB 16 RB 20 RB 5, RB 7RB 10 RB 12-RB 14 RB 16 RB 20 RB 21-RB 22 call DECODE I MODULE CR 1 =DO 1 = 12, EOF 1 = O CRI( 13) = CRI( 12) + DN(I) OVL = O, call DECODE II MODULE CR 2 = DO 2 = 13, EOF 2 = O EOFL EOF 2 = O CR 1 =CR 2 = 13 call DECODE I MODULE CRI= DOI = 11,EOFI = O C Rl( 12) = CRI( 1 1) + DN(I) OVL = O call DECODE II MODULE CR 2 = DO 2 = 12, EOF 2 = O EOFL EOF 2 = O CR 1 I= CR 2 = 12 call DECODE I MODULE CRI =DOI = 10, EOFI = O CR( 1) = C Rl( 10)+ DN( 1) OVL = O call DECODE II MODULE CR 2 = DO 2 = 11, EOF 2 = O EOF 1 I= EOF 2 = O CR 1 =CR 2 = 11 call DECODE I MODULE CR 1 =DO 1 = 9,EOF 1 = O CRI( 10) = CR( 9) + DN( 1) OVL= O call DECODE II MODULE CR 2 = DO 2 = 10, EOF 2 = O EOFL EOF 2 = O CR 1 = CR 2 = 10 call DECODE I MODULE CR 1 = DO 1 = 8,EOF 1 = O CRI( 9) = CRI( 8) + DN(I) OVL = O ‘.
call DECODE II MODULE CR 2 = DO 2 = 9,EOF 2 = O EOFL EOF 2 = O CR 1 = CR 2 = 9 call DECODE I MODULE CR 1 =DO 1 = 7,EOF 1 = O CRI( 8) = CRI( 7) + DN(I) call DECODE II MODULE CR 2 = DO 2 = 8,EOF 2 = O EOF 1 EOF 2 = O CR 1 =CR 2 = 8 call DECODE I MODULE CR 1 =DO 1 = 5,EOF 1 = O CRI( 6) = CRI( 5) + DN( 1) OVL = O call DECODE II MODULE CR 2 = DO 2 = 7, EOF 2 = O EOF 1 EOF 2 = O CR 2 ( 7) > CRI( 6) EI = CR 2 = 7 call ENCODE MODULE shift read DECODE II MODULE XOR read DECODE I MODULE shift XOR read shift XOR read shift read XOR XOR read XOR read shift send CR 2 to ENCODE MODULE output it 1.570344 69 RB 12-RB 14 RB 16 RB 20 RB 23-RB 24 RB 25-RB 29 RB 16 RB 20 RB 5, RB 7RB 10 RB 12-RB 14 RB 16 RB 20 RB 5, RB 7RB 9 RB 12-RB 14 RB 16 RB 20 RB 21-RB 22 RB 12-RB 15 RB 16 RB 20 RB 23-RB 24 RB 25-RB 29 RB 16 RB 20 RB 5, RB 7, RBI; RB 12-RB 14 RB 16 RB 20 RB 21-RB 22 RB 12, RBI 3, RB 15 RB 16 RB 17-RB 19 1,570,344 call DECODE II MODULE CR 2 = DO 2 = 5, EOF 2 = O EOF 1 EOF 2 = O CRI( 6) > CR 2 ( 5) FI =CR 1 = 6 call ENCODE MODULE call DECODE I MODULE CR 1 =DOI = 4, EOFI = O CRI( 5) = CRI( 4) + DN(I) OVL = O EOFI EOF 2 = O CR 1 =CR 2 = 5 call DECODE I MODULE CRI =DOI = 3, EOF 1 = O CRI( 4) = CRI( 3) + DN( 1) OVL = O call DECODE II MOD CR 2 = DO 2 = 4, EOF 2 = O EOF 1 EOF 2 = 0 CRI =CR 2 = 4 call DECODE I MODULE CR 1 =DO 1 = 1, EOFI = O CRI( 2) = CRI( 1) + DN(I) OVL = O call DECODE II MODULE CR 2 = DO 2 = 3, EOF = O EOFL EOF 2 = O CR 2 ( 3) > CRI( 2) EI = CR 2 = 3 call ENCODE MODULE call DECODE II MODULE CR 2 = D 02 = 1, EOF 2 = O EOF 1 EOF 2 = 0 CRI( 2) > CR 2 ( 1) EI =CR 1 = 2 call ENCODE MODULE call DECODE I MODULE CRI =DO 1 =-0, EOFI = O CR(I) = CRI( 0) + DN(I) OVL = O EOF EOF 2 = O CRI = CR 2 = 1 call DECODE I MODULE CR 1 =-1, EOFI = 1 call DECODE II MODULE CR 2 = DO 1 = 0, EOF 2 = O EOF 1 EOF 2 = O CR 2 ( 0) > CRI(-1) EI =CR 2 = O call ENCODE MODULE call DECODE II MODULE CR 2 = -1 EOF 2 = O EOF 1 EOF 2 = 1 ‘.
set ELAST call ENCODE MODULE MLNI, MLN 2 = MLN 3 read DECODE II MOD again send CRI to ENCODE MODULE read shift XOR read XOR read XOR output CR 2 read DECODE II MOD again XOR output CR 1 read DECODE I MODULE shift XOR read EOF reached DECODE I MOD XOR output CR 2 EOF reached DECODE II MOD output last value from ENCODE MODULE reset lengths RB 2-RB 4 call DELTA MODULE; get next DELTA value DN = O DELEND = 1 reset DECODE I and II, ENCODE MODULES DELEND= I 5 RB 6 RS = 1 EXIT Upon EXIT the MEMORY MODULE contains line 7 of the iso-entropicgram of Table 4-B which in absolute decimal occurrence values is 7, 6, 3, 2, 0.
VII REVOLVER The portion of the DPM SYSTEM including the MEMORY, ENCODE, 10 DECODE I and II, DELTA, and REVOLVE MODULES forms an isoentropicgram revolver Fig 19 is a block diagram of the iso-entropicgram revolver.
The iso-entropicgram revolver revolves a received binary coded input line signal to a new line signal in the iso-entropicgram for the input line The MEMORY MODULE forms a means for storing a received input line As is explained above, the MINI COMPUTER with user program causes an event occurrence vector, or some other binary coded number, to be stored into an area of the MEMORY MODULE Though not essential to the present invention, in the disclosed embodiment the number is stored in the MEMORY MODULE in hybrid code The number which forms the input line comprises a binary coded signal 20 representing one or more actual occurrence values from a group of decreasing monotonically ordered possible occurrence values The actual occurrence values correspond to what has been referred to as event-times and the possible occurrence values are all of the event-times which are within the width of the isoentropicgram.
The DELTA MODULE forms a means for forming a signal indicating the 25 number of lines the received input line signal is to be revolved.
The REVOLVE MODULE forms a new line signal forming means and includes means such as the CRI and CR 2 registers, the DN register, the RD 52 selection circuit, the ALU, and the control counter depicted in Fig 17 which is responsive to the number of lines signal indication provided in the DELO register 30 by the DELTA MODULE and the input line signal stored in the MEMORY MODULE for forming a binary coded signal corresponding to the received input line shifted relative to itself by the number of possible occurrence values identified by the number of lines indication signal.
The new line signal forming means also includes means such as the CRI, CR 2 35 and DN registers, the RD 53 selection circuit, the ALU and the control counter of the REVOLVE MODULE, the ENCODE, DECODE I and II and the MEMORY MODULES for exclusive O Ring (XO Ring) the occurrence values represented by the received input line signal and the shifted input line signal for forming a resultant signal representing one or more occurrence values in monotonical value 40 order.
By way of example, the resultant signal is coupled through the RD 54 selection circuit to register El of the ENCODE MODULE which then converts the absolute coded value of the occurrence values in the result back to hybrid code for storage in the MEMORY MODULE The new line signal forming means also includes 45 means such as the ALU and its OVL and OVL output circuits and the related portions of the REVOLVE MODULE which are operative during RB 5, RB 8, RB 9, RB 10, RB 25, RB 27, RB 28 and RB 29 for eliminating the shifted occurrence values from the resultant series of occurrence values which are not within the group of possible occurrence values making up the width of the iso-entropicgram 50 According to a preferred embodiment of the invention, the DELTA MODULE receives a signal representing the total number of lines to be revolved and contains internal means for converting such representation into one or more signals representing one or more of its component powers of 2.
Also preferably, the means for shifting includes means such as the ALU, the 55 CRI, CR 2 and DN registers and the DECODE I and II MODULES which are operative during RB 5, RB 8, RB 9, RB 10 and RB 25-RB 28, for responding to a component power of 2 signal, received as input to the DN register for forming a shifted line signal corresponding to one of the input line signals The occurrence values represented by the shifted line signal represent the occurrence values of the 60 line signal received as input shifted by the number of possible occurrence values designated by the component power of 2 signals stored in the DN register The 1,570,344 exclusive O Ring means includes means such as the CRI and CR 2 registers and the ALU operative during such flow boxes as RB 20, RB 21, RB 5 and RB 23 for exclusive O Ring the occurrence values represented by a line signal received as input by the shifting means and the corresponding shifted line signal for forming a corresponding resultant line signal 5 In this connection it will be noted that the unshifted and shifted values successively stored in the CRI and CR 2 registers are ordered into monotonical value order and those values which are found to be equal (indicated by a true signal at the E output of the ALU) are dropped or eliminated.
In order to revolve from one line across successive lines in an iso 10 entropicgram, the switching matrix (yet to be described) forms a means for coupling the input line signal and the resultant line signal, formed as a result of the exclusive O Ring, as an input to the means for shifting described above.
Additionally, the connection from the DELO register in the DELTA MODULE to the DN register in the REVOLVE MODULE and the load control for the DN 15 register forms a means for coupling, as input, to the means for shifting one of the component powers of 2 signals for operation on each one of the line signals which are received as input by the shifting means.
Preferably, the means for shifting includes the ALU and the RD 53 selection circuit of the REVOLVE MODULE-for combining the value of each component 20 power of 2 signal stored in the DN register with each actual occurrence value stored in the CRI register.
According to a preferred embodiment of the invention, the input line signals are stored in a composite code such as the hybrid code and first and second decoders such as the DECODE I and II MODULES are operable independently 25 for separately providing an individual actual occurrence value signal representative of each occurrence value of the input line signal The decoders each provide the actual occurrence value signals in the order of the values in the input line signal.
Also preferably, the resultant signals are encoded by means such as the ENCODE MODULE from the actual occurrence value code back to the 30 composite code before the result is stored in the MEMORY MODULE.
VIII SEED MODULE A General Description
The SEED MODULE takes an occurrence vector and locates the shortest line of the occurrence vector in its iso-entropiegram The shortest line is referred to as 35 the seed line.
Though the seed line can be located by revolving the occurrence vector line by line through its iso-entropicgram, noting the length of each line and looking for the shortest line, such an approach would be time consuming Therefore it is desirable to minimize the seed finding time in data processing equipment 40 Additionally, as discussed above, information is actually stored in memory in encoded or hybrid coded form which further reduces the size of the stored information.
Generally speaking then the disclosed embodiment of the invention locates seeds as follows An event occurrence vector, to be converted to seed form, is 45 stored in the MEMORY MODULE and is presented to a seed finding machine which includes the SEED, ENCODE, DECODE I and II, DELTA and REVOLVE MODULES.
The revolver, including the ENCODE, DECODE I and II, DELTA and REVOLVE MODULES, revolves the input line down through the lines of the iso 50 entropicgram and as this is done each line is presented to the ENCODE MODULE for encoding to hybrid form The physical length of each line is noted and the encoded or hybrid coded line that is physically shortest in length is the one selected as the seed line.
According to a preferred embodiment of the invention, seed finding employs 55 the SEED MODULE which receives as input, primarily, an event occcurrence vector signal forming an input line signal of an iso-entropicgram and a signal that represents the iso-entropicgram width for such input line The event occurrence vector or input line signal represents actual occurrence values out of a group of possible occurrence values arranged in a decreasing incremental value order from 60 a largest to a smallest value The SEED MODULE computes the difference between the largest two occurrence values represented by the input line and computes the difference between the value represented by the width signal and the largest occurrence value in the input line The largest of the two differences 1,570,344 indicates the number of lines to be revolved in the iso-entropicgram The SEED MODULE calls the REVOLVE MODULE, causing it to revolve the input line signal down the number of lines indicated by the largest difference The new line signal (in hybrid code) is then checked against the original input line signal and the shorter is kept as the possible seed line The above procedure is then repeated 5 using the possible seed line signal as the input line signal The newly revolved line signal is compared against the retained possible seed line signal and the shorter is again retained as the possible shortest line This operation is repeated until the REVOLVE MODULE has revolved over all possible lines in the isoentropicgram.
At that time, the possible seed line is retained in the ENCODE MODULE as the 10 seed line.
The right hand side of Table 4-B indicates an example of this implementation of the SEED MODULE.
B Components Refer now to Figs 20 and 21 The SEED MODULE has the following input 15 registers, each containing eight flip flops for storing 8 binary coded bits: ONOC, SDN, SLINE, SLN, SMHW, SMLI, TO, Tl and T 3 Additionally, a two bit, two flip flop register OAR is provided The registers ONOC, SLINE, SLN, SMLI, TO and Tl are formed of register type SN 74100 disclosed at page 259 of the above TTL book and the registers SMHW and SDN are formed of registers of type SN 74116 20 disclosed at page 261 of the above TTL book where a true signal at the L input causes the 8 bits of information at the upper input to be stored therein.
Additionally, the SMHW and SDN registers are responsive to a true signal at the CLR input for resetting or clearing to 0 The other registers in the system are characterized in that all registers in the SEED MODULE are of the type that the 25 output signal follows or reproduces the information input signals during the presence of a true clock signal at the clock or load (L) input The register retains at its output and stores the signals being applied at its information input when the true signal at the clock or load input terminates The T 3 register is formed of an SN 4174 type register disclosed in the above TTL book where the leading edge or true 30 excursion of the pulse at L loads and retains the then existing information input signals even though the information input signals change before the true pulse at L terminates This is done since during the true signal at P 2 it is only desired to strobe the initial signals from DOI into register T 3 The register OAR is formed of two flip flops of the same type as the reset of the flip flops whose lower left side clock input 35 is connected to designated L input and whose inputs are connected to upper left side information inputs.
The SEED MODULE also has flip flops SCE, CNG, SMB and a control counter 513 having flip flops PO to P 10 Each of these flip flops are of the same type SN 7474 disclosed above under Conventions and Components Used in the Figures 40 Selection circuits SDSI-SD 56 are provided for gating any one of the information input signals indicated along the upper side of each selection circuit to the output responsive to a true signal applied to one of the control inputs at the side of the selection circuits These selection circuits are of the same type as that disclosed above in the section Conventions and Components Used In the Figures 45 An arithmetic unit ALU is provided for adding, subtracting and comparing the information signals applied to the two information inputs indicated along the upper side of the ALU The arithmetic unit ALU is of the same type as that disclosed above in the section Conventions and Components Used in the Figures An OR gate 516 has its inputs connected to the G and E outputs of the ALU and forms a 50 true signal at the GE output when a true signal is formed in either the G or E output In addition, the SEED MODULE has conventional OR gating circuits 516, 517 and 518 and a conventional AND gating circuit 520 Additionally, the SEED MODULE has logical gating circuits which form true and false signals enabling the operation of many of the circuits shown in the SEED MODULE These gating 55 circuits are indicated by logical equation for simplicity A logical signal inverter 526 is connected between the clock CLK output of AND gate 520 and the input to the CLK output for forming pulses between the CLK pulses.
The SEED MODULE also has one-shot multi-vibrators SMGO and SMEND as well as a clock 512 The clock 512 is a source of regularly recurring true clock 60 pulses as indicated The one-shot multi-vibrators are responsive to a true signal applied at the input indicated along the left hand side for triggering to a 1 state where a true signal is formed at an unprimed output The one-shots remain in a 1 state for a time interval equal to that between the beginning of two successive clock 1,570,344 pulses from the clock 512 and then returns to an 0.
The SEED MODULE has three sets of switches 526, 528 and 530 The switches 526, 528 and 530 are mechanical or electronic switches which represent, respectively, the decimal values 1, 2 and 3 in binary coded form as 01, 10 and 11, respectively Table 16 lists the primary registers, flip flops and oneshots and 5 identifies their primary purpose.
Similar to other modules, the control inputs and outputs are indicated along the right hand side of Fig 20 and the information inputs and outputs are indicated by large solid lines also along the right hand side.
C Detailed Description 10
Consider now the details of organization of the SEED MODULE, making particular reference to the schematic and block diagram of Figs 20 and 21, and the SEED MODULE flow diagram of Fig 22 The flow diagram contains blocks indicating the sequence of operation The symbols SB I through SB 18, shown next to the blocks, are used to identify the boxes in the flow diagram The symbols 15 designating the various flip flops of the control counter 513 are also shown in parentheses adjacent the various blocks to help relate the operation indicated in each box of the flow with the state of the control counter 513.
Initially, the OR gates 516 and 517 receive true signals from the MINIT output of the MINI COMPUTER which causes flip flops P 0-P 10 and SCE to be reset to O 20 states Subsequent true signals formed at SMEND by one-shot SMEND cause OR gate 517 to reset flip flops P 0-Pl O to 0.
Table 11 shows the primary inputs to the SEED MODULE as well as the inputs to the ENCODE, DECODE I and II, DELTA and REVOLVE MODULES making up the seed finder The initial inputs come principally from the IPRF (Fig 25 52) and the MEMORY MODULE Accordingly, the MINI COMPUTER, in the manner described hereinafter, first loads the IPRF and the MEMORY MODULE with the required initial input information To this end the MINI COMPUTER initially stores an event occurrence vector, in hybrid code, into MEMORY MODULE area 1 This event occurrence vector is the input line for an iso 30 entropicgram and at the beginning of the operation of the seed finder forms what is currently assumed to be the seed line.
To be explained in more detail, the input or current line may not necessarily be line 0 of its iso-entropicgram and accordingly the number of the input line as well as the width value for the iso-entropicgram are initially stored by the MINI 35 COMPUTER into registers LINE # and HW of the IPRF (Fig 52) The length of the input line is variable and hence a length value specifying the number of words in this input line is stored in register LINE # of the IPRF.
After the IPRF and MEMORY MODULE area 1 are loaded, the SEED MODULE is called by the MINI COMPUTER or the CHANGE MODULE by 40 forming signals at the USER and CM 2 outputs, respectively A true signal at either of these outputs causes the OR gate 518 to apply a true signal to the oneshot SMGO, triggering it to a 1 state causing a true signal at the SMGO output The true signal at the SMGO output sets the SCE flip flop to a I state The output from clock suspension logic 522 is initially true Therefore, the true signal at the SCE output of 45 the SCE flip flop enables the AND gate 520 to couple clock pulses from the clock 512 to the CLK output, which in turn causes an inverter 526 to form pulses at the CLK output The 0 state of the flip flops PO to Pl O causes true signals at the P 0, Pl P 10 outputs, thereby causing the flip flop PO to be set to a 1 state at the following pulse at CLK, thereby causing SB I of the SEED MODULE flow to be 50 entered.
During SB I of the flow during the true signal at PO output, the input parameters for the SEED MODULE are stored into their proper registers During the true signal at the PO output of the SEED MODULE, the initial input parameters for SEED MODULE are also enabled and clocked into their proper 55 registers Additionally, the SWITCH MATRIX is set so that the REVOLVE MODULE when called for the first time will cause the DECODE I and IIMODULES to read the input line from the MEMORY MODULE area I and cause the ENCODE MODULE to write the revolved or new line into the MEMORY MODULE area 2 60 It should be noted that the CHANGE MODULE forms a true signal at the CM 4 output, thereby setting the CNG flip flop to a 1 state only when the CHANGE MODULE is the calling module Referring to the right hand side of Fig 20, true signals at the P 0, CNG and CLK outputs cause true signals at the SM 1, SM 2 and 1,570,344 74 1,570,344 74 SM 3 outputs to the SWITCH MATRIX and also cause input parameters to be loaded into the ENCODE, DECODE I and II, and DELTA MODULES in the manner and from the sources discussed above for each of these modules.
A true signal is only formed at the outputs SM 1, SM 2 and SM 3 when the MINI COMPUTER is the calling module Thus, assuming that the MINI COMPUTER is the 5 calling module, true signals are formed at the SMI, SM 2 and SM 3 outputs The true signal at S Ml causes flip flops 511, 522 and 531 to be set to I in the SWITCH MATRIX The true signal at SM 2 causes the length value LNI in IPRF to be gated to registers MLNI and MLN 2 of the DECODE I and II MODULES and the pulse at SM 3 actually causes the length value to be loaded into the registers MLNI and MLN 2 and 10 into register EHW of the ENCODE MODULE Additionally, the true signal at output PO resets the SMB flip flop to an 0 state The true signals at P 0, CNG (CHANGE MODULE is not the calling module) cause the SD 56 selection matrix to couple the line number in the LINE # register of the IPRF to the information input of the SMLI register Note that if the CHANGE MODULE were the calling module, the 15 true signals at CNG and PO would cause the switching circuit SD 56 to couple the line number from the CLINE register of the CHANGE MODULE to the register SMLI During the true signal at the PO output, the pulse at CLK causes the line number from SD 56 to be stored into register SMLI and causes the SMHW register to store the iso-entropicgram width signal from the HW register of the IPRF (Fig 20 52).
Thus, the SMLI register contains the line number of the input line (stored in MEMORY MODULE area I) and the SMHW register contains the isoentropicgram width value.
The true signal at PO causes flip flop Pl to be set to a I state Therefore, also 25 during SB I of the SEED MODULE flow, the true signal at the Pl output causes the selection circuit SB 57 to couple the length value from register MLNI of the DECODE I MODULE to the information input of register SLN Additionally, the true signal at Pl causes the SDN register to be reset or cleared to 0 and causes the SMB flip flop to be set to a 1 state The 1 state of the SMB flip flop causes a true 30 signal at the SMB output to be removed and thereby remove the true signal at the SMIO output As explained above, the signal SM 1 O goes to the DECODE I MODULE, and when false, inhibits the count down of the physical length of the input line in MLNI The SEED MODULE is about to become operative during SB 2 through SB 5 for causing the DECODE I MODULE to do a read on the input 35 line from the MEMORY MODULE only for the purpose of reading the largest two occurrence values of the input line and the count down of MLNI is inhibited during this operation because the DECODE I MODULE will later be called to go back to the beginning of the same input line to again read the same occurrence values 40 At this point in time, the input line is retained as the current possible seed line since this is the only line considered to this point The register SLINE stores the number of the current possible seed line Accordingly, the true signal at the Pl output causes the SD 55 selection circuit to couple the input line number from register SMLI 1 to the information input of register SLINE and the true signal at the 45 CLK output causes the line number to be loaded into register SLINE.
Additionally, it is necessary to prevent the SWITCH MATRIX from allowing the MEMORY MODULE area 1 containing the input line to be overwritten since this line is to be retained as the current possible seed line In order to insure that the SWITCH MATRIX retains the input line in MEMORY MODULE area 1, the true 50 signal at the Pl output causes the SMS flip flop to be set to a 1 state which in turn causes a true signal to be formed at the SM 5 output of the SEED MODULE The SM 5 output in turn is connected to the SWITCH MATRIX and a true signal at SM 5 in conjunction with RM 12 from the REVOLVE MODULE causes the SWITCH MATRIX to prevent overwriting of MEMORY MODULE area 1 55 During SBI, SB 2 of the SEED MODULE flow is entered During SB 2, the true signal at the Pl and CLK outputs causes a true signal at the SM 6 output which in turn calls the DECODE I MODULE by setting the DIGO one-shot to a 1 state.
The DECODE I MODULE then commences its operation of obtaining the largest occurrence value from theinput line in MEMORY MODULE area 1 The true 60 signals at the outputs PI, CLK and DIMEND (from the DECODE I MODULE) causes SM 6 to be true and the clock suspension logic 522 removes the true signal at the corresponding input of gate 520 and stops clock pulses from being formed at the CLK and CLK outputs, thereby suspending operation of the SEED MODULE while the DECODE I MODULE completes its operation and provides a decoded occurrence value.
After the DECODE I MODULE provides the largest occurrence value from the input line stored in MEMORY MODULE area 1, the true signal of DIMEND is removed, thereby causing the clock suspension logic 522 to again apply a true 5 signal at the corresponding input of gate 522 enabling pulses to be formed at the CLK and CLK outputs.
The true signal at the Pl output, together with the true signal at the EOFI output, causes the flip flop P 2 to be set to a 1 state The true signal thus formed at the P 2 output in coincidence with a true clock signal at output CLK causes this 10 largest occurrence value from register DOI of the DECODE I MODULE to be stored into the T 3 register Note that should a true signal be formed at the EOFI output, a false signal is fomed at the EOFI output and, hence, the flip flop PIO would be set to a 1 state rather than the P 2 flip flop If EOFI is set, there is no meaningful output from DECODE I MODULE As a result, the output from the 15 DECODE I MODULE would not have been stored into register T 3 Hence, state SB 16 of the SEED MODULE flow would be entered from SB 3 During SB 4 of the flow, the true signal at the P 2 output also causes the SD Sl and SD 52 selection circuits to couple the iso-entropicgram width value from register SMHW and the largest occurrence value from the DOI register of the DECODE I MODULE to 20 the inputs of the ALU and causes the ALU to subtract the largest occurrence value from the width value The resultant difference formed at the OP output of the ALU is coupled to the information input of register TI by the SD 54 selection circuit, under control of output P 2, and the true signal at the P 2 output causes the difference signal formed at the OP output to be stored into register TI at the 25 following pulse at CLK Thus, following SB 4 of the SEED MODULE flow, the largest occurrence value is contained in register T 3 and the register TI contains the difference between the iso-entropicgram width value and the largest occurrence value of the input line.
SB 5 of the SEED MQDULE flow is then entered and true signals are formed 30 at the outputs P 2 and CLK thereby forming a true signal at the SM 6 output which again calls the DECODE I MODULE by setting DIGO to a 1 state The MARI register of the DECODE I MODULE has now been counted up by 1 address, thereby forming the address of the next to the largest occurrence value of the input line contained in MEMORY MODULE area 1 Thus, the DECODE I MODULE 35 now reads out the next to the largest occurrence value and stores it in its DOI register While this takes place, the true signals at the P 2, CLK and DIMEND outputs again cause the clock suspension logic 522 to disable the AND gate 520 thereby terminating the pulse at CLK When the DECODE I MODULE has completed its operation thereby providing the next to the largest occurrence value 40 in its register DOI, the true signal is removed at the DIMEND output thereby causing the clock suspension logic 522 to enable the AND gate 520 to start causing pulses at CLK and C The true signal at the P 2 and EOFI output also causes the flip flop P 3 to be set to a I state at the following pulse at CLK If EOFI is set, then flip flop Pl O is set to 45 1 The signal at the P 3 output causes the SDSI and SD 52 selection circuits to couple the largest occurrence value in register T 3 and the next to the largest occurrence value from register DOI (DECODE I MODULE) to the information input of the ALU and causes the ALU to subtract the next to the largest occurrence value from the largest occurrence value and form a corresponding 50 difference signal at the OP output.
SB 7 of the SEED MODULE flow is now entered The true signal at the outputs P 3 and CLK causes the register TO to store the difference signal Thus, at this point in time, the register TO contains the difference between the largest two occurrence values of the input line, and the register TI contains the difference 55 signal representing the difference between the width value and the largest occurrence value.
Again, note that should the DECODE I MODULE be at the end of a file and a.
true signal be formed at the EOFI output, a true signal is not formed at the EOFI output Hence, the flip flop P 3 would not have been set and instead the flip flop Pl O 60 would have been set to a I state, causing SD 16 of the SEED MODULE flow to be entered.
Assume now that true signals are formed at the output P 3 The P 4 flip flop is set to a I state causing SB 8 of the SEED MODULE flow to be entered During SB 8, a true signal is formed at the P 4 output The true signal at the P 4 output causes 65 1,570,344 7.S the difference between the largest two occurrence values of the input line, contained in register TO, and the difference between the width value and the largest occurrence value, contained in register Tl, to be coupled through selection circuits SDSI and SD 52, respectively, to the information inputs of ALU and causes the ALU to compare the two difference values Note carefully that should the 5 difference between the largest two occurrence values contained in register Tl to be greater, a true signal is formed at the G output of ALU and the contents of register TI remain unchanged However, should the difference between the width value and the largest occurrence value in register TO be larger, a true signal is formed at the L output of ALU A true signal at the P 4 and L outputs causes the selection 10 circuit SD 54 to couple the content of the register TO to the information input of register Tl and the true signals at the P 4, L and CLK outputs cause the content of register TO to be stored into register Tl Thus, it now can be seen that register TI stores the larger of the difference between the largest two occurrence values of the input line and the difference between the iso-entropicgram width value and the 15 -largest occurrence value Note that the larger of the difference values now contained in Tl is the number of iso-entropicgram lines by which the input line stored in the MEMORY MODULE is now to be revolved.
The true signal at the P 4 output causes the P 5 flip flop to be set to a 1 state at the following pulse at CLK, thereby causing the SB 9 of the SEED MODULE flow 20 to be entered.
The register SDN is used to accumulate and keep track of the total number of iso-entropicgram lines revolved by the REVOLVE MODULE Thus, during SB 9, the number of lines next to be revolved (the largest difference signal) contained in register Tl is added to the content of register SDN The first time through SB 9 the 25 register SDN contains 0 To be explained in more detail, during SB 10 the total lines revolved contained in register SDN is compared with the iso-entropicgram width value contained in register SMHW to determine when the number of lines revolved exceeds the width value for the iso-entropicgram.
To this end, the true signal at the P 5 output causes selection circuits SD Sl and 30 SD 52 to couple the content of registers SDN and Tl to the information inputs of the ALU, and causes the ALU to add the values together and form a sum If no overflow occursd, OVL is true and the logic P 5 CER L becomes true and stores the sum into register SDN Note that if an overflow occurs, the signal at OVL will be false, preventing the result at the output of OP being stored back into SDN Also 35 if overflow occurs, it is necessary to clear the width value in register SMHW to 0 so that the subsequent compare during P 7 will cause a GE condition which will in turn cause Pl O to be set to 1 and terminate the operation It is desired to terminate because if overflow occurs, an attempt is being made to revolve to a line which is not within the iso-entropicgram for the input line 40 The true signal at the P 5 output causes the flip flop P 6 to be set to a 1 state at the following pulse at CLK The true signal at the P 6 output causes the SDS I and SD 52 selection circuits to couple the line number value contained in register SMLI and the number of lines to be revolved value contained in register Tl to the information inputs of the ALU and causes the ALU to add the values together and 45 form the sum at the OP output The true signals at the outputs P 6 and CTK cause the SD 56 selection circuit to couple the sum to the information input of SM 1 and to store the sum into register SMLI Thus, register SMLI now contains the number of lines revolved relative to the number of the input line Note that should overflow have occurred, the sign bit at the output of ALU is disregarded because this 50 amounts to an additional module of the iso-entropicgram length.
The true signal at the P 6 output causes the P 7 flip flop to be set to a 1 state responsive to the following pulse at CLK and causes SB 10 of the SEED MODULE flow to be entered During SB 10, the number of lines revolved value is compared with the width value as described in connection with SB 9 If the number of lines 55 revolved value contained in register SDN is greater than the isoentropicgram width value contained in register SMHW, the SEED MODULE goes to SB 16-18 following which the operation of the SEED MODULE exits An exit is taken at this point in the operation since the REVOLVE MODULE will have revolved across all lines in the iso-entropicgram If the number of lines revolved value contained in 60 register SDN is less than the iso-entropicgram width value contained in register SMHW, meaning that the SEED MODULE has not revolved across all lines of the iso-entropicgram, SB II through SB 14 of the SEED MODULE flow are entered.
Assume during SB 10 that the number of lines revolved value contained in register SDN is less than the width value contained in register SMHW, the true 65 1,570,344 signal at the P 7 output causes the SD Sl and SD 52 selection circuits to couple the number of lines revolved value (register SDN) and the width value (register SMHW) to the information inputs of the ALU and causes the ALU to compare the two values forming a true signal at the L output The true signal at the L output of the ALU in coincidence with the true signal at the P 7 output causes the P 8 flip flop 5 to be set to a 1 state at the following CLK pulse and SB 11 of the SEED MODULE flow is entered.
During SB 11, the number of lines to be revolved value contained in register Ti is sent to the DELTA MODULE which in turn forms the component powers of 2 of this value beginning with the largest component power of 2 as discussed above in 10 connection with the DELTA MODULE To this end, the true signal at the P 8 output causes a true signal at the SM 7 output which in turn causes the DELS selection circuit in the DELTA MODULE to couple the largest difference value from register T 1 to the information input of the register 302 in DELI A true signal at the P 8 output of the SEED MODULE in coincidence with the true signal at the 15 CLK output causes a true signal at the SM 8 output which in turn causes the load circuitry of register 302 in DELI to store the larger difference value from register Tl into register 302 of DELI.
SB 12 of the SEED MODULE is now entered The true signals at the outputs P 8 and CLK also cause a true signal at the SM 9 output which in turn calls the 20 REVOLVE MODULE by setting the REVGO one-shot to a 1 state The REVOLVE MODULE in turn calls the DELTA MODULE as discussed above and the REVOLVE MODULE and DELTA MODULE in conjunction with the DECODE 1, DECODE II and ENCODE MODULES revolve the input line, contained in MEMORY MODULE area 1, down the number of lines indicated by the largest 25 difference value sent to the DELTA MODULE During this operation, the true signal at the P 8 and REVEND output causes the clock suspension logic 522 to again disable gate 520 and thereby suspend the operation of the SEED MODULE After the designated number of lines have been revolved by the REVOLVE MODULE, the true signal is removed at the REVEND output, thereby causing the clock 30 suspension logic 522 to again enable gate 520, thereby enabling a clock pulse to again be formed at tyhe CLK and =K outputs in the SEED MODULE The following pulse at CLK causes the flip flop P 9 to be set to a 1 state, thereby causing SB 13 of the SEED MODULE flow to be entered The true signal at the P 9 output of the control counter 513 in the SEED MODULE causes the SD 51 and SD 52 35 selection circuits to couple the length value (number of words in the hybrid coded line written into the MEMORY MODULE by the ENCODE MODULE) contained in register MLN 3 of the ENCODE MODULE to be gated to one input of the ALU and causes the length of the original input line which length value is contained in register SLN to be gated to the other input of ALU and causing the 40 ALU to compare the two values If the length of the new line as indicated by register MLN 3 is smaller than the current seed line as indicated by register SLN, the ALU forms a true signal at the L output indicating that MLN 3 is less This causes SB 15 of the SEED MODULE flow to be entered where the content of register MLN 3 (which is smaller) is stored into the SLN register If, on the other 45 hand, the length value for the new line (in register MLN 3) is equal to or greater than the length value of the original input line (in register SLN), true signals are formed at the G or E outputs of the ALU, causing the OR gate 516 to form a true signal at the GE output This causes SB 14 of the SEED MODULE flow to be entered In this manner, the smallest of the length values for the original input 50 (current possible seed) line (register SLN) or for the new line (register SLN 3) is retained in register SLN.
Consider now the actual operation in this regard Assume that the length of the new seed line is smaller and hence a true signal is formed at the L output of the ALU during the true signal at P 9 The SD 57 selection circuit couples the length 55 value from register MLN 3 of the ENCODE MODULE to the information input of register SLN and the following pulse at CLK in coincidence with the true signals at P 9 and L cause the load circuit of register SLN to store the length value from register MLN 3 into register SLN Additionally, since the new line is now shorter, it is necessary to store the line number of the new line into register SLINE 60 Accordingly, the true signal at P 9 causes the SD 55 selection circuit to couple the line number value for the new line from register SMLI to the information input of register SLINE and the true signals at the P 9, L and CLK outputs cause the load circuit of register SLINE to store the line number value Additionally, the true signals at the outputs P 9, L and CLK cause the SMS flip flop to be set to a I state 65 1,570,344 which, as discussed above, causes a true signal at the SM 5 output thereby indicating to the SWITCH MATRIX that the new line stored into the MEMORY MODULE area 2 should be retained as the possible seed line Following SB 15, SB 14 of the SEED MODULE flow is entered and the true signal at the P 9 output causesthe SMB flip flop to be set to a 1 state, thereby removing the true signal at 5 the SMB output This is required since the DECODE I MODULE is going to read the new line for computing the larger of the difference between the largest two occurrence values of the new line and the difference between the width value and the largest occurrence value The lack of a true signal at the output SMB and hence at the output SM 10, causes the DECODE I MODULE to prevent the MLN 1 10 register of the DECODE I MODULE from being counted down.
Return to SB 13 of the SEED MODULE flow and assume that a control signal is formed at the GE output of OR gate 516, indicating that the length value of the new line is equal to or larger than the current possible seed line contained in reigster SLN This causes SB 14 of the SEED MODULE flow to be entered, 15 skipping SB 15 and accordingly, the current seed length value register SLN and its current seed line number value in register SLINE remain unchanged Likewise, flip flop SMS remains unchanged, thereby causing a false signal at the SMS output and, hence, at the SM 5 output of the SEED MODULE, thereby signalling the SWITCH MATRIX that the new line contained in MEMORY MODULE area 2 can be 20 overwritten and need not be saved The true signals at the P 9 and P 9 CLK outputs cause true signals at the SM 1 1 and SM 12 outputs.
At this stage the first revolve has just been completed and the new line is in the MEMORY MODULE area designated by the 531 flip flop in the SWITCH MATRIX Though the description has been made up to this point for only the first 25 or input line stored in the MEMORY MODULE, the same general operation takes place if a new current seed line is formed In this latter case, during SB 13 the new seed line may be stored in any one of the MEMORY MODULE areas The area will be specified by the true state of one of flip flops 531, 532 and 533 as more fully described in connection with the MEMORY MODULE and the SWITCH 30 MATRIX.
The 531 signal has to be relayed to the 511, 512, 513 flip flops of the SWITCH MATRIX before the DECODE I MODULE can read the new current seed line At the same time the existing information must not be modified in the MEMORY MODULE areas designated by the 521, 522, 523, or 531, 532 or 533 flip flops 35 Thus, a true signal is formed at the SM 11 output This inhibits the clock signal to flip flops 521, 522, 523, 531, 532 and 533 The true signal at SM 12 then clocks the proper’information from 531, 532, 533 to Sll, 512, 513 in the SWITCH MATRIX When all is done, 52 i, 53 i (i = 1, 2, 3) in the SWITCH MATRIX are unaltered, whereas Sli (i = 1, 2, 3) is able to gate the information 40 from the new line to the DECODE I MODULE Also since the rest of the system remains unchanged, when REVOLVE is called and a true signal is formed at RM 8, the operation proceeds as normal True signals at the P 9 and CLK outputs cause a true signal at the SM 4 output which causes the gate 228 to set flip flop D l FST to a 1 state in the DECODE I MODULE and cause a true signal at the SM 6 output which 45 calls the DECODE I MODULE by setting the DIGO one-shot to a 1 state.
Following SB 14,_B 2 of the SEED MODULE flow is again entered The true signals at the P 9, CLK and ITMEND outputs again cause the clock suspension logic 522 to suspend the operation of the SEED MODULE until the DECODE I MODULE has completed its operation and provides the largest occurrence value 50 in register DOI Note that the DECODE I MODULE now reads the current possible seed line which is contained in the MEMORY MODULE area and which was found by the SEED MODULE during SB 13 to be the shortest After the DECODE I MODULE has completed its operation and is forming the largest occurrence value of the current possible seed line, the true signal is removed at the 55 D 1 MEND output, and the clock suspension logic 522 again enables the gate 520, allowing a pulse to be formed at the CLK output The true signal at the P 9 and EOFI output in coincidence with the true signal at the CLK output causes flip flop P 2 to again be set to a 1 state The resulting true signal at the P 2 output causes the SB 2 of the SEED MODULE flow to again be entered where the largest occurrence 60 value is stored in register T 3 and the difference between the width value and the largest occurrence value is stored via the SD 54 selection circuit into register TI.
The operation during SB 3 through SB 15 is again repeated as discussed above, this time utilizing the current possible seed line which was previously determined during SB 13 65 1,570,344 Assume now that during SB 10 it is found that the total number of lines revolved value contained in register SDN is equal to or greater than the isoentropicgram width contained in register SMHW The ALU then forms a true signal at either the G or the E output, causing the OR gate 516 to form a true signal at the GE output The true signals at the P 7 and GE outputs in turn cause the flip 5 flop P 10 to be set to a true state, thereby causing SB 16 of the SEED MODULE flow to be entered.
During SB 116, the number of the current possible seed line contained in register SLINE is compared with the width value contained in register SMHW If the number of the current possible seed line value in register SLINE is larger, then 10 SB 17 is entered, whereas if it is less, S B 18 is entered.
Consider now the details of the above operation The true signal at the P 10 output causes the SDS 1 and SD 52 selection circuits to couple the current possible seed line number value contained in register SLINE and the width value contained in register SMHW to the information input of the ALU for comparison Assume 15 that the current possible seed line value is larger The ALU forms a true signal at the G or E output which in turn causes the OR gate 516 to form a true signal at the GE output and SB 17 is entered Additionally, the true signal at the P 10 output causes the ALU to form the difference between the current possible seed line value contained in SLINE and the width value contained in register SMHW and forms a 20 difference value at the OP output The true signal at the P 10 output also causes selection circuit SD 55 to couple the difference value from ALU to the information input of the register SLINE The true signal at the P 10, GE and CLK outputs causes a load circuit to store the difference value into the register SLINE Note that the current line number value stored in register SLINE during SB 17 is the seed line 25 number less the iso-entropicgrarn width value That is, the current possible seed line contained in SLINE is greater than the iso-entropicgram width value, the REVOLVE MODULE has revolved past the end of the iso-entropicgram and it is therefore necessary to subtract the width value from the current possible seed line value in order to determine the actual number of the seed line This operation is 30 taken to insure that the current possible seed line value contained in register SLINE lies within the bounds of the iso-entropicgram If a revolve has taken place past the end of the iso-entropicgram, then line values are contained in register SLINE which are greater than the iso-entropicgram width However, these values would be inaccurate and to find the value of the actual seed line value it is 35 necessary to subtract the width value from the line value to arrive at the true number of the seed line.
Following S B 16 or S B 17 of the SEED MODULE flow, S B 18 is entered The true signals at the P 10 and CLK outputs cause the load circuit for the ONOC register to be activated and store the number of occurrences that have appeared in 40 the possible seed line from register ENOC of the ENCODE MODULE into register ONOC.
It should be noted that true signals occur at the P 9, L and CLK outputs during SB 15 when the new iso-entropicgram line is found to be shorter than the current possible seed line The true signals at the P 9, L and CLK outputs cause the register 45 OAR to load values corresponding to MEMORY MODULE areas 1, 2 and 3,respectively, from switches 526, 528 and 530 The one which is selected is determined by the outputs 531, 532 and 533 of the corresponding flip flops in the SWITCH MATRIX which indicate the output area in the MEMORY MODULE so currently being used for the new line 50 D Example of Operation Consider now an example of operation of the SEED MODULE and related portions of the DPM forming the SEED MODULE Assume that the SEED MODULE is to revolve down through the iso-entropicgram shown in Table 4-B discussed above in I GENERAL DESCRIPTION Assume that the input line to be 55 revolved is line 0; thus the revolve will revolve from line 0 to line 2 and then to line 7 Lines 0, 2 and 7 broken down into 7 bit words with a 0 bit indicating absolute word code and a 1 bit indicating hybrid word code at the lefthand end are as follows:
10001110 00011010 E hybridline O 60 01110101 length = 3 1,570,344 10001011 1 00000111 hybrid encoding of line 2 00011010 J length = 3 words 10000111 hybrid encoding of line 7 01011001 J length = 2.
The subsequent sequence of operation of the seed finder is as follows:
Input to the SEED MODULE is from “LINE NO” of IPRF from HW of IPRF from MLN 1 of DECODE I MODULE from DOI of DECODE I MODULE sequence of control line # of the seed ( 0) to SMLI isoentropicgram width ( 16) to SMHW length of input line ( 3) to SLN line ( 0) in MEMORY MODULE area 1 SBI-SB 14, SB 2-SB 13, SBI 5, SB 14, SB 2-SB 10, SB 16-SB 17 SBI SDN= O SML 1 = 0 SLINE ( 0) = SMLI ( 0) SLN = 3 DIFST= 1 SB 2 call DECODE I MODULE CRI=D Ol= 14 EO Fl= O SB 3 EOFI = SB 4 SB 4 TI( 2) = SMHW ( 16)-CR( 14) SB 5 call DECODE I MODULE D Ol = 12 EOFI = O SB 6 EOF 1 = O ‘ SB 7 SB 7 T O ( 2) = C Rl( 14)-DO 1 ( 12) assume beginning line # and length are SEED and initialize modules; difference between iso-entropicgram width and largest occurrence value difference between the two largest occurrence values; SB 8 Tl( 2) = MAX(TI( 2), TO)) SB 9 SDN( 2) = SDN( 0) + T 1 ( 2) SMLI( 2) = SMLI( 0) + Tl( 2) SBIO 10 SDN( 2) < SMHW( 16) goto SB 1 l SB 11 DELI( 2)-TI( 2) SB 12 The REVOLVE MODULE is called and creates line No2 of the iso-entropicgram SB 13 SLN( 3) = MLN 3 ( 3) ' goto SB 14 go to SB 2 DIFST= 1 SB 2 call DECODE I MODULE CR 1 = DO 1 = 11 EOFI = O SB 3 EOFI = O go to SB 4 SB 4 Tl( 5) = SMHW( 16)-CRI( 1 1) SB 5 call DECODE I MODULE DOI = 10 EOF 1 = O the maximum of these differences; how far revolved; line position in the iso-entropicgram largest to DELTA MODULE input; the possible shortest seed line is not less than 2; therefore iso-entropicgram line 2 is not considered as a seed line; reset the DECODE I and II MODULES read the largest occurrence; difference between iso-entropicgram width and largest occurrence; SB 6 EO Fl = O goto SB 7 SB 7 T O (I), CRI( 11)-DOI( 10) difference between the two largest occurrences; 1,570,344 SB 8 Ti( 5) = MAX(Tl( 5), T O ( 1)) number of lines to be revolved; SB 9 SDN( 7) = SDN( 2) + Ti( 5) number of lines revolved; SMLI( 7) = SMLI( 2) + Ti( 5) position of the seed line after the revolve; SB 10 SDN( 7) < SMHW( 16) - go to SB 11 SBI 1 DELI( 5) = Ti( 5) number of lines to be revolved to the 5 DELTA MODULE SB 12 line 2 is now revolved down 5 lines to line 7 by the REVOLVE MODULE the format and length of this line were given in the input discussion SB 13 SLN( 3) > MLN 3 ( 2) – SB 15 SB 15 SLN( 2) = MLN 3 ( 2) save new iso-entropicgram line as possible 10 SLINE( 7) = SMLI( 7) shortest seed line; SB 14 DIFST = I reinitialize DECODE I and II MODULES inhibit the overwriting of the seed line go to SB 2 in the MEMORY MODULE area; SB 2 call DECODE I MODULE 1 s CRI =DOI = 7 EOFI = O IX SEED FINDER Briefly, an electronic data processing SEED FINDER or data compactor has been disclosed The compactor is for a coded occurrence signal, such as an event occurrence signal, which represents actual occurrence values out of a group of 20 possible occurrence values The possible and actual values are arranged in a monotonical, preferably decreasing, value order Memory means such as the MEMORY MODULE stores such a coded occurrence signal Means such as the DECODE I and DECODE II MODULES form a first signal representing the stored coded occurrence signal Means such as the seed finder of Fig 26 responds 25 to the first signal for selectively forming, for each different first signal, any one of a set of equivalent signals, the set including such first signal Each equivalent signal is related to another one by an exclusive OR of the values thereof and the values thereof relatively shifted The means for forming equivalent signals further includes means for enabling one or more of the equivalent signals to be sequentially formed 30 In this connection the SEED MODULE, including its control counter, enables a coded occurrence signal such as an event occurrence signal to be revolved through its iso-entropicgram.
Means such as the SLN register of the SEED MODULE and the MLN 3 register of the ENCODE MODULE store and form a signal indicative of the length 35 of the occurrence signal and the equivalent signals Means is provided for forming a signal identifying the equivalent signal which is associated with the shortest length signal In this connection the SEED MODULE is operative during SB 13 of its flow for comparing the length of the value stored in the MLN 3 and SLN registers to determine which is the smallest The signal in register SLN indicates the length of 40 the shortest seed to that point and the content of register MLN 3 indicates the length of the line value being stored in the MEMORY MODULE from the ENCODE MODULE.
The purpose of the seed finder is to locate the seed of an event occurrence vector Stating it differently, an event occcurrence vector signal is to be revolved 45 through its corresponding iso-entropicgram until an equivalent signal is found that is shortest in length The iso-entropicgram has a set of unique but equivalent signal sets which include the input or event occurrence vector Each signal set is related to another one in the set by an XOR of the value thereof and the value thereof so relatively shifted by one possible occurrence value In a preferred embodiment of 50 the invention the shortest length is that which is shortest when stored in hybrid coded form in the MEMORY MODULE.
Fig 23 is a block diagram showing the internal control/data flow for the seed finder The ENCODE, DECODE I and II, REVOLVE, DELTA, and SEED MODULES shown in Fig 23 in conjunction with the MEMORY MODULE and 55 the SWITCH MATRIX (not shown) are a part of the DPM system depicted in Fig.
1 and function together as a data compactor.
What has been disclosed is a data processing method for compacting a line signal which represents actual occurrence values out of a group of possible occurrence values, the possible and actual occurrence values being arranged in 60 monotonical value order An example of the line signal in the disclosed embodiment of the invention is an event occurrence vector which is stored in memory in hybrid coded form (see Table 9) However, it will be understood the line 1,570,344 signal might be in other codes within the concepts of the invention under consideration.
The steps are as follows Such a line signal is stored in a memory, such as the MEMORY MODULE, as the possible shortest line signal In this connection, the SEED MODULE applies a signal to the MEMORY MODULE which stores an 5 event occurrence vector (whose seed is to be found) and the SEED MODULE applies a signal the the SWITCH MATRIX causing the appropriate switches to be set identifying area 1 as the one containing the current shortest line signal (i e, the seed).
The SEED MODULE responds to the values of the possible shortest line 10 signal for forming at least one signal representative of a total number of lines to be revolved Such an operation takes place during SB 8 when the largest of the two different signals contained in registers TI and TO is transferred to register Tl In this connection, register TO contains the difference between the values represented by the last two occurrence values at one end (i e, the largest end) of the shortest 15 line signal and register Tl contains the difference between the values represented by the maximum length (is Q-entropicgram width) signal stored in register SMHW and the occurrence value at one end (i e, largest occurrence value) of the possible shortest line signal.
The steps include the step of responding to the total number of lines to be 20 revolved signal for forming one or more incremental revolve signals representative of the incremental number of lines by which a revolve is to be effected In this connection, the DELTA MODULE breaks the total number of lines to be revolved into its component powers of 2 thereby specifying the actual increments by which the revolve is to be effected 25 Continuing with the method is the step of revolving the input line, which involves the step of forming a resultant incremental line signal representing the value of the possible shortest line signal exclusive OR’d with the value of the possible shortest line signal shifted by the number of occurrence values specified by one of the incremental revolve signals This step is accomplished by the REVOLVE 30 MODULE during the revolve portion of the operation disclosed in connection with SB 12 of the SEED MODULE flow The step of revolving further includes the step of enabling the resultant incremental line signal to be used in the preceding step for exclusive O Ring, using another one of the incremental revolve signals In this connection, after each exclusive OR, the result is stored into the MEMORY 35 MODULE and the DELTA MODULE provides the next component power of 2 signal which is then used for exclusive O Ring the result formed by the REVOLVE MODULE This operation is repeated until all of theincremental powers of 2 have been used in the revolve process by the REVOLVE MODULE Further included in the step of revolving is the step of storing the final incremental line signal, after all 40 of the incremental revolve signals have been used In this connection, the final line signal stored in the MEMORY MODULE during the revolve process is identified by the OAR and the SWITCH MATRIX The length of the stored possible shortest line signal (contained in register SLN) and the length of the new incremental line signal contained inregister MLN 3 of the ENCODE MODULE are compared and 45 the ALU of the SEED MODULE forms a signal indicating the shortest one during SB 13 of the SEED MODULE flow Subsequently, the preceding steps are repeated utilizing the line signal which is indicated to be the shortest one In this connection note that following SB 13, SB 14 and SB 15 may then be entered following which SB 2 is reentered where the repeat operation takes place 50 Preferably, the steps also include that of combining values represented by a series of the total number of lines to be revolved signal to thereby form a further signal representing a line number value for the stored possible shortest line signal.
This is accomplished using the ALU and registers SMLI and Tl of the SEED MODULE during SB 9 55 Preferably, the step of forming a resultant incremental-line signal involves the step of combining the values represented by the possible shortest line signal in one of the incremental revolve signals to form a corresponding shifted signal In this connection, the absolute occurrence values provided by the DECODE II MODULE are combined with the incremental power of 2 values from the DELTA 60 MODULE to form a shifted value by the REVOLVE MODULE The step of forming a resultant incremental line signal further comprises the step of exclusively O Ring the values represented by the shifted and unshifted possible shortest line signals to form the resultant incremental line signal.
In terms of apparatus, there has also been disclosed a data compactor for an 65 1,570,344 input line signal (i e, event occurrence vector) which represents actual occurrence values out of a group of possible occurrence values The possible and actual occurrence values are arranged in an incremental, preferably decreasing, value order Included is memory means such as the MEMORY MODULE for storing the input line signal Decoding means such as the DECODE I and II MODULES 5 convert a line signal stored in the memory means including the stored input line signal from a first compact code (i e, hybrid code) to a second expanded code (i e, absolute code) Means including the SEED and DELTA MODULES are responsive to a converted line signal from the decoding means for forming one of a selected number of value signals The number of value signals correspond to such 10 signals as the component power of 2 signals provided from DELO in the DELTA MODULE Means such as the REVOLVER is responsive to one of the number value signals and the corresponding converted line signal from the decoding means for further converting the converted line signal, as a function of the number value signal, to a modified but equivalent line signal This process is effected in the 15 REVOLVER through the exclusive O Ring process Encoding means, such as the ENCODE MODULE, converts the equivalent line signal from the second to the first code for storage in the memory means Included is means such as the OAR, the ALU and SLN and MLN 3 (ENCODE MODULE) for selecting one of the equivalent sets of signals During SB 13 the shortest one, in hybrid code, is selected 20 The ALU of the SEED MODULE in combination with the MLN 3 register of the ENCODE MODULE and the SLN register of the SEED MODULE are operative during SB 13 for forming a signal indicating the shorter of the original stored line signal and the equivalent line signal The control counter of the SEED MODULE is operative following SB 14 to enable the foregoing means such as the DECODE I 25 and II, SEED, DELTA, and ENCODE MODULES and the REVOLVER to repeat their operation However, means is responsive to the shortest indication signal for enabling the decoding means to decode the shorter one of the stored original line signal and the equivalent line signal during the repeat In this connection, either SB 314 is entered directly or SB 15 is entered followed by SB 14 depending on the 30 result of the comparison by the ALU during SB 13 During SB 15 the memory area number in the OAR register is changed if necessary to identify the MEMORY MODULE area containing the possible shortest seed line before entering SB 14 where the DECODE I and II MODULES are called to decode the possible shortest line signal It will also be noted in connection with the SWITCH MATRIX that the 35 flip flops of the SWITCH MATRIX are appropriately set to identify the MEMORY MQDULE area containing the possible shortest seed line.
Preferably, the decoding means involves a first decoding means and a second decoding means (such as DECODE I and II MODULES) to enable the actual occurrence values of a line signal to be provided to the REVOLVER at different 40 rates upon demand It will be noted that the repeat operation enabled by the control counter of the SEED MODULE going from SB 14 back to SB 2, et seq, will be repeated until the original input line has been revolved completely through its iso-entropicgram, thereby insuring that the shortest equivalent new line signal (seed) has been formed Means is provided for disabling the repeat enabling means 45 after the shortest of the equivalent new line signals has been formed To this end, the value of the current number of lines revolved relative to the input line is stored in register SDN and is compared with the iso-entropicgram width value contained in register SMHW by the ALU of the SEED MODULE, during SB 10 If the current number of lines revolved relative to the input line contained in register SDN is the 50 greater, then SB 16 et seq is entered where the operation of the SEED MODULE is subsequently exited.
It will also be noted that the DECODE I and II and MEMORY MODULES form a means for storing and retrieving the input line signal which is to be compacted 55 It should also be noted that means is provided for combining the value of the successive number of lines to be revolved signal in such a way as to form a line number for the shortest line This function is provided by means such as the ALU, the SM Ll, TI, and SMHW registers and the ALU during SB 7 and SB 17 of the SEED MODULE flow 60 X CHANGE MODULE A General Description
Section I GENERAL DESCRIPTION describes a method whereby changes may be made in an occurrence vector These changes include insertions, deletions 1,570,344 RI and the addition of new information A deletion removes an occurrence value from an event occurrence vector An insertion adds an occurrence value to an event occurrence vector An addition of new information may be the addition of new occurrence values to an existing event occurrence vector or the addition of new event occurrence vectors 5 According to a preferred embodiment of the invention changes may be made to an event occurrence vector at any line number of its iso-entropicgram.
Preferably, the change is applied to the seed line and the resultant changed line is then revolved until the new seed is found.
Describing the change operation in more detail, a seed which is to be changed 10 is defined in terms of a line number, a line value, and a length of line value The change vector is composed at the input line for its iso-entropicgram (line 0 and includes an occurrence value for each insertion, for each deletion, and for each new addition that is to be made in the seed.
Generally, the method followed is as follows: 15 (I) revolve the change vector in its iso-entropicgram down to the line number corresponding to that of the seed which is to be changed This will provide a revolved change vector having a line number the same as that of the seed, a change value and a length the same as that of the seed; ( 2) merge the occurrence values of the line values in the seed and change vector by 20 exclusive O Ring the two together.
More specifically, the operation involved is as follows The line value of the change vector, in hybrid code, is placed in MEMORY MODULE area 1 The line value of the seed is placed in MEMORY MODULE area 2 The change vector is revolved down to the same line of the iso-entropicgram as that of the seed At this 25 point, the change vector is defined in terms of the line number of the seed, the line value for the change vector and the length of seed The merge operation involves XO Ring the line value of the seed and the line value of the change vector resulting in a changed line value The changed seed is then defined in terms of the line number for the original seed, a changed line value and the length of the seed The 30 changed seed is then revolved down to its seed.
Fig 24 is a schematic and block diagram of the CHANGE MODULE which enables the above operation Fig 26 is the internal control/data flow for the seed line changer, which is a portion of the overall DPM system It will be seen from this figure that the CHANGE MODULE makes use of the ENCODE, DECODE I, 35 DECODE II, DELTA, REVOLVE, and SEED MODULES as well as the MEMORY MODULE, the SWITCH MATRIX and IPRF in its operation.
B Components The CHANGE MODULE, Fig 24 has two 8 bit 8 flip flop registers CLINE and CLN Both of these registers are of type SN 74100 disclosed in the above TTL 40 book, having the same characteristics as those described above.
In addition, the CHANGE MODULE has a control counter 613 with flip flops Pl-P 4 Flip flops Pl-P 4 are the same type disclosed in Section I GENERAL DESCRIPTION, F Components.
The CHANGE MODULE has a generalized clock control circuit 700 The 45 generalized clock control circuit 700 is described in more detail in the subsequent section entitled “Generalized Clock Control Circuit”.
The CHANGE MODULE also has clock suspension logic 622 connected to the CS input of the clock control circuit 700.
As described with respect to the ENCODE MODULE, logical equations are 50 used to indicate gating required to control various circuits and to generate various signals, all indicated in the CHANGE MODULE.
Depicted along the right hand side of the CHANGE MODULE Fig 24 are input and output control lines and information inputs and outputs The information inputs and outputs are depicted by heavy lines 55 C Detailed Description
Reference should be made in the following discussion to the CHANGE MODULE schematic of Fig 24 and the CHANGE MODULE flow diagram of Fig.
The following discussion will describe the CHANGE MODULE using an example of a specific seed line and change line in order to provide a better 60 understanding of the system The specific example is that given hereinabove in I.
GENERAL DESCRIPTION with respect to Tables 9-A and 9-B.
As noted, the CHANGE MODULE when combined with the ENCODE, 1,570,344 DECODE I, DECODE II, DELTA, SEED and MEMORY MODULES, the SWITCH MATRIX and IPRF, forms a seed line changer The seed line changer sub-system of the DPM is depicted in the general block diagram of Fig 26 (the MEMORY MODULE, SWITCH MATRIX and IPRF are not shown).
Initially, the MINI COMPUTER forms a true signal at the output MINIT, 5 thereby applying a true signal to the IP input of the clock control 700 The true signal at the input IP causes a true signal at the MR output which resets flip flops Pl-P 4 of the control counter 613 to 0 without a clock pulse The MEMORY MODULE areas 1 and 2 and LINE # and LNI and LN 2 of the IPRF initially are loaded by the MINI COMPUTER with the inputs illustrated in Table 11 Thus, the 10 values for the examples of Tables 9-A and 9-B which are now stored are as follows:
MEMORY MODULE area I 1 3689 11 12 MEMORY MODULE area 2 06 12 LINE# 6 15 LN 2 8 LNI 7 The MINI COMPUTER then forms a true signal at the CNGO output causing the clock control 700 to start forming its clock puses at the CLK and CLK output.
At the first true pulse at the CLK output, the logic Pl P 2 P 3 P 4 is true and 20 the flip flop Pl is set to a 1 state, thereby forming a true signal at the Pl output The true signal at the Pl output causes the CLINE register to couple the line number of the seed from LINE # of the IPRF to the output of the CLINE register.
The true signal at the Pl output also causes a true signal at the CM 4 output of the CHANGE MODULE which in turn goes to the DECODE I, DECODE II, 25 SEED and DELTA MODULES, and the SWITCH MATRIX The true signal at CM 4 causes the CNG flip flop in the SEED MODULE to be set to a I state where gates 218 and 226 couple thelength of line value for the change vector from LNI of IPRF to the registers MLNI and MLN 2 in the DECODE I and DECODE II MODULES; causes the selection circuit DELS to couple the line number of the 30 seed from the output of the CLINE register of the CHANGE MODULE to the input of register 302 in DELI of the DELTA MODULE; and causes flip flops 531 and 523 in the SWITCH MATRIX to be set to 1 states The 1 states of flip flops 531 and 523 cause the DECODE I and DECODE II MODULES to read from MEMORY MODULE area 1 and the ENCODE MODULE to write into 35 MEMORY MODULE area 3 To be explained, when the true signal at Pl terminates, the CLINE register stores the line number from LINE # of the IPRF.
* Subsequently, a true signal is formed at the CLK output of the clock control 602, thereby causing the logic Pl CLK to be true, thereby forming true signals at the CM 3, CM 5 and CM 6 outputs The true signal at the CM 3 output causes the 40 length of line value from LNI of IPRF to be stored into the MLN 1 and MLN 2 registers of the DECODE I and II MODULES; causes the length of seed line from LN 2 of IPRF to be stored into the CLN register in the CHANGE MODULE; and causes the line number from the output of the CLINE register of the CHANGE MODULE to be stored into the register 302 of DELI in the DELTA MODULE; 45 and causes the one-shot REVGO in the REVOLVE MODULE to be set, thereby calling the operation of the REVOLVE MODULE __ In addition, a true signal is now formed by the logic Pl REVEND CLK in the clock suspension logic 622, thereby causing a true signal at the CS input of the so clock control 700 The true signal at input CS causes the clock control 700 to 50 suspend the clock pulses at CLK and CLK, thereby suspending operation in the CHANGE MODULE until the operation of the REVOLVE MODULE is complete and removes the true signal at REVEND so indicating.
Using the example shown in Tables 9-A, 9-B, the following conditions now exist: 55 ( 1) register MLNI (DECODE I) contains the length of the line value for the change vector (MLN = 7); ( 2) register MLN 2 (DECODE II) contains the length of the line value for the change vector (MLN 2 = 7); ( 3) register DELI (DELTA) contains the line number of the seed line value (DELI 60 = 6); ( 4) CNG flip flop (SEED) is in a 1 state; ( 5) flip flops 531 and 523 (SWITCH MATRIX) are in a I state; 1,570,344 ( 6) MEMORY MODULE area 1 contains the change line value signals (MEMORY MODULE area 1 = 1, 3, 6, 8, 9, 11, 12); ( 7) MEMORY MODULE area 2 contains the seed line value signal (MEMORY MODULE area 2 = 0, 6, 12); ( 8) register CLINE (CHANGE) contains the line number of the seed line value 5 (CLINE = 6); ( 9) register CLN (CHANGE) contains the length of the line value of the seed (CLN = 2); ( 10) REVOLVE MODULE has been called.
Following its call, the REVOLVE MODULE forms a true signal at the RM 8 10 output, thereby indicating that the SWITCH MATRIX has been clocked Since flip flops 531 and 523 of the SWITCH MATRIX had been set previously, this results in the setting S 11, 521 and 533 of the SWITCH MATRIX Thus, the DECODE I and II MODULES will read from MEMORY MODULE area 1 and the ENCODE MODULE will write to MEMORY MODULE area 3 The true 15 signal at the RM 8 output of the REVOLVE MODULE sets the flip flops Sl l, 512 and 533 in the SWITCH MATRIX to a 1 state Additionally, the input SM 5 to the REVOLVE MODULE is false, indicating that the current line value in MEMORY MODULE area I is not to be kept as a possible seed The signal at RM 12 output of the REVOLVE MODULE causes the SP flip flop in the SWITCH MATRIX to be 20 reset to 0 Therefore, the first pass of the REVOLVE MODULE causes the change vector to be revolved down four lines to line 4 of its iso-entropicgram and the revolved line value of the change vector is now stored in MEMORY MODULE area 3 as specified by the I state of flip flop 533 Thus, the revolved line value stored in MEMORY MODULE area 3 now contains the absolute values 1, 2, 5, 7, 25 9, 11, 12, 15 and the line value 4 is stored.
At this point, the register MLN 3 of the ENCODE MODULE contains the length value for the revolved change line value now stored in MEMORY MODULE area 3 (i e, a length of 8) The REVOLVE MODULE then forms true signals at the RM 14 and RM 10 outputs, thereby causing the length value contained 30 in MLN 3 of the ENCODE MODULE to be enabled to the input of the registers MLNI and MLN 2 of the DECODE I and II MODULES and stored.
The REVOLVE MODULE then embarks on a second pass through its flow At this point in time, flip flops 533 and 521 in the SWITCH MATRIX are in a I state; therefore, when the REVOLVE MODULE forms a true signal at its RM 8 output it 35 causes the flip flops 513, 523 and 531 in the SWITCH MATRIX to be set to a 1 state The 1 states of these flip flops cause the DECODE I and II MODULES to both read the revolved change line value contained at MEMORY MODULE area 3 and cause the ENCODE MODULE to write the resultant revolved line value into MEMORY MODULE area 1 40 It should be carefully noted at this juncture that although reading and writing is taking place in MEMORY MODULE areas 3 and 1, MEMORY MODULE area 2 contains the original seed value and it remains there unaltered at this point.
A true signal is subsequently formed at the RM 12 output of the REVOLVE MODULE which causes the SP flip flop in the SWITCH MATRIX to be reset to 45 an 0 state The REVOLVE MODULE then revolves the revolved change line value (i.e, 1, 2, 5, 7, 9, 11, 12, 15) down two lines from iso-entropicgram line 4 to 6, and the ENCODE MODULE writes the new revolved change line value in MEMORY MODULE area 1 Thus at this point in time (conclusion of this second pass of the
REVOLVE MODULE), MEMORY MODULE area 1 contains the revolved 50change line value 1, 6, 12 (see h of Table 9 A) Additionally, the length value of the new revolved change line value is contained in register MLN 3 of the ENCODE MODULE Subsequently, the REVOLVE MODULE forms a true signal at the RM 14 and RM 10 outputs, causing the value to be stored from register MLN 3 into register MLNI and MLN 2 of the DECODE I and II MODULES 55 The DELTA MODULE has now provided all of the component powers of 2 of the total number of lines to be revolved for the change line and therefore the REVOLVE MODULE terminates its operation and forms a false signal at its REVEND output This causes logic Pl REVEND in clock suspension logic 622 to become false which causes the clock control 700 to again form pulses at CLK and 60 CLK.
The next true signal at the CLK output resets the P 9 flip flop to a 0 state and sets the P 2 flip flop to a 1 state in the control counter 613, thereby forming a true signal at the P 2 output.
The true signal at output P 2 causes a true signal at the CM 2 output of the 65 1,570,344 CHANGE MODULE which causes the length ( 2) of the seed line value in the CLN to be coupled to the input of MLN 2 of the DECODE II MODULE.
The true signal at P 2 also causes a true signal at the CM 1 output to the SWITCH MATRIX thereby inhibiting any input to the 521, 522 or 523 flip flops.
When the pulse is formed at the CEK output, the logic P 2 CL:becomes true, 5 which in turn causes a true signal at the CM 6 and e M 8 outputs of the CHANGE MODULE.
The true signal at the CM 8 output causes the MLN 2 register in the DECODE II MODULE to be loaded with the content of the CLN register Thus the length 2 of the seed line value (in MEMORY MODULE area 2) is stored in the MLN 2 10 register of the DECODE II MODULE.
The true signal at CM 6 causes the clock control 700 to suspend the clock in the CHANGE MODULE It also causes the REVGO mono-stable to be fired in the REVOLVE MODULE thereby initiating the revolve process.
Note that nothing was loaded into DELI of the DELTA MODULE This will 15 cause the REVOLVE MODULE to merge or XOR the seed line value and the change line value.
The REVOLVE MODULE forms a true signal at the RM 8 output causing Sl I and 533 flip flops in the SWITCH MATRIX to be set to 1 Also the RM 12 CMI logic becomes true, causing the 522 flip flop in the SWITCH MATRIX to be set 20 This indicates that the DECODE I MODULE will be reading from MEMORY MODULE area 1, the DECODE II MODULE will be reading from MEMORY MODULE area 2, and the ENCODE MODULE will be writing to MEMORY MODULE area 3.
Upon completion of the merge operation, the REVOLVE MODULE forms a 25 false signal at the REVEND output which causes the logic P 2 REVEND CLK to go false which in turn, causes the clock control 700 to again form pulses at the CLK and CLK outputs.
The next true signal at the CLK output resets the P 2 flip flop to a 0 state and sets the P 3 flip flop to a 1 state in the control counter 613, thereby forming a true 30 signal at the P 3 output.
When the pulse is formed at the CLK output, the logic P 3 CLK becomes true, which in turn forms a true signal at the CM 2 output of the CHANGE MODULE.
The true signal at the CM 2 output sets the SMGO one-shot in the SEED MODULE to a 1 state, thereby calling the operation of the SEED MODULE The 35 SEED MODULE then commences its operation of locating the seed in the manner described hereinabove with respect to the SEED MODULE.
To this end, the SEED MODULE causes the new seed line value contained in MEMORY MODULE area 3 to be revolved through its iso-entropicgram and locate the seed which, in the case of the disclosed embodiment, is the line from the 40 ENCODE MODULE which has the fewest number of words The SEED MODULE causes the line value of the seed value to be saved in the MEMORY MODULE in the area specified by OAR of the SEED MODULE At the time the true signal is formed at the CM 2 output, the logic P 3 SME Nb CLK becomes true, thereby forming a true signal at the CS input to the clock control 700 which 45 again causes the clock control 700 to terminate its pulses at the CLK and CLK outputs and suspend the operation of the CHANGE MODULE.
When the SEED MODULE has completed its seed finding operation, its register OAR identifies the MEMORY MODULE area containing the line value of the new seed; its register SLN contains the length of such line value; its register 50.
SLINE contains the line number value of such line value, and its register ONOC contains the number of occurrences in such line value When the SEED MODULE completes its operation, a true signal is formed at the SMEND output from the SEED MODULE, which in turn causes a false signal at the SMEND output This causes logic P 3 SMEND CLK to go false and causes the clock control 700 to 55 start forming its pulses at CLK and CLK.
The following pulse at CLK resets the P 3 flip flop to a 0 state and sets the P 4 flip flop to a 1 state in control counter 613.
The true signal at the P 4 output causes a true signal at the MT input of the clock control 700 which, as discussed above, sets a one-shot in the generalized 60 clock control 700 which in turn causes true signals to be formed at the MR and FC outputs The true signals at the MR output of the clock control 700 cause all of the flip flops including T 4 of control counter 613 to be reset to 0 The true signal at output FC causes the CNGEND output of the CHANGE MODULE to turn true 1,570,344 81.70 4 8 and signals the calling module that the operation of the CHANGE MODULE is complete.
D Example of Operation An example of the operation of the CHANGE MODULE in the seed line changer will now be given in symbolic notation using the example depicted in Tables 9 A and 9 B The corresponding blocks in the flow diagram are shown along the left hand side.
The following is expected as input:
CLINE = 6 HW,= 8 LNI = 7 LN 2 DELI = 6 Change line value Seed line value Sequence of control is CBR-CB 5; CB 1 initialize CLINE = LINE #= 6 CLN = LN 2 CB 2 DELI( 6) = CLINE( 6) call REVOLVE MODULE CB 3 MLN 2 -CLN reset DECODE II MODULE CB 4 call REVOLVE MODULE CB 5 SMLI = CLINE CNG= 1 call SEED MODULE Line number of the seed line value; Iso-entropicgram width; Length of line value for the change vector; Length of the line value for the seed; Line number of the line value for the seed; In MEMORY MODULE area 1; 1, 3, 6, 8, 9, 11, 12 where 6, 12 are deletions; the remainder insertions; In MEMORY MODULE area 2; 0, 6, 12; clock proper information into the proper registers; seed line number; length of seed line value number of lines to revolve to DELTA MODULE; revolve the change vector down to same line number as the seed line; load the length register with the length of the line value of the seed; set DECODE II MODULE to read from MEMORY MODULE area 2; the change line value and the seed line value are XOR’d with the results as shown in h of Table 9-A; line number value clocked to SMLI of the SEED MODULE, CNG flip flop set the new seed is located; HALT output taken from the SEED MODULE SLINE = 5 (seed line number) OAR = MEMORY MODULE area which contains the seed SLN = I (seed line value length) ONOC = 1 (number of occurrences in seed line value) XI SEED LINE CHANGER From the foregoing description of the CHANGE MODULE it will be understood that the ENCODE, DECODE I and II, REVOLVE, DELTA and SEED MODULES depicted in Fig 26 in association with the MEMORY MODULE and the SWITCH MATRIX (not shown) form a Seed Line Changer which allows a seed to be changed without revolving it back to the zero or input line of the corresponding iso-entropicgram The seed line changer forms an electronic data processing system for changing an occurrence value signal, such as a seed, utilizing a change value signal such as a change vector The aforementioned occurrence and change value signals each represent an actual occurrence value out of a group of possible occurrence values, the possible and actual occurrence values being arranged in monotonical, preferably decreasing value order, as depicted in Tables I and 2 Means such as the MEMORY MODULE area 1 is provided for storing the occurrence value signal which is to be changed Means such as the is 1,570,344 CLINE register of the CHANGE MODULE is provided for storing a line number signal in association with the stored occurrence value signal The line number signal stored in register CLINE specifies the number of the line of the line value of the seed Means such as the MEMORY MODULE area 2 stores the change occurrence signal (i e, the change vector) which specifies the changes in the values of the stored occurrence value signal Means such as the REVOLVER depicted in Fig 19 forms a means for responding to the change occurrence value signal for selectively forming, for each different change value signal, any one of a set of equivalent signals, the set including such occurrence value signal Each equivalent signal within each set is unique and is related to another one by an exclusive OR of 10 the values thereof and the values thereof relatively shifted Included in the foregoing means is means for forming any one of the equivalent signals in a set as specified by a received number of lines signal Means such as the SEED and DELTA MODULES respond to the stored line number signal for applying a number of lines signal to the equivalent signal forming means It will be recalled in 15 connection with the DELTA MODULE that the DELTA MODULE forms a number of lines signal in the form of component powers of 2 of the total number of lines to be revolved.
Further included is means such as the REVOLVER for exclusive O Ring the values represented by an equivalent signal and the occurrence value signal to 20 thereby form the changed occurrence value signal.
XII GENERALIZED CLOCK CONTROL Individual clock control circuits have been disclosed for the previously described ENCODE, DECODE I, DECODE II, REVOLVE, DELTA and SEED MODULES However, it should be noted that a generalized clock control circuit 25 may be employed Therefore, with respect to the CHANGE MODULE just described and other modules subsequently to be disclosed in connection with the DPM SYSTEM, a generalized clock control 700 shown in Fig 27 will be used.
Specifically, the generalized clock control circuit 700 includes one-shot multivibrators 702 and 704, a flip flop 708, OR gates 712 and 714, an AND gate 718 and 30 logical signal inverters 720 and 722, all of the same types disclosed for the ENCODE MODULE A source of regular recurring clock pulses 701 provides clock pulses to one input of the AND gate 718 The clock control 700 has input circuits IN, CS, IP and MT and has outputs MR, CLK, CLK’and FC Modules subsequently to be disclosed only disclose the clock control 700 in block form with 35 the prior mentioned input and output circuits.
The one-shots 702 and 701 are of the same type disclosed for the ENCODE MODULE and, responsive to a true signal at the input at the left side, are triggered to a 1 state where a true signal is formed at the output indicated on the right hand side The one-shot remains in a 1 state for a time interval equal to that between the beginning of two successive clock pulses from the source of clock signals 701 and then automatically resets to a 0 state where a false signal is formed at the corresponding output.
The flip flop 708 is a conventional flip flop of the same type disclosed hereinabove with respect to the ENCODE MODULE The one-shot 702 has its 45 input connected to the IN input and the IN input is the one which receives a true signal whenever the corresponding module is called A true signal at the IN input triggers the one-shot to its 1 state, causing its output to go from a false to a true signal The OR gate 712 also has inputs connected to the output of oneshot 704 and to the IP input The IP input is the one which receives a true signal whenever it 50 is desired to reset the control counter in the corresponding module Additionally, the one-shot 704 has its input connected to the MT input of the clock control 700.
The MT input receives true signals whenever the corresponding module has completed its function Thus, a true signal at the MT input causes the oneshot 704 to be set to a 1 state which, in turn, applies a true signal at the FC output, thereby 55 indicating that the function of the corresponding module is complete The true signal at FC is also applied to the OR gate 712 Whenever any of the inputs to the OR gate 712 receives a true signal, a true signal is formed at the MR output The MR output is connected to the control counter in the corresponding module and resets each of it flip flops to a 0 state when a true signal is applied 60 The AND gate 718 is connected to the CLK output and is connected through the logical signal inverter 722 to the CLK output of the clock control 700 The gate 718 is an AND gate which has one input connected through the logical signal inverter 720 to the CS input, a second input to the unbored output of the flip flop 1,570,344 708, and a third input connected to the clock 701 The CS input is the one which receives true signals from the clock suspension logic of the corresponding module.
The flip flop 708 is set to a 1 state which, in turn, applies a true signal to the gate 718 whenever a true signal is formed either at the control counter reset circuit IP or the end of function input MT As a result, the AND gate 718 causes true clock pulses to 5 be formed at the CLK and CLK outputs whenever the CS input is false (due to a false condition for the corresponding clock suspension logic) and the flip-flop 708 has been set to a 1 state and a pulse occurs from the clock 701 The logical signal inverter 722 inverts the clock signals at CLK, forming the complement thereof at the CLK output 10 XIII OUTPUT MODULE A General Description
The OUTPUT MODULE operates in conjunction with other portions of the DPM SYSTEM generally depicted in Fig 34 for performing two functions The first is to cause a simple retrieval or decompaction type of operation wherein an is event occurrence vector which is represented by one of the non-input lines (usually the seed) is revolved back to the input line of its iso-entropicgram The second is called the DEL function and causes a check to determine if an event occurrence vector which is represented by a non-input line (usually a seed) contains particular actual occurrence values back at the input line of its iso-entropicgram 20 Significantly, the second function is done without revolving the noninput line clear back to the input line of its iso-entropicgram.
Briefly, the operation of the OUTPUT MODULE in carrying out the retrieval or decompaction function is as follows: an event occurrence vector, at one of the non-input lines of its iso-entropicgram (usually the seed), is represented by a line 25 value signal and a line number signal The OUTPUT MODULE determines the difference between the value of the line number signal and the width of the isoentropicgram The difference thus identifies the number of lines required to revolve the line value signal back to the input line of its isoentropicgram The difference is then provided to the DELTA MODULE which forms signals 30 representing its component powers of 2 beginning with the largest (as discussed above) The REVOLVE MODULE then causes the line value signal to be revolved in its iso-entropicgram by the specified number of lines back to the input line of the iso-entropicgram.
Consider now the operation for the DEL function A reference line (in hybrid 35 coded form) is stored in the MEMORY MODULE and represents one or more test values Each test value identifies an actual occurrence value whose presence is to be checked in a line of an iso-entropicgram However, the given line to which the test is to be applied is one of the non-input lines of its isoentropicgram (usually the seed) Also the presence of an occurrence value is desired at the input line, not at 40 the non-input line The DEL function allows the presence of an occurrence value, at the input line, to be determined without revolving a given line (usually the seed) clear back from its non-input line to its input line.
The given line (usually a seed) is represented at its non-input line by a line value signal and a line number signal The OUTPUT MODULE utilizes the same 45 hardware and method described for the regular output and finds the difference between the values of the line number signal and the width of the isoentropicgram.
The DELTA MODULE then determines the integral powers of 2 of the difference beginning with the largest The largest integral power of 2 is saved and the line so value signal is revolved by the number of lines specified by the remaining integral 50 power (or powers) of 2 to form a revolved line value signal to determine if the occurrence value identified by the test signal is present The revolved signal is examined and information as to the presence of an occurrence value, equal to the line value, is exclusive OR’d with information as to the presence of an occurrence value which is displaced from the one under test by the value of the saved signal If 55 either occurrence value exists in the revolved signal then the actual occurrence value under test exists at the input line The checking and exclusive OR is performed by forming an absoluve coded value representing each actual occurrence value of the revolved line value signal, from largest to smallest, until one is found that is equal to or less than the value of the test occurrence value If 60 equality exists, a signal is stored in a flip flop representing a 1 Otherwise a 0 is stored The test occurrence value is then decreased by the largest component power of 2 signal which has been saved The absolute coded values representing the actual occurrence values of the revolved line are then continued to be formed 1,570,344 beginning with the next one in order until one is found whose value is equal to or less than the decreased test occurrence value If equality exists the 1 or 0 signal previously stored in a flip flop is complemented Otherwise the previously stored 1 or 0 signal is left unaltered If the result of the last complement is a 1, the actual occurrence value under test exists at this input line’ If the result is a 0, the actual 5 occurrence value under test does not exist in the input line.
B Components Figs 28-31 show a schematic and block diagram of the OUTPUT MODULE.
Included are registers OHW, ORI, ORTI, OLINE, OR 2, ORSN, ORT 2, ORT 3, OLN and OAR, all 8 bit or 8 flip flop registers of type SN 74100 described 10 hereinabove with respect to the ENCODE MODULE The only exception as to size is register OAR which contains 2 bits or flip flops of storage.
Also included are selection circuits D 53, D 56 and D 57 These are conventional selection circuits of the type and operating in the manner discussed hereinabove in section I F CONVENTIONS AND COMPONENTS USED IN 15 FIGURES.
Also included are switches 810 and 812 The switches 810 and 812 are conventional mechanical switches or other circuits which form a 2 bit coded signal at the respective switch output representing a binary coded 1 and 3, respectively.
Also included are flip flops DELOP, SS, SW, and PI-Pl O Flip flops P 1-Pl O 20 are a part of the control counter 813 for the OUTPUT MODULE The flip flops are of the same type and have the same characteristics as that described hereinabove in section I F.
The OUTPUT MODULE includes an arithmetic unit ALU of the same type disclosed hereinabove with respect to section I-B 25 The OUTPUT MODULE also has an AND gate 802, an exclusive OR gate 804, and a conventional OR gate 805 The exclusive OR gate 804 is of the type wherein a true signal is formed at its output whenever a true signal is formed at either one, but not at both, of its two inputs simultaneously.
The OUTPUT MODULE contains a generalized clock control 700 The 30 generalized clock control is described in detail hereinabove in section X.
GENERALIZED CLOCK CONTROL.
Similar to the ENCODE MODULE, the OUTPUT MODULE also has gating which is depicted by logical equation for controlling various input circuits and output circuits of the OUTPUT MODULE Included among the logic gates is a 35 clock suspension logic 822 for controlling the suspension of the clock formed by the clock control 700.
The input and output control lines and the information inputs and outputs of the OUTPUT MODULE are depicted along the right hand side of Figs 30 and 31.
Table 17 at the end of the specification lists the various registers and flip flops 40 and gives the general purpose of each in the OUTPUT MODULE.
C Detailed Description
Reference should primarily be made in the following discussion to the OUTPUT MODULE schematic and block diagram of Figs 28-31 and the flow of Fig 32 Consider now a detailed description of the OUTPUT MODULE during its 45 “regular output” operation The “regular output” operation of the OUTPUT MODULE is the retrieval or decompaction operation which is to revolve any line of an iso-entropicgram, preferably the seed, back to the 0 or input line.
Initially, a control signal is formed at the MINIT output of the MINI COMPUTER, thereby causing the following to be reset to 0; flip flops DELOP, 50 OPSW and PI-Pl O The MINI COMPUTER then loads MEMORY MODULE area 1 with the line value of the seed which is to be revolved back to its isoentropicgram input line (or 0 line) and the IPRF is loaded as follows:
LNI with the length of the line value of the seed; HW with the width of the iso-entropicgram for the seed; 55 LINE #with the line number of the line value for the seed Also, flip flop DELOP of the DMP INTERFACE is set to 0 to indicate a “regular output” If set to 1, DELOP indicates a DEL function.
Since flip flop DELOP in the DPM INTERFACE MODULE is in a 0 state, a false signal is formed at the SET DELOP output and therefore flip flop DELOP in 60 the OUTPUT MODULE remains in a 0 state Flip flop DELOP being in a 0 state 1,570,344 indicates a “regular output” operation It will be noted that the generalized clock control circuit 700 has its input IP connected to output MINIT and is responsive to the true signal at MINIT for forming a true signal at the MR output which, in turn, resets the flip flops P 1-Pl O to 0.
Within the OUTPUT MODULE, the true signal at Pl causes the ORSN 5 register to be cleared to 0 The true signal at the CLK output causes the logic Pl CLK to become true which causes the register OLINE to store the LINE NO (see line number from IPRF) Subsequently, the true signal at the CLK output causes the logic Pl CLK to become true which, in turn, causes the following: in the OUTPUT MODULE, register OHW stores the iso-entropicgram width from 10 HW of the IPRF; and a true signal at the output OMI; also register ORT 3 stores the length of the line value of the change vector, if one exists, from LN 2 of the IPRF It should be noted that the length of reference line from LN 2 is only of interest during the DEL operator function which will be discussed in more detail hereinafter 15 The true signal at the OMI output causes the registers MLNI and MLN 2 of DECODE I and II MODULES to store the length of the line value for the seed from LNI of the IPRF and causes registers EBL and ETL and EIR to store the value from BL and TL and IR from the IPRF.
O 83-0 86 of the OUTPUT MODULE flow revolves the line value in 20 MEMORY MODULE area 1 through its corresponding iso-entropicgram to its input or 0 line The revolve is done in two steps to help implement the DEL function and for clipping, which will be explained in more detail after completing the description of the “regular output” function The number of lines through which the line value must be revolved to reach the input line is the difference between the 25 iso-entropicgram width in OHW and the line number of the line value in OLINE.
This value is computed during OB 3 Using the DELTA MODULE, the largest component power of 2 of that difference is determined and stored in register ORSN during OB 5 and the remaining component powers of 2 are represented by the value left in DELI of the DELTA MODULE It will be recalled that the number of lines 30 equal to all component powers of 2 must be revolved before the input line will be reached However, again to help implement the DEL function, the OUTPUT MODULE first causes the REVOLVE MODULE to revolve the line value through the remaining lines to be revolved designated by the value remaining in DELI of the DELTA MODULE ( O 86) and later OB 8 revolves the revolved line value 35 through lines equal to the largest component power of 2 Return now to the actual operation.
0 83-0 86 of the OUTPUT MODULE flow is used for revolving the line value in MEMORY MODULE area 1 towards the input line of its isoentropicgram and to determine the largest component power of 2 for storage in the register 40 ORSN for use during the DEL function OB 2 of the OUTPUT MODULE flow is used to check the content of register OLINE to see if it is 0 Register OLINE contains the line number for the line value stored in the MEMORY MODULE If the line number is 0, it is not necessary to revolve the line value since it is already at the input row Hence, OB 3-OB 6 can be skipped Therefore, if the content of 45 OLINE is 0, a true signal is formed at the output O Lo of the OLINE register Also, the DEL function is not being performed and flip flop DELOP is in state 0 and a signal is formed at output DELOP The logic Pl O Lo DELOP becomes true and the following pulse at CLK resets flip flop P 2 to 0 and sets flip flop P10 to 1, causing OB 7 of the OUTPUT MODULE flow to be entered, thereby skipping the 50 revolve sets of O 83-0 86.
However, return to OB 2 and assume that the line value is not at 0 and hence register OLINE does not contain a line number of 0 and O Lo is true The true signal at CLK is formed while a true signal is formed at the Pl output A true signal is formed at the G Lo output of register OLINE (thereby indicating that its contents 55 are not 0) and the logic Pl O Lo is true and the pulse at CLK resets the Pl flip flop to 0 and sets the P 2 flip flop to 1.
At this point, the OUTPUT MODULE forms a true signal at the P 2 output and OB 3 of the OUTPUT MODULE flow is entered As mentioned, O 83-0 86 are used to partially revolve the line value of the seed toward the 0 or input line of its 60 iso-entropicgram During OB 3, the difference between the seed line number contained in register OLINE and the iso-entropicgram width contained in register OHW is computed This difference is the actual number of lines by which the seed’s line value contained in MEMORY MODULE area 1 must be revolved in order to get its input line Thus, in the OUTPUT MODULE, the true signal at the 65 1,570,344 93 1,570,344 9 P 2 output causes selection circuits D 54 and D 55 to couple the content of registers OHW and OLINE to the ALU and causes a true signal at the S input of ALU The ALU forms a signal at its OP output, representing the difference between the isoentropicgram width and the seed line number contained in registers OHW and OLINE The true signal at P 2 also causes the D 56 selection circuit to couple the 5 difference signal from the OP output of ALU through to its output The true signal at the P 2 output also causes a true signal at the O M 2 output of the OUTPUT MODULE The true signal at O M 2 causes the output from the D 56 selection circuit to be coupled in the DELTA MODULE through the DELS selection circuit to the DELI register The true signal at CERK causes true signals to be formed at the 10 0 M 3 and O M 4 outputs of the OUTPUT MODULE The true signal at the O M 4 output causes the DELI register to store the difference value from selection circuit D 56 of the OUTPUT MODULE into its shift register 302 The true signal at O M 3 calls the DELTA MODULE by triggering the DELGOmulti-vibrator The DELTA MODULE then computes the highest component power of 2 of the 15 difference value (OHW OLINE) and forms it in its register DELO in the manner described for the DELTA MODULE.
Before the DELTA MODULE completes its operation it forms a true signal at the DELMEND output The true signal at the P 2 output, together with true signalsat the DELMEND and CLK outputs cause the logic P 2 DELMEND CLK t 6 20 become true in the clock suspension logic 822 This causes the CS input to the clock control 700 to become true and thereby suspend the pulses at the CLK and CLK outputs The DELTA MODULE continues, as described hereinabove, to determine the largest component power of 2 of the difference value stored in the DELI register, and when this is complete, control is returned back to the OUTPUT 25 MODULE.
When the DELTA MODULE has finished, control is returned back to the OUTPUT MODULE by the DELTA MODULE by forming a true signal at the DELMEND output, thereby forming a false signal at the DELMEND output The false signal at the DELMEND output causes the clock suspension logic 822 to form 30 a false signal at the CS input to the clock control 700 which, in turn, causes clock pulses to be formed at the CLK and CLK outputs The first pulse at CLK causes the flip flop P 2 to be reset to 0 and causes flip flop P 3 to be set to a 1 state.
At this point, OB 5 of the OUTPUT MODULE flow is entered, output P 3 being true The true signal at P 3 causes register ORSN to store the largest 35 component power of 2 from register DELO in the DELTA MODULE OB 6 of the OUTPUT MODULE flow is now entered After all component powers of 2 are formed, a true signal is formed at the output DELMEND of the DELTA MODULE The true signal formed at the DELMEND output of the DELTA MODULE and the P 3 output of flip flop P 3 (OUTPUT MODULE) sets the DD flip 40 flop in the OUTPUT MODULE to a 1 state The logic P 3 DELMEND is true, causing a true signal at the O M 5 output which, in turn, triggers the REVGO oneshot in the REVOLVE MODULE, causing the REVOLVE MODULE to revolve the value line contained in MEMORY MODULE area 1 through the number of lines of its iso-entropicgram specified by the remaining lines to be revolved signal 45 contained in the DELI register of the DELTA MODULE after computing the largest component power of 2 As discussed above, the remaining lines to be revolved can be represented by the following: iso-entropicgram width (HW) line number (OLINE) = largest component power of 2 (ORSN) During the operation of the REVOLVE MODULE, the true condition of logic P 3 REVEND DD 50 causes the clock suspension logic 822 to form a true signal at the CS input of the clock control thereby causing the clock control to disable further pulses at the CLK and CLK output Finally, when the REVOLVE MODULE finishes its operation (i e, revolved the line value through a number of lines equal to HW-OLINE-ORSN), the REVOLVE MODULE forms a false signal at the 55 RE.VEND output, thereby causing the logic P 3 REVEND DD of the clock suspension logic 822 to become false and enable clock pulses at CLK and CLK.
Additionally, the logic P 3 DELOP is true, thereby setting flip flop P 10 to a true state and resetting flip flop P 3 to a 0 state at the following pulse at CLK.
At this point, true signals are formed at the P 10 output and OB 8 of the 60 OUTPUT MODULE flow is entered The true signal at P 10 causes the OPSW flip flop to be set to a 1 state to indicate that clipping may take place, if required, in the ENCODE MODULE Clipping may only take place during the production of the original occurrence vector and at no other time, otherwise errors may result during 65 the revolve operation.
1,570,344 During the true signals at P 10 and r ER, true signals are formed by the logic P 10, (Pl + P 10) CLK, P 10 CIE, causing true signals at the outputs O M 2, O M 4, OM 5 of the OUTPUT MODULE The true signal at P 10 causes the selection circuit D 56 to couple the largest component power of 2 from register ORSN to ‘ register DELI in the DELTA MODULE The true signal at OM 5 calls the 5 REVOLVE MODULE which, in turn, revolves the revolved line value contained in the MEMORY MODULE down the remaining number of lines specified by the largest component power of 2 stored in DELI of the DELTA MODULE.
The true condition of logic P 10 CLK REVEND causes clock suspension logic to disable clock pulses at the CLK and CLK outputs of clock control 700 10 When the REVOLVE MODULE completes its operation, the signal at REVEND goes false and clock suspension logic 822 again causes clock control 700 to form pulses at CLK and CLK One of the flip flops 531 and 533 in the SWITCH MATRIX is true, indicating the MEMORY MODULE area containing the revolved line value and the selection circuit D 57 couples the coded signal from the 15 corresponding switch to the information input of register OAR The true condition of the logic P 10 REVEND causes the register OAR to store the signal so that it will identify the MEMORY MODULE area containing the revolved line value.
The revolved line value is now the input line of the iso-entropicgram Note that the MLN 3 register of the ENCODE MODULE now contains the length of the revolved 20 line value The true condition of logic P 10 REVEND also causes register OLN to store the length of the revolved line value from register MLN 3 of the ENCODE MODULE.
The true condition of logic P 10 REVEND also causes a true signal at the MT input of clock control 700 which in turn causes a true pulse at output OUTEND 25 and at M 7, thereby signalling an end of the OUTPUT MODULE operation and terminating further pulses at CLK and CLK and resetting control counter 813 to 0.
With the detailed description of the “regular output” operation for the
OUTPUT MODULE in mind, consider now the DEL function.
As discussed above, the DEL function is to check for the presence of an 30 occurrence value in the input line using one of the non-input lines of the isoentropicgram The sequence of operation required for the DEL function is briefly set forth under section XIII-A above.
Additionally, the MINI COMPUTER loads the MEMORY MODULE area 1 with the line value of the seed (non-input line) and loads MEMORY MODULE 35 area 2 with the change vector The change vector is in hybrid coded form and represents one or a plurality of occurrence values, each of which identifies an occurrence value in the input line for the seed which is to be checked for presence.
In other words, if the change vector represents occurrence values 2, 6 and 8, each one of occurrence values 2, 6 and 8 in the input line for the seed is to be checked 40 for presence The DEL function allows this checking operation to be performed without revolving the non-input line value of the seed back to the input line of the iso-entropigram.
In addition, the IPRF is loaded as follows:
LN 2 with the length of the line value of the change vector; 45 LNI with the length of the line value of the seed; HW with the width of the iso-entropicgram for the seed; LINE #with the line number of the line value for the seed.
Also flip flops DELOP of the DPM INTERFACE MODULE is set to I to indicate a DEL function operation This causes a true signal at the SET DELOP 50 output of the DPM INTERFACE MODULE thereby setting the DELOP flip flop to a 1 state, indicating that the DEL function is to be performed.
The operation of the OUTPUT MODULE is then called by the MINI COMPUTER by forming a true signal at the OUTGO, thereby triggering the clock control 700, causing it to reset the control counter 813 and start forming pulses at 55 the CLK and C outputs The operation during OBI through OB 6 of the OUTPUT MODULE flow is identical to that described hereinabove with respect to the “regular output” operation and will not be repeated.
Assume now that the operation of the OUTPUT MODULE during the DEL function has progressed through OB 6 of the OUTPUT MODULE flow similar to 60 that described above At this point the following has taken place: the difference between the iso-entropicgram width (OHW) and the line number (OLINE) has been computed and sent to DELI in the DELTA MODULE; the largest 1.570344 1,570,344 95 component power of 2 of this difference has been determined by the DELTA MODULE and the result has been stored in register ORSN of the OUTPUT MODULE; the REVOLVE MODULE has revolved the line value of the seed down a number of lines in its iso-entropicgram where the number of lines is equal to the remaining number of lines after the largest component power of 2 (e g, OHW 5 OLINE ORSN) In other words, the original seed line value has now been revolved through its iso-entropicgram until it is within a number of lines from the input line which equals the largest component power of 2 contained in ORSN.
However, in contrast to the operation during the regular output, the operation during the DEL function has flip flop DELOP in a I state and therefore, during 10 OB 7, when a true signal is formed at the P 3 output of flip flop P 3 of the control counter 813, the logic P 3 DELOP is true and the following pulse at CLK resets flip flop P 3 to 0 and sets flip flop P 4 to a 1 state.
The MINI COMPUTER forms a true signal at output OUTGO which causes a true signal in the IN input of the clock control 700 Subsequently, pulses are formed 15 at the CLK and CLK outputs of the clock control 700.
The outputs P 1-Pl O are now in a 0 state, causing the logic Pl + P 2 + P 10 to be true The following pulse at CLK sets flip flop Pl to a 1 state, thereby forming a true signal at the Pl output Block OB 1 of the OUTPUT MODULE flow is now entered During OB 1, the ENCODE, DECODE I and II and DELTA MODULES 20 and the SWITCH MATRIX are initialized, thereby gating information to the proper registers To this end, the true signal at the Pl output causes the OUTPUT MODULE to form a true signal at the output OM 16 The true signal at the output OM 16 causes the following action in the DECODE I and II MODULES: gates 218 and 220 of DECODE I and a data selector DD Sl of DECODE II couple the length 25 value from LN 2 of IPRF to registers MLNI and MLN 2, respectively; in the ENCODE module BL (bottom limit) and TL (top limit) from IPRF are coupled through their respective data selectors to the input of registers EBL and ETL.
The logic Pl CLK becomes true, causing a true signal at output O Ml which in turn initializes the DELTA MODULE by setting DELFST A true signal at Pl 30 also initializes the SWITCH MATRIX.
OB 9 of the OUTPUT MODULE flow is now entered and a true signal is formed at the P 4 output, which in turn causes true signals at the following OUTPUT MODULE output circuits: O M 6, O M 8, O M 21 The true signal at the O M 6 output causes an inhibit signal from inverter 1444 in the SWITCH MATRIX 35 while a clock signal is formed at the O M 7 output of the OUTPUT MODULE The reason for the inhibit signal will be explained in detail in connection with the SWITCH MATRIX However, in general terms the current revolved line value is now stored in either area 1 or area 3 of the MEMORY MODULE and must now be read by the DECODE I MODULE during the subsequent operation by the 40 OUTPUT MODULE Also the SWITCH MATRIX remains set so that the DECODE II MODULE re-reads the change vector from MEMORY MODULE area 2 and the ENCODE MODULE writes into the other one of areas 1 and 3 where the revolved line value is not stored Accordingly, the inhibit signal prevents the setting of the SWITCH MATRIX from being changed for the DECODE II 45 MODULE but permits a change in setting for the DECODE I and ENCODE MODULES during the subsequent clock at the O M 7 output of the OUTPUT MODULE.
The true signal at the O M 21 and O M 8 outputs initializes the DECODE I abd II MODULES by setting the DIFST and D 52 FST flip flops therein to 1 states 50.
Additionally, the true signal at P 4 sets the OPSW flip flop to a 1 state, thereby indicating that the clipping function may now be performed by the ENCODE MODULE and causes the register ORT 2 to store the length value from register MLNI in the DECODE I MODULE into register ORT 2 of the OUTPUT MODULE Register MLNI in the DECODE I MODULE now contains the length 55 of the revolved line value and this value must now be saved in register ORT 2 to enable a re-read of this line value.
The following pulse at the CLK output causes flip flop P 4 to be reset to 0 and flip flop P 5 to be set to a I state, thereby causing OB 10 of the OUTPUT MODULE flow to be entered 60 During OB 10, a true signal is formed at the P 5 output of the control counter 813 The true signal at the P 5 output causes true signals at the OM 10 output of the OUTPUT MODULE The true signal at the OM 10 output causes flip flop 522 in the SWITCH MATRIX to be set to a 1 state, thereby indicating that the DECODE II MODULE is to be read from MEMORY MODULE area 2 (where the change 65 96 1,570,344 96 vector is stored) and causes a selection circuit in the DECODE II MODULE to enable the length of the line value for the change vector contained in register ORT 3 to be coupled through to the information input of register MLN 2 in the DECODE II MODULE.
The following pulse at the CLK output causes the logic P 5 CLK to be come 5 true and true signals are formed at the OM 11 and O M 20 outputs of the OUTPUT MODULE The true signal at the O Mi I output calls the DECODE II MODULE by setting its D 2 GO one-shot multi-vibrator and causes the register MLN 2 in the DECODE II MODULE to store the length of reference line from register ORT 3.
The true signal at P 5 also causes OB 11 of the OUTPUT MODULE flow to be 10 entered It is during this block that the DECODE II MODULE is called, thereby causing the first occurrence value from the change vector to be provided.
The logic P 5 D 2 END CLK forms a true signal at the CS input of the clock suspension logic 822, thereby causing the clock control 700 to suspend further clock pulses After the DECODE II MODULE has finished its operation of 15 reading and decoding the first occurrence value from the change vector, the true signal at the D 2 END output of the DECODE II MODULE goes false, causing the clock suspension logic 822 to remove its signal from the CS input of the clock control 700, thereby enabling clock pulses to again be formed at the CLK and CLK outputs 20 If, during the operation of the DECODE II MODULE, it was found that the last occurrence value from the change vector had previously been read and that no additional occurrence values could be provided, the DECODE II MODULE sets its EOF 2 flip flop to a 1 state, thereby causing a true signal at the EOF 2 output The true signal at P 5 causes the flip flop P 6 to be set to a 1 state and flip flop P 5 is reset 25 to a 0 state at the following pulse at CLK and OB 27 is entered.
During OB 27 of the OUTPUT MODULE flow the true signal at the P 6 output, together with true signals at the EOF 2 and CLK outputs causes the logic P 6 EOF 2 CLIK to be become true, thereby forming a true signal at the OM 15 output which in turn causes the ENGO one-shot to be set, thereby calling the 30 operation of the ENCODE MODULE In addition, the logic P 6 EOF 2 is true, forming a true signal at the OM 18 output, thereby causing the ELAST flip flop in the ENCODE MODULE to be set to a 1 state indicating that this is the last call on the ENCODE MODULE and that the last entry from the input line,if any, is to be written out into a MEMORY MODULE area in hybrid coded form To be 35 explained in more detail the values so written out are in hybrid coded form and represent the occurrence values, identified by the change vector, which are present at the input line of the seed.
Continuing with the operation, the true signal at the P 6 output causes the flip flog P 7 to be set to a 1 state and flip flop P 6 is reset to a 0 state at the following pulse 40 at CLK, causing OB 29 to be entered.
During OB 29 of the OUTPUT MODULE flow, registers OAR and OLN contain values identifying the MEMORY MODULE area containing final output and the length of this area and the OUTPUT MODULE is exited.
However, consider now the operation assuming that the last occurrence value 45 from the reference line has not been read and that the signal at the EOF 2 output is true and consider the operation following OB 11 after the DECODE II MODULE has been called to provide the next occurrence value from the change vector.
The true signal at the P 5 output at the CLK following the clock suspension causes flip flop P 6 to be set to a 1 state and flip flop P 5 to be reset to a 0 state, 50 thereby causing OB 12 to be entered.
The true signal at the P 6 output causes the selection circuit D 53 to couple the occurrence value (from the change vector) in the D 02 register of the DECODE II MODULE to the information input of the OR 2 register, and causes the register OR 2 to store the occurrence value Additionally, the true signal at P 6 causes the 55 ORTI register to store the same occurrence value into register ORTI.
The true signal at the P 6 output also causes the flip flop SS to be set to a 1 state and the flip flop SW to be reset to a 0 state Flip flop SS is set to a I state and will subsequently be reset to 0 to indicate that the first pass through OB 18 and OB 20 is about to be undertaken To be explained, the next time through OB 18 and OB 20, 60 flip flop SS will be in a I state The flip flop SW is used to indicate if an occurrence value, corresponding in value to the occurrence value from the change vector, is present at the input line corresponding to the revolved line As previously explained, an occurrence value is present at the input line if the revolved line value in the MEMORY MODULE, being read by the DECODE II MODULE, has an 65 97 1,570,344 97 occurrence value equal either to the occurrence value from the change vector or equal to the occurrence value from the change vector minus the largest component power of 2 in the register ORSN In actual operation, the flip flop SW is used to exclusive OR the presence of an occurrence value in the revolved line value equal to the occurrence value from the change vector with the presence of an occurrence 5 value in the revolved line which is equal to the same change vector occurrence value less the largest component power of 2 In order to cause the flip flop SW to perform its exclusive O Ring function, it is initially set to a 0 state and, to be explained in more detail, the flip flop SW will end up in a 1 state if the exclusive OR results in a true condition, whereas it ends up in a 0 state if the exclusive OR is a false 10 condition _ d B 13 of the OUTPUT MODULE flow is now entered The true signals at the P 6 output and the EOF 2 output (the latter indicates that the DECODE II MODULE has not reached the end, or last occurrence value of the change vector) and the true signal at the CLK output causes the logic P 6 EOF 2 CLK to become 15 true, thereby forming a true signal at the OM 12 output: The true signal at the 0 M 12 output of the OUTPUT MODULE causes the DIGO one-shot in the DECODE I MODULE to be set, thereby calling the operation of the DECODE I MODULE, causing it to read the first occurrence value from the revolved line value The logic P 6 DIMEND CLK is true, thereby causing the clock suspension 20 logic 822 to disable the clock control thereby suspending further pulses at the CLK and CLK outputs When the DECODE I MODULE has provided the occurrence value from the revolved line value, a false signal is formed at the DIMEN Doutput from the DECODE I MODULE, thereby causing the logic P 6 DIMEND CLK to become false, thereby causing the clock suspension logic to enable the clock 25 control 700 to commence forming pulses at the CLK and CLK outputs Assume that the DECODE I MODULE has not reached the end of the revolved line value and hence a true signal is not formed at the EOFI output and a true signal is formed at the EFI output The true signal at the P 6 output causes flip flop P 7 to be set to a 1 state and P 6 is reset to a 0 state at the following pulse at CLK, thereby causing 30 OB 14 of the OUTPUT MODULE flow to be entered.
During OB 14, a true signal is formed at the P 7 CLK output of the control counter 813 which causes the register ORI to form at its output the occurrence value which was read from the revolved line value by the DECODE I MODULE.
When the signal at P 7 is removed, the register ORI will retain and store the value, 35 which is a characteristic of the register.
OB 15 of the OUTPUT MODULE flow is entered During OB 15, the true signal is still formed at the P 7 output The true signal at the P 7 output causes the selection circuits D 54 and D 55 to couple ( 1) the line value occurrence value from register ORI, and ( 2) the test occurrence value (from the reference vector) from 40 register OR 2 to the inputs of the ALU Initially, the true signal at the P 7 output causes the compare (C) input of the ALU to be activated, thereby causing the ALU to compare the two input values It should be noted that three possible conditions may result from the compare These possible conditions are as follows: (I) O Rl = OR 2; ( 2) ORI > OR 2; and ( 3) ORI < OR 2 It will be recalled from the 45 theoretical discussion that the revolved line value of the delta is to be aligned so that its rightmost or largest occurrence value, continued in ORI, is aligned with the rightmost occurrence value in the line of the iso-entropicgram to which it is applied If the rightmost occurrence value is equal to the test occurrence so value, the contents of ORI = OR 2 at this point, and the two lines are aligned and 50 the state ( 0) of flip flop SW is exclusive OR'd with I and therefore is set to a I state. Thus, if the ALU forms a true signal at the E output, one input to the AND gate 802 is true Additionally, at this point, output EOFI from the DECODE I MODULE is false Hence, a true signal is formed by the logic P 7 EOFI at the other input, causing AND gate 802 to form a true output The flip flop SW forms a false signal at 55 the SW output and hence the exclusive OR gate 804 forms a true signal at the upper side input of flip flop SW Additionally, since the ALU forms a true signal at the LE output, the OR gate 805 forms a true signal at the LE output Therefore, the logic P 7 (LE + EOFI) CLK is true and the exclusive O Ring flip flop SW is set to a 1 state corresponding to the true input from exclusive OR gate 804 60 Assume a non-aligned condition where the occurrence value (from the revolved line) contained in ORI is greater than (>) the test occurrence value contained in register OR 2 The ALU will form a true signal at the G output but will not form a true signal in either the L or E output The gate 805 will therefore form a false signal at the LE output, causing the logic P 7 (LE + EOFI) CLK to be false 65 and flip flop SW will remain unchanged Additionally, if ORI > OR 2, a decision cannot be made and values must be read from the revolved input line until a decision can be made, i e, ORI < OR 2 Accordingly, the logic P 7 EOFI G will be true and hence flip flop P 7 will be reset to a I state, causing OB 13, OB 14 and OB 15 of the OUTPUT MODULE flow to be re-entered where the DECODE I MODULE 5 provides the next lower occurrence value from the revolved linevalue It should be noted that the DECODE I MODULE provides the occurrence values from the revolved line value in decreasing value order Accordingly, the DECODE I MODULE will be moving through the revolved line value in a direction toward the smaller values to bring the line value into alignment with the larger occurrence 10 value contained in the OR 2 register. Assume that during OB 15 the third condition is found where the occurrence value from the line value in ORI is less than (<) the test occurrence value (from the reference line) contained in OR 2 Under these conditions, the occurrence value ' from the line value is less than (<) the occurrence value from the reference line 15 contained in OR 2 and hence lies to the left of the position under test This means that it is no longer necessary to look for the test occurrence value because the revolved line value does not contain this occurrence value Therefore, the occurrence value in the revolved line value which is to the left of the one under test (OR 2) by the number of occurrence value specified by the largest component 20 power of 2 contained in register ORSN is next to be checked for presence This is done by incrementally decrementing the value in register OR 2 by the value in register ORSN and by causing the DECODE I MODULE to continue providing the occurrence values in the revolved line value in sequence. To this end, OB 16 of the OUTPUT MODULE flow is entered The second 25 time through the status of flip flop SW is not known but it is to remain unchanged. Therefore, its state is XOR'd with O To this end, the output E from the ALU is false and the gate 802 forms a false input to the OR gate 804 causing the exclusive OR gate in turn to apply a false signal at the upper left side of the flip flop SW. Hence, during OB 16, the exclusive OR flip flop remains unchanged Following 30 OB 30, or following OB 16, a true signal is formed at the P 7 and LE outputs This causes thelogic P 7 (LE + EOF 1) to become true and the following pulse at CLK resets flip flop P 7 to a false state and sets the flip flop P 8 to a I state, thereby causing OB 17 to be entered. The true signal at the P 8 output causes OB 17 to be entered The leading edge 35 of the true pulse at P 8 triggers the SS flip flop from a I to a 0 state OB 18 is now entered where the state of the SS flip flop is checked Since the SS flip flop is now in a 0 state indicating that this is the first pass through OB 18 et seq, for the particular test occurrence value from the reference line contained in OR 2, OB 24 and OB 25 of the OUTPUT MODULE flow are entered 40 During OB 24 and OB 25, the test occurrence value in register OR 2 is modified to a test occurrence value which is to the left of the test occurrence by the number of occurrence values specified by the value in ORSN In other words, it is necessary to form a test occurrence value signal which identifies the next occurrence value in the line of the delta iso-entropicgram which corresponds to the largest component 45 power of 2 in register ORSN. Considering the above operation in more detail, the true signal at the P 8 output causes the selection circuits D 54 and D 55 tocouple the test occurrence value from register OR 2 through to the left input of the ALU and couple the largest component power of 2 from register ORSN to the right hand input of the ALU The 50 true signal at P 8 also causes the ALU to subtract the content of ORSN from OR 2 and form a difference value signal at its output OP If the result is greater than or equal to 0, which is the usual case, the resultant difference signal has not resulted in a value which is to the left of or off the end of the iso-entropicgram To be explained in more detail, should the difference signal have resulted in a value 55 which is less than 0 (OR 2 < 0), a position off the end of or to the left of the isoentropicgram would result and OB 19 would be entered. Assume that the difference is equal to or greater than 0 (OR 2 > 0) The true signal at the P 8 output causes fli flop P 9 to be set to a 1 state and flip flop P 8 to be reset to 0 at the following CLK, thereby causing OB 20 to be entered 60 The true signal at the P 8 output causes the difference signal formed at the output of ALU to be coupled through the D 53 selection circuit back to the input of register OR 2 and the true condition of logic F 8 M S K causes register OR 2 to store the difference value Thus, OR 2 now contains the original test 1,570,344 occurrence value decreased by the largest component power of 2 contained in register ORSN.
During OB 20, true signals are formed at the P 9 and S outputs (i e, flip flop SS is in a 0 state), thereby causing OB 26 to be entered.
If during OB 26 the content of register OR 2 is equal to or greater than ( 2) 0, 5 meaning that it is still within the width of the iso-entropicgram, then it is necessary to reenter OB 14 et seq where the new test occurrence value contained in register OR 2 is compared against the occurrence value from the revolved line value stored in ORI to determine whether they are equal To this end, a true signal is formed at the O Rh O out ut of the OR 2 register, indicating that the OR 2 register is not 0 and 10 the logic P 9 PS TYRM becomes true and the following pulse at CLK triggers theP 7 flip flop to a 1 state and resets the P 9 flip flop to a false state, thereby causing OB 14 of the OUTPUT MODULE flow to be entered.
During OB 14, a true signal at the P 7 CLK output again causes the register ORI to store the next occurrence value from the revolved line value which is still 15 stored in register DO 1 of the DECODE I MODULE.
During OB 15, register ORI contains the occurrence value from the revolved line value and register OR 2 contains the test occurrence value As discussed above, should the values contained in ORI and OR 2 be equal, OB 30 is entered If flip flop SW is now in a 1 state, the AND gate 802 and the exclusive OR gate 804 will apply a 20 true signal to the exclusive O Ring flip flop SW, causing it to change to a O state A O state of the SW flip flop at this point indicates that the revolved line value contains occurrence values equal to those designated by both the test occurrence value from the reference line and the calculated occurrence value which the ORSN positions to the left This indicates that an occurrence value equal to the test occurrence 25 value from the reference line is not present in the input line of the isoentropicgram for the seed If, on the other hand, the comparison during OB 15 reveals that the occurrence value from the revolved line value contained in ORI is greater than (>) the value contained in register OR 2, the OUTPUT MODULE, through the DECODE I MODULE, has not yet reached the position in the revolved line value 30 corresponding to that now specified by register OR 2 Accordingly, OB 13 is again entered where the DECODE I MODULE is again called, causing the next occurrence value from the revolved line value to be provided and during OB 14, stored in register ORI It will be noted that OB 13 is re-entered with flip flop P 7 in a true state, the logic P 7 EOFI G causing flip flop P 7 to be reset at the pulse at 35 CLK.
This operation continues causing occurrence value after occurrence value in the revolved line value to be provided by the DECODE I MODULE until one is stored in ORI which is equal to or less than the computed test occurrence value stored in register OR 2 If an equality is found, then OB 30 is entered where, as 40 discussed above, the exclusive OR flip flop is complemented If an entry is stored in register ORI that is less than the value in register OR 2 before an equality is detected, OB 16 of the OUTPUT MODULE flow is entered where the SW flip flop remains in its previous state The 0 state of the SW flip flop then indicates that the occurrence value under test is not present at the original input line If SW flip flop 45 is in a 1 state, the occurrence value under test is present.
If during OB 15 it is found that the content of ORI is equal to (E) or less than (L) that of register OR 2, the OR gate 805 forms a control signal at the LE output.
The true signal at the LE output causes the logic P 7 (LE + EOPI) to become true and flip flop P 8 is set to a 1 state and flip flop P 7 is reset to a 0 state at the following 50.
pulse at CLK as described above.
OB 17 is now entered for the second time The true signal at the P 8 output causes the SS flip flop to be reset from a 0 to a I state, thereby indicating that this is the second pass through OB 18 et seq The 1 state of the SS flip flop and the true signal at the SS output causes OB 19 to be entered where the state of the SW flip 55 flop is checked.
If the SW flip flop is in a 1 state, OB 22 is entered During OB 22, the true signal at the P 8 output causes the OM 13 output of the OUTPUT MODULE to be true and thereby enable the appropriate circuits in the ENCODE MODULE in preparation for causing the ENCODE MODULE to write out the occurrence value 60 contained in ORTI The test occurrence value from the reference is still in register ORTI where it was stored during OB 12.
During OB 23, true signals are formed at the SS and SW outputs and the following pulse at CLK causes the logic P 8 SS SW CLK to become true which in 1.570344 1,570,344 100 turn forms a true signal at the O M 14 output, thereby calling the ENCODE MODULE.
The true signal at the P 8 output causes the flip flop P 9 to be set to a I state and flip flop P 8 is reset to a 0 state at the following pulse at CLK and OB 20 is entered.
Assuming that the flip flop SS is in a 1 state, a true signal is now formed by the 5 logic P 9 SS causing the output circuits OM 17 and O M 21 from the OUTPUT MODULE to be true The true signal at the O M 17 output is applied to the DECODE I MODULE, causing its MLNI counter to be set to the value contained in register ORT 2 in the OUTPUT MODULE (Dl FST causes MA Rl to be reset on the first call to DECODE I) It will be recalled that ORT 2 contains the length of the 10 revolved line value Additionally, the true signal at the O M 21 output sets the DIFST flip flop in the DECODE I MODULE Thus, the DECODE I MODULE has now been set so that its next call will cause it to again start reading the beginning of the revolved line value to use for a further test occurrence value from the reference line 15 OB 11 of the OUTPUT MODULE flow is now re-entered and the true signal at the P 9 SS CEK logic causes a true signal at the OM 11 output The true signal at the OM 11 output causes the DECODE II MODULE to again be called, this time reading out the next test occurrence value from the reference line designating the next occurrence value in the input line of the iso-entropicgram to be tested (if any) 20 The value is stored in registers ORTI and OR 2 during OB 12 as discussed above for the first test occurrence value from the reference line.
The sequence of operation dismissed above is then repeated to determine whether there is an actual occurrence value in the input line of the isoentropicgram specified by the test value contained in registers ORTI and OR 2 If 25 so, the occurrence value is encoded by the ENCODE MODULE and stored in the MEMORY MODULE This operation continues until the last test occurrence value of the reference line has been read by the DECODE II MODULE and processed After this occurs, the operation of the OUTPUT MODULE returns from OB 21 to O Bll at which time it is found that the EOF 2 flip flop in the 30 DECODE II MODULE is in a 1 state, indicating that the last test occurrence value from the reference line has been read A true signal is now formed at the EOF 2 output causing OB 27 and OB 28 to be entered where the true signal at P 6 causes the ENCODE MODULE to be called for the last time and the last encoded value, if any, is stored in the MEMORY MODULE 35 D Example of Operation The following is an example of the “regular output” operation of the OUTPUT MODULE, using the example of Table 4-B Symbolic notation is used to indicate the sequence of operation.
The line value of the seed is assumed to be in MEMORY MODULE area 1 40 and in hybrid code is as follows:
10000111 occurrence values 7, 6, 3, 2, 0, 01011001 J physical length = 2 The following is stored in the IPRF:
LINE = 7 seed line number; 45 HW = 16 iso-entropicgram width; LN 1 = 2 physical length of seed line value; TL = 16 top clipping limit; Bl = 0 bottom clipping limit; IR = 0 interval value; 50 DELOP = 0 DEI function not requested.
Sequence of control OB 1-OB 8:
OB 1 OPSW = 0 turn off clipping f/f; ORSN = O clear; OHW = HW = 16 iso-entropicgram width; 55 OLINE= LINE = 7 seed line number; OB 2 OLINE O go to OB 3 101 1,5) U,344 -iul OB 3 DELI( 9)= OHW( 16) OLINE( 7) DELI contains the number of line seed line value must be revolved to get original input; OB 4 call DELTA MODULE DELTA MODULE generates highest DELO = 8 component power of 2 in 9 which is 8 and DELI contains the remainder of 1 upon return; OB 5 ORSN = DELO = 8 save the result in ORSN; OB 6 call REVOLVE revolve the seed line value down the number of lines remaining in DELI, in this case, generate line 8; OB 7 DELOP = O ‘ go to OB 8 OB 8 DELI = ORSN = 8 turn on the clipping; call REVOLVE function and revolve down ORSN ( 8) OPSW = 1 lines; OB 9 OAR = output area which contains the event’s original occurrence vector; OLN = 3 the length of this area HALT.
The following is an example of the DEL operation of the OUTPUT MODULE 20 using the example of Table 4-B Symbolic notation is again used to indicate the sequence of operation The content of IPRF is as follows:
LINE = 7 HW= 16 TL= 16 25 BL= 0 IR= 0 LNI = 2 LN 2 = 4 physical length of reference line to DELOP = 1 indicate the DEL function 30 MEMORY MODULE area 2 contains the following hybrid coded representation of seed line value:
10000111 occurrence values 7, 6, 3, 2, 0, 01011001 J physical length = 2; MEMORY MODULE area 1 contains the following hybrid coded representa 35 tion of the reference line:
10001100 10001000 10000011 10000000 test occurrence values 12, 8, 3, 0 40 Intermediate seed line result line 8 of iso-entropicgram (Table 4-B):
10001000 01101010 occurrence values 8, 6, 4, 2, 1, O 00000001 length = 3; Sequence of control: 45 OB I-OB 6 same as for example of regular output given above At this point, line 8 of the iso-entropicgram has been generated.
ins 1 ^fi 7 ^ N A A 0 B 7 DEL 01 =l x OB 9 0 B 9 initialize DECODE I, II and ENCODE MODULES; DI 1 FST =_D 2 FST = 1 ORT 2 =MLNI = 3 S OB Set 522 in SWITCH MATRIX; assure DECODE II reads from proper area; ML-N 2 +ORT 3 = 4 length of reference line; OB 11 call DECODE II read a column index; D 02 =12 EO Fl = 0 to be checked; SS= 1 SW = O O B 120 OR 2 =ORT 1 = 12 save the value read; OR 13 call DECODE I read a value fromline 8 of the isoDO 1 = 8 EOF= 0 entropicgram; OB 14 ORI = 8 save it; 0 R 15 O R 11 ( 8) < O OR 2 ( 12) ' go to OR 16 stimulate XOR; OB 16 SW( 0) =SW( 0) XOR O OR 17 SS = O OR 18 SS = O go to O B 24 0 B 24 OR 2 ( 4) = OR 2 ( 12) ORSN( 8) next position to be checked; O 825 OR 2 ( 4) > 0 go to O 820 0 820 SS = O go to O 826 0 826 OR 2 ( 4) > 0: go to OR 14 OR 14 OR 1 = D O 11 = 8 OR 15 ORI ( 8) > O R 2 ( 4) ‘ go to OR 13 OR 13 call DECODE I D O l= 6 EOF 1 = O OB 14 ORI = DOI = 6 OR 15 ORI ( 6) > O R 2 ( 4) go to OB 13 OR 13 call DECODE I D O l= 4 EOF 1 = O ORI 4 ORI =D 130 = 4 O 15 ORI 1 = O R 2 = 4: go to O 830 OB 30 SW(l)= SW( 0) O 1 0 R 17 SS= 1 OB 18 SS= go to OB 19 OR 19 SW = 1 go to O 822 0 822 E 1 ( 12) = ORTI( 12) 0 R 23 call ENCODE 0 820 SS= 1 go to B 21 OB 21 l MLNI 3 D 11 FST = 1 OR 11 call DECODE II D 02 = 8 EOF 72 = 0 ORI 2 SW= 0 SS= 1 O R 2 =ORT 1 = 8 OR 13 set DECODE I DOI= 8 EOF 1 = O O B 14 O Rl =D Ol = 8 O B 15 ORI 1 ( 8) = OR( 2)8 go to O 830 OB 30 SW(l) =SW()0) 1 OR 17 SS = O OR 18 SS = O: go to O 824 0 824 OR 2 ( 0) = OR 2 ( 8) ORSN( 8) 0 8250 OR 2 = O go to B 20 0 R O 20 SS = O: go to O 826 0 826 O R 2 = O go to OR 14 OB 14 ORI = 8 OR 15 ORI (S) > O R 2 ( 0) ‘ go to OR 13 0 B 13 DECODE I DOI= 6 EOF 1 = O O B 14 O Rl=DO 1 = 6 OB 15 ORI( 6)> O R 2 ( 0),go to OR 13 OB 13 call DECODE I D 01 = 4 EOF 1 = O :35 write out the test occurrence value; reset the DECODE I MODULE; 102 102 1,570,344 103 1 570 34410 OBI 4 OR 1 =DOI = 4 OB 15 OR 1 ( 4) > O R 2 ( 0) go to OB 13 0 B 13 call DECODE I DOI= 2 EO Fl=O OBI 4 OR 1 I=DO Il= 2 013 15 ORI( 2) > O R 2 ( 0) go to OB 13 OB 13 call DECODE I DO 1 = 1 EOFI= O O B 14 ORI =D 3 = 1 OB 15 O R 11 > OR 2 go to O B 113 01313 call DECODE I DOI= 0 EOF 1 = O OB 14 ORI = DOI = O OB 15 O R 11 = OR 2 go to O OB 30 O OB 30 SW( 0) = SW(l) 1 O B 17 SS 1 013 18 SS = 1 go to 0319 OB 19 SW = O go to 01 820 OB 20 OSS = 1 go to 01321 01321 ML-NI ORT 2 = 3 DI 1 FST= 1 0 8131 call DECODE II DO 2 = 3 E O F 2 = O 01312 SS= 1 SW= 0 OR 2 =OR Tl= 3 OB 13 call DECODE I DOI= 8 EOF 1 = O OB 14 OR 1 = 13 l = 8 013 5 OR 1 ( 8)>OR 2 ( 3) go to OB 13 OB 13 -OB 14 OB 15 O B 14 OR 1 =DOI = 2 OB 15 ORI( 2) < O OR 2 ( 3): go to O B 116 01316 SW( 0) = SW( 0) O OB 17 SS= O OB 18 SS = O go to 01324 OB 24 OR 2 (-5) = OR 2 ( 3) ORSN( 8) OB 25 OR 2 (-5) < O go to 01319 013 19 SW = O go to OR 20 OB 320 SS = 0go to OB 26 0 B 26 OR 2 (-5) < O x go to 01321 01321 MI-NI = ORT 2 = 3 OB 11 call DECODE II D 02 = 0 E O F 2 = O OBI 2 SS= 1SW= 0 OR 2 =OR Tl = 0 OB 13 call DECODE I D O l= 8 EOF 71 =O 013140 R 1 =DOI = 8 01 8150 R 1 ( 8)> O R 2 ( 0), goto OB 13 0 81313-0 814 -0 OB 15 01 BI 40 R 1 = DOI = 0 OB 15 ORI(O) = O R 2 ( 0): go to OB 30 OB 30 OSW(l) =SW()0) 1 013 17 SS = O OB 18 SS = 0 go to OB 24 01324 O R 2 (-8) = OR 2 ( 0) ORSN( 8) 01325 OR 2 (-8) < 0 go to 01319 OB 19 SW = 1go to OB 22 01322 EI =ORTI = O 01323 call the ENCODE MODULE 01320 SS = O go to O B 26 01326 O R 2 (-8) < O go to 01321 S 8 does not appear as an occurrence in input line reset decode to given point; loop repeats until the 2 is read from the iso-entropicgram line number 8 if O R 2 is negative, then we need not consider further; the DECODE I loop repeats until the 0 value is read 103 103 OB 21 MLNI = ORT 2 = 3 reset DECODE I; DIFST= I OB 11 call DECODE II D 02 = 0 EOF 2 =I - goto 3 827 OB 27 set ELAST 5 OB 28 call ENCODE OB 29 OAR = output area written by ENCODE OLN = length of this area HALT OUTPUT OAR 10 as described above OLN actual output 10001100 12 10000000 0 The test occurrence values stored in the MEMORY MODULE output area 1, 15 in hybrid code, are now as follows: 10001100 (occurrence values of 12) 10000001 (occurrence value of 0) This indicates that of test occurrence values 12, 8, 3 and 0, in the reference line, only 12 and 0 appeared in the original input line of the isoentropicgram 20 XIV DATA COMPACTION AND RETRIEVAL MACHINE It will be recognized from the foregoing description of the SEED MODULE and OUTPUT MODULE in conjunction with the REVOLVE, DELTA, ENCODE, DECODE I and II MODULES depicted in Fig 34, that a data compaction and retrieval machine has been disclosed The data compaction retrieval system forms 25 a sub-part of the overall DPM SYSTEM The data compaction and retrieval system has several features Specifically, the OUTPUT MODULE in conjunction with the ENCODE, DECODE I, DECODE II, REVOLVE and DELTA MODULES, forms an output machine which retrieves compacted information that has been retrieved into iso-entropicgram form of representation 30 Specifically, an electronic data processing system is disclosed for retrieving a desired coded signal from a representation in the form of a line value signal, a line number signal and a length signal The line value signal represents a line of an isoentropicgram, eliminating leading zeros The line number designates the line in the iso-entropicgram for the line value signal The length signal is equal to the width of 35 the iso-entropicgram which in turn is equal to the length of the line value signal without excluding leading zeros So as not to confuse the length with the storage space, the length signal would be equal to the total number of possible occurrence values in the line of the iso-entropicgram which in turn is equal to the largest possible occurrence value in a line of the iso-entropicgram The data processing 40 system includes a memory, such as the MEMORY MODULE, for storing the line value signal Means such as the OLINE register of the OUTPUT MODULE stores the line number signal Means such as the OHW register of the OUTPUT MODULE stores the length signal Means such as the ALU of the OUTPUT MODULE forms a difference signal corresponding to the difference in values 45 represented by the stored line number signal and the stored length signal Means such as the REVOLVER, discussed hereinabove, responds to the provided line value signal and a provided number signal for forming any one of a set of equivalent signals The set includes the line value signal Each equivalent signal within a set is unique and is related to another one by an exclusive OR of the values thereof, and 50 the values thereof relative shifted The formed equivalent signal represents the desired coded signal Means such as the DECODE I and II MODULES provides a line value signal to the means for forming an equivalent signal which corresponds in value to that stored in the memory means Means such as the DELTA MODULE provides to the means for forming an equivalent signal a number value signal 55 corresponding in value to that of the difference signal. The ENCODE MODULE provides signals from the memory means (MEMORY MODULE) to the equivalent signal forming means (REVOLVER). The means for providing a number value signal, i e, the DELTA MODULE. 104 1,570,344 104 1 7034 105 scomprises means for forming as the number value signal one or more signals representative of the component powers of 2 of the difference signal. Preferably, the equivalent signal forming means, i e, the REVOLVER, includes means such as the ALU REVOLVE MODULE for combining the provided number signals with the provided line value signal to form a further signal 5 which corresponds to the shifted signal formed by the REVOLVER Additionally, the ALU and associated logic form a means for combining the line value signal and the further signal to form the equivalent signal Preferably, the line value signal has one or more actual occurrence value signals out of a group of possible occurrence value signals The possible and actual occurrence value signals are arranged 10 in an incremental, preferably increasing incremental, value order With such a signal representation the means for forming an equivalent signal includes means such as the ALU of the REVOLVE MODULE for combining the value represented by the provided number value signal with each of the values represented by the occurrence value signals of the line value to form a further 15 signal, and the ALU and associated control and logic of the REVOLVE MODULE form a means for exclusive O Ring the values represented by the provided line value signal and the further signal to form the equivalent signal. It will be recalled that in the REVOLVER the means for exclusive O Ring involves the ALU control and logic of the REVOLVE MODULE for sorting the 20 occurrence value signals represented by the provided line value signal and the further signal into an incremental value order Additionally, those occurrence value signals which are equal are deleted The ALU control unit and associated logic of the REVOLVE MODULE sort the values representing the further signal and the occurrence value signals from the provided line value signal to form a 25 series of occurrence value signals arranged incrementally in the order of the values thereof During the process of sorting, those occurrence value signals which are outside of the width of the iso-entropicgram, i e, not among the possible occurrence values, are eliminated. As indicated above, the SEED MODULE and OUTPUT MODULE in 30 association with the other modules of Fig 34 form a data compaction and retrieval system The data compaction and retrieval system is actually an electronic data processing system for both compacting a coded signal and for retrieving a compacted signal Included in this system is a memory means such as the MEMORY MODULE for storing and making available coded signals for 35 compaction and retrieval Means such as the REVOLVER of Fig 19 responds to a coded signal and a provided number signal for forming any one of a set of equivalent signals The set includes the coded signal Each equivalent signal within a set is unique and related to another one by an exclusive OR of the values thereof and the values thereof relative shifted Decode means such as the DECODE I and 40 II MODULES decodes a coded signal for compaction or a coded signal for retrieval from the memory means from a first code to a second expanded code for the means for forming equivalent signals In this connection it will be recalled that the DECODE MODULES decode occurrence vectors from hybrid code to the expanded absolute coded form representing occurrence values Encode means, 45 such as the ENCODE MODULE, encodes the equivalent signal from the second code to the first code for storage in the memory means Means such as the SEED MODULE is responsive to at least a portion of the decoded signal for compaction for forming a total number value signal which represents a quantity of the so equivalent signals In this connection the larger of the largest and next largest 50 occurrence value differences stored in the register Tl designates the total number of lines by which a revolve is to be taken. Means such as the OLINE register of the OUTPUT MODULE stores a line number signal associated with a coded signal for retrieval Means such as the OHW register of the OUTPUT MODULE stores a length signal associated with the 55 stored line number signal The OUTPUT MODULE forms a means for forming a different signal representing the difference in values of the stored line number signal and the stored length signal Means such as the DELTA MODULE provides the number signal to the equivalent signal forming means (REVOLVER). Specifically, the DELTA MODULE forms a means which is responsive to either 60 the total number value signal, for a compaction, or the difference signal, for a retrieval, for forming, corresponding thereto, the number signal In this connection the number signal is one or more signals representing the component powers of 2 of the total number value signal or the difference signal. Preferably, the compaction and expansion provided by the DECODE I and II 65 1.570,344 and ENCODE MODULES are provided in the system However, this further compaction would not be essential within the broader concepts of the present invention In this connection then the DECODE I and II and ENCODE MODULES form, broadly, a means for providing coded signals corresponding to those available from the memory means and corresponding to those from the 5 means for forming equivalent signals to the other. The OUTPUT MODULE in conjunction with the REVOLVE, DECODE I and II, REVOLVER, DELTA and ENCODE MODULES, provide the DEL function described above The DEL function allows a test to be made to determine whether an actual occurrence value is present in an input line of an iso 10 entropicgram given one of the non-input lines Broadly, the steps include the steps of forming a line representing the non-input line The formed line signal represents one or more actual occurrence values of the possible occurrence values making up each line of an iso-entropicgram This step corresponds to OB 6 of the OUTPUT MODULE flow During OB 5 of the OUTPUT MODULE flow a length signal is 15 formed representing the number of lines of displacement in the isoentropicgram between the non-input line and the input line A test signal is formed during OB 12 representing the value of an absolute occurrence value in the input line to be checked for presence The test signal corresponds to an occurrence value in a test vector 20 During OB 24 the values represented by the test signal and the length signal are combined to form a further test signal identifying a further occurrence value for test This step corresponds to forming a further one of the occurrence values in one of the lines of the inverted DEL (Table 9-C). During OB 15 in the first pass, the value of the test signal is compared with the 25 values of the formed line signal for equality, i e, a predetermined relation During OB 15 in the second pass the value of the further test signal is compared with the values of the formed line signal for equality, also a predetermined relation A predetermined signal is formed during OB 19 by causing the flip flop SW to be in a I state responsive to the results of both of these tests of comparing When the SW flip 30 flop is in a I state following both comparisons, the occurrence value specified by the test signal is present in the input line Due to the exclusive OR gating to the input of the SW flip flop detection of equality in one step of comparing and the detection of inequality in the other step of comparing is required for the flip flop SW to end up in a 1 state and thereby indicate the presence of the occurrence value 35 at the input line If both tests produce equality or inequality, the SW flip flop ends up on a 0 state, thereby indicating the lack of the pressure of the occurrence value in the input line. In terms of the system, involving the DEL function, an electronic data processing system is disclosed for checking for the presence of an actual 40 occurrence value out of a series of possible occurrence values arranged in an incremental value order The checking is for the presence of the actual occurrence value in the input value line of the iso-entropicgram utilizing one of the non-input lines of the same iso-entropicgram There is disclosed memory means such as the MEMORY MODULE for storing a line value signal representative of a noninput 45 line Means such as the OLINE register stores a line number signal corresponding to the stored line value signal Means such as the OHW register stores a length signal Means such as the ALU of the OUTPUT MODULE forms a difference signal corresponding to the difference in values represented by the stored line number signal and the stored length signal Means such as the REVOLVER 50 responds to a provided line value signal and a provided number signal for forming any one of a set of equivalent signals The set includes the line value signal Each coded signal within a set is unique and related to another one by an exclusive OR of the values thereof and the values thereof relative shifted. Means such as the DELTA MODULE responds to the difference signal for 55 forming a first signal representing the largest component power of 2 of the difference and for forming a second signal representing the remaining component power of 2 of the difference Means such as the ORSN register in the OUTPUT MODULE stores the largest component power of 2 signal The DELTA MODULE provides the remaining component power of 2 signal and the line value signal to the 60 means for forming an equivalent signal (REVOLVER) thereby causing an equivalent signal to be formed Means such as the ORTI register forms a means for storing a test signal representing the value of the absolute occurrence value in the input line to be checked for presence Means such as the ALU of the OUTPUT MODULE forms a means for combining the values represented by the test signal 65 106 106 1.570344 and the length signal to form a further test signal identifying a further occurrence value for test Means such as the ALU of the OUTPUT MODULE compares the value of the test signal with the value of the formed equivalent signal for a predetermined relation The ALU and the associated timing and logic additionally forms a means for comparing the value of the further test signal with the values of 5 the formed equivalent signal for a predetermined relation Means such as the SW flip flop is operative during OB 19 and responsive to the results of both of the predetermined relations to thereby indicate the presence of an actual occurrence value in the input line corresponding to the test signal. XV PIPE MODULE 10 A General Description The general purpose of the PIPE MODULE is to help in the process of locating requests for data out of a large mass of data provided in the data base The data base disclosed herein is arranged, by way of example only, into paragraphs, each of which in turn contains sentences, each of which in turn contains words, 15 each of which in turn contains characters The request may be a word, a phrase, a sentence, or a paragraph. If a request is always in the data base exactly, it is no problem to retrieve the requested information from the data base The inexactness between the request and the data base may come about because of misspelling of words, transposing of 20 words, or may be caused just by a lack of knowledge by the requestor as to the exact wording in the data base For example, the request word "SIT" may be a misspelled word such as "THIS" Problems arise where there is an inexact relation between the request and the data base The PIPE MODULE and the BRIGHTNESS MODULE cooperate in locating those requests which are exactly 25 or inexactly contained in the data base. The purpose of the PIPE MODULE then is to determine whether the request is located in the data base exactly or inexactly To locate inexact requests from the data base, the PIPE MODULE requests or determines which entries (occurrences) in the data base could be used for further selection criteria employed by the 30 BRIGHTNESS MODULE Thus, the PIPE MODULE selects those entries in thedata base which would be candidates for processing by the BRIGHTNESS MODULE These candidates are then used by the BRIGHTNESS MODULE to select the best possible candidate for the request. Before considering the theory of the PIPE MODULE, the following 35 terminology should be carefully noted An "event" is composed of primitive elements which lie between two "delimiters" For example, in the letter layer 0 of Table 1, the events are letters "Event time", also called "possible occurrence position", identifies a possible relative position or value in a data base for an event or delimiter occurrence value An "event occurrence vector" represents event 40 occurrence values, each of which identifies the event time at which an event has occurred An "entry" is a series of primitive elements, i e, letters which lie between two delimiters where the delimiters identify the beginning of two successive entries For example, in the letter layer 0 an entry such as "THIS" is a word composed of a series of events (letters) between the two delimiters positioned 45 at event times 0 and 5. Considering the theory of the PIPE MODULE in more detail, the PIPE MODULE employs a selection criteria for indicating to the requestor those possible entries in the data base which might be a response to a request Two selection criteria are employed by the PIPE MODULE and are as follows 50 The first selection criterion is a "pipe width" (PW) The pipe width is an offset value which identifies how far to the right or to the left (above or below) each particular possible occurrence value an actual occurrence value may lie for purposes of the piping function Those which fall within + the "pipe width" (PW) are called "hits" 55 The second criterion is the relationship of the length of the request (LNRQ) to the number of hits within each entry in the data base The second criterion is important in determining a meaningful number of hits in a data base entry before the entry should be considered as a candidate for the BRIGHTNESS MODULE function The relationship between the length of the request (LNRQ) and the 60 number of hits is determined by a "threshold" value which represents the minimum number of hits before a data base entry is considered by the BRIGHTNESS MODULE for processing. The importance of the second criterion becomes evident by considering the 107 1,570,344 107 following example Assume the data base contains the word "THIS" and the request word is "BIG" It is apparent that the I in BIG lies at a position within + I of the position of the I in THIS However, it is quite apparent that one would not select the word THIS to be sent to the BRIGHTNESS MODULE since there are four events in the word THIS and only one bit 5 The rest of the theory of the PIPE MODULE is best understood by reference to an actual example Assume the data base depicted in Table 1 Also assume a request occurrence vector THIS The first step is to pull out the event occurrence vectors for the events T H I S from the data base of Table 1 Table 18 sets out the decimal values of the event occurrence values for each of the events T H I S Table 10 18 also shows the event occurrence vectors for T H I S lifted out from the data base of Table 1 in columnar notation Table 18 on the right side shows the actual occurrence values, in decimal form of the event occurrence values for each event. The first step is to find out whether the request is in the data base exactly or inexactly To this end, "bias" values are assigned to the event occurrence vectors 15 identified by a request Increasing valued bias values are assigned to the event occurrence vectors starting with the number 0 For example, in the request word THIS, the event occurrence vectors for the events T H I S are respectively assigned bias values 0, 1, 2 and 3 The bias values are then subtracted from event occurrence values in the corresponding event occurrence vector The results are "biased event 20 occurrence values". Table 19, in columnar notation, depicts each event occurrence value in the data base of Table 18, decreased by its bias value Thus, the bias value for the event "t" is 0 and the corresponding event occurrence values remain unchanged The bias value for the event "h" is 1 and the corresponding event occurrence values are 25 decreased by 1 or moved left one place The bias value for the event "i" is 2 and the corresponding event occurrence values are decreased by 2 or moved left two places The bias value for the event "s" is 3 and the corresponding event occurrence values are decreased by 3 or shifted left three places. It will now be apparent with reference to Table 19 that each of the event 30 occurrence values between the delimiters for event time 0 and 5 will be shifted so that they line up at event time 1 This then gives four hits in event time 1 which is exactly the length of the request word "this" Therefore, an exact entry exists in the data base for the request word "this" It should also be noted that the biased occurrence values for the word "this" in the data base are all lined up at event time 35 1 which is just one event time away from the delimiter in event time 0 and are therefore associated with the beginning delimiter at event time 0 The resultant biased event occurrence values are depicted at the right of Table 19 in decimal form. Consider now another example where there is an inexact match between the 40 request and the data base Assume that the request is the word "SIT" First, the event occurrence vectors for the delimiter and the events S, I and T are pulled out of the data base of Table 1 as depicted in Table 20 The right hand side of Table 20 depicts, in decimal form, the event occurrence values in the event occurrence vectors for the events S I T Next, the bias values 0, 1, and 2 are assigned for the 45 events S I T and the bias values are subtracted from each of the occurrences in the corresponding event occurrence vectors Thus, the bias value for the event S is 0 and the corresponding event occurrence values remain unchanged The bias value for the event I is 1, and the corresponding event occurrence values are decreased or shifted to the left by 1 and the bias value 2 for the next event is 2 and the 50 corresponding event occurrence values are decreased or shifted to the left by 2. The resultant biased event occurrence values are depicted in decimal form on the right side of Table 21. With respect to the event T, it should be noted that the circled occurrences were biased or shifted below the beginning delimiter for their entry It is necessary 55 to tag or somehow identify each event occurrence value which is shifted past the corresponding beginning delimiter and hence no longer represents the entry in which it originally appeared. It is now necessary to satisfy the second criterion, that is, to relate the length of the request (LNRQ) to the number of hits in the data base This is accomplished by 60 assuming a "total pipe width" of twice the "pipe width" (PW) and associating the center of the "total pipe width" with the rightmost event time in the entry under consideration; counting the number of hits within the "total pipe width"; retaining the number of hits; and moving onto the lower event times to the left, one by one, and for each event time, counting the number of hits within the "total pipe width" 65 1,570,344 108 108 Using the biased event occurrence values of Tables 21 and 28, the first test is made on the biased event occurrence values appearing between event times 10 and The test is depicted in Table 22 It is assumed that the "pipe width" (PW) is 1, and hence the "total pipe width" is 2 Thus, the test starts with event time 14 and the possible biased event occurrence values between + 1 of 14 are checked It will 5 be noted that there is a biased event occurrence value at event time 13 for the event S hence there is a hit value of 1 for event time 14 Event time 13 is then tested. Thus, in effect, the "total pipe width" is slid one place to the left so that it is now centered on event time 13 Again, the number of hits within the "total pipe width" are computed There is a hit for the event S at 13 and a hit for the event T at 12 and 10 hence the number of hits for event time 13 is 2 This same process is repeated for event times 12 and 11, resulting in hits of 2 and 1 for event times 12 and 11. For simplicity, if two pipe centers are found with the same number of hits, the first one encountered is selected as the center Thus, with reference to the lower part of Table 22, event time 13 is selected as the one with the largest number of hits 15 To be explained in more detail, these values are sent to the BRIGHTNESS MODULE for processing. Event time 10, containing a delimiter, is skipped, and event time 9 is next selected as the next pipe center Referring to Tables 1 and 23, it will be seen that this portion of the data base deals with the word "a" and there are no hits for the 20 request S I T. Referring to Tables 1 and 24, the pipe center is next slid over the delimiter 8 and tests are performed at event times 7 and 6 Two hits are found for the center at event time 6, whereas only 1 is found at event time 7 Event time 5 is skipped over and event times 4, 3, 2 and 1 are selected as centers It will be noted that for the 25 center at event time 3, 2 hits are again found It should also be noted that for each of the tests depicted in Tables 22-25, the occurrence value in the ending delimiter had no effect on the rightmost pipe test The reason for this will become clear when considering the operation of the PIPE MODULE The three entries for the words "test", "is" and "this" are then passed to the BRIGHTNESS MODULE which 30 makes a decision as to which is the best hit for the request S I T Before considering the operation of the BRIGHTNESS MODULE, consider in more detail precisely how the PIPE MODULE carries out the foregoing operation. Within the concepts of the present invention, it is possible to form a module that operates in parallel and looks vertically down across each entry in a data base 35 array such as that in Table 1 The disclosed embodiment of the present invention involves a PIPE MODULE which does not look down vertically across each entry but instead looks at the entries serially by occurrence value and entry To this end, the PIPE MODULE is arranged to keep track of the left shifted or biased event occurrence values This is accomplished by storing in the PIPE/BRIGHTNESS 40 MEMORY (P/B MEMORY) each different biased occurrence value and a "hit count" equal to the number of times the biased event occurrence value occurs In other words, in subtracting the bias value from each event occurrence value in the same event occurrence vector, the same biased occurrence value may occur more than once By storing each different biased event occurrence value and its hit 45 count, it is possible to keep track of the number of times it has occurred simply by upping the hit count by 1 whenever a further one is encountered. Referring to the example shown in Table 19, the following will be noted At event time 1, the biased event occurrence values for the entry "THIS" are all lined up at event time 1 and hence event time I can be assigned a maximum hit count of 50. 4 It will also be noted that the length of the request (LNRQ) for "THIS" is 4 and therefore is exactly the same as the hit count This indicates that the entry appears exactly in the data base Thus, instead of placing one row beneath the other as depicted in Table 19, the PIPE MODULE disclosed herein utilizes the approach where information is represented by biased actual event occurrence values and hit 55 counts One further condition should be noted If the biased event occurrence value is less than or passes across a beginning delimiter for the corresponding entry, a decision is made as to whether it is included or is not included within the corresponding entry For example, in Table 21, the biased event occurrence values -I and 9 for the event T are less than the beginning delimiter values 0 and 10, 60 respectively A rule has been laid down that if a biased event occurrence value lies within the "pipe width" of the lowest event occurrence value in an entry and its value is less than the beginning delimiter for the corresponding entry, then use a biased occurrence value equal to the beginning delimiter for the entry This is an artificial value which avoids computational problems relating to those biased event 65 109 1,570,344 109 occurrence values which slide into another entry from their original entry. Consider now how the PIPE MODULE handles an exact match between the request and the data base Table 26 depicts the transformation of the columnar notation of Table 19 into linear notation Four passes are required The transformation is done serially by event and serially by event time (possible 5 occurrence value position) within each event Consider the example of Table 26 (corresponding to Table 19) for the request "THIS" The entry "THIS" is now linearized in four passes During pass 1, the event occurrence vector for "T" is processed Table 18 reveals that the "T" event occurrence vector, in decimal notation, is 1, 11, 14 Table 19 reveals that the bias value is 0 for the first event T 10 Therefore, the decimal form of the biased event occurrence values is 1, 11 and 14 directly With reference to Table 26, the decimal biased event occurrence values 1, 11 and 14, along with a hit count of I for each, are stored in the P/B MEMORY. During pass 2, the event occurrence vector for the event H is processed. According to Tables 19 and 20, for the second event H the bias value is 1 and the 15 event occurrence vector is the decimal value 2. Subtracting the biased value 1 from the occurrence value 2 results in a biased event occurrence value of 1 Accordingly, a biased event occurrence value of I and a hit count of I were stored in the auxiliary memory Therefore it is only necessary to up the hit count from 1 to 2 for the previously stored biased event occurrence 20 value 1. During pass 3, the event I is processed According to Tables 19 and 20, the bias value for the third event I is 2 and the decimal occurrence vector is 3, 6. Subtracting the bias value 2 results in the biased event occurrence values 1 and 4. The biased occurrence value I and hit count of 2 are already present in the 25 auxiliary memory from pass 2 and therefore the hit count of 2 is merely increased to 3 and the biased occurrence value of 4 with its hit count of 1 are added to the auxiliary memory. During pass 4, the event S is processed According to Tables 19 and 20, the fourth event S has a bias value of 3 and a decimal event occurrence vector of 4, 7, 30 13 Subtracting the bias value 3 results in the biased event occurrence values 1, 4 and 10 Referring to Table 26, pass 3, the auxiliary memory already contains biased occurrence values 1 and 4, hence it is only necessary to up the hit counts for biased occurrence values 1 and 4 from 3 to 4 and 1 to 2, and introduce the biased event occurrence value 10 with its hit count of 1 Thus, what has been disclosed above is a 35 method for linearizing from the information layer depicted in Tables 1, 2 a request represented by the occurrence vector for "THIS" The linearization is represented by the biased event occurrence values and hit counts depicted at pass 4 of Table 26. This linearized result corresponds to that depicted in Table 19 Thus, the linearized result formed by the PIPE MODULE and stored in the P/B MEMORY is nothing 40 more than a translation of the columnar array-type display depicted in Table 19. Table 27 provides an example of how the columnized information of Table 21 may be converted into linearized form Quite importantly, Table 27 involves an inexact match between the request and the data base array The first event is S and its bias value is 0 Therefore, during pass 1, the decimal occurrence values 4, 7, 13 45 for the event occurrence vector of S are transferred directly to auxiliary memory, each associated with a hit count of 1 The second event is I and its bias value is 1. During pass 2, the decimal occurrence values 3 and 6 for the event occurrence vector of I are decreased by 1, resulting in biased event occurrence values 2 and 5. so Since during pass 1 these biased event occurrence values were not formed, they are 50 stored along with their corresponding hit counts of 1 in the P/B MEMORY The third event is T and its bias value is 2 During pass 3, the decimal event occurrence values 1, 11 and 14 for the event occurrence vector of T are decreased by 2, resulting in biased event occurrence values of-1, 9 and 12 Assume a "pipe width" (PW) of 1 The lowest event occurrence value for the entry THIS is I and 55 therefore the biased event occurrence value of is outside of the pipe width As a result, the biased event occurrence value of -I is ignored Similarly, the biased event occurrence value 9 is less than the delimiter 10 for the entry "TEST", and is more than the I below the lowest occurrence value and is likewise disregarded. Therefore, the biased event occurrence value of 12 with its hit count of 1 is added 60 to the result depicted in pass 2 with the result depicted at pass 3 in Table 27 The linearized result depicted at pass 3 corresponds to the columnar result depicted in Table 21. Steps are now taken to satisfy the second criterion, namely, to determine the relationship of the length of request (LNRQ) to the number of hits within each 65 1-570344 entry in the data base More specifically, the number of biased event occurrence values within + the pipe width of each possible event time is determined The next step then is to perform the operation depicted in Tables 22-25 using the linearized results depicted at pass 3 of Table 27. Table 28 depicts the linearized result depicted at pass 3 of Table 27 All of the 5 possible event times 0 through 15 are depicted and immediately below event times 2, 4, 5, 7, 12 and 13 are shown the number of hit counts for the corresponding event time Those event times which are underlined in Table 28 have no corresponding biased event occurrence value The next step is to pass the total pipe width across the linearized result and transform it into the piping values This step corresponds 10 to the steps depicted in Tables 22 through 25 The procedure as outlined above is to select the total pipe width and count the total number of hits within the total pipe width, using each event time as a pipe center except for the event times corresponding to the delimiter occurrence values. Table 29 depicts the operation where the pipe width is passed across the event 15 between delimiters 15 and 10, centering the total pipe width at event times 14, 13, 12 and 11 At the right side of Table 29 the total number of hits for each pipe center is depicted With the pipe centers at 13 and 12, maximum hit count of 2 is reached and therefore the first pipe center of 13 is selected for output along with its hit count of 2 20 The next entry lies between the delimiters at event times 10 and 8 Therefore, the total pipe width is placed with its center at event time 9 No biased occurrence values are present at this pipe location and a -1 is outputted to indicate that there are no hits. Referring to Table 31, the next tests are made for the event times 6 and 7 25 between the delimiters 8 and 5 With the pipe centers at 7 and 6, the number of hits depicted at the right of Table 31 are found, with the maximum number of hit count being 2 for the pipe center at event time 6 Therefore, the biased event time 6 and the hit count 2 are outputted as being the maximum hit count. Similar tests are made for event time 4, 3, 2 and 1 between delimiters 5 and 0 as 30 depicted in Table 32 Here it is found that the pipe center at event time 3 produces the maximum hit count of 2 and therefore the bias value 3 and hit count 2 are output. B Components. * Figs 35-38 form a schematic and block diagram of the PIPE MODULE 35 Table 33 lists the various registers, counters and flip flops in the PIPE MODULE. The registers and counters are of the following types shown in the above TTL book and have the following states and/or bits (or flip flops) of storage: counters M l, M 2, M 3, N, BIAS are of type SN 74161 and each has 8 bits of storage; registers OUT, PSAV, MAX, DI, T, RII, RI, S, PW, LNRQ, are of type SN 74100 and each has 8 40 bits of storage (except MAX, which has 7 bits); counters CV, PWC are of type SN 74191 and each has 8 buts of storage The most significant flip flop (or bit) in register RII is for a sign bit An output SRII is connected to this flip flop and receives a true signal when the sign is (sign flip flop is in a I state) and a false signal when the sign is + 45 Also included are switches 901-904 The switches are conventional mechanical switches or other electronic circuits which form an 8 bit binary coded signal at the information input of the corresponding selection circuit representing, in binary code, the decimal digit depicted inside each box. The flip flops PFIRST, PLAST, PFLG, SM, SGN, ET and ET and control 50 counter flip flops Pl through P 35 are each of the same type and have the same characteristics as that described above The flip flops Pl through P 35 and the corresponding gating circuitry form the control counter 913. The generalized clock control 700 is the same as that discussed above and is depicted here in block diagram 55 The PIPE MODULE also includes an arithmetic unit (ALU) The ALU is the same type disclosed hereinabove with respect to the ENCODE MODULE. The G output of the arithmetic unit ALU is connected to the G output through a logical signal inverter 918 The logical signal inverter which forms a complementary logical signal at its output corresponding to the signal at its input 60 Fig 38 depicts the input/output control lines and the information input/output circuits for the PIPE MODULE The arrows to the right depict outgoing signals whereas arrows to the left depict incoming signals The outgoing control input/output lines each have a symbol at the arrowhead identifying the line and, in 1,570,344 lll oll 112 1,570,344 112 parentheses following the symbol, symbols corresponding to the part of the rest of the system to which the control signal lines are primarily intended to go Heavy lines depict multiple lines for carrying multiple bits of information in parallel throughout the PIPE MODULE and block diagram. Logical equations are used to represent the required gating for operating the 5 PIPE MODULE Clock suspension logic 922 causes the clock generator 700 to suspend the pulses at CLK and thereby suspend operation of the PIPE MODULE under the conditions outlined in more detail hereinafter. C Detailed Description Figs 35-38 for a schematic diagram of the PIPE MODULE Figs 39-41 10 form a flow diagram depicting the sequence of operation of the PIPE MODULE. Symbols are shown adjacent each of the boxes in the PIPE MODULE flow A symbol PB followed by different numerals identifies the various boxes in the PIPE MODULE flow In addition, the symbols Pl-P 35 are used to correlate the corresponding boxes to one of the flip flops PI-P 35 of the control counter 913 15 which is in a l state. In operation, the PIPE MODULE linearizes the event occurrence vectors for a corresponding request during PB 1 through PB 20 of the PIPE MODULE flow A special loop is formed at PB 20, PB 21 and PB 22 of the PIPE MODULE flow to assure that everything has been written out to the P/B MEMORY at the 20 appropriate point in operation of the module The maximum number of hits within the pipe, for each pipe center, is determined during PB 26-PB 48 of the PIPE MODULE flow. Consider now the details of the system, assuming that a pipe operation is about to take place The MINI COMPUTER and its program perform the following 25 operations: First a request is formed at the operator console of the MINI COMPUTER. Second, the MINI COMPUTER determines the layer in the data base contained in the auxiliary memory to which the request is to be applied Third, the event occurrence vector for each event, which is stored in auxiliary memory, is retrieved 30 using standard data processing techniques The request events are used as indices into the data base Fourth, the seed of the event occurrence vector for each event in the request is selected one by one by the MINI COMPUTER, stored in the MEMORY MODULE and passed to the OUTPUT MODULE for conversion from seed form to the input line of the corresponding iso-entropicgram (in hybrid coded 35 form) Fifth, the hybrid coded event occurrence vector is passed to the PIPE MODULE Each subsequent event occurrence vector is selected, converted and passed to the PIPE MODULE only after the previous event occurrence vector has been processed Sixth, the MINI COMPUTER causes the pipe width (PW) and length of request (LNRQ) to be sent to the PIPE MODULE which, in turn, 40 processes the event occurrence vectors one by one Seventh, following the processing of each event occurrence vector, the PIPE MODULE notifies the MINI COMPUTER that it is ready for the next event occurrence vector Eighth, the MINI COMPUTER responds by repeating the above procedure of obtaining the seed of the next event occurrence vector, passing it through the OUTPUT 45 MODULE, thereby converting it to its input line form, storing the input line in the MEMORY MODULE, and calling the PIPE MODULE for processing The foregoing operation continues until the PIPE MODULE processes the last event in the request, at which time the PLAST flip flop in the PIPE MODULE is set to a 1 state by the MINI COMPUTER, notifying the PIPE MODULE that the last event 50 is being processed. With the foregoing general operation in mind, consider now the example depicted at Tables 20, 21, 26-30 Table 11 illustrates the major input/output for the PIPE MODULE Before each call on the PIPE MODULE, it is assumed that the event occurrence vector about to be processed has been passed through the 55 OUTPUT MODULE and has therefore been converted from seed form to the input line ( 0) of its iso-entropicgram and stored, in hybrid code, in MEMORY MODULE area 1 Initially, the delimiter occurrence vector is also passed through the OUTPUT MODULE, converted from seed form to the input line of its isoentropicgram, and stored, in hybrid code, in MEMORY MODULE area 2 60 Initially, all of the registers and flip flops in the PIPE MODULE are cleared or reset to 0, by a control signal at MINIT from DPM INTERFACE MODULE. At this point the DPM INTERFACE MODULE forms a control signal at the output FIRST = l, setting the PFIRST flip flop inthe PIPE MODULE to a I state. 113157,413 The I state of flip flop PFIRST indicates that this is the first pass through the PIPE MODULE. The inputs for operating the PIPE MODULE for the example depicted in Tables 20, 21, 26-30 are as follows: pipe width = 1; length of request (LNRQ) = 3; length of the first event occurrence vector (LNI)= 3; length of delimiter occurrence vector (LN 2) = 4; 5. Memory Area 1 of MEMORY MODULE Memory Area 2 of MEMORY MODULE 10001101 00100000 } event occurrence vector = 13, 7, 4 in hybrid code 10001111 delimiter occurrence vector = 01010000 I 15, 10, 8, 5,0 lin hybrid code 00000001 The MINI COMPUTER forms a control signal on the control line PIPGO, causing the clock control 700 to be activated and commence forming clock pulses at CLK and CLK Since all of the flip flops Pl through P 35 have been reset to a 0 state, the upper left hand input of flip flop Pl is true and therefore the true pulse at CLK (hereinafter called pulse CLK) sets the Pl flip flop to a 1 state, causing PB 1 of the PIPE-MODULE flow to be entered. During PB I, a true signal is formed at the Pl output of flip flop Pl and hence the control counter 913, causing the L input of register PW and the CLR inputs of address counters M l and M 2 to be true, which in turn causes the PIPE WIDTH in IPRF to be stored into register PW and address counters M l and M 2 to be cleared to 0 Additionally, the logic Pl PFIRST is true, causing the CLR input of the register BIAS to be true, thereby clearing the register BIAS to 0 The logicPI.PFIRST CLK also comes true which, in turn causes a true signal at the L inputs of the PWC counter and LNRQR register, causing the PIPE WIDTH signal and the LNRQ signal from the IPRF (Fig 52) to be stored into the PWC counter and LNRQR register, respectively. Additionally, during PB 1, the control signal at P 2 PFIRST causes the pipe width signal stored in the PWC register to be counted down 1 Since the pipe width is initially I, the resultant signal in the PWC register is 0 Thus, at the end of PB I of the PIPE MODULE flow, the PW register contains the pipe width value 1, the LNRQR register contains the request length of 3, and the PWC counter contains a 0 _ In summary then, during PB 1, the registers and various flip flops in the PIPE MODULE are initialized and since this is the first time through the PIPE MODULE, the PFIRST flip flop is in a 1 state. Referring to the control input/output lines in Fig 38, the true signal at the Pl output causes a true signal at the Pl 1 output which, in turn, causes an ENABLE signal to be applied to the DECODE I MODULE, thereby resetting register MARI to 0, enabling LNI through a data selector to the MLNI register and setting DIFST to 1 The true signal at the PI 1 output is also applied to the DECODE II MODULE thereby resetting register MAR 2 to 0, enabling the LN 2 through a data selector to register MLN 2 and to the SWITCH MATRIX, thereby setting flip flops S 1 I, 522 and 533 to 1 Additionally, logic Pl CLK is true, causing a true signal al the P 12 output which in turn causes a true signal to be applied at the L inputs of the MLNI and MLN 2 registers of the DECODE I and II MODULES, causing the LNI and LN 2, respectively, to be stored therein. The true condition of logic Pl CLK also causes a true signal at output P 16 which sets the D 2 GO one-shot multi-vibrator in the DECODE II MODULE thereby calling the operation of DECODE II MODULE This causes the last delimiter occurrence value 15 for the last entry to be read and discarded. The true signal at the Pl output of flip flop Pl causes the P 2 flip flop to be set to a 1 state and the Pl flip flop to be reset to a 0 state with the following CLK pulse and thus PB 2 of the PIPE MODULE flow is entered. It should be note Adat thleoutset that Ahleshock suspension logic 922 is depicted by the equation P 13 DIMEND + B 16 D 2 MEND P 13 and P 16 become true when the DECODE I and II MODULES, respectively, are called 1 fnce, the generalized clock 700 is disabled, thereby disabling the CLK and CLK pulses whenever the DECODE I and II MODULES are called When the DECODE I and II MODULES complete decoding and providing an occurrence value to the PIPE 1,570,344 113 113 MODULE, DI MEND and D 2 MEND become true and hence the suspension logic 922 goes false and the generalized clock control is enabled to provide its CLK and CLK pulses. The DECODE 11 MODULE operates on the delimiter occurrence vector in the MEMORY MODULE area 2 During PB 2, the DECODE II MODULE is 5 called twice On the first call, the ending delimiter 15 for the last entry in the data base is decoded and skipped Thus, the second call causes the beginning delimiter for the last entry to be decoded and formed in register D 02. To this end, the true signal at the P 2 output of flip flop P 2 causes no action except that at the following CLK pulse, the P 3 flip flop is set to a I state and the P 2 10 flip flop is reset to a 0 state, thereby forming a true signal at the P 3 output. The true condition of logic P 2 CRK again causes a true signal at the output PI 6 and thereby sets the D 2 GO one-shot multivibrator in the DECODE II MODULE for a second time This time the DECODE II MODULE reads the beginning delimiter 10 for the last entry and subsequently forms the delimiter signal at the 15 D 02 output The DI register is connected to the D 02 output from the DECODE II MODULE and the true signal at the P 3 output causes the L input of the DI register to be true and hence couple the delimiter from D 02 to the output of the DI register The true signal at the P 3 output also causes the D 510 selection circuit to couple the delimiter 10 from the output of the DI register to one input of the ALU 20 and causes the DSI 1 selection circuit to couple the decremented PIPE WIDTH 0 from the PWC counter to the other input of the ALU The true signal at the P 3 output also causes the S input to the ALU to be true and the ALU subtracts 0 from the delimiter 10, forming the result 10 at OP When the true signal is formed at the CULK output, the logic CLK P 3 becomes true, the L input of the T register receives 25 a true signal and the T register stores the result 10 at OP It should be noted that the value in T is equal to the delimiter 10 minus the decremented PIPE WIDTH in PWC This value in T is the minimum occurrence value (or event time) that will be considered for a biased event occurrence value Any biased event occurrence value for the entry between delimiter values 0 and 15 that is smaller will be ignored 30 During PB 3, the state of the PFIRST flip flop is checked Since this is the first pass through the PIPE MODULE, the PFIRST flip flop is in a 1 state and hence PB 19 is entered. During PB 19 the following action takes place in response to the true signal at the Pl output The logic Pl PFIRST is true, thereby causing the -I ( 2 's 35 complement of 1) formed at the output of the switches 904 to be coupled through to the input of register RII by the D 57 selection circuit The logic CLK Pl causes the L input to the RII register to be true and hence the RII register is loaded with a -1. This is a forced value that is used during PB 10 to insure that all event occurrence values are decoded and stored in the P/B MEMORY Flip flops P 2 and P 3 are 40 sequentially set to a 1 state and when P 3 is 1, PB 5 is entered. During PB 5, the logic P 3 CLK is true and causes the output PI 3 to be true which in turn sets the DIGO one-shot multivibrator in the DECODE I MODULE true This in turn causes the DECODE I MODULE to be called so that it decodes and provides the first event occurrence value 13 from the event occurrence vector 45 stored in hybrid form in MEMORY MODULE area 1. The true signal at PI 3 always calls the operation of the DECODE I MODULE and the operation of the PIPE MODULE is suspended until the DECODE I MODULE has decoded the next event occurrence value 13 The logic P 6 +P 8 is true and hence the D 58 selection logic receives a true signal at the DI input, 50 causing the event occurrence 13 from DOI to be coupled through to the input of the RI register The end of file has not been reached by the DECODE I MODULE and a true signal is formed at the EOFI output from the DECODE I MODULE. Therefore, logic EOFI P 3 is true, causing the P 4 flip flop to be set to a 1 state and the P 3 flip flop to be reset to a 0 state at the following CLK pulse and PB 5 is 55 entered During PB 5, a true signal is now formed at the P 4 output The true signal at the P 4 output of the flip flop P 4 causes the L input of the RI register to be true and hence load the event occurrence value 13 from the event occurrence vector into the RI register Though the flow shows DECODE I MODULE being called during PB 5, the actual load into RI takes place during PB 6 60 The true signal at the P 4 output also causes the control input for register RI of the D 510 selection circuit and the control input for register DI of the DS 1 I selection circuit to receive true signals and hence couple the output of the registers RI and DI to the input of the ALU The true signal at the P 4 output also causes the compare input of the ALU to be activated and hence the first occurrence from the 65 114 1.570,344 114 event occurrence value contained in register RI is compared with the delimiter 10 contained in the DI register If the event occurrence value contained in register RI is Ä the delimiter contained in register DI, PB 7 is entered However, should the event occurrence vector contained in register RI be < the delimiter contained in Dl I the PIPE MODULE would have in register RI an event occurrence value 5 which is less than the delimiter and hence would fall into the next lower entry and, under this situation, PB 18 would be entered. Since the event occurrence value is 13 and the delimiter is 10, the content of register RI will be the larger, hence the ALU will form a true signal at the G output which, in turn, causes the OR gate 910 to form a true signal at the GE output A 10 true signal is now formed by the logic P 4 GE, causing the P 6 flip flop to be set to a I state and the P 4 flip flop to be reset to a 0 state at the following CLK pulse, thereby causing PB 7 of the PIPE MODULE flow to be entered. Since we are now dealing with the first entry in the request, or the first event occurrence vector, the bias is 0 and hence the BIAS register contains a 0 During 15 PB 7, the bias of 0 is subtracted from the event occurrence value contained in register RI and the result is stored back into register RI To this end, the true signal at the P 6 output of flip flop P 6 causes true signals at the control inputs of the DS 11 and D 510 selection circuits for registers BIAS and RI, respectively, thereby causing these registers to be coupled to the inputs of the ALU Additionally, the 20 true signal at the P 6 output causes the S input of the ALU to be true and the control input of the D 58 selection circuit for OP to be true Thus, the ALU subtracts the content 0 of the BIAS register from the content 13 of the RI register, forming a biased event occurrence value 13 The D 58 selection circuit couples the biased event occurrence value 13 to the input of the RI register Additionally, the logic 25 P 6.CLK is true, causing the L input of the RI register to be true and the biased event occurrence 13 is stored back into register RI. The true signal at the P 6 output causes the flip flop P 7 to be set to a I state and the flip flop P 6 to be reset to a 0 state at the following CLK pulse, causing PB 8 to be entered During PB 8, the biased event occurrence value 13 in register RI is 30 compared with the lower occurrence value limit 10 contained in register T To this end, the true signal at the P 7 output causes true signals at the control input of selection circuits DSIO and D 51 1 for the RI and T registers, respectively, thereby causing these registers to be coupled to the inputs of the ALU Additionally, the true signal at P 7 causes the C input of the ALU to be true The biased event 35 occurrence value in register RI is > the lower occurrence value limit in register T, causing the ALU to form a true signal at the G output which in turn causes the OR gate 910 to form a true signal at the GE output The logic P 7 GE now becomes true and at the following CLK pulse, the P 8 flip flop is set to a 1 state and the P 7 flip flop is reset to a 0 state, causing PB 9 to be entered Note that if the biased event 40 occurrence value in register RI were smaller, a true signal would have been formed at the L output of the ALU and PB 5 would be re-entered where the next to lower event occurrence value would be read.
During PB 9, the biased event occurrence value in register RI is compared with the delimiter, of the entry now under consideration, in register DI To this end, the 45 true signal at the P 8 output causes a true signal at the control input of registers D 510 and DSI 1 for the registers RI and DI, which, in turn, couples these registers to the input of the ALU The true signal at P 8 also causes the C input of the ALU to be true and hence the ALU compares the content of RI with that of DI The biased event occurrence value 13 in register RI is > the delimiter 10 in register DI and 50 hence a true signal is formed at the GE output of gate 910, causing PB 10 to be entered.
It should be noted that should the biased event occurrence value in register RI be < the delimiter of DI, the PIPE MODULE would be operating on a biased occurrence value which is below the delimiter for the entry under consideration 55 Therefore, according to the rules laid down above, the delimiter in register DI would be transferred to register RI for subsequent storage in the P/B MEMORY. Return now to the example During PB 9, the biased occurrence value in register RI is > the delimiter in register DI and hence a true ssgnal is formed at the P 8 output and the following CLK pulse causes the P 9 flip flop to be set to a 1 state 60 and the P 8 flip flop to be reset to a 0 state, thereby causing PB 10 to be entered.
Register RII was forced to store a value during PB 19 Register RI contains the biased event occurrence value 13 During PB 10, content of these registers are compared Since the biased event occurrence value 13 in register RI is the larger, PB 11, PB 15 and PB 16 is entered where biased occurrence value 13 is stored in the 65 I 1,570,344 116 1,570,344 116 P/B MEMORY along with a hit count of 1 In operation, the true signal at the P 9 output causes a true signal at the control input of the D 510 and DS 1 I selection circuits corresponding to registers RII and RI, causing the content of these registers to be coupled to the input of the ALU The true signal at the output P 9 also causes the C input of the ALU to be true, causing the ALU to compare the 5 content of registers RII and RI Since register RII contains a -1, it is the smaller, and a control signal is formed at the L output of the ALU.
A true signal is formed by the logic P 9 L CLK hence PB 11 is entered Also, the control input of the D 56 selection circuit corresponding to the switches 903 receives a control signal and the Ct input of the N counter receives a true signal 10 Thus, the D 56 selection circuit couples the signals representing a I from the switches 903 to the input of the N counter and the true signal at the L input causes the I to be stored into the N counter The true signal at the P 9 output also causes the Pl O flip flop to be set to a 1 state and the P 9 flip flop to be reset to a 0 state at i 5 the following CLK pulse, thereby causing PB 15 to be entered 15 During PB 15 and PB 16, the biased event occurrence value 13 in register RI and its hit count of 1 now in the N counter are stored into the P/B MEMORY To this end, the CLK pulse, in combination with the true signal at the P 9 output, causes the flip flop P 10 to be set to a 1 state and the P 9 flip flop to be reset to a 0 state, thereby causing PB 15 to be entered At this time, the GT flip flop is in a 0 20 state, causing a true signal at the GT output Hence, the logic P 10 GT is true, causing a true signal at the control input of the D 52 selection circuit, corresponding to the RI register This causes the D 52 selection circuit to couple the biased event occurrence value register RI to the P/B MEMORY The true signal at the P 10 output causes a true signal at the P 17 output of the input/output 25 control signal lines going to the P/B MEMORY This then causes the P/B MEMORY to store the biased event occurrence value contained in register RI into the location specified by the address contained in address counter M 2.
Additionally, when the CLK pulse occurs, the logic P 17 CLK is true, causing the Ct input of the address counter M 2 to receive a true signal and the address therein is 30 increased by one Thus, the M 2 address counter now stores the address 1 The true signal at the P 10 output at the following CLK pulse causes the flip flop Pl 1 to be set to a 1 state and flip flop P 10 to be reset to a 0 state, thereby causing PB 16 of the PIPE MODULE flow to be entered.
During P 1316, a true signal is formed at the YH I output The true signal at the 35 Pl 1 output causes the control input of the D 52 selection circuit corresponding to the N counter to receive a true signal and hence the D 52 selection circuit couples the output of the N counter to the input of the P/B MEMORY Additionally, the true signal at Pl 1 causes the input/output control signal line P 17 to receive a true signal and enable the write operation of the P/B MEMORY Thus, the hit count of 1 40 contained in the N counter is stored into the P/B MEMORY at the location immediately following the location of the biased event occurrence value.
Additionally, the true signal at P 18 output causes the Ct input of the M 2 address counter to again receive a true signal which, in turn, causes the address to be counted up to address 2 45 Following PB 16, PB 5 is again entered where the next event occurrence value 7 in the event occurrence vector is obtained by the DECODE I MODULE from MEMORY MODULE area 1 Referring to the input/output control signals, the logic P L GT CLK is now true, thereby causing a true signal at the P 13 output which in turn sets the DIGO one-shot multi-vibrator in the DECODE I MODULE 50 to a true state, calling the operation of the DECODE I MODULE, causing the event occurrence 7 to be read and stored into the RI register as discussed above.
PB 6 is now entered where the next event occurrence value 7 in register RI is compared with the delimiter 10 in register DI This time it is found that the event occurrence value 7 contained in register RI is < the delimiter 10 in register DI 55 Therefore, a true signal is formed at the L output of the ALU Returning to PB 6, a true signal is now formed at the P 4 output and the logic P 4 L is true Therefore, at the following CLK pulse, the flip flop P 5 is set to a 1 state and the flip flop P 4 is reset, causing PB 18 of the PIPE MODULE flow to be entered. During PB 18, the next lower delimiter 8 is read from MEMORY MODULE 60 area 2 and the modified pipe width value of 0 contained in PWC is subtracted therefrom to form a new lower event occurrence value limit in the T register To this end, the true condition of logic P 4 L formed during PB 6 causes the logic P 4.L CLK to be true and form a true signal at the PI 6 output The true signal at the P 16 output causes the D 2 GO one-shot multivibrator to be set true and the 65 DECODE II MODULE to be called again, causing it to read the next lower delimiter occurrence value 8 from the delimiter occurrence vector contained in MEMORY MODULE area 2 The logic PI 6 D 2 MEND is now true and the operation of the PIPE MODULE is suspended while the DECODE II MODULE decodes the next delimiter After the DECODE II MODULE provides the next 5 delimiter, the D 2 MEND output therefrom becomes false and hence the logic PI 6132 MEND goes false, enabling generalized clock generator 700 to again provide the CLK pulses The true signal at the P 5 output enables a true signal at the L input of register DI and hence the delimiter occurrence value 8 formed at the D 02 output of the DECODE II MODULE is coupled through the DI register As 10 before, the 0 value contained in register PWC is subtracted from the newly provided delimiter occurrence value 8, causing a lower event occurrence value limit of 8 which is stored into the lower limit register T During PB 6, the event occurrence value 7 in register RI is compared with the new delimiter in register DI. The event occurrence value 7 is still smaller and therefore PB 18 is again entered 15 where the next lower delimiter occurrence 5 is read out, decremented by the content 0 of register PWC to form a new lower event occurrence value limit of 5 in lower limit register T. Following PB 18, PB 6 is again entered where the event occurrence value 7 in register RI is compared against the new delimiter occurrence 5 in register DI This 20 time, the event occurrence value 7 is larger and the gate 910 forms a true signal at the GE output, causing the logic P 4 GE to be true thereby causing the P 6 flip flop to be set to a 1 state and PB 7 is entered. During PB 7, the bias value of 0 contained in the BIAS register is subtracted from the event occurrence value 7 in register RI and the resultant biased event 25 occurrence value 7 is stored back into the RI register Following PB 7, PB 8 is again entered. During PB 8, the biased event occurrence value 7 in register RI is compared against the lower event occurrence value limit 5 in register T The biased event occurrence value 7 is the larger and therefore PB 9 and PB 10 are reentered 30 During PB 10, the RII register still contains a -1 and therefore is the smaller, causing PB 11, PB 15 and PB 16 to again be entered where the N counter is stored with a I and the biased event occurrence value 7, with its hit count of 1, are stored from register RI and counter N into the next two subsequent memory locations in the P/B MEMORY 35 Following PB 16, PBS is again entered where the next event occurrence value 4 is provided by the DECODE I MODULE and stored in the RI register PB 6 is reentered where the new event occurrence value 4 in register RI is compared with the delimiter 5 in register DI The event occurrence value in register Rl is the smaller and therefore PB 18 is re-entered where the next lower delimiter 0 is stored 40 into the DI register The content 0 of PWC is subtracted from the delimiter 0 to form a new lower limit of 0 in lower limit register T At this point, the DI register and the T register each contain 0. PB 6 is now re-entered where the event occurrence value 4 in register RI is compared with the new delimiter 0 in register DI The event occurrence value 4 in 45 register RI is the larger, and therefore PB 7 is entered. During PB 7, the bias value 0 in register BIAS is subtracted from the event occurrence value 4 in register RI and the resultant biased event occurrence value 4 is stored back into the RI register. During PB 8, the biased event occurrence value 4 in register RI is compared so with the delimiter 0 in register DI and since the biased event occurrence value 4 is the larger, PB 10 is re-entered Again, the -1 value contained in register RII is smaller and therefore PB 11, PB 15 and PB 16 are re-entered where the biased event occurrence value 4 and its hit count of 1 in the RI register and the N counter are stored into the subsequent two available memory locations in the P/B MEMORY 55 The sequence of operation from PB 5 to PB 16 and to PB 23 or PB 21 should be noted If EOFI is true (last event occurrence read from MEMORY MODULE area 1) and the last entry (a -I to indicate end of entries) has been read from the P/B MEMORY and stored in register RII, a true signal will be formed at the SRII output of register RII which causes control to go from PB 5 through PB 20 to PB 23 60 If, on the other hand, EOFI is true and the last entry (-1) has not been read from P/B MEMORY and stored in register RII, a non-negative value will now be stored in register R 11, causing a false signal at the SRII (true signal at SRII) output of register R 11 Under these conditions, control goes from PB 5 through PB 20 to PB 21 (P 13) where the loop involving PB 20, PB 21 and PB 22 is entered Control stays in 65 117 1,570,344 117 PB 20, PB 21 and PB 22, causing event occurrences and hit counts to be read out of the P/B MEMORY until the last entry (-1) is reached at which time control goes from PB 20 to PB 23. Continuing with the example of operation, following PB 16, PB 5 of the PIPE MODULE flow is re-entered The last event occurrence has now been read from 5 the MEMORY MODULE area 1, hence the EOFI flip flop in the DECODE I MODULE is in a 1 state, causing a true signal at the EOFI output The last entry (-1) from the P/B MEMORY has been read and stored in register RII and hence a true signal exists at output SRII Flip flop Pl 1 is in a I state, causing a true signal at the Pl 1 output As a result, the logic EOFI Pl I GT SRII is true This causes the 10 flip flop P 16 to be set to a 1 state and flip flop Pl 1 is reset to a 0 state, thereby causing control to go through PB 20 to PB 23. During PB 23 and PB 24, a forced value of-I stored in the P/B 3 MEMORY at the end of the field of biased event occurrence values and hit values identifies the end of the event occurrence To this end, a true signal is formed at the P 16 output 15 of flip flop P 16, causing a true signal at the input of the D 52 selection circuit which causes the-I signal from the switches 901 to be coupled through to the input of the P/B MEMORY The true signal at P 16 also causes a true signal at the P 17 input/output control signal lines which, in turn, causes the P/B MEMORY to store the -1 value from the D 52 selection circuit The true signal at the PI 18 output in 20 turn causes a true signal at the Ct input of address counter M 2, causing it to count up by one address Additionally, the true signal at P 16 causes a true signal at the Ct input of the bias counter Significantly, this signal causes the BIAS counter to count up one bias value so that it now has a bias value of 1 Additionally, the logic P 16 CLK is true, causing a true signal at the output P 113, thereby causing the P/B 25 MEMORY to be switched. The logic P 16 ELK being true, causes the PFIRST flip flop to be reset to a 0 state This is important since the first pass through the PIPE MODULE, wherein the first event occurrence vector is biased and stored into the P/B MEMORY, has been completed 30 Following PB 24, the PLAST flip flop is in a 0 state since this is not the last pass through the PIPE MODULE Accordingly, the logic P 16 PLAST CLK becomes true, resetting the generalized clock generator 700 which, in turn, stops further pulses at CLK and CLK, causing the operation of the PIPE MODULE to exit or terminate 35 The PIPE MODULE has now completed its first pass for the first entry "S" and is now ready for its second pass for the second entry "I" The P/B MEMORY contains the following pairs of biased event occurrence values and hit values: 13-1, 7-1, 4-1 At the end in the P/B MEMORY there is stored a-I to identify the end of the field This then is the linear representation of the row S depicted in 40 Table 26 and in Table 27 at pass 1. Next, the PIPE MODULE enters pass 2 where the results depicted at pass 2 of Table 27 are formed. During pass 2, the I event occurrence value is processed With reference to Table 20, it will be seen that the I occurrence vector has event occurrence values 6 45 and 3 With reference to Table 21 and pass 2 of Table 27, it will be seen that the bias number is I and therefore event occurrence values 6 and 3 are decreased by I, resulting in biased occurrence values 5 and 2 Thus, during pass 2, biased occurrence values 5 and 2 with hit values of 1 are stored in proper numerical order among the results of pass 1 in the P/B MEMORY To this end, initially the MINI 50 COMPUTER causes the I event occurrence vector to be stored in MEMORY MODULE area 1 in hybrid coded form. The hybrid coded I event occurrence vector stored in MEMORY MODULE area 1 is as follows: 1 0000 1 1 O I = event occurrence vector 00000100 J 6, 3 55 MEMORY MODULE area 2 still contains the delimiter occurrence vector 15, 10, 8, 5 and 0 in hydrid coded form Additionally, the MINI COMPUTER stores the length 2 of the event occurrence vector into LNI of the IPRF. The MINI COMPUTER initiates the next pass by forming a true signal at the PIPGO output, enabling the generalized clock control 700 to again form CLK and 60 CLK pulses and thereby enalbling the operation of the PIPE MODULE as described hereinabove Additionally, the address counters Ml and M 2 are reset to 118 1,570 344 118 119 1,570,344 119 0 and register PSAV is again loaded with the length 4 of delimiter occurrence vector LN 2 from the IPRF Thus, the following all contain 0: Ml, M 2, M 3 The content of the following can be disregarded: OUT, MAX, N, DI, T, Rll, RI, CV, S. The content of the following are as follows: PSAV= 4: PW= 1; PWC= O; BIAS=l: and LNRQR= 3 5 During PB 2, the DECODE II MODULE again decodes and discards the end delimiter 15 of the event occurrence vector then decodes and provides the next to end delimiter 10 The ALU subtracts the 0 in register PWC from the delimiter 10 to determine the lowest or minimum event occurrence value 10 which is stored into the minimum event occurrence register T The delimiter 10 is stored in register DI and the delimiter 10 less the 0 in PWC, namely 10, is stored into the minimum event occurrence register T. During PB 3, the state of the PFIRST flip flop is again checked and this time is found to be 0 Hence, PB 4 is entered and PB 19 is skipped because this isnot the first pass through the PIPE MODULE. During PB 4, the largest stored biased event occurrence value and its hit count (i.e 13 -1) are read from the P/B MEMORY and stored into register RI 1 and counter N, respectively This operation is as follows: Referring to the input/output control signals, the logic P 1 WPFIRST is now true, causing a true signal at the PI 4 output The true signal at the P 14 output enables the P/B MEMORY to read the 20 biased event occurrence value 13 from address 0 specified by address counter Ml. Additionally, the logic P 1 PFIRST is true, causing the selection circuit D 57 to couple the 13 from the P/B MEMORY through to the input of register Ri I The logic P 14 CLK causes a true signal at the Ct input of address counter Ml which causes the address therein to be counted up to 1, thereby forming the address of the 25 corresponding hit count The logic CLK Pl then becomes true, causing a true signal at the L input of register RII, causing the register RII to store the biased event occurrence value 13 Additionally, the true signal at the Pl output of flip flop Pl causes the flip flop P 2 to be set to a 1 state and flip flop Pl to be reset to a 0 state at the occurrence of the CLK pulse 30 At this point, the logic P 2 PFIRST is true, again causing a true signal at the P 14 output of the input/output control signal lines The true signal at the P 14 output again causes the P/B MEMORY to read out the hit count of I from memory location 1 specified by address counter M l The logic P 9 is now true, causing the D 56 selection circuit to couple the output of the P/B MEMORY to the input of the 35 N counter Fig 35 shows a logic equation representing the logical gates for forming a signal at PN It will be noted that the logic P 2 PFIRST is now true, causing a true signal at the PN output The logic PN CLK causes a true signal at the Linput of the N counter, causing the N counter to store the hit count of I provided by the P/B MEMORY Additionally, the true condition of logic P 14 CLK causes a true signal 40 at the Ct input of the Ml address counter, causing it to count up to address 2, pointing at the biased occurrence value 7 contained in the P/B MEMORY. The true signal at P 2 causes the flip flop P 3 to be set to a I state and the flip flop P 2 to be reset to a 0 state, thereby causing PB 5 of the PIPE MODULE flow to be entered 45 During PB 5, the DECODE I MODULE provides the largest event occurrence value 6 from the event occurrence vector for I and it is stored into register RI as described above. PB 6 of the PIPE MODULE flow is then entered where the event occurrence value 6 stored in register RI is compared with the delimiter 10 stored in register DI 50 Since the event occurrence 6 in register RI is less than (<) the delimiter 10 in register DI, PB 18 is entered where the DECODE I MODULE is called, causing it to decode and provide the next lower delimiter 8 and the delimiter 8 ( 86) is stored back into register RI. PB 6 of the flow is re-entered where it is found that the event occurrence value 55 6 in register RI is again found less than the new delimiter 8 stored in register DI, causing PB 18 to be reentered During PB 18, the DECODE I MODULE provides the next lower delimiter 5 and the delimiter 5 ( 5 -0) is stored back into register RI. PB 6 of the flow is reentered where the event occurrence value 6 in register RI is compared with the new delimiter 5 in register DI and is found to be the larger 60 Accordingly, the ALU and gate 910 form a true signal at GE, causing the logic P 4.GE to be true causing the control counter 913 to set flip flop P 6 to a 1 state and reset flip flop P 4 to a 0 state Thus PB 7 is entered. During PB 7 of the flow, register BIAS contains a 1 Register RI contains the unbiased event occurrence value 6 and true signals are formed at the output P 6 65 1,570,344 120 This causes the DSIO and DSI I selection circuits to couple the RI and BIAS registers to the ALU, causing the bias value of I to be subtracted from the unbiased event occurrence 6 and the resultant biased event occurrence 5 to be stored back into the register RI. PB 8 of the PIPE MODULE flow is now entered where the biased event S occurrence value 5 contained in register RI is compared with the minimum occurrence value 8 in register T, and the biased event occurrence value 5 is the larger, therefore PB 9 is entered. During PB 9, the biased event occurrence value 5 in register RI is compared with the delimiter 5 in register DI and is found equal Therefore, PB 10 is entered 10 During PB 10, the biased event occurrence 13 from the previous pass read from the P/B MEMORY and stored in register RII is compared with the newly biased event occurrence value 5 in register RI The previous biased occurrence value 13 in register RII is the larger and therefore the ALU forms a true signal at the G output and PB 13 is entered To this end, the true signal at the P 9 output causes flip flop 15 P 10 to be set to a I state and the flip flop P 9 is reset to a 0 state. The true signal at the P 10 output causes the output P 17 to receive a true signal. The true signal at the P 17 output causes the P/B MEMORY to write the previous biased event occurrence value 13 from register RII into the memory location 0 specified by address counter M 2 and the address counter M 2 counts up one 20 address to address 1 The true signal at the P 10 output causes flip flop Pl 1 to be set to a I state and flip flop Pl O to be reset to a 0 state, again causing true signals at the P 17 output which, in turn, cause the hit count 1 in the N counter to be stored in the next P/B MEMORY address 1 Additionally, the address counter M 2 is counted up to address 2 25 The true signal at the G output of the ALU during PB 10 causes the logic P 9.G C X to be true and thereby set the GT flip flop to a 1 state, causing a true signal at the GT output Thus, at PB 14, the logic Pl I GT is true, causing the output P 14 to receive a true signal The true signal at PI 4 causes the P/B MEMORY to read out the next previous biased event occurrence value 7 and its hit count of 1 for 30 storage in register RII and counter N PB 10 is now re-entered. During PB 10, the previous biased event occurrence value 13 in register Rll is compared with the newly formed biased event occurrence value 7 in register RI and the first is the larger Therefore, PB 13 and PB 14 are re-entered where the previous biased event oc currence value 7 and its hit count I in register RH and 35 counter N are stored in the next two memory locations, 2 and 3, of the P/B MEMORY and the next previous biased event occurrence value 4 and its hit 1 are read out of the P/B MEMORY from the memory locations, 5 and 6, specified by address counter Ml for storage in register RII and counter N, respectively The address counter M 2 is appropriately incremented 40 PB 10 is re-entered where the previous biased event occurrence value 4 is again compared with the newly formed biased event occurrence value 5 in register RI. The previous biased event occurrence value 4 in register RII is now smaller and therefore PB 11, PB 15 and PB 16 are now entered where the newly formed biased event occurrence value 5 and its hit count of 1 are stored into the P/B MEMORY at 45 locations 4 and 5 specified by the address counter M 2 and the address counter M 2 is appropriately incremented. Following PB 16, PB 5 is re-entered where the next event occurrence value 3 for the event I is decoded and provided by the DECODE I MODULE and stored in register RI and the operation continues as discussed above until the MEMORY 50 MODULE area 2 of the P/B MEMORY contains the biased event occurrence values and hit counts depicted at pass 2 of Table 19 At the end of pass 2, the PIPE MODULE exits from PB 25 as discussed above after incrementing the BIAS register to a bias value of 2. The MINI COMPUTER then obtains the event occurrence vector for the 55 event T and stores it in MEMORY MODULE area 1 The hybrid coded event occurrence vector for the event T is as follows: 1 000 1 1 1 0 T-event occurrence vector 14,11,1 00100000 60 The PIPE MODULE is initialized with appropriate information as discussed above and is again called, causing it to go through the third pass, resulting in the 1,570,344 information depicted at pass 3 of Table 19. One of the things which the MINI COMPUTER does when initializing the PIPE MODULE for the last event occurrence value is to form a true signal at the PLAST-A output _causing the PLAST flip flop to be set to a I state Therefore, the logic P 16 PLAST CLK does not become true and hence, the flip flop PCE is not 5 reset to 0 As a result, the PIPE MODULE does not exit and PB 26 is entered following PB 25 Additionally, the logic P 16 PLAST causes a true signal at the P 15 output which resets the DECODE II MODULE by setting the flip flop D 2 FST in the DECODE II MODULE to a 1 Additionally, the true conditions of the logic P 16 PLAST CLK causes a true signal at the PI 6 output The true condition of this 10 logic causes the M l, M 2, M 3, S and MAX registers and counters to be reset to 0 and PB 27 is entered. The linearization process was completed during PB I through PB 25 The P/B MEMORY contains the biased event occurrence values and hit counts depicted at pass 3 of Table 27 The next step is to start at the rightmost or largest biased event 15 occurrence value and its hit count and pass a pipe across the data to obtain the maximum number of hits at each pipe center To this end, PB 26 through PB 48 is entered where the DECODE II MODULE is reset so that it starts redecoding the delimiter occurrence vector 15, 10, 8, 5, 0, starting at the largest one. The true condition of logic P 16 and the CLK P 16 PLAST causes the DSI 20 selection circuit to couple the -I signals at the output of switches 902 to the input of register OUT and causes the L input of register OUT to receive a true signal. This causes the register OUT to store the -1 signal The true condition of logic P 16 PLAST CLK causes a true signal at the PI 6 output which, in turn, calls the DECODE II MODULE, causing it to decode and discard the last delimiter 15 of 25 the delimiter occurrence vector The true signal at the P 16 output of the flip flop P 16 causes the P 16 flip flop to be reset to a 0 state and the logic P 17 PLAST sets the flip flop P 16 to a 1 state, thereby causing PB 28 to be entered During PB 28, the next to the last delimiter 10 of the delimiter occurrence vector is read by the DECODE II MODULE To this end, the logic P 17 CLK forms a true signal at the 30 P 16 output, setting the D 2 GO one-shot to a I state, calling the operation of the DECODE II MODULE, causing the delimiter 10 to be stored in the register DI. The true condition of logic P 17 causes a true signal at the P 14 output of the PIPE MODULE, causing the P/B MEMORY to read out the la I Rgest biased event occurrence value 13 and its hit count 1 (see Table 27) The logic Pl PFIRST is now 35 true, causing the D 57 selection circuit to couple the biased event occurrence value 13 to the input of register RI Additionally, the logic CLK P 17 becomes true, causing a true signal at the L input of register RII which in turn causes the biased event occurrence value 13 to be stored into register RII. The logic P 14 CLK causes a true signal at the Ct input of address counter M 1, 40 causing it to count up to address 1, which is the address of hit count 1 The true signal at the P 17 output of flip flop P 17 causes flip flop P 18 to be set to a 1 state and flip flop P 17 to be reset to 0 The true condition of output P 18 causes the output of the P/B MEMORY to be true, causing the P/B MEMORY to read out the hit count 1 Additionally, the logic CLK is true, causing the address counter Ml to count up 45 to address 3, thereby pointing at the next lower biased event occurrence value 12 in the P/B MEMORY The logic P 9 is now true, and therefore the selection circuit D 56 couples the hit count 1 from the P/B MEMORY to the input of the N counter. With reference to Fig 35, the logic P 18 is now true, causing a true signal at the PN output The logic PN CLK causes the N counter to be loaded with the hit count 1 50 from the P/B MEMORY. The CV counter keeps track of the pipe center The first pipe center will be the largest or rightmost biased event occurrence To this end, the true signal at P 17 causes the D 59 selection circuit to couple the largest biased event occurrenct 13 to the input of the CV counter Additionally, the logic P 17 CLK causes the biased 55 event occurrence 13 to be stored into the counter CV The true signal at the P 18 output causes the flip flop P 19 to be set to a 1 state and the flip flip P 18 is reset to a 0 state at the following CLK pulse, thereby causing PB 30 to be entered. During PB 30, the hit count 1 in the N counter is compared with the length of request 4 contained in the LNRQR register Since an inequality exists, PB 31 is 60 entered If, however, an equality exists, the content of counter N equals that of register LNRQR and PB 20 is entered where the biased event occurrence value in register RHI is transferred to register OUT and the hit count in counter N is transferred to register MAX. Continuing on with the example, the true signal at the P 19 output of flip flop 65 121 1,570,344 121 Pl 9 causes flip flop P 20 to be set to a I state and flip flop P 19 to be reset to a 0 state at the following CLK pulse. During PB 31, the largest biased event occurrence value 13 in register RHI is compared with the largest delimiter 10 in register D 1 The purpose of PB 31 is to determine whether the biased event occurrence value in register RI 1 is within the 5 event specified by the beginning delimiter in register DI If the biased event occurrence value in register RI is the larger or equal to the delimiter, then it is within the event and PB 32 is entered. In the example, the true signal at the P 20 output causes the DSIO and DSI 1 selection circuits to couple the content of register R 1 I and DI to the inputs of the 10 ALU and causes a true signal at the C input of the ALU The ALU in turn compares the values The biased event occurrence 13 in register RII is larger than the delimiter 10 in register DI, therefore a true signal is formed at the G output of the ALU Flip flop ET is in a 0 state, hence, the logic P 20 GET is true, causing the flip flop P 21 to be set to a I state and the flip flop P 20 is reset to a 0 state at the 15 following CLK pulse, thereby causing PB 32 to be entered. During PB 32, the pipe center value in counter CV is subtracted from the biased event occurrence value in register R 2 to form a value which, during PB 33 is compared with the pipe width to determine if the biased event occurrence value in register RI 1 is inside or outside of the permissible pipe width on the + side of the 20 pipe center To this end, the true signal at the P 21 output causes the DSIO and DS 11 selection circuits to couple the 13 and 13 in register RII and counter CV to the input of the ALU The true signal at P 21 causes a true signal at the S input of the ALU which in turn subtracts the 13 in counter CV from the 13 in register R 11, forming 0 output at OP The logic CLK P 21 causes the T register to load the 0 25 output at OP into the T register Thus the T register now contains a 0. The true signal at P 21 causes flip flop P 22 to be set to a I state and flip flop P 21 is reset to a 0 state at the following CLK pulse, causing PB 33 to be entered. The content of register T and PW are now compared to determine whether the biased event in register RI 1 is within or outside of the permissible pipe width on the 30 + side of the pipe center To this end, the true signal at P 22 causes the DSIO and DS 11 selection circuits to couple the 0 and I, respectively, in registers T and PW to the input of the ALU The true signal at P 22 causes a true signal at the C input of the ALU, causing the 0 in register T to be compared with the 1 in register PW The 0 of register T is the smaller and therefore PB 34 is entered 35 To this end the ALU forms a true signal at the L output which in turn causes the OR gate 911 to form a true signal at the LE output The logic P 22 LE is true, causing flip flop P 25 to be set to a 1 state and flip flop P 22 is reset to a 0 state at the following CLK pulse. During PB 34 the biased event occurrence value in register RH is checked to 40 make sure it is not outside of the pipe width on the left or side of pipe center To this end, the true signal at the P 25 output causes the D 510 and DSII selection circuits to couple the 13 stored in registers CV and RII to the input of the ALU. The ALU subtracts the biased event occurrence value 13 in register RII from the pipe center 13 in register CV and the result 0 is formed at the output OP The logic 45 CLK P 25 now is true, causing a true signal at the L input of register T, causing the 0 output at OP to be stored into the T register. The true signal at the P 25 output causes the flip flop P 26 to be set to a 1 state and flip flop P 25 to be reset to a 0 state at the following CLK pulse, causing PB 35 to so be entered The true signal at the P 26 output causes the D 510 and DS 1 I selection 50 circuits to couple the 0 and 1, respectively, in the T and PW registers to the input of the ALU Since the value 0 in register T is the lesser, the ALU forms a true signal at the L output The logic P 26 L is true, causing flip flop P 27 to be set to a 1 state and flip flop P 26 is reset to a 0 state at the following CLK pulse, and PB 36 is entered. During PB 36, the hit count in counter N is added to the content of the S 55 register The S register keeps a running tally of the total number of hits within the "total pipe width" Since the S register is initially 0, and the N counter initially contains a I (the hit count for biased event occurrence value 13), the result formed in register S during PB 36 is 1. Considering the actual operation, the true signal at P 27 causes the DSIO and 60 DS II selection circuits to couple the output of the N counter and the S register to the input of the ALU and causes a true signal at the A input The true signal at the A input causes the 0 and 1 in the S counter and N register to be added, and the result I is formed at the OP output The logic P 27 CLK is true, causing a true signal at the L input of the S register, causing the S register to store the 1 at OP The true 65 122 I 1,570,344 122 signal at the P 27 output causes the flip flop P 30 to be set to a I state and the P 27 flip flop to be reset to a 0 state at the following CLK pulse and PB 37 is entered. During PB 37, the next biased event occurrence value 12 and its hit count I are read from the P/B MEMORY from the addresses specified by the MI address counter To this end, the true signal at P 30 causes a true signal at the P 14 output of 5 the PIPE MODULE, causing the P/B MEMORY to read out the biased event 12. The logic PI 4 CLK is true, causing the Ml address counter to count up one address, pointing at the corresponding hit count of 1 Flip flop P 31 is set to a I state and flip flop P 30 is reset to a 0 state The true signal at the P 31 output again causes a true signal at the P 14 output and causes a true condition of logic PI 4 Ce K, thereby 10 causing the hit count of I to be read from the P/B MEMORY and the address counter MI is counted up one address Referring to the RII register and the N counter, the PI PFIRST logic causes the D 57 selection circuit to couple the biased event occurrence value 12 to the input of register RII and the true condition of logic CEMP 30 causes the biased event occurrence value 12 to be stored in register 15 R Il Similarly, the true condition at P 9 and, hence, the true condition of logic PN.CLK causes the hit count 1 formed at the OP output of the ALU to be stored into the N counter The true signal at the P 31 output of the flip flop P 31, causes the flip flop P 19 to be set to a 1 state and flip flop P 31 to be reset to a 0 state at the following CLK pulse, thereby causing PB 30 to be re-entered 20 During the subsequent pass through PB 30 and PB 31, the hit count 1 in counter N and the length of request 4 in register LNRQR are again compared and found not equal, causing PB 31 to be entered During PB 31, the biased event occurrence value 12 in register RII is compared with the next to last delimiter 10 in register DI and found to be larger Therefore, PB 32 and PB 33 are re-entered 25 During PB 32 and PB 33, the biased event occurrence value 12 in register RII is checked and found within the pipe width on the + or right side of the pipe center, as discussed above Therefore, PB 34 and PB 35 are re-entered where the biased event occurrence 12 in register RII is found to be within the pipe width on the or left side of the pipe center as discussed above, and therefore PB 36 is reentered 30 During PB 36, the hit count of I for the biased event occurrence value 12 is added to the 1 already in the S register and the resultant hit count of 2 is stored back into the S register. The next biased event occurrence value 7 and its hit count of 1 are read from the P/B MEMORY stored in register RII and the counter N and the Ml address 35 counter are appropriately incremented. PB 30 through PB 35 are now entered where the hit count in the N counter is compared with the length of request 4 in the LNRQR register and found to be the smaller Hence, PB 31 is re-entered where the biased event occurrence value 7 in register RII is compared with the delimiter 10 in register DI and the former 40 is found to be the smaller or outside of the event presently under consideration. Referring to the flow diagram, it will be seen that when this occurs, the PIPE MODULE branches from PB 31 to PB 39 To this end, the ALU forms a true signal at the L output, causing the logic P 20 L to become true and at the following CLK pulse, the flip flop P 28 is set to 1 and the flip flop P 27 is reset to 0 45 During PB 39, the content of register MAX is compared against the S register. The register MAX is a temporary storage register to hold the current maximum number of hits within a total pipe width in one entry The S register is keeping a running tally of the number of hits within a total pipe The reason for the comparison during PB 39 is to determine if the tally, being kept in the S register, has 50 become larger than the current maximum contained in register MAX If this occurs, then PB 41 is entered where the pipe center contained in counter CV is transferred to register OUT and the content of register S is transferred to register MAX To be explained in more detail, if the content of register MAX is the larger, PB 40 is entered directly where the pipe center in register CV is decremented 55 Returning to the example under consideration, register MAX was initially set to 0 and therefore its content is smaller than the hit count of 2 in the S register. Thus PB 41 is next entered To this end, the true signal at the output P 28 causes the D 510 and D 51 I selection circuit to couple registers MAX and S to the input of the ALU and the ALU in turn forms a true signal at the L output The true signal at the 60 output P 28 causes the DSI and D 55 selection circuit to couple the 13 and 2, respectively, from registers CV and S to the input of registers OUT and MAX The true condition of logic P 28 L causes a true signal at the L input of register OUT, causing the pipe center 13 in counter CV to be stored in register OUT The true condition of logic P 28 CLK causes the L input of register MAX to be true, thereby 6-5 I 1,570,344 123 123 causing register MAX to store the total hit count 2 in register S. Following PB 41, PB 40 is entered where the pipe center in counter CV is decreased by one to 12, thereby moving the pipe one place to the left or down To this end, the logic P 28 CLK applies a true signal at the Ct input of counter CV, causing counter CV to count from 13 down to 12. The true signal at the P 28 output of the flip flop 28 causes flip flop P 29 to be set to a I state and flip flop P 28 to be reset to a 0 state at the following CLK pulse, thereby causing PB 42 to be entered. During PB 42, a check is made to determine if the new pipe center in counter CV is above the lower delimiter contained in register DI and therefore still within 10 the entry under consideration If the pipe center stored in counter CV is equal to or larger, the pipe center in counter CV it is still within the entry and PB 43 is next entered However, if the pipe center in counter CV is less than the delimeter in register DI, then the pipe center has passed below the lower delimeter for the present entry and PB 44 is entered 15 Returning to the example, counter CV contains a 12 and register DI contains a Therefore, the pipe center in counter CV is the larger The true signal at the P 29 output causes the DSIO and DSI 1 selection circuits to couple the 12 from counter CV and 10 from register DI to the input of the ALU and a true signal is applied at the C input of the ALU Since the content of counter CV is the larger, a true signal 20 is formed at the G output, causing PB 43 to be entered Since we are about to test the new pipe center 12, the number of hit counts in register S is reset to 0 and the M I address counter is reset to the state of M 2 which contains the address of the first event occurrence value 13 in the entries under test (see Table 29) Considering the actual operation, the true signal at the G output of the ALU causes the OR gate 25 610 to form a true signal at the GE output This in turn causes the logic P 29 GE CLK to be true and clear or reset the S register to 0 The same logic causes a true signal at the L input to the Ml address counter and the address in counter M 2 is stored into Ml Thus, the S register now contains 0 and the address counter M l contains the address of the P/B MEMORY for the largest event occurrence 13 30 A true signal is now formed by the logic P 29 G, causing the flip flop P 30 to be set to a I state and flip flop P 29 is reset to a 0 state at the following CLK pulse, causing PB 37 to be entered. During PB 37 the largest event occurrence 13 and its hit count of 1 are read out by the P/B MEMORY and stored into register RII and counter N, respectively 35 During PB 30, it is found that the hit count in counter N is less than the length of request in register LNRQ and PB 31 is entered During PB 31, it is found that the event occurrence value 13 in register RII is greater than the delimiter 10 in register DI and PB 32 and PB 33 are entered During PB 32 and PB 33, it is found that the event occurrence value 13 is within the pipe width on the + side of the pipe center 40 12 in counter CV and, accordingly, PB 34 and 35 are entered During PB 34 and PB 35 it is found that the event occurrence value 13 in register RII is within the pipe width on the side of the pipe center 12 and, accordingly, PB 36 is entered During PB 36, the hit count contained in counter N is added to the 0 in register S so that the S register now contains a hit count of 1 PB 37 is then entered where the next lower 45 event occurrence value 12 and its hit count of 1 are read from the P/B MEMORY and stored into register RII and counter N and the address counter MI is appropriately incremented. PB 30 through PB 36 are re-entered with the same results found for the event occurrence 13 and thus during PB 136, the hit count of I contained in counter N is 50 added to the hit count of 1 already contained in the S register, causing a total hit count of 2 in the S counter PB 37 is again re-entered where the next lower event occurrence value 7 and its hit count of 1 are read from the P/B MEMORY and stored in register RII and counter N, and the M l address counter is appropriately incremented. PB 30 and PB 31 are then re-entered During PB 31 it is found that the event occurrence value 7 in register RII is smaller than the delimiter 10 in register DI, indicating that the event occurrence is not within the event presently under consideration as specified by the beginning delimiter 10 in register DI. Accordingly, PB 39 is entered as discussed above 60During PB 39, the maximum hit count of 2 in register MAX is compared with the total hit count of 2 in register S and found equal Accordingly, PB 40 is entered directly (bypassing PB 41) where the pipe center 12 in the CV counter is decreased to 11. It will now be noted that where, as just discussed, there is an equality between 65 124 1,570,344 124 12 1150,4515 the previous stored maximum hit count in register MAX and the accumulated hit count in register S, that the previous maximum hit count and the corresponding pipe center in registers MAX and OUT are retained Referring to Table 29, it is noted that the first pipe center with a hit count of 2 is 13 and it is the one which is used as the output from the PIPE MODULE 5 During PB 42, the comparison is made to determine if the pipe center in counter CV has passed below the beginning delimeter 10 in register DI Since the pipe center 11 in counter CV is the larger PB 43 is entered where the address counter M l is reset to the address of the largest event occurrence 13, which address is contained in register M 2 and the S register is reset to 0 10 Following PB 43, PB 37 is entered where the largest event occurrence 13 and its hit count of 1 are reread, stored in the register RII and counter N and the M 1 address counter appropriately incremented During PB 30, the hit count of I is not equal to the length of request of 3 contained in register LNRQR, accordingly, PB 31 is is entered During PB 31, the event occurrence value 13 is found greater than the 15 delimiter 10 Accordingly, PB 32 is entered. The operation during PB 32 through 35 should now be carefully considered. The event occurrence 13 in register RII is decreased by the pipe center of 11 contained in counter CV, and the difference of 2 is stored in the total register T. During PB 33, the difference of 2 contained in register T is compared with the pipe 20 width of I contained in register PW and the former is larger Accordingly, the ALU forms a true signal at the G output and PB 38 is entered directly from PB 33 The reason for this change in operation at this point is that the event occurrence value 13 is now outside of the pipe width for the pipe center 11 in counter CV and therefore the PIPE MODULE no longer needs to consider the event occurrence 25 value 13 Accordingly, the address of the next lower event occurrence value 12 is transferred to the M 2 address counter and this value is read from the P/B MEMORY, stored into the register RII and its associated hit count of I is stored in counter N To this end, the true signal at the P 22 output, in combination with the true signal at the G output of the ALU, causes the logic P 22 G CLK to be true, 30 causing a true signal at the L input of the address counter M 2 Accordingly, the address of the event occurrence value 12 is loaded into the M 2 address counter. The true signal at the P 22 output causes a true signal by the logic P 22 G and accordingly, the flip flop P 23 is set to a I state and the flip flop P 22 is reset to a 0 state, causing a true signal at the P 23 output The true signal at the P 23 output, in 35 turn, causes a true signal at the PI 4 output of the PIPE MODULE, causing the P/B MEMORY to read out the event occurrence value 12 specified by the address counter and stored in register RII and the Ml address counter is incremented by 1, pointing at the hit count corresponding to event occurrence value 12 The true signal at the P 23 output causes the flip flop P 24 to be set to a I state, and flip flop 40 P 23 to be reset to a 0 state at the following CLK pulse, again causing a true signal at the P 14 output of the PIPE MODULE and causing the P/B MEMORY to read out the hit count of 1 for storage in counter N and the Ml address counter to be incremented by one additional address, pointing at the event occurrence value 7 in the P/B MEMORY Following PB 38, Pb 30 is re-entered To this end, the true 45 signal at the P 24 output causes the input to the P 19 flip flop to be true and accordingly at the following pulse at CLK, flip flop P 19 is set to a 1 state and flip flop P 24 is reset to a 0 state, causing PB 30 to be re-entered, followed by PB 31. During PB 31, it is found that the event occurrence value 12 in register RI is greater than the delimiter 10 in register DI, accordingly PB 32 and 33 are entered 50 During PB 32 and PB 333, the comparison indicates that the event occurrence value 12 in register RII is within the pipe width on the + side of the pipe center in counter CV Accordingly, PB 34 is entered During PB 34 and PB 35, it is found that the event occurrence value 12 in register RII is within the pipe width on the side of the pipe center 11 in counter CV, accordingly PB 36 is entered, where the hit count 55 I in counter N is added to the 0 in register S, resulting in a total hit count of 1 in register S PB 37 is then entered where the next event occurrence value 7 and its hit count I are read out from P/B MEMORY stored in register RH and counters N and Ml appropriately incremented PB 30 and PB 31 are then re-entered where it is found that the event occurrence value 7 in register RII is less than the beginning 60 delimiter 10 in register DI Accordingly, PB 39 is directly entered where the maximum hit count 1 in register MAX is compared with the total hit count I in register S and found to be equal Accordingly, PB 40 is entered where the pipe center 11 in the CV counter is decreased by one to 10 During PB 42, the pipe center 10 in counter CV is compared with the lower delimiter 10 and is 65 1,570,344 125. found equal A false signal is thus formed at the G output of the ALU, causing the inverter 918 to form a true signal at the G output The signal at the U output indicates that the pipe center equal is less than the lower delimiter 10 for the present entry and hence the logic P 29 G is true, causing flip flop P 32 to be set to a I state, and flip flop P 29 to be reset to a 0 state at the 5 following CLK pulse Accordingly, PB 44 is entered where the event occurrence value 7 in register RII is compared with the beginning delimeter 10 in register D 1 To this end, the true signal at the P 32 output causes the D 510 and DSI 1 selection circuits to couple the output of registers RII and Dl to the input of the ALU The ALU detects that the biased event occurrence 10 value 7 in register RII is smaller and, accordingly, forms a true signal at the L output, thereby causing logic P 32 L to be true and flip flop P 34 is set to a I state and PB 32 is reset to a 0 state at the following CLK pulse, and PB 46 is thereby entered. It should be noted that during PB 44, should the event occurrence value in register R 11 have been found larger or equal to the beginning delimiter in register DI, PB 45 15 would have been entered where the next lower biased event occurrence value and its hit count would be read from the P/B MEMORY. Continuing with the example, during PB 46 the DECODE II MODULE decodes and provides the new lower delimiter 8 for storage in the DI register. Additionally, the pipe center in register OUT along with the corresponding 20 maximum hit count in register MAX, along with the sign represented by the SGN flip flop, are stored into the MEMORY MODULE at the address specified by the M 3 address counter Thus, the pipe center 13 and its corresponding hit count of 2 are stored into the MEMORY MODULE at the two consecutive memory locations specified by address counter M 3 This then specifies the center of the best pipe for 25 the event between delimiters 10 and 15. Consider now the operation during PB 46 The logic P 32 L CLK causes the output P 16 to receive a true signal, causing the DECODE II MODULE to decode and provide the next lower delimiter 5 for storage in the DI register The true signal at the P 34 output causes a true signal at the L input of the DI register, which in turn 30 causes the DI register to store the delimiter 5 The true signal at P 34 causes the D 53 selection circuit to couple the best pipe center of 13 from register OUT to the input of the MEMORY MODULE The true signal at the PI 9 output causes the MEMORY MODULE to write the best pipe center of 13 into the address of area 3 specified by the M 3 address counter The true signal at the output PI 10 also causes 35 the address counter M 3 to count its address by one so that it now specifies the address of the next available address in MEMORY MODULE area 3 The true signal at the P 34 output causes the flip flop P 35 to be set to a 1 state and flip flop P 34 to be reset to a 0 state at the following CLK pulse. The true signal at the P 35 output now causes new signals at the PI 9 and P 110 40 outputs Additionally, the true signal at P 35 causes the D 53 selection circuit to couple the SIGN output of the SGN flip flop and the output from register MAX to the input of MEMORY MODULE area 3 The true signal at PI 9 then causes the MEMORY MODULE to store the provided signals at the locations specified by the address counter M 3 Additionally, the signal at P 110 causes the address counter 45 M 3 to the counter up to the next available memory location. PB 47 is now entered The true signal at the P 35 output causes the D 51 selection circuit to couple the signals representative of a -1 from switches 902 to the input of register OUT, the true condition of logic P 35 CLK causes the register OUT to store the -1 sinals Additionally, the true condition of logic P 35 CLK 50 causes registers MAX and S to be cleared or reset to 0 Additionally, the new or next pipe center to be considered is that specified by the next event occurrence value stored in register RI Accordingly, the event occurrence value is stored from register RH to register S The true signals at P 32 and L cause the logic P 32 L CLK to be true, transferring the content of counter M l to M 2 The logic P 34 +P 35 is true 55 during the true signals at P 34 and P 35 As a result, the countdown input of counter M 2 receives, a true signal causing counter M 2 to count down 2 addresses. Considering the actual operation, the true signal at the P 35 output causes the D 59 selection circuit to couple the biased event occurrence value 7 in register RII to the input of counter CV and the true condition of logic P 35 CLK causes the L 60 input of counter CV to be true and hence the counter CV stores the biased event occurrence value 7 from register RII, thus creating the next pipe center for consideration. Following PB 47, PB 48 is entered and since the end of file for the delimiter field has not been reached by the DECODE II MODULE, the EOF 2 flip flop is in a 65 I 1,570,344 126 126 0 state Accordingly, PB 30 is re-entered. Thus, at this point, PIPE MODULE has completed the phase of operation depicted in Table 29 The true signal at the P 35 output causes the logic P 35 EOF 2 to be true, accordingly, flip flop P 19 is set to a 1 state and flip flop P 35 is reset to a O state at the following CLK pulse Hence, PB 30 is re-entered The operation of the 5 PIPE MODULE drops down to PB 31 where the event occurrence value 7 in register Rll is found to be less than the delimiter 8 in register DI Accordingly, PB 39, 40 and 42 are entered where the pipe center in counter CV is decreased from 7 to 6 and the new pipe center of 6 is found less than the delimeter of 8 in register DI Accordingly, PB 44 is entered During PB 44, the biased event occurrence value 10 7 in register RII is compared with the delimiter 8 and found to be smaller. Accordingly, PB 46 is re-entered. Note at this point that register OUT contains a -I and that register MAX contains a 0 Accordingly, during PB 46, a -1 and 0 is written out in the next two IS available memory locations in MEMORY MODULE area 3 Also, the DECODE 15 II MODULE reads out the next lower delimiter 5 for storage in register DI The operation depicted in Table 15 has now been completed and the -I stored in MEMORY MODULE area 3 indicates that there are no hits for the entry between delimiters 5 and 8. Register OUT is again stored with a -I and register MAX and the counter S 20 are again reset to 0 The biased event occurrence value 7 contained in register RII is again transferred as the pipe center to counter CV and 2 is subtracted from the address in address counter Ml and the result is stored in address counter M 2 The PIPE MODULE then goes through PB 48 back to PB 130. Finally, the PIPE MODULE reaches a point during PB 40 where the pipe 25 center stored in counter CV is reduced to O At this point the beginning delimiter in register DI is 0 and the pipe center in counter CV is 0 and, accordingly, are equal, causing PB 44 to be entered Register RI 1 contains the biased event occurrence -1, and since RIL < DI, control goes to PB 46. During PB 46, the best possible pipe center of 3 contained in register OUT and 30 its corresponding hit count of 2 are written out into MEMORY MODULE area 3 at the address specified by the M 3 address counter PB 47 and PB 48 are now entered and during PB 48, the EOF 2 flip flop is in a I staqte, indicating that the DECODE II MODULE has now completed all of the delimiter event occurrence vector Accordingly, the DECODE II MODULE forms a true signal at the EOF 2 35 output, causing the logic P 35 EOF 2 CLK to be true, resetting the generalized clock generator 700 so that it stops forming CLK and CLK pulses, thereby causing the PIPE MODULE to exit its operation. In summary, PB I through PB 20 are used to linearize from an information layer a request represented by an event occurrence vector A loop is formed around 40 PB 20, PB 21 and PB 22, which assures that a biased event occurrence and corresponding hit count are stored in the P/B MEMORY for each event occurrence value in the event occurence vectors under consideration PB 26 through PB 48 are used to determine the maximum number of hits within a total pipe width This is accomplished by sliding the pipe across the entry positions or 45 event times one by one, from right to left, until the maximum number of hits for a particular pipe center within each event is outputted or stored in the MEMORY MODULE area 3. XVI BRIGHTNESS MODULE A General description 50 The PIPE and BRIGHTNESS MODULES cooperate together to select the best response out of a data base to a -request As discussed above, the PIPE MODULE forms a set of pipe center signals each of which identifies the beginning delimiter event for a possible response to the request. The user programs the MINI COMPUTER to select from among the pipe 55 centers those pipe centers which are to be sent to the BRIGHTNESS MODULE. The user selects pipe centers based on some prearranged criteria, such as the number of hits within a "total pipe width" computed by the PIPE MODULE. Thus, for example, the user may decide that all pipe centers associated with hit counts above some preselected value will be sent to the BRIGHTNESS 60 MODULE Alternatively, the user may select all pipe centers whose hit counts bear a certain relation to the length of the request, i e, 90 %. The BRIGHTNESS MODULE receives the selected pipe centers from the 127 I 1,570,344 127 MINI COMPUTER and develops data about each pipe center that can be used to select the "best response" from among the entries for each pipe center The "best response" is used herein to indicate the closeness with which the events and their order in the response (from the data base) match that of the request. "Scatter value" (S) is one value used to determine the best response Scatter 5 value is a measure of the closeness with which events of the request match the events of the response By definition, a scatter value of unit 1 indicates a request that is contained exactly in the data base response A scatter value of 0 indicates that the request is not contained in the data base If some or all of the events of the request are scattered throughout the data base response, the scatter value is 10 somewhere between zero ( 0) and one ( 1), reflecting the amount of scatter or mismatch. Situations may arise where a second value will be helpful in determining the brightness value This value is called the "length factor" (L) and relates to the length of the request to the length of the response The L value also ranges between 15 0 and 1 The L value is desirable in locating misspelled words or where the response is desirably nearly an exact duplicate of the request Thus, responses which have a much larger or smaller number of events than the request would get a much lower L value than those which have nearly the same number of events. The following discussion is directed to the background for development of the 20 scatter value (S). Table 34 gives an example of a data base response word of "POISSON" and a request word of "PRISON" The scatter value is determined by positioning the request word "PRISON" so that all of its event (letters) are to the left of the events in the response word "POISSON" Then the number of events of displacement or 25 offset between each event in the request and the matching event in the response is determined and summed together Next, the request word "PRISON" is shifted one event position to the right with respect to "POISSON" and the offsets are again summed These steps are continued, right shifting the request as long as the sum of offsets is less than the previously determined sum Eventually the sum of offsets will 30 go through a minimum value and then start increasing To be explained in more detail, the sum of these offsets provides desirable variables for use in computing the scatter value S. Table 34 depicts the word "PRISON" shifted to the right, beginning with a 0 shift A 0 shift is where the last event (N) of the request word "PRISON" is 35 positioned immediately at the left of the first event (P) in the response "POISSON" This relation of the request to the response is desirable since it minimizes the displacement of the request The sum of the offsets for the 0 shift is designated at D, in Table 35 Thus, the offsets for the events POISSON are 6, 6, 6, 6, 7 and 7 It will immediately be noted that the event R of the request "PRISON" 40 does not have a corresponding event in the response "POISSON" Under this condition where the event in the request does not have a match in the response, that event is arbitrarily given an offset value equal to the length of the request This is important and will be explained subsequently Thus, the sum of offsets Do is equal to 38 45 Note carefully that if the request were aligned farther to the left, then for the 0 shift position the sum of offsets would be larger The sum of offsets would only remain the same regardless of shift position if none of the events in the request match an event in the response A minimum sum of offsets can be determined as so explained above by making a series of one event right shifts and computing the sum so of offsets for each position until the minimum sum of offset values is determined. Tables 34 and 35 depict shifts of 0, 3, 6, 7, and 9 The sum of offset values is identified in Table 35 for these shifts as D 0, D 3, D, D 7, D%, the number following the letter D indicating the number of event positions of shift Each shift beginning with D, pjroduces a sum of offsets value which is less than the sum of offsets for the 55 previous position until the minimum sum of offsets value, 8, is reached This condition is assured since the request is being shifted one position closer towards the match A shift of 6 produces the minimum sum of offset value 8 Subsequent right shifts after the minimum sum of offset values increases the sum of offset values Fig 42 A is a graph depicting a sum of offset values as a function of right 60 shifts The sum of offset values decreases so long as there are more request events to the left of their matching response events than there are on the right As soon as half or more of the request events either match or lie to the right of the position of their matching response events, the minimum sum of offset values occurs on the graph 65 128 1,570,344 128 129 1,570,344 129 From this information the following equation for scatter value has been derived: Equation 1 S = Do-Dmin Do where S=scatter value Do = sum of offsets first response event Dmin = smallest sum of offsets Where no match exists between an event in the request and an event in the response, use an offset equal to the length of request (LNRQ). The significance of assigning an offset value equal to the length of the request will now be explained Fig 42-B illustrates the offset for the R event as a function 10 of the number of shifts Since the request event R does not have a corresponding response event R, the offset value is constant at 6 which is the length or number of events in the request word "PRISON" However, with reference to Fig 42-C, it will be seen that offsets as a function of shifts for the events P, I, S, decrease from 6 to O and then start increasing following a shift of 6 Fig 42-D depicts the offset as 15 a function of shift for the events 0, N The offsets decrease to O and then start increasing at a shift of 7. Considering Equation I, if there is no match, D, will equal Dmin Therefore, the scatter will be 0 If, on the other hand, there is an exact match between the request and the response, the offset at Dmn will be 0 and therefore the scatter value will be 20 1 Thus, the above equation for scatter value produces the desired result of S= I for a complete match, and S= 0 for a complete mismatch. The implementation of the BRIGHTNESS MODULE for determining the scatter value requires minor rearrangement of the above formula This rearrangement can be best understood with reference to Table 36 Table 36 shows the 25 request word "PRISON" and the response "PROMISE" i e the word "COMPROMISE" Event times 11 through 20 are assigned to the events of the word "COMPROMISE" The offset for a particular request event is generally depicted by the following equations: Equation 2 Offset= BIAS + (t,-mini) 30 Equation 3 =(BIAS + t,)-min where: BIAS = minimum displacement from a request event to the corresponding response event: ti=event time in the response corresponding to the request event in question, 35 min =minimum event time in response. A value of importance in the implementation of the BRIGHTNESS MODULE is BIAS+t, Therefore, the following symbol is used to represent the equation: Equation 4 8 =BIAS+t, 40 6 is also referred to herein as the intermediate (IV) value An equation for scatter value S can then be written as follows: Equation 5 S= (d O +NM)-(dmn+NM) d O +NM 1,570,344 n Equation 6 Where; do = ( -min) and Equation 7 n den 2 ( 51-6 mid) i= intermediate value S for the i-th event time; 8 mid = intermediate value a closest to the mid a value; 5 n= no of request events that are present in response; min minimum event time (t) of response; NM _ (LNRQ-n) LNRQ (Note: this value adds in the length of the request for each request event for which there is not a corresponding event in the response). Equation 5 then reduces to 10 Equation 8 S = do-d,, d + NM The final scatter value equatio then becomes; Equation 9 X (ni-min) (si Omid) n 1(imin)+NM i 1 where: Si, Smid, NM and N are given under Equation 7. Applying the final equation 9 to the example of Table 36 the values depicted in 15 Table 37 can be derived Taking the request event P by way of example, the BIAS from the beginning of the response word "PROMISE" is 6 events The event time for the event "P" in the response "PROMISE" is 14 The & value is 6 + 14 = 20 Along the right hand side of Table 37 the a values are shown in ascending order of magnitude and this is the final order in which the 0 values are stored in the P/B 20 MEMORY. It should be noted from Table 37 that neither a t value nor a a value is shown for the request event "N" This is because the request event "N" does not have a corresponding event in the response word "COMPROMISE". A number of intermediate arrays of data are stored in P/B MEMORY but the 25 final intermediate array of data is depicted in Table 38 First, a pipe center (CP) value 18 is stored This is the largest event time within the entry in question Next is the "min" value which is defined above as the beginning (or smallest) event time in the response Next are stored the a values in ascending value order The & values shown are taken from the right hand side of Table 37 30 The d and dmjn values for the example of Table 38 are computed by the BRIGHTNESS MODULE as follows: M d O o ( 6-mmn) ( 18-14) + ( 20-14) + ( 20-14) + ( 22-14) + ( 22-14) =4 + 6 + 6 + 8 + 8 32 M d 5 nin= ( 8; rin) 5 118-201 + 120-201 + 120-201 + 122-201 + 22-201 = 2 + 0 + 0 + 2 + 2 where M=the number of events which are concurrently in the request and the 10 response. The BRIGHTNESS MODULE then stores a final output into MEMORY MODULE area 3 as depicted in Table 39 The first value stored is the beginning delimiter for the response entry in question In the example of Table 36, the delimiter would be located one event time to the left of the C in "COMPROMISE" and therefore is 10 Next in MEMORY MODULE area 3 is stored the number "n" 15 of matching events between the request and the response The number of matching events N is also referred to in connection with the BRIGHTNESS MODULE as the "# of hits" for brevity In this case, "PRISON" has six events whereas only five match and hence the # of hits is 5 Next in MEMORY MODULE area 3 dmin is stored The dmin value is 6 for the example of Table 36 Next do is stored As 20 computed above, do is 32 in the example of Table 36. The second factor mentioned above for determining the quality of response is the length factor L The length factor is concerned with the length of the request as compared to the length of the response One preferable use of the length factor would be at the word layer of the data base to catch misspelling and cull out words 25 which contain the request but which are obviously not the request desired For example, the length factor would help eliminate the return of the word "FUNDAMENTAL" as a response to the request "MEN" The preferred length factor equation was derived empirically from the following considerations: ( 1) a function is needed which has a near unity so long as the lengths of the response and 30 request are close; ( 2) after a definable difference in lengths, the curve should drop off sharply. The equation for the length factor L is as follows: Equation 11 L= 01 fx ( R A < LNRQ Where LNRQ = length of request 35 N = length of the response A = ILNRQ-NI = 0 63-the value which maintains a relatively flat curve for L until A = 1 At this point-(A = 1) L has a value of 0 75 This value could be adjusted depending upon user requirements 40 131 1,570,344 132 1,570,344 132 If L is taken into account, the quality of the response (B) is defined as Equation 12 B = L S where; S is scatter value, and L is length factor DSI through D 510 are data selectors (hereinafter referred to as selection circuits) and are represented by rectangular boxes with symbols on the inner sides 5 of the boxes corresponding to the inputs When a true signal is received at the input on the side of the selection circuit box, the correspondingly labeled data input circuit is coupled through to the output circuit of the selection circuit For example, the DSI selection circuit has control circuits along the side of the rectangular box labeled "Ml and T" and data inputs to the selection circuit DSI 10 are from the M l address counter and the T register A true signal at the M I input causes the output of the M l address counter to be coupled through to the output of the DSI selection circuit and a true signal at the P input circuit causes the DSI selection circuit to couple the T register through to the output. The BRIGHTNESS MODULE also contains the following flip flops: B FIRST, 15 BLAST, FLG, FF, Pl through P 36, GT, LT and ET Each of the flip flops is of the type identified above in the above TTL book The flip flops Pl through P 36 form a control counter 1113 which controls and sequences the operation of the BRIGHTNESS MODULE In addition, the BRIGHTNESS MODULE includes a generalized clock control 700 of the same type as that discussed above To be 20explained in more detail, the generalized clock control 700 has its operation controlled by clock suspension logic 1132. The BRIGHTNESS MODULE also includes an arithmetic unit (ALU) which is of the same type disclosed hereinabove with respect to the ENCODE MODULE. The ALU forms a true signal at the G and L outputs when the value represented by 25 the signal at the left data input is > and <, respectively, the value of the signal at the left hand data input The E output receives a true signal when the value of the two data inputs is equal An OR gate 1150 is connected to the G and E outputs of the ALU and forms a true signal when either the G or E output receives a true signal. An OR gate 1152 is connected to the L and E outputs of the ALU and forms a true 30 signal at the LE outputs whenever true signals are formed at the L or E outputs A signal inverter circuit 1140 inverts the signal at the L output and forms a true signal at the L output whenever a false signal is formed at the L output. Fig 46 depicts the control input/output lines and the information input/output for the BRIGHTNESS MODULE The arrows to the right depict outgoing signals, 35 whereas arrows to the left depict incoming signals The outgoing control input/output lines each has a symbol at the arrowhead identifying the line and, in parentheses following the symbol, additional symbols corresponding to the part of the rest of the system to which the control lines go Heavy lines depict multiple lines for carrying multiple bits of information in parallel throughout the 40 BRIGHTNESS MODULE schematic and block diagram. Also included are switches 1130, 1132 and 1134 The switches are conventional mechanical switches or other electronic circuits which form a continuous 8 bit binary coded signal at the output thereof Switches 1132 and 1134 form signals representing a -I whereas the switch 1130 forms signals representing the value 255 45 Logical equations are used throughout the BRIGHTNESS MODULE schematic and block diagram to represent gates which in turn control the operation of the indicated circuits. It should be noted that the outputs of all of the flip flops are not shown in the BRIGHTNESS MODULE but the same convention is used as described in the 50 section I F CONVENTIONS AND COMPONENTS USED IN THE FIGURES. C Detailed Description An abreviated discussion of the general operation of the BRIGHTNESS MODULE is now given with reference to the BRIGHTNESS MODULE flow diagram of Figs 47-50 The BRIGHTNESS MODULE flow diagram generally 55 depicts the brightness operation by a sequence of interconnected boxes labeled B 1 through B 58 Within the boxes are labels indicating actions within and between registers, flip flops, the DECODE I and II MODULES, the MEMORY MODULE and the P/B MEMORY Also associated with the B designations are the letters P followed by numbers These P numbers correspond to the flip flops of the control 60 counter in the BRIGHTNESS MODULE which are in a I state at the particular points in the operation. 132 1,570,344 132 133 1,570,344 133. Considering the operation, initially, the MINI COMPUTER under program control obtains the "S" request event occurrence vector and the corresponding delimiter occurrence vector from auxiliary memory, in seed form, and causes the OUTPUT MODULE to revolve them back to the input line in their isoentropicgrams The "S" event occurrence vector and delimiter occurrence vector 5 in hybrid code are stored in MEMORY MODULE areas l and 2, respectively, as depicted in Table 41 The MINI COMPUTER also loads the IPRF with the length of the request (LNRQ), the length of the first E O vector of the request (LNI), the length of the delimiter occurrence vector (LN 2), and sets the FIRST and LAST flip flops to states l and 0, respectively Also, the MINI COMPUTER selects pipe 10 center values from among those stored by the PIPE MODULE in the P/B MEMORY which are to be used during the brightness operation and stores those in P/B MEMORY area l These conditions are depicted by way of example in Part 1 of Table 41. During the subsequent operation, the DECODE II MODULE always reads 15 and decodes from the delimiter occurrence vector in MEMORY MODULE area 2, going from the largest (end) to the smallest delimiter Similarly, the DECODE I MODULE always reads and decodes from the event occurrence vector in MEMORY MODULE area l going from the beginning (largest) to last (smallest) event occurrence value Likewise, the P/B MEMORY is read going from the 20 beginning (largest) to the last (smallest) pipe center values. Bl of the BRIGHTNESS MODULE flow is now entered where the BRIGHTNESS MODULE is initialized, the Ml read address counter and the M 2 write address counter for the P/B MEMORY are reset to 0, the DECODE II MODULE provides a beginning delimiter from the delimiter vector into its register 25 D 02 The beginning delimiter is also an end delimiter. During B 2, a pipe center value is read from the P/B MEMORY area 1 using the M l address counter, the MIN register is set to 255 (a forced value equal to the largest possible pipe center value for an 8 bit word) and the T register is set to a minimum value of 0 During B 3, the beginning delimiter is stored in register DI and 30 the DECODE I MODULE provides an event occurrence value from the stored event occurrence vector If this is not the last end of the event occurrence vector file (EOFI 1), then B 7 is entered where the event time value is stored into RI register. During B 8 of the BRIGHTNESS MODULE flow, the pipe center value 35 contained in the RII register is checked against the beginning delimiter contained in the DI register to see if the pipe center lies between the beginning and end delimiters in registers DI and DII By virtue of the sequence of operation and the fact that the first pipe center is never greater than the ending delimiter of a delimiter occurrence vector, it is only necessary to check the pipe center against 40 the beginning delimiter in the DI register to see if the pipe center lies between the two delimiters If the pipe center does not lie between the two delimiters, it is < the beginning delimiter in the DI register Under these circumstances, B 14 through B 16 are entered If the pipe center does lie between the two delimiters, it is > the beginning delimiter in the DI register Then B 9-B 13 are entered 45 During B 14 and B 15, the DECODE I MODULE is adjusted so that it passes over each of the event occurrence values in the event occurrence vector for the entry designated by the beginning delimiter in the register DI However, the smallest event occurrence value is saved in register RI To this end, at B 14 the contents of the RI and DI registers are compared and if the event occurrence value 50 in register RI is > the beginning delimiter in register Di, then B 15 is entered where the DECODE I MODULE provides the next event occurrence value from the event occurrence vector This operation continues, reading the event occurrence values from largest to smallest value, until, during B 14, the event occurrence value in register RI is smaller than the beginning delimiter in register DI B 16 is then 55 entered.
During B 16, the next lower valued delimiter is provided by the DECODE II MODULE and stored in the DI register and the lower delimiter previously stored in register DI is transferred to register DII B 8 is then re-entered This operation continues through B 8, B 14, B 15 and B 16 until the delimiter in register DI is smaller 60 than the pipe center value in register RII When this occurs, the DECODE II MODULE has been adjusted so that the pipe center in register RII lies in the proper event as specified by the delimiter in register DI and B 9 is entered.
During B 9, the event occurrence value for the event occurrence vector contained in register RI is compared against the beginning delimiter in register DI 65 and if greater or equal to, there is an event occurrence value within the entry designated by the beginning delimiter in register DI B 10 through B 13 is then entered.
During B 10, the difference between the event occurrence value in register RI and the pipe center in RII is computed and the absolute value is stored in register 5 D During B 11, the difference value contained in the D register is compared with the content of the MIN register and if the former is smaller, then B 12 is entered where the difference value in register D is transferred to the MIN register, and the corresponding event occurrence value in register RI is transferred to the T register.
In this manner, the event occurrence value of the event occurrence vector with the 10 smallest displacement from the corresponding pipe center (in register R 11) is stored into the T register for future use It will be recognized that the smallest event occurrence value from all event occurrence vectors of a response that lies in one entry (i e, between two adjacent delimiters) is the “min” value of Equation 9 above 15 During B 13, the DECODE I MODULE provides the next smaller event occurrence value for storage in the RI register The loop through B 9-B 13 is then repeated until each event occurrence value in the entry lying above the delimiter in register DI has been processed and the one closest to the current pipe center has been found and stored in register T 20 When the event occurrence value is found and stored in register RI that is smaller than the beginning delimiter in register DI, the last event occurrence from the entry specified by the delimiter in register DI has been processed B 17 of the BRIGHTNESS MODULE flow is then entered.
During B 17 the register MIN is again initialized to the forced maximum value 25 of 255 and the pipe center in register RII is increased by one so that it is equal to the event occurrence value for the next higher event in the response The incremental value, to be explained in more detail, is stored in the P/B MEMORY and is subsequently read out for processing the next event occurrence vector in the response Incrementing of the pipe center is similar to prejudicing or moving the 30 request one event position to the right with respect to the response as discussed above.
During B 18, the BFIRST flop flop is checked The BFIRST flip flop is in a 1 state while processing the first event occurrence vector and is in a 0 state while processing the second and subsequent event occurrence vectors Thus, for the first 35 event occurrence vector; B 19 is next entered where the N and NP registers are reset to 0 and subsequently B 22 is entered.
If during B 18 the BFIRST flip flop is in a 0 state indicating that the second or subsequent event occurrence vector of the response is being processed, B 20 and B 21 are entered where the current minimum event occurrence value and hit count, 40 previously stored in P/B MEMORY, are read and stored into the MIN, N (and NP) registers, respectively Thus, the MIN register contains the minimum event occurrence value up to this point for one particular entry (corresponding to one delimiter value in register DI) and the N and NP registers contain the # of hits which is equal to the number of 8 values for such entry up to this point 45 B 22 of the BRIGHTNESS MODULE flow is now entered Hence, the minimum of the pipe center (RI 1) and ending delimiter -1 (i e, DII -1) is stored into the P/B MEMORY The purpose for the choice is that a pipe center (CP) value is being stored into the P/B MEMORY at the beginning of a list of information for one particular entry This value, as mentioned above, identifies the next higher 50 event occurrence value next to be processed for the next event occurrence vector of the response However, there is a limitation as to the possible event times and that limitation is the ending delimiter (DII -I) for the entry being processed Thus, the next to end delimiter DII -l is the highest event occurrence value that is obtainable within the entry and the highest event occurrence value stored during 55 B 22.
B 23 of the B RIGHTNESS MODULE is now entered during which the register T is checked to see if it contains an event occurrence value If an event occurrence value is contained in the T register ( 0), this indicates that there is an event occurrence value in the present entry designated by the beginning delimiter in DI 60 and B 26 and B 27 are entered.
During B 26, the new minimum event occurrence value in the T register is compared with the minimum event occurrence value read from P/B MEMORY from a previously processed event occurrence vector of the response If the new minimum event occurrence value (T) is smaller, then B 27 is entered where the new 65 134 1,570,344 134 minimum event occurrence value (T) is stored into the MIN register, this becoming “min” of Equations 2 and 3 above If the formerly stored min in register MIN is smaller or equal, then B 28 is entered directly, skipping B 27, thereby saving the min value in register MIN.
During B 28, the # of hits count in counter N corresponding to the total 5 number of matching events counter to this point is incremented by one Also, the length of request value, which corresponds to the BIAS above, is contained in the LNRQR register and is added to the new event occurrence value presently being processed in register T and the result is stored back into the T register Returning to the theory, it will be recognized that this corresponds to t, + BIAS = Si in the 10 scatter value (S) equation Thus, at this point, a new a value has been formed and stored into the T register and the total number of 8 values in the present entry has been counted by the N counter.
Following B 28, B 29 is entered If there are no event occurrence values in the present entry for the current event occurrence vector being processed (which lies 15 betwen DI and DII), the T register will not contain a new minimum event occurrence value (T = 0) at B 23, and B 24 and B 25 will then be entered following B 23 During B 24 and B 25, a previously stored 8 value, if one exists, for the entry specified by DI from previously processed event occurrence vectors, is read from the P/B MEMORY and stored in the T register The NP counter keeps track of the 20 number of a values stored in the P/B MEMORY for the entry being processed If there are 8 values, the NP counter will not be 0 and B 25 is entered following B 24 where a a value is read from the P/B MEMORY and stored into the T register and the NP counter is decremented by one Following B 25, B 29 is entered If the NP counter was 0, then B 29 would have been entered directly from B 24 25 During B 29 and B 30, the minimum event occurrence value for the present entry specified by DI is stored from the MIN register into the P/B MEMORY and the # of hits count is stored from the N counter into the P/B MEMORY Following B 30, B 31 of the BRIGHTNESS MODULE flow is entered.
During B 31, the NP counter is checked to see if is 0 If it is 0, then all of the 8 30 values for the present entry (specified by DI) and contained in the P/B MEMORY are in sorted order If, however, the NP counter is not 0, a 8 value remains in the P/B MEMORY to be sorted into increasing value order as discussed hereinabove.
To this end, during B 32, a 8 value is read out of the read area of the P/B MEMORY, stored into the RII register and the NP counter is decreased by one 35 During B 33, the magnitude of the 8 value in register RII is compared with that of the 8 value in the T register If the S value in T is larger, then B 34 is entered where the smaller 8 value in the RII register is stored into the P/B MEMORY If the & value in RII is larger, then B 35 is entered where the 8 value in the T register is stored in the P/B MEMORY and the larger 8 value in RII register is transferred to 40 the T register In this manner, the 8 values are stored in increasing value order in the write area of the P/B MEMORY.
After all the incremental values in the P/B MEMORY have been processed through B 31 through B 35, then the NP counter will be reduced to 0 and B 36 through B 38 will be entered 45 If during B 36 the FLG flip flop is in a I state, having been set there during B 28, a new 8 value will have been formed in the T register which is to be stored into the corresponding field of the P/B MEMORY To this end, B 37 is entered where the content of the T register is stored in the P/B MEMORY If the FLG flip flop is in a 0 state, B 37 is skipped as there is N S value to be stored During B 38, the next pipe 50 center value (CP) is read out of the P/B MEMORY into the RII register, the forced maximum value of 255 is stored in the MIN register and the T register is set to 0.
If during B 39 the pipe center value contained in RII register is > 0, it contains another pipe center value, (read during B 38 from P/B MEMORY) to be processed.
Accordingly, B 16 is re-entered where the DECODE I and II MODULES for the 55 event occurrence vector and delimiter occurrence vector are repositioned for the next entry which corresponds to the pipe center (CP) in the RII register.
This operation continues, returning to B 16, until after the last pipe center (CP) value has been read in from the P/B MEMORY The end of field value -I is then read from the P/B MEMORY and stored in RII register during B 38 Subsequently, 60 during B 39, RII contains the -1 (end of field) value and B 40 is entered.
During B 40, a -I is written into the P/B MEMORY at the end of the 8 field, thereby indicating the end of field for the corresponding entry Additionally, the length of request value contained in the LNRQR register is counted down one to reflect that one of the event occurrence vectors of the response has been 65 1,570,344 processed The LNRQR register now contains the BIAS value for the next event occurrence vector of the response.
During B 41, the BLAST flip flop is checked The BLAST flip flop indicates when the last event occurrence vector of the response has been processed If the BLAST flip flop is a 0, the last event occurrence vector has not been processed and 5 the BRIGHTNESS MODULE exits If the BLAST flip flop is a 1, the last event occurrence vector has been processed and B 42 is entered B 1-B 41 sets up phase I in which the S, and min are computed B 42-B 58 are entered only after all entries have been processed and it does the summing to compute Do and Dmin.
At this point, the P/B MEMORY contains an array of data such as that 10 depicted at Part 6 Table 41.
Consider now the second half of the operation of the BRIGHTNESS MODULE commencing with B 42 When the last event occurrence vector of the response has been processed and the BLAST flip flop is set to a 1 state by the MINI COMPUTER, B 42 is entered following B 41 During B 41, the switching flip flop 15 (SM) for the P/B MEMORY is toggled, thereby interchanging the read and write areas In other words, the B RIGHTNESS MODULE will now read from the area 2 in which it originally wrote and will write into area 1, from which it was originally reading Additionally, the Ml, M 2 and M 3 address counters are set to 0 and the DECODE II MODULE is reset so that is starts reading at the largeest or end 20 delimiter of the delimiter occurrence vector Also during B 42, the DECODE II MODULE reads and discards the end delimiter.
During B 43, the DECODE II MODULE reads the next to end delimiter which is the beginning delimiter of the last entry and the delimiter is stored into the DI register 25 B 44 through B 58 are then entered repeatedly until each of the CP values and their associated min values (# of hits) and a values have been processed More specifically, the purpose of B 44 through B 58 is to process each CP and associated field of values and store back in MEMORY MODULE area 3 the delimiter for the beginning of the corresponding entry followed by the number of matching events 30 between the request and the response (# of hits) and the dmin and do values which go into the computation of the scatter value (S).
* To this end, during B 44 the CP value for an entry is read from the P/B MEMORY and stored into the RII register During B 45, the content of the Rll register is checked to see if the end of field (-1) value has been reached If an end 35 of field value has been reached, the BRIGHTNESS MODULE exits If the end of field has not been reached, then B 46 is entered.
During B 46 and B 47, the DECODE II MODULE is adjusted so that it provides to the register DI the beginning delimiter for the CP value now stored in the RII register when this has been accomplished, the CP value in RII is > the 40 delimiter in the DI register and B 48 is entered During B 48 and B 49, the S and D 1 registers are set to 0, the P/B MEMORY reads out the minimum event time value (min) for storage in the MIN register and the P/B MEMORY reads out the # of hits value for storage in the N and NP counters.
During B 50, the binary value represented by the content of the NP register is 45 right shifted with respect to the corresponding ALU inputs by one binary bit, thereby dividing the number by two and the result is added to the address in the address counter Ml with the result being stored in the T register The right shift is done by a wiring connection betwen the NP register and D 510 selection circuit In this manner, the address of the midpoint of the & values in the P/B MEMORY is 50 computed and stored in the T register The S value specified by the address in the T register is now read out of the P/B MEMORY and stored in the RII register The S value in the RII register is the S mid value discussed above.
During B 51, a check is made to see if the P/B MEMORY contains any S values left for processing for the entry presently being processed If the NP counter is 0, 55 there are no S values left to be processed and B 55 is next entered If, however, the NP counter is not 0, then there is one of more remaining S values in the P/B MEMORY for the present entry and B 52 through B 54 are entered.
During B 52, the S value is read out of the P/B MEMORY and stored in the RI register and the NP counter is decreased by one to reflect that one of the & values 60 has been removed During B 53, the absolute value of the difference between the S mid value in RII and the S value in RI is formed and stored in the D register Also during B 53, the S register is used as an accumulator to store the source of the present and previous difference values stored into the D register Thus, the S register contains the sum of the difference values which corresponds to the dmn value 65 136 1,570,344 136 During B 54, the difference between each 8 value and the min value stored in the RI and MIN registers is taken and the result is stored in the D register The Do register is used as an accumulator for accumulating the present and previous difference values stored into the D register during B 54 Thus, the Do register contains the sum of 8 -min difference values which corresponds to the d value 5 The loop around B 51 through B 54 is repeated until all of the 8 values have been processed For each 8 value read from the P/B MEMORY, the NP counter is reduced by I and when 0, B 55 through B 58 are entered.
During B 55, the beginning delimiter of the current event stored in the DI register is first stored into the MEMORY MODULE area 3 During B 56, the # of 10 hits (number of matching request and response events) is stored from the N counter into the next location in MEMORY MODULE area 3 During B 57, the dmin value is stored from the S register into the next location of MEMORY MODULE area 3.
During B 58, the do value in register Do is stored into the next location of MEMORY MODULE area 3 15 Following B 58, B 44 is re-entered where the CP value, min value, # of hits value, and 8 values for the next entry are processed.
Finally, when the values for the last entry have been processed, a -1 end of field value is stored into the RII register during B 50 and is detected upon reentering B 45, causing the BRIGHTNESS MODULE to exit 20 After the last exit by the BRIGHTNESS MODULE, the MEMORY MODULE area 3 contains a field of information such as that shown in Part 7 of
Table 41 The field of information is then read by the MINI COMPUTER which computes the scatter value, using the formula discussed above.
The following discussion makes reference to the calls upon the DECODE I 25 and II MODULES wherein these modules decode a value from the hybrid code to absolute code Time is required for the module to perform its conversion.
Accordingly, the clock suspension logic 1132 forms a true signal at the CS input of the generalized clock control 700 whenever a call is made on the DECODE I and II MODULES and this causes a suspension of the CLK and CLK pulses and hence a 30 suspension of the BRIGHTNESS MODULE operation until the called module completes its decode operation The D 1 MEND and D 2 MEND outputs from the DECODE I and II MODULES are normally true and go false momentarily when the corresponding decode module finishes a decode operation Thus, when the DECODE I MODULE is called by the BRIGHTNESS MODULE, the 35 BRIGHTNESS MODULE output B 5 is true, causing a true condition of logic B 5.DI MEND and hence a true condition of the clock suspension logic 1132 This true condition causes the CS input to be true and hence the generalized clock control 700 terminates the CLK and CLK pulses.
When the DECODE I MODULE finishes its decode operation and has the 40 decoded value in register D Ol ready to be read, D 1 MEND becomes false, causing a false condition of logic B 5 DIMEND and hence of the clock suspension logic 1132 This causes the CLK and ELK pulses to resume and operation of the BRIGHTNESS MODULE resumes at P 6 of the control counter 1113.
The B 6 output of the BRIGHTNESS MODULE receives a true signal 45 whenever the DECODE II MODULE is called Thus the B 6 D 2 MEND logic performs a similar function for the DECODE II MODULE as logic B 5 DIMEND does for the DECODE I MODULE.
Consider now an actual operation of the BRIGHTNESS MODULE taking the example used in the PIPE MODULE The data base reply is the sentence “THIS IS 50 A TEST” depicted in the PIPE MODULE Table 1 The request is the word “SIT”.
Initially, the DPM INTERFACE MODULUS forms a control signal at the MINIT output and MINIT is fed to the general clock control circuit 700 which causes MR to become high thus resetting control counter 1113 to 0.
Table 41 depicts the data stored in the MEMORY MODULE, the P/B 55 MEMORY, and the IPRF during the operation of the BRIGHTNESS MODULE.
Part 1 of Table 41 depicts the information stored into the IPRF and MEMORY MODULE to process the event “S” from the request word “SIT” Thus, the MINI COMPUTER, under program control, initially stores 3, the number of events in the request (length of request) into the LNRQ of IPRF; stores 3, the number of 60 physical words in the event occurrence vector (length of event occurrence vector) into LNI of IPRF; and stores 4, the number of physical words needed to store the delimiter event occurrence vector (delimiter occurrence vector length) into LN 2 of IPRF All are depicted in Part I of Table 41 Also, the MINI COMPUTER initially stores the “S” event occurrence vector, in hybrid coded form, into MEMORY 65 1,570,344 137 137 MODULE area 1; stores the delimiter occurrence vector for the response “THIS IS A TEST” into MEMORY MODULE area 2; and stores the pipe center values (selected from among those provided by the PIPE MODULE) into P/B MEMORY area 1, all as depicted in Part I of Table 41 Additionally, as depicted in Part 1 of Table 41, the FIRST and LAST flip flops are set to 1 and 0, respectively The I state 5 of flip flop FIRST indicates that the first event occurrence vector of the request is being processed and the 0 state of flip flop LAST indicates that the last event occurrence vector is not being processed.
The DPM INTERFACE MODULE then forms a true signal at the BMGO output to the IN input to the generalized clock control 700, causing it to commence 10 applying CLK and CLK clock pulses Since all of the Pl flip flops in the control counter 1113 are initially in a 0 state, the first CLK pulse sets the Pl flip flop to a 1 state, causing Bl of the BRIGHTNESS MODULE flow to be entered. During B 1, a true signal is formed at the Pl output of the Pl flip flop,
causing the M l and M 2 P/B MEMORY read and write address counters to be reset to O and 15 causing true signals at the B 3 and B 4 outputs of the BRIGHTNESS MODULE (see Fig 50) The true signal at the B 3 and B 4 outputs causes the Dl FST flip flop in the DECODE I MODULE and the D 2 FST flip flop in the DECODE II MODULE to be set to 1, thereby indicating that the first call is about to occur on the corresponding decoders The true signal at the Pl output also causes the logic 20 PL.CLK to be true, thereby causing a true signal at the B 6 output of the BRIGHTNESS MODULE The true signal at the B 6 output causes the D 2 GO multi-vibrator to be set to a 1 state, thereby calling the operation of the DECODE II MODULE The DECODE II MODULE then reads i the beginning delimiter 15 for the word “TEST” from MEMORY MODULE area 2 (see Part 1 of Table 41) 25 into its register DOL Subsequently the true signal at P 2 stores the value from register DO 1 into DI The subsequent true signal at P 3 causes the value to be stored from DI into the DII register.
The true signal at the-PT output causes the P 2 flip flop to be set to a 1 state and the Pl flip flop is reset to a 0 state at the following CLK pulse, thereby causing B 2 30 of the flow to be entered.
The true signal at output Pl also causes a true signal at the B 1 output of the BRIGHTNESS MODULE which goes to various modules in the system thereby enabling values to the following modules: SWITCH MATRIX, DECODE I MODULE and DECODE II MODULE The true condition of the logic P 1 CLK 35 also causes a true signal at the B 2 output of the BRIGHTNESS MODULE, thereby applying a system clock to the modules in the system, causing the above values enabled by the output B 1 to be stored in the respective modules.
During B 2 of the flow, the true signal at the P 2 output of the P 2 flip flop causes true signals at the B 5 and B 6 outputs of the BRIGHTNESS MODULE which, in 40 turn, call the operation of the DECODE I MODULE The DECODE I MODULE is now operating on the entry “TEST” (see PIPE MODULE, Table 1) Calling of the DECODE I MODULE causes it to provide the largest event occurrence value 13 from the “S” E O vector stored in MEMORY MODULE area 1 (see Part 1 of Table 41) Additionally, the true signal at the P 2 output causes the D 57 selection 45 circuit to couple the signals representing the forced maximum value of 255 from the switches 1030 to the input of the MIN register The DSI selection circuit receives a true signal at the P 25 output, causing the output of the Ml register to be coupled to the address input of the P/B MEMORY The true signal at the B 7 output causes the P/B MEMORY to read out the first pipe center value 13 (see Part 50 1 of Table 41) using the address 0 in the read address counter Ml The true condition of logic P 2 CLK causes the RII register to store the pipe center value 13 from P/B MEMORY and causes the MIN register to store the forced maximum value 255 The true signal at the P 2 output also causes the P 3 flip flop to be set to a 1 state, and the P 2 flip flop to be reset to a 0 state at the following CLK pulse, 55 thereby causing B 3 of the flow to be entered.
During B 3 of the flow, true signals are formed at the P 3 and P 22 outputs of flip flops P 3 and P 22, respectively The logic P 3 CLK becomes true, thereby forming a true signal at the B 6 output of the BRIGHTNESS MODULE, causing the D 2 GO flip flop in the DECODE II MODULE to be set, thereby calling the operation of 60 the DECODE II MODULE, causing it to read out the beginning delimiter 10 for the response word “TEST” The logic P 4 causes the beginning delimiter 10 to be stored into the register DI.
The EOFI flip flop in the DECODE I MODULE is now in a 0 state because the end of the “S” E O vector field has not been reached The P 22 flip flop is in a 0 65
138 1,570,344 138 state and B 7 of the flow is entered The P 22 flip flop is in a 0 state and B 7 of the flow is entered Accordingly, the logic EOFI P 22 is true, causing the D 56 selection circuit to couple the event occurrence value 13 in register DOI of the DECODE I MODULE to the input of the RI register Additionally, the logic P 3 CLK causes the RI register to store the “S” E O value 13 from the DECODE I MODULE The 5 true signal at the P 3 output of flip flop P 3 also causes the P 4 flip flop to be set to a I state and the P 3 flip flop is reset to a 0 state at the following CLK pulse, thereby causing B 8 of the BRIGHTNESS MODULE flow to be entered.
During B 8 of the flow, a true signal is formed at the P 4 output of flip flop P 4.
The true signal at the P 4 output causes the D 59 and D 510 selection circuits to 10 couple the output of the Rll ( 13) and the DI ( 10) registers to the input of the ALU and also to form a true signal at the C (compare) input of the ALU In the preceding sentence and in the following discussion, a parentheses () following a register label indicates the value contained therein Thus register RII contains a value 13 and register DI contains a value 10 The ALU detects that the content of 15 register RII ( 13) is larger than that of register DI ( 10), and is therefore within the event designated by the delimiter in register DI Accordingly, the ALU forms a true signal at the output G, causing the OR gate 1150 to form a true signal at the GE output The true signal at the GE output causes the logic P 4 GE to be true and the following pulse at the CLK output causes the P 6 flip flop to be set to a 1 state, 20 and the P 5 flip flop to be reset to a 0 state, causing B 9 of the flow to be entered.
During B 9 of the flow, the true signal at the P 6 output causes the register RI ( 13) and the register DI ( 10) to be coupled through the D 59 and DSIO selection circuits to the two inputs of the ALU and causes a true signal at the C input of the ALU The ALU compares the two values and finds that the event time value 13 in 25 register RI is the larger and hence is within the entry designated by the delimiter 10 in register DI and forms a true signal at the G output, causing the OR gate 1150 to form a true signal at the GE output The logic P 6 GE then becomes true and the following pulse at the CLK output causes the P 7 flip flop to be set to a I state, and the flip flop P 6 to be reset to a 0 state 30 B 10 is now entered The true signal at the P 7 output causes the event time 13 in register RI to be coupled through the D 59 selection circuit to one input of the ALU and the pipe center value 13 in register RII to be coupled through the D 510 selection circuit to the other input of the ALU Additionally, the S (subtract) input of the ALU receives a true signal and the ALU subtracts the two values, resulting in 35 signals representing a 0 at the OP output The logic P 7 CLK becomes true, causing the D register to store the 0 output at OP It should be noted at this point that should the subtraction have resulted in a negative value, such as when the contents of RI is < that of RII, a true signal would be formed at the L output of the ALU during the subtraction process, causing the logic P 7 L to become true, thereby 40 causing the P 8 flip flop to be set to a 1 state and the P 7 flip flop to be reset to a 0 state What will happen under these circumstances is that the D 59 and D 510 selection circuits will recouple the RI and RII registers to the ALU again, but this time reversed, so that a positive number will result and the positive number will be restored into the D register In this manner, a positive or absolute value result 45 always ends up in the D register as indicated in B 10 of the flow. In the example where the difference is 0, a true signal is formed at the L output of the signal inverter 1140 and accordingly, the logic P 7 L is true, causing the P 9 flip flop to be set to a 1 state. Note carefully now what has happened during B 10 The difference between so the pipe center 13 and the first event occurrence value 13 has been computed and found to be 0 Therefore, the displacement therebetween is the smallest possible, namely, 0 The event occurrence value 13 is then the value min for the entry "TEST" designated by the delimiter 10 in register DI. B 11 is now entered where the true signal at the P 9 output causes the D 59 and 55 D 510 selection circuits to couple the difference of 0 from the D register and the forced maximum value 255 from the MIN register to the two inputs of the ALU and a true signal at the C input causes the ALU to compare the two values Since the displacement value 0 in the D register is the smaller, a true signal is formed at the L output The true signal at P 9 causes the D 57 selection circuit to couple the output 60 of the D register to the input of the MIN register and the logic P 9 L is true, causing the MIN register to store the 0 value Additionally, the true signal at P 9 causes the D 58 selection circuit to couple the output of register RI to the input of the temporary storage register, T, and the logic P 9 L CLK causes the T register to store the minimum event occurrence value 13 from register RI 65 1,570,344 139 139 B 13 of the flow is now entered The true signal at the P 9 output causes a true signal at the B 5 output of the BRIGHTNESS MODULE, thereby setting the DIGO multi-vibrator in the DECODE I MODULE, calling the operation of the DECODE I MODULE The DECODE I MODULE than decodes the next event occurrence value 7 from the "S" E O vector (see Part 1 of Table 41) and stored it 5 into its DOI register Also, the EOFI flip flop is in a 0 state Accordingly, the D 56 selection circuit couples the output of register DOI of the DECODE I MODULE to the input of the RI register and the logic P 6 FLG causes the event occurrence value 7 to be stored into the RI register The true signal at the P 9 output causes the P 6 flip flop to be set to a 1 state and the P 9 flip flop to be reset to a 0 state at the 10 following CLK pulse, thereby causing B 9 of the flow to be reentered. With reference to the PIPE MODULE, Table 1, event occurrence value 7 of the "S" E O vector is in the entry "IS", not the entry "TEST" specified by the delimiter 10 During B 9, the RI and DI registers are again coupled to the input of the ALU and this time it is found that the event occurrence value 7 contained in 15 register RI is smaller than the delimiter 10 in register DI and is therefore, not in the same entry designated by DI Accordingly, a true signal is formed at the L output of the ALU and B 17 of the flow is entered The true signal at the P 6 output causes the forced maximum value 255 from the switches 1030 to be coupled to the input of the MIN register The logic P 6 E CE is true, thereby causing the MIN register to 20 again store the value 255 Additionally, the logic P 6 L CEK is true, causing the initial pipe center value of 13 to be counted up to a CP value of 14 in register RII. The true condition of logic P 6 L causes the P 10 flip flop to be set to a I state and the P 6 flip flop to be reset to a 0 state at the following CLK pulse thereby causing B 18 to be entered The "S" E O vector is the first to be processed and the 25 BFIRST flip flop is in a 1 state Accordingly, B 19 of the flow is entered. During B 19, the logic P 10 BFIRST is true, causing the N and NP counters to be cleared to Q B 22 of the flow is then entered. During B 22 is the only time that the content of register DII is used Also DII is clocked down by one during pulse P 4 Thus when the compare is done in pulse P 10, 30 it is a compare of RII and DII -1. The true signal at the P 10 output causes the D 59 and D 510 selection circuits to couple the center pipe value 14 in register RII and the upper delimiter value 14 in register DII to the input of the ALU and a true signal is formed at the C input The ALU compares the two values and determines that center pipe value 14 in register 35 RII is equal and forms a true signal at the E output This in turn causes the gate 1152 to form a true signal at the LE output, causing the logic P 10 LE to be true. Responsive thereto, the D 54 selection circuit couples the output of the RII register to the input of the P/B MEMORY Additionally, the true signal at P 10 causes a true signal at the B 8 output of the BRIGHTNESS MODULE, causing the P/B 40 MEMORY to write the center pipe value 14 from the D 54 selection circuit into its memory location, 0, specified by the M 2 write address counter The logic B 8 CLK increments the address in register M 2 up one address to address 1 The true condition of the P 10 flip flop causes the logic P 10 BFIRST to be true and the following CLK pulse sets the P 13 flip flop to a 1 state and resets the Pl O flip flop to 45 a 0 state, thereby causing B 23 of the flow to be entered. During B 23, the content of the T register is checked to see if it is 0 It is not 0, since a minimum event occurrence value of 13 was stored there during B 12 and accordingly a true signal is formed at the To output of the T register This causes the logic P 13 T 17 to be true and causes the FF flip flop to be set to a I state B 26 of the 50 flow is now entered. During B 26, a true signal is formed at the P 13 output of flip flop P 13, causing the D 59 and D Si O selection circuits to couple the T and MIN registers through the D 59 and D 510 selection circuits to the ALU and causes a true signal at the C input of the ALU The T register now contains the minimum event occurrence value 13 55 which is < the value 255 in register MIN Accordingly, the ALU forms a true signal at the L output The true signal at P 13 causes the D 57 selection circuit to couple the minimum event occurrence value 13 from register T to the input of register MIN and the logic P 13 L CLK becomes true, causing the register MI Nto store the event occurrence value 13 B 28 of the flow is now entered 60 During B 28, the true condition of logic B 13 To also causes the N counter to count up I state to reflect the fact that one 8 value is about to be formed for the "S" E.O vector being processed The N counter was set to 0 during B 19, accordingly the N counter is now in state I, indicating there has been one hit or entry Also, the NP counter is now in state 0 and a true signal is formed at the N Po output The logic 65 1,570,344 P 137 Tl is true, causing the FLG flip flop to be set to a I state Ihe F F flip flop is now true, accordingly the logic P 13 FF becomes true and the following CLK pulse sets the P 14 flip flop to a 1 state and resets the P 13 flip flop to a 0 state. The true signal at the P 14 output of flip flop P 14 causes the D 59 and DSIO selection circuits to couple the content of the T and LNRQR registers to the input 5 of the ALU and causes a true signal at the A input of the ALU The T register now contains the minimum event occurrence value 13 and the LNRQR register contains the actual length of the request, 3 This value 3 is the BIAS value discussed above Accordingly, the sum at the output of OP is now 16 ( 13 + 3) The true signal at P 14 causes the D 58 selection circuit to couple the value 16 at OP to the input of 10 the T register and the logic P 14 CLK subsequently becomes true, causing the value 16 to be stored into the T register The true signal at P 14 additionally causes the flip flop P 15 to be set to a I state and the flip flop P 14 to be reset to a 0 state. Accordingly, B 29 is entered. During B 29, the minimum occurrence value for the event corresponding to the 15 CP value 14 written during B 22 is now contained in register MIN and is written into the P/B MEMORY To this end, the true signal at PI 5 causes a true signal at the B 8 output circuit of the BRIGHTNESS MODULE causing a write operation in the P/B MEMORY area 2 at the location specified by the write address in counter M 2. The true signal at the P 15 output causes the D 54 selection circuit to couple the 20 minimum event occurrence value 13 (min) from the MIN register to the input of the P/B MEMORY allowing it to be written at address 1 following the CP value written during B 22 Additionally, the true condition of logic B 8 CLK causes the M 2 address counter to count up by one address to address 2 The content of addresses 0 and 1 of P/B MEMORY area 2 is depicted in Part 2 of Table 41 25 The true signal at the P 15 output causes the P 15 flip flop to be reset to a 0 state and the P 16 flip flop to be set to a I state at the following CLK pulse, thereby causing B 30 of the flow to be entered. During B 30, the # of hits stored in address counter N is stored into the P/B MEMORY at the next subsequent location following the min value To this end, 30 the true signal at P 16 causes the D 54 selection circuit to couple the # of hits value from the N counter to the input of the P/B MEMORY and causes the B 8 output of the BRIGHTNESS MODULE to receive a true signal Additionally, logic B 8 CLK is again true As a result, the P/B MEMORY stores the # of hits value 1 from counter N at address 2 (as specified by the M 2 address counter) and the address 35 counter M 2 is counted up by one so that it now contains address 3. Addresses 0-2 of the P/B MEMORY area 1 now contain the values depicted in Part 2 of Table 41 During B 31, the NP counter is at 0, causing a true signal at the N Po output of the NP counter Accordingly, the logic P 16 NP, is true, causing the flip flop P 19 to be set to a 1 state and the flip flop P 16 is reset to a 0 state at the 40 following CLK pulse, causing B 36 of the flow to be entered. During B 36, the FLG flip flop is in a 1 state, having been set there during B 28, and accordingly B 37 is now entered During B 37, the logic P 19 FLG is true, causing the D 54 selection circuit to couple the 8 value contained in the T register to the input of the P/B MEMORY causing a true signal at the B 8 output of the 45 BRIGHTNESS MODULE This causes the P/B MEMORY to write the 8 value 16 at address 3 as specified by the address counter M 2 The true conditin of logic B 8.CLK again causes the M 2 address counter to count up one address to address 4 Thus addresses 0 through 3 of the P/B MEMORY area 1 contain the values so indicated in Part 2 of Table 41 50 During B 38, true signals are formed at P 19 and P 26 outputs of the P 19 and P 26 flip flops Accordingly, the true signal at the P 26 output causes the DSI selection circuit to couple the address 1 contained in the M l address counter to the input of the P/B MEMORY and causes the B 7 output of the BRIGHTNESS MODULE to receive a true signal As a result, the P/B MEMORY reads out the second pipe 55 center value 6, contained at address I of P/B MEMORY area 1 (see Part I of Table 41) The true condition of logic P 19 CLK causes the RII register to store the second pipe center value 6 read from the P/B MEMORY With reference to the PIPE MODULE, Table 1, it will be seen that the pipe center value 6 corresponds to the entry "IS" Additionally, the logic B 7 P 26 CLK becomes true, causing the Ml 60 address counter to count up to address 2 The true signal at the P 19 output also causes the D 57 selection circuit to couple the signals representing the value 255 from the switches 1030 to the input of the MIN register The true condition of logic P 19 CLK causes the value 255 to be stored into the MIN register and causes the T register to be reset to 0 The true signal at the P 19 output of the P 19 flip flop causes 65 141 141 1,570,344 the flip flop P 20 to be set to a I state and the P 19 flip flop to be reset to a 0 state at the following CLK pulse, thereby causing B 39 of the flow to be entered. During B 39, a true signal is formed at the P 20 output and register RII now contains the new pipe center value 6 and hence does not contain a minus quantity. S SRII is the sign bit of the RII register (SRII = OXXXXXXX- positive # or 0, 5 SRII = l XXXXXX-X negative #) Accordingly a true signal is formed at the SRII output of the RII register, causing the logic P 20 SRII to be true and at the following CLK pulse, flip flop P 4 is set to a 1 state and flip flop P 20 is reset to a 0 state. During B 16, the true condition of the P 20 output of flip flop P 20 causes the DII register to store, as the new upper delimiter, the lower delimiter 10 from the 10 lower delimiter register DI Additionally, the true consition of the logic P 20 SRT CLK causes the output B 6 of the BRIGHTNESS MODULE to become true, set D 2 GO to 1, and call the operation of the DECODE II MODULE, thereby causing the next lower delimiter value 8 (see Part 1 of Table 41) to be provided to the lower delimiter register DI The logic B 6 D 2 MEND is true in the clock 15 suspension logic 1132 and the operation of the BRIGHTNESS MODULE is suspended until the DECODE It MODULE is finished and reactivates the B RIGHTNESS MODULE by forming a false signal at the D 2 MEND output The logic P 20 SRII is now true and flip flop P 4 is set to 1. The logic P 4 causes the register DI to store the new lower delimiter value 8 20 Following B 16, the logic P 20 SRII causes the B RIGHTNESS MODULE flow to go from B 16 back to B 8 The lower delimiter 8 in register DI is for the entry "A" (see Table 1) Accordingly, the "S" E O vector does not contain any event occurrence values for this entry. During B 8 of the flow, the true signal is again formed at the P 4 output of the P 4 25 flip flop Accordingly, as described above, the ALU compares the new pipe center value 6 contained in the RII register with the new lower delimiter value 8 contained in the DI register and finds the former to be smaller This indicates that pipe center in register RII is for a lower entry than the entry "A" specified by the lower delimiter 8 Accordingly, the next lower delimiter needs to be read by the 30 DECODE II MODULE To this end, B 14 and B 16 are reentered where the lower delimiter 8 in register DI is transferred to the upper delimiter register DII and the DECODE II MODULE provides the next lower delimiter 5 (see Part 2 of Table 41) The lower delimiter 5 is for the entry "IS" (see PIPE MODULE Table 1). Following B 16, B 8 of the flow is reentered where the pipe center value 6 in 35 register RII is again compared with the new lower delimiter 5 in register DI This time the pipe center 6 is found to be the larger, indicating it lies in the entry specified by register DI and accordingly B 9 is entered. During B 9, the event time 7 from the "S" E O vector (which is stored in register RI during the preceding pass through B 13) is compared with the lower 40 delimiter 5 in register DI and the former is found to be larger Accordingly, B 10 of the ENCODE MODULE flow is entered During B 10, the ALU computes the absolute value of the difference between the event occurrence value 7 in register RI and the pipe center 6 contained in register RIL The absolute value of the difference is 1 and is stored in the D register Note carefully that this difference 45 value is for the entry "IS", whereas the difference previously formed during B 10 is for the entry "TEST". During B 11, the difference stored in the D register is compared with the content of register MIN Register MIN contains the forced maximum value of 255. Accordingly, the difference value 1 in the D register is the smaller, causing B 12 to 50 be entered. During B 12, the new difference value 1 is transferred from register D to register MIN and the new event occurrence value 7 is transferred from the RI register to the T register as a potential min value. During B 13, the DECODE I MODULE is again called, causing the next lower 55 event occurrence value 4 from the "S" E O vector to be decoded and stored into the RI register (see Part 1 of Table 41) This is not the end of the "S" E O vector. Accordingly, the EO Fl flip flop is in a 0 state. During B 9, the event occurrence value 4 in register RI is for the entry "THIS" (see PIPE MODULE Table I) and therefore is found to be smaller than the 60 beginning delimiter value 5 in register DI Accordingly, B 17 is entered During B 17, the maximum forced value of 255 is stored into register MIN and the pipe center value 6 in register RII is counted up by 1, forming a CP value of 7. During B 18, the flip flop BFIRST is in a I state since the BRIGHTNESS MODULE is still operating on the first or "S" E O vector Accordingly, B 19 is 65 142 1,570,344 142 entered where the N and NP counters are reset to 0 During B 22, the test CP value 7 is written into the P/B MEMORY at address 4 as specified by the address counter M 2 and the M 2 address counter is counted up to address 5 The content of addresses 0 through 4 of the P/B MEMORY area 2 is depicted in Part 2 of Table 41. During B 23, the T register does not contain a 0 but contains the minimum 5 event occurrence value 7 Therefore B 26 is entered During B 26, the minimum event occurrence value 7 in register T is compared with the forced maximum value 255 in register MIN and is found to be smaller Accordingly, B 27 is entered where the minimum event occurrence value 7 in register T is transferred to register MIN. During B 28, the counter N is increased by I to reflect that a new 8 value is about to 10 be formed Additionally, the minimum event occurrence value 7 in register T is added to the length of request value 3 contained in the LNRQR register, forming a 8 value of 10, which is stored back into the T register Additionally, the FLG flip flop is set to a 1 state. During the subsequent B 29 and B 30, the minimum event occurrence value 7 in 15 register MIN is written into addressd 5 of P/B MEMORY area 1 (see Part 2, Table 41) and # of hits value 1 in counter N is stored into address 6 of P/B MEMORY area 1 (see Part 2, Table 41) Additionally, the address counter M 2 is counted up one for each write so that it now contains address 7. Following B 30, B 31 of the flow is entered The NP counter is now 0, and 20 accordingly B 36 and B 37 are entered The FLG flip flop is in a 1 state and accordingly the 8 value 10 in register T is stored at address 7 of the P/B MEMORY area I (see Part 2, Table 41) and the address counter M 2 is counted up to address 8. During B 38, the P/B MEMORY reads out the next lower pipe center value 3 from area 1 and it is stored in register RI With reference to PIPE MODULE 25 Table 1, pipe center value 3 is associated with the response word "THIS" Also, during B 38 the MIN register is set to the forced maximum value of 255 and the T register is reset to 0. During B 39 of the flow, the register RII contains the new pipe center 3 and is therefore not -1, and accordingly B 16 is reentered The operation continues now 30 through B 16, B 8, B 9, B 10, Bil and B 12 of the flow, similar to that described above This operation is depicted below in symbolic form. B 16 DI( 5)- DII; set new end delimiter from DECODE II MODULE; call DECODE II MODULE 35 DO 2 ( 0)-DI; get new beginning delimiter; B 8,B 9 RII( 3)>DI(O); pipe center lies in the current entry of “S” E O vector RI( 4)>DI( 0); pipe center lies in the current entry of “S” E O vector; 40 B 10 D=IRI( 4)-RII ( 3)1 = 1; calculate absolute value of difference; B Il,B 12 D(l)MINB 28 N( 0) +; update # of hits T( 4) + LNRQR ( 3)-T( 7); compute E O value + BIAS FLG 4-l 15 B 29, B 30 write MIN = 4 &; output current minimum and current DI = 1 #of hits; to P/B MEMORY B 31 NP=O:.
FLG 4 20 B 37 write T = 7 to; output last value P/B MEMORY During the next B 38 of the flow, the end of field value -I is read out of the P/B
MEMORY and stored in the register RII and the read address counter Ml is counted up one address, the MIN register is set to the forced maximum value 255, 25 and the T register is reset to 0.
During the subsequent B 39 of the flow, it is found that the content of the RII register is < 0, causing a true signal at the L output of the ALU, causing B 40 to be entered. During B 40 of the flow, a true signal is formed at the P 20 output of the P 20 flip 30 flop causing a true signal at the B 8 output of the BRIGHTNESS MODULE The true signal at the P 20 output causes the D 54 selection circuit to couple the -1 value from the switches 1134 to the input of the P/B MEMORY The true signal at the B 8 output of the BRIGHTNESS MODULE causes the P/B MEMORY to write the -I end of field value at address 12 of the P/B MEMORY area 2 At this point in 35 time, the contents of addresses 0 through 12 of the P/B MEMORY area 2 are as indicated in Part 2 of Table 41 The logic B 8 CLK becomes true, causing the write address counter M 2 to count up one address The -I stored in register RII causes its sign bit to be true which in turn causes a true signal at the SRTI output of register RII Thus, logic P 20 SRII is true, causing the LNRQR register to count down one 40 address, reducing the BIAS value from 3. B 41 of the flow is now entered The BLAST flip flop is now in a 0 state, indicating that this is not the last E O vector of the response and accordingly the BRIGHTNESS MODULE exist its operation. The example of operation being given herein assumes a request of "SIT" and 45 the response "THIS IS A TEST" The "S" E O vector has been processed and the MINI COMPUTER now sets up the conditions for the second call on the 1,570,344 144 144 1,570,344 145 BRIGHTNESS MODULE for the "I" event of "SIT" as indicated in Part 3 of Table 41 To this end, the MINI COMPUTER stores in IPRF the following: length of -I" E O vector (value 2) in LNI, and length of delimiter occurrence vector (value 4) in LN 2 LNRQU is loaded only for the first E O vector Therefore, the LNRQ register in IPRF need not be refilled The MINI COMPUTER 5 also stores the "I" E O vector ( 6, 3) into MEMORY MODULE area I and sets flip flop BLAST to 0 to indicate this is not the last E O vector being processed MEMORY MODULE area 2 contains the same delimiter occurrence vector indicated in Part 1 of Table 41 and the P/B MEMORY area 2 contains the information stored by the BRIGHTNESS MODULE during the first call on the 10 BRIGHTNESS MODULE During the second call on the BRIGHTNESS MODULE, reading will take place at area 2 of the P/B MEMORY and writing will take place at area 1. Part 4 of Table 41 shows the content of the P/B MEMORY area 1 after the is second call and exit from the BRIGHTNESS MODULE and should be noted in is the following discussion. The BRIGHTNESS MODULE is called for the second time by the MINI COMPUTER and DPM INTERFACE MODULE as described above, causing B 1 to be entered. During Bl, the BRIGHTNESS MODULE causes the DECODE I and II 20 MODULES to be initialized by resetting them so that they commence decoding at the beginning, or largest, value in the corresponding event occurrence vectors. Additionally, the Ml and M 2 address counters are reset to 0 so that reading and writing take place, starting at address 0 of the P/B MEMORY areas, and the switching matrix (SM) for the P/B MEMORY is toggled, causing the read and write 25 areas in the P/B MEMORY to be reversed This causes writing to take place in P/B MEMORY area 1 using address counter M 2, whereas reading takes place in the P/B MEMORY area 2 using address counter M 1 The way in which the switching matrix for the P/B MEMORY is toggled or switches areas will be discussed in more detail hereinafter 30 Additionally, the DECODE II MODULE is called, causing it to read out the end delimiter 15 for storage in register DII. During B 2, the address 0 of the P/B MEMORY area 2 is read, using address counter Ml, causing the CP value 14 (see Part 2, Table 41) to be read and stored in register RII This is the incremented pipe center value stored during the first call 35 Additionally, the Ml register is incremented to address 1, the forced maximum value of 255 is stored in the MIN register and the T register is reset to 0. Additionally, the DECODE I MODULE is called, causing the first event occurrence value 6 from the "I" E O vector to be read and stored in the DOI register of the DECODE I MODULE 40 During B 3, the DECODE II MODULE is called, causing the beginning delimiter 10 to be read and stored in the DI register During B 5, the EOFI flip flop in the DECODE I MODULE is 0 because the last event occurrence value has not been decoded Accordingly, B 7 is entered. During B 7, the event occurrence value 6 from the "I" E O vector is 45 transferred from the DOI register into register RI During B 8, it is found that the pipe center value 14 in register RII is larger than the beginning delimiter value 10 in register DI Hence, the pipe center is within the delimiter designated by the content of register DI and B 9 is entered. During B 9, the event occurrence value 6 in register RI is compared with the 50 beginning delimiter 10 in register DI and the latter is found to be the larger. Accordingly, B 17 is entered. During B 17, the forced maximum value 255 is stored into register MIN and the pipe center value in register RII is incremented from 14 to 15. During B 18, the BFIRST flip flop is found to be in a 0 state, and accordingly 55 B 20 and B 21 are entered Considering the operation in detail, during B 18 the P 10 flip fiop is in a 1 state and the Bl FIRST flip flop is in a 0 state, causing the logic P 10 BFIRST to be true This causes the Pl flip flop to be set to a 1 state and the P 10 flip flop to be reset to a 0 state at the following CLK pulse, therby causing B 20 of the BRIGHTNESS MODULE flow to be entered 60 A true condition at the Pl 1 output of the Pl 1 flip flop causes the B 7 output of the BRIGHTNESS MODULE to receive a true signal Additionally, the flip flop P 26 is now in a 0 state and the true condition of the P 26 output of the P 26 flip flop :auses the DSI selection circuit to couple the address 1 contained in the Ml address counter to the P/B MEMORY The true signal at the B 7 output causes the 65 P/B MEMORY to read the min value 13 from address I of P/B MEMORY area 2 (see Part 2 of Table 41) The true signal at output Pl 1 causes the D 57 selection circuit to couple the min value 13 from the P/B MEMORY to the input of register MIN and the logic Pl l CLK causes the MIN register to store the min value 13. Additionally, the logic B 7 P 26 CLK causes the M l address counter to count up to 5 address 2 The following CLK pulse causes the P 12 flip flop to be set to a 1 state and the Pl 1 flip flop to be reset to a 0 state, causing B 21 of the flow to be entered. During B 21, a true signal is formed at the P 12 output causing another true signal at the B 7 output of the BRIGHTNESS MODULE, again causing the P/B MEMORY to read out, this time from address 2 Referring to Part 2 of Table 41, 10 the # of hits value 1 is read out to the input of the N and NP counters The logic P 12 ULK becomes true, causing the # of hits value 1 to be stored into the N and NP counters Additionally, the Ml address conter is counted up to address 3 A true signal being formed at the P 12 output causes the P 13 flip flop to be set to a 1 state and the P 12 flip flop to be reset to a 0 state at the following CLK pulse, thereby 15 causing B 22 of the flow to be entered. During B 22, an updated or incremented pipe center value of 15 is contained in register RII whereas the upper delimiter minus 1 ( 15 1 = 14) is contained in register DII DII was decremented by one during the true signal at P 4 Since the incremented pipe value is not allowed to cross the upper delimiter 15, the upper 20 delimiter 15 I, or 14, is now stored into the P/B MEMORY using address counter M 2 Thus, address 0 of P/B MEMORY area I now contains the CP value 14 indicated in Part 4 of Table 41 Following B 22, B 23 is entered. During B 23, the content of the T register is checked and it now contains a 0. The reason it contains a 0 is that no event occurrence values from the "I" E O 25 vector are present in the entry "TEST" (see PIPE MODULE, Table 1), defined by the beginning delimiter 10 in register DI Accordingly, B 24 is entered B 24 and B 25 are used for checking the 8 values stored in the P/B MEMORY while processing the previous "S" E O vector. During B 25, the NP counter contains a value I and hence does not contain a 0 30 Accordingly, its output N Po is true Additionally, the T register contains a 0 and accordingly its output To is true Thus, the logic P 13 T NPO is now true, causing a true signal at the B 7 output Also, the output P 6 of flip flop P 26 is still true, causing the D 51 selection circuit to couple the address 2 from the Ml address counter to the P/B MEMORY The true signal at B 7 causes the P/B MEMORY to 35 read out the 8 value 16 from the address 3 (see Part 2 of table 41) The logic P 13 T O causes the D 58 selection circuit to couple the 8 value 16 to the input of the T register and the true condition of logic P 13 T, CLK causes the 8 value 16 to be stored into register T Additionally, the Ml address counter is counted up to address 4 and the true condition of logic P 13 T, NPO causes the NP counter to 40 count down to O It should be noted that the NP counter keeps track of the number of 8 values in the corresponding CP field in the P/B MEMORY which have been processed Additionally, during B 25 of the flow, the logic P 13 TA NPO causes the FLG flip flop to be set to a 1 state. Following B 25, B 29 and B 30 of the flow are again entered where the minimum 45 & value 13 contained in the MIN register is stored into address 1 of the P/B MEMORY area 1, # of hits value I in counter N is stored into address 2 of the P/B MEMORY area 1 (see Part 4 of table 41) and the address counter M 2 is incremented to address 3. B 31, B 36 and B 37 of the flow are now entered where the 8 value 16 contained So in register T is written into address 3 of the P/B MEMORY area 1 and the M 2 address counter is incremented to address 4. During B 38, the next pipe center value of 7 (see Part 2, Table 41) is read from address 4 of the P/B MEMORY area 2 and stored in the register RII, and the M l address counter is incremented to address 5 The forced maximum value of 255 is 55 stored into the MIN register and the T register is reset to 0 During B 39, the 8 CP value in register RII is not 0, and accordingly B 16 of the flow is reentered. This operation depicted by the flow continues until the end of field marker in the P/B MEMORY area 2 is detected This occurs when during B 39 it is found that register RII contains a 1 (less than 0), causing B 40 to be reentered The 60 operation for the example being described from the point where the above description leaves off to the entry into B 40 is depicted symbolically below. 146 1,570,344 146 1,570,344 B 16 B 8 B 14 B 16 DII, DI ( 10) call DECODE II MODULE DI, DO 2 ( 8) RII ( 7) < DI ( 8) RI ( 6) < DI ( 8) DII,-DI ( 8) Call DECODE II MODULE DI, DO 2 ( 5) get a new end delimiter read a new beginning delimiter; get new end delimiter get new end delimiter B 8 RII ( 7) > DI ( 5) B 9 RI ( 6) > DI ( 5) B 10 D = RI ( 6)RII ( 7) 1 D= I Bll B 12 D ( 1) < MIN ( 255) MIN DI ( 1) T -RI( 6) B 13 Call DECODE I MODULE EOFI = 0 ' RI DOI ( 3) B 9 RI ( 3) < DI ( 5) B 17 MIN,-255 RII = 8 B 18 BFIRST = O '. B 20, B 21 MIN -P/B MEMORY ( 7) N,NP P/B MEMORY( 1) B 22 Write DII 1 ( 7) to P/B MEMORY B 23 T O '. B 24 T ( 6) < MIN ( 7) B 27 MIN T ( 6) B 28 N( 1)=N+ 1 = 2 T ( 6) + LNRQR ( 2) = T ( 8) FLG I 1 B 29, B 30 Write MIN ( 6) N ( 2) to P/B MEMORY B 31 NP= 1 O '. B 32 Read RII P/B MEMORY ( 10) NP( 1), NP 1 = NP ( 0) B 33 T ( 8) < RII ( 10) B 35 write 8 to P/B MEMORY T RII( 10) B 31, B 36 NP = O & FLG= 1 '. B 37 write T ( 10) to P/B MEMORY B 38 Read RII P/B MEMORY ( 4) MIN 255 T-0 B 39 RII ( 4) > O ‘B 16 B 16 DII, DI ( 5) call DECODE II MODULE DI, DO 2 ( 0) B 8 RII ( 4) > DI ( 0) B 9 RI ( 3) > DI ( 0) B 10 D=IRI-RIII = 13-41 = 1 B 11, B 12 D ( 1) < MIN ( 255) MIN, D ( 1) T RI ( 3) B 13 Call DECODE I MODULE EOFI = 1 RI 1 B 9 RI < DI B 17 MIN 255 RII ( 4) + 1 = RII ( 5) D is less save D and save position in T reset MIN update RII write out center pipe -do not allow it to cross definite boundaries write out the current minimum and # of hits NP isnot O O read in the next value decrement # of hits T < new value output T set T = to new value no more to be read write T read the next center pipe get new end delimiter get new beginning delimiter compute offset its minimum save value save position done reset MIN shift the center pipe 147 147 148 1,570,344 148 B 18 B 20,21 B 22 FIRST O Read MIN = 4 & N = 1 from P/B MEMORY Write DII 1 ( 4) to P/B MEMORY B 23 T O B 26 T ( 3) < MIN ( 4) B 27 MIN T ( 3) B 28 N( 1)N + 1 =N( 2) T = T ( 3) + LNRQR ( 2) = T ( 5) Set flag FLG 1 B 29, B 30 Write MIN ( 3) & N ( 2) to P/B MEMORY B 31 NP O '. B 32 Read RII P/B MEMORY ( 7) NP ( 0), NP-1 = NP ( 0) B 33 T ( 5) < RII ( 7) B 35 Write out T = 5 to P/B MEMORY T ( 7) to P/B MEMORY B 31, B 34 NP= O ' FLG = 1 B 37 Write out T ( 7) to P/B MEMORY B 38 Read RII 1 MIN 255 T, O B 39 RII < O B 40 Write I as end of data to AM-II LNRQ ( 2) = LNRQ -1 = LNRQ ( 1) B 41 BLAST = O EXIT not the first time read MIN and # of hits from AM-II write adjusted center pipe do not allow to cross boundary update the number of hits add BIAS to the position write out the new minimum and # of hits read in new value decrement count read end of field end of data lower the bias count Following B 41 of the flow, the addresses 0 through 14 of the P/B MEMORY area 1 are as depicted in Part 4 of Table 41. The "I" E O vector has been processed and the MINI COMPUTER now sets up the conditions depicted in Part 3 of Table 41 for the third call on the BRIGHTNESS MODULE for the "T" event of the request word "SIT" To this end, the MINI COMPUTER stores in IPRF the following: length of "T" E O. vector (value 3) in LNI 1; length of delimiter occurrence vector (value 4) in LN 2. LNRQ is not changed The MINI COMPUTER also stores the "T" E O vector ( 14, 11, 1) into MEMORY MODULE area 1 MEMORY MODULE area 2 contains the same delimiter occurrence vector indicated in Part 1 of Table 41 and the P/B MEMORY area contains the information stored by the BRIGHTNESS MODULE during the second call on the BRIGHTNESS MODULE as depicted at Part 4 of Table 41 Additionally, the DPM INTERFACE MODULE forms a true signal at the BLAST 1 output causing the BLAST flip flop in the BRIGHTNESS MODULE to be set to a I state, indicating that the last E O vector for the last request event is about to be processed. The operation of the BRIGHTNESS MODULE is again called by forming a signal at BMGO causing the operation of B 11 through B 40 of the flow to be reentered However, it should be noted that at B 1, the switching matrix for the P/B MEMORY is again toggled, causing the read and write areas to reverse. Hence, writing now takes place in P/B MEMORY area 2, whereas reading takes place in the P/B MEMORY area 1 The operation of the BRIGHTNESS MODULE is similar to that described above and will not be repeated in detail, but instead is indicated in symbolic notation below. 148 1,570,344 148 1.49 1,570,344 -O Bl initialize DECODE I & II MODULES call DECODE II MODULE DII DO 2 ( 15);g B 2 Read RII 4 P/B MEMORY ( 14); r MIN 255; reset MIN & T to 0 T-0 Call DECODE I B 3 Call DECODE II MODULE ge va DI DO 2 ( 10) B 5-B 7 EOFI = O ' RI DO 1 ( 14) tin B 8 RII ( 14) > DI ( 10); de Dl B 9 RI ( 14) > DI ( 10); e de DlI et end delimiter ead pipe center (CP) value t a beginning delimiter lue read in a “T” event ne P value lies within entry signated by delimiter in I vent time lies within entry signated by delimiter in Bl O D = IRI ( 14)-RII( 14)1 = O B 1, B 12 D < MIN ( 255) '. MIN, D ( 0) T RI ( 14) B 13 Call DECODE I MODULE E O FI = O RI, DOI ( 11) B 9 RI ( 11) > DI ( 10) B 10 D, IRI( 11)-RII ( 14)I = D ( 3) B 11 D( 3) > MIN( 0) B 13 Call DECODE I MODULE EOFI = O RI DOI ( 1) B 9 RI ( 1) < DI ( 10) B 17 MIN 255 RII RII ( 14) + 1 = RII ( 15) B 18 BFIRST = O B 20, B 21 Read MIN -P/B MEMORY( 13) Read N, NP P/B MEMORY ( 1) B 22 Write DII -1 ( 14) -, P/B MEMORY B 23 T O B 26 T ( 14) > MIN ( 13) B 28 N N ( 1) + 1 = N ( 2) T T ( 14) + LNRQR ( 1) = T( 15) Set FLG, 1 B 29, B 30 Write out MIN ( 13) -+ P/B MEMORY Write out N ( 2) P/B MEMORY B 31 NP O B 32 Read RII P/B MEMORY ( 16) NP NP ( 1) 1 = NP ( 0) B 33 T ( 15) < RII ( 16) B 35 Write T ( 15) -> P/B MEMORY T,RII ( 16) B 31 NP= O B 36 FLG = 1 B 37 Write out T ( 16)P/B MEMORY B 38 Read RII P/B MEMORY B 39 B 16 B 8 B 14 B 16 MIN 255 T -0 RII( 7)> O B 16 DII DI ( 10) Call DECODE II MODULE DI DO 2 ( 8) RII ( 8) < RI ( 8) RI ( 1) < DI ( 8) DII DI ( 8) save MIN save event time reset MIN shift pipe center write out the shifted pipe center adjust N add BIAS read in new value read in next pipe center value get new end delimiter get new beginning delimiter 1,570,344 149 1 AQ 1,570,344 Call DECODE II MODULE DI DO 2 ( 5) RII ( 7) > DI ( 5) RI ( 1) < DI ( 5) MIN 255 RII RII ( 7) + I = RII ( 8) B FIRST = O BFIRST = O =. Read MIN P/B MEMORY ( 6) Read N, NP P/B MEMORY ( 2) Write DII 1 ( 7) -, P/B MEMORY B 23 T = O B 24 NP O B 25 Read T P/B MEMORY ( 8) NP NP( 2) 1 =NP ( 1) Set FLG I 1 B 29, B 30 Write MIN ( 6) P/B MEMORY Write N ( 2) P/B MEMORY B 31 NP: O B 32 Read RII P/B MEMORY ( 10) NP NP( 1) 1 = O B 33 T ( 8) < RII ( 10) B 35 Write T ( 8)P/B MEMORY; T = RII ( 10) B 31 NP= O '. B 36 FLG = 1 B 37 Write T ( 10) -} P/B MEMORY B 38 Read RII P/B MEMORY ( 4) MIN 255 T-0 B 39 RII ( 4) > O B 16 DII DI ( 5) Call DECODE II MODULE DI DO 2 ( 0) B 8 RII ( 4) > DI ( 0) B 9 RI ( 1) > DI( 0) B 10 D -IRI( 1)-RII( 4)1 = D ( 3) Bl l, B 12 D ( 3) < MIN( 255) MIN D ( 3) T RII ( 1) B 13 Call DECODE I MODULE EOFI = 1 'RI 1 B 8 RI (1) < DI ( 0) B 17 MIN 255 RII + RII ( 4) + 1 = RII ( 5) B 18 BFIRST = O B 20, B 21 Read MIN -P/B MEMORY ( 3) Read N, NP P/B MEMORY ( 2) B 22 Write DII1 ( 4)> P/B MEMORY B 23 T-:0 B 26 T(l) < MIN( 3)= B 27 MIN T ( 1) B 28 N-N ( 2)+ 1 =N( 3) T T ( 1) + LNRQR ( 1) = T( 2) B 29, B 30 Write MIN (I) - P/B MEMORY N ( 3)- P/B MEMORY B 31 NP O B 32 Read RII P/B MEMORY ( 5) NP < NP ( 2) 1 = NP ( 1) B 33 T ( 2) < RII ( 5) B 35 Write T ( 2)P/B MEMORY write adjusted pipe center read a new pipe center reset min reset T get new beginning delimiter delimiters CP lies in entry designated by beginning delimiter in DI event time save min value save 8 value write out adjusted pipe center save new min 8 update # of hits add the BIAS B 8 B 9 B 17 B 18 B 20 B 21 B 22 T R 11 ( 5) B 31 NP O B 32 Read RII P/B MEMORY ( 7) NP -NP(l) I =NP( 0) B 33 T ( 5) < R 1 I ( 7) 5 B 35 Write -, P/B MEMORY ( 5) T +RII ( 7) B 31 NP= 0:. B 36 FLG = 1 B 37 Write T ( 7) -P/B MEMORY 10 B 38 Read RII P/B MEMORY ( 1);read end of field value MIN + 255 T 40 B 39 RII (-1) < O 15 B 40 Write 1 -+ P/B MEMORY LNRQR LNRQR (l) = LNRQR ( 0) B 41 BLAST= 1 It should be noted that at B 41 of the operation depicted in symbolic form 20 above, the BLAST flip flop is in a 1 state (see Part 5 of Table 41) Accordingly, B 42 is entered At this point, the P 20 flip flop is in a I state, causing a true signal at the P 20 output Accordingly, the logic P 20 BLAST is true, causing a true signal at the B 4 output of the BRIGHTNESS MODULE which in turn resets the DECODE II MODULE so that it will commence reading at the beginning of the delimiter 25 occurrence vector depicted in Part I of Table 41 Additionally, the register RII now contains the end of field marker 1 causing the sign bit of the register RII to be true, thereby causing a true signal at the SRII output The logic P 20 BLAST SRII is now true, thereby causing the M 2 address counter to be reset to 0 The logic P 20 BLAST= is true, thereby causing a true signal at the B 6 output of the 30 BRIGHTNESS MODULE which in turn calls the operation of the DECODE II MODULE, causing it to read the end delimiter 15 The end delimiter 15 is merely read and discarded as it is not needed in the subsequent operation. The true condition of the logic P 20 BLAST SRII also causes, at the following CLK pulse, the flip flop P 21 to be set to a 1 state and the flip flop P 20 to be reset to 35 a 0 state The true condition of the output P 21 of flip flop P 21 causes the M 2 and M 3 address counters to be reset to 0 During B I of the flow, the true condition of logic PI CLK causes the length of the delimiter event occurrence vector to be transferred from LN 2 of the IPRF to the BSAV register of the BRIGHTNESS MODULE The length 3 is retained for resetting of the DECODE II MODULE 40 During B 42 of the flow, the true condition of the logic P 20 SRII BLAST causes a true signal at the Bl O output of the BRIGHTNESS MODULE, which in turn enables the length 3 in register BSAV to the input of register MLN 2 of the DECODE II MODULE The logic B 10 CLK causes a true signal at the B 11 output of the BRIGHTNESS MODULE which in turn causes the length 3 to be stored 45 into register MLN 2 from the BSAV register. B 43 is now entered The true condition of logic P 21 CLK causes a true signal at the B 6 output of the BRIGHTNESS MODULE, which in turn again calls the operation of the DECODE II MODULE, causing it to read out the beginning delimiter 10 (see Part 1 of Table 41) The logic P 22 causes the delimiter 10 50 contained in register D 02 of the DECODE II MODULE to be stored into the DI register. During B 44 of the flow, a true signal is formed at the output P 21 of flip flop P 21 which in turn causes a true signal at the B 7 output of the BRIGHTNESS MODULE The true signal at the B 7 output causes the content of address 0 of P/B 55 MEMORY area 2 to be read out as specified by address counter Ml With reference to Part 6 of Table 41, address 0 contains the first CP value 14 Logic P 21 CLK becomes true, causing the CP value 14 to be stored into register RII. Additionally, the logic B 7 P 26 CLK is true, causing the address counter Ml to be counted up to address 1 60 The true signal at the output P 21 causes the flip flop P 22 to be set to a 1 state and the flip flop P 21 to be reset to a 0 state at the following CLK pulse, thereby causing B 45 of the flow to be entered. 151 I 1,570,344 1 1 i 152 1,570,344 152 During B 45 of the flow, register RII does not contain the end of field value (- 1) Accordingly, B 46 is entered. During B 46 the output P 22 is true, causing the D 59 and D 510 selection circuits to couple the content of registers RII and DI to the input of the ALU and causing a true signal at the C input of the ALU The CP ( 14) value in a register RI 1 is larger 5 than the beginning delimiter 10 in register DI and accordingly a true signal is formed at the L output of the signal inverter 1140 The logic P 22 L is now true, causing the P 23 flip flop to be set to a I state, and flip flop P 22 is reset to a 0 state at the following CLK pulse, thereby causing B 48 of the flow to be entered. During B 48, a true signal is formed at the output P 23 of flip flop P 23 The true to signal at the output P 23 causes the DO and S counters to be reset to 0 These registers, it will be recalled, store the do and dmin values The true signal at the output P 23 also causes a true signal at the B 7 output from the BRIGHTNESS MODULE The true signal at the B 7 output causes the content of address 1 of P/B MEMORY area 2 to be read out, using address register Ml With reference to Part is 6 of Table 41 address 1 contains the min value 13 Accordingly, the min value 13 is read out of the P/B MEMORY and the D 57 selection circuit couples it through to the input of the MIN register The true condition of logic P 23 causes the min value 13 to be stored into the MIN register and causes the Ml address counter to be counted up to address 2 The true signal at the P 23 output causes the flip flop 20 P 23 to be reset to a 0 state and the flip flop P 24 to be set to a 1 state at the following CLK pulse, thereby causing B 49 of the flow to be entered. During B 49 of the flow, a true signal is formed at the P 24 output of flip flop P 24, causing a true signal at the B 7 output of the BRIGHTNESS MODULE This causes the content of address 2 of P/B MEMORY area I to read out using address 25 counter Ml With reference to Part 6 of Table 41, address 2 contains the # of hits value 1 Accordingly, the # of hits value 1 is read out to the input of the N and NP counters The logic P 24 C is now true, causing the # of hits value 1 to be stored into the N and NP counters The Ml counter is then incremented to address 3 The true condition of the P 24 output causes the flip flop P 25 to be set to a 1 state, and 30 the P 24 flip flop to be reset to a 0 state at the following CLK pulse, thereby causing B 50 of the flow to be entered. During B 50 of the flow, the mid 8 ( 8 mid) value is read from the P/B MEMORY area 1 and stored into the T register The address of the 8 mid value is located by adding to the address in Ml the number of 8 values to reach the mid 8 35 value in the field of a values The NP counter at this point contains the # of hit values 2 which is the total number of 8 values in the field One half of the # of hits gives the number of addresses over from the beginning of the 8 field where the 8 mid lies In order to divide in half the # of hits value in NP, the NP is connected to the D 510 selection circuit so as to provide a one digit shift to the right, discarding 40 the bit shifted past the decimal point It will be understood that in binary notation, a one binary bit shift to the right is the same as dividing the number by 2 Thus the P 25 output causes the D 510 selection circuit to couple the output of the NP counter, with a 1 bit wired in right shift, to the input of the ALU and causes the D 59 selection circuit to couple the Ml address counter to the other input of the 45 ALU The NP counter at this point contains the value 2 and the Ml address counter contains the address 3 One-half of the value 2 is 1 Accordingly, the ALU now forms at the OP output signals representing the value 4 ( 2 + 3) The true signal at the P 25 output causes the address of the 8 mid to be coupled through the D 58 selection circuit to the input of the T register The true condition of logic P 25 CIX 50 causes the address 4 to be stored into the T register The true signal at the P 25 output causes the flip flop P 26 to be set to a 1 state and the P 25 flip flop to be reset to a 0 state at the following CLK pulse. The true signal at P 26 causes the DSI selection circuit to couple the address 4 of the 8 mid from the T register to the input of the P/B MEMORY and causes the 55 output B 7 to receive a true signal The true signal at output B 7 causes the P/B MEMORY to read out the 8 mid value 16 (see Part 6 of Table L) The true condition of the logic P 26 M causes the RII register to store the 8 mid value 16. B 51 of the flow is now entered where the content of the NP counter is checked to see if it is 0 The NP counter now contains the value 2 corresponding to the # of 60 hits value and a true signal is formed at the NFP output The logic P 26 WP, is now true, causing the P 27 flip flop to be set to a 1 state and the P 26 flip flop to be reset to a 0 state at the following CLK pulse, thereby causing B 52 of the flow to be entered. Also during B 52, the true signal at the P 27 output causes the output B 7 of the BRIGHTNESS MODULE to receive a true signal, thereby causing the P/B 65 152 1,570,344 152 MEMORY area 2 to read out the 8 value 15 from address 3, using the address counter Ml The 8 value 15 is coupled through the D 56 selection circuit to the input of the RI register The true condition of logic P 27 CLK causes the 8 value 15 to be stored into register RI and the address counter M l is counted up to address 4. Additionally, the true signal at the P 27 output of flip flop P 27 causes the NP 5 counter to count down from 2 to 1, thereby indicating that there is one 8 value left to be processed in area 2 of the P/B MEMORY The true signal at the P 27 output causes flip flop P 28 to be set to a 1 state, and flip flop P 27 to be reset to a 0 state at the following CLK pulse thereby causing B 53 to be entered. During B 53, the true signal at the P 28 output causes the D 59 and D 510 10 selection circuits to couple the Rll and RI registers to the inputs of the ALU That causes a true signal at the S input of the ALU Register RH now contains the 8 mid value 16 whereas the register RI contains the smallest 8 value 15 Therefore the ALU forms at OP the difference of 1 between the two values Since the content of register Rll is the larger, a true signal is formed at the T output of the signal 15 inverter 1140 and the logic P 28 T CLK is true, causing the register D to store the difference value of 1 Register D now contains one of the offset values to be used in forming dmn. The true signal at the P 30 output causes the D 59 and D 510 selection circuits to couple the D and S registers to the inputs of the ALU, and causes the A input of the 20 ALU to receive a true signal Thc D register contains the difference value of 1 whereas the S register contains a 0 Accordingly, the ALU forms the sum of the two values namely, a 1 at the output OP The logic P 30 CLK becomes true, causing the sum value of I at the output OP to be stored into the S register Additionally, flip flop P 31 is set to a 1 state and the flip flop P 30 is reset to a 0 state at the following 25 CLK pulse It should now be noted that the din value is being formed in the S register by the action during B 53. Should the 8 mid value in register RII be smaller than the 8 value in register RI, there would have been a negative result Since the absolute value is desired, flip flop P 29 would have been set to 1 rather than P 30 and the difference value at the 30 OP output therefore would not be stored into the D register The true signal at P 29 would cause the registers RII and RI to be coupled to the ALU reversed from that during P 28 and therefore would result in a positive value at the OP output which would then be stored into the D register and subsequently summed with the S register during the true signal at P 30 35 Assume now that the P 31 flip flop has been set to a true state and that B 54 is entered. During B 54, a true signal is formed at the P 31 output Accordingly, the RI and MIN registers are coupled through the D 59 and D 510 selection circuits to the input of the ALU The register RI contains the smallest 8 value 15, whereas register MIN 40 contains the min occurrence value 13 The true signal at the P 31 output causes a true signal at the S input of the ALU, causing the ALU to select the min values 13 from 8 value 15, resulting in a difference value of 2 at the UP output The logic P 31 PCLK becomes true, causing the value 2 at the OP output to be stored into the D register The true signal at the P 31 output causes the flip flop P 32 to be set to a 1 45 state and the flip flop P 31 is reset to a 0 state at the following CLK pulse Thus, at this point, the D register now contains the offset between the smallest event time of the request and the first 8 value, making up the first offset value making up do The true signal formed at the P 32 output causes the difference value 2 in register D and the 0 content of register D, to be coupled through the D 59 and D 510 selection so circuits to the inputs of the ALU and causes a true signal at the A input of the ALU. The D register contains the difference 2 whereas the Do register contains a 0. Accordingly, the ALU forms the value 2 at its output OP The following pulse at -P 32 causes the difference value 2 at the OP output to be stored back into the D register Thus, register Do now contains the first sum of offsets value do 55 The NP counter now contains a 1 and accordingly is not 0 Thus a true signal is formed at the " P output of the NP counter The logic P 32 NPO is now true, accordingly, the following CLK pulse sets the P 32 flip flop to a 0 state and sets the P 27 flip flop to a 1 state, causing B 51 of the flow to be reentered. During B 51 of the flow, the NP register counter stores a 1 and accordingly is 60 not 0, and B 52 is entered. During B 52 of the flow, the next 8 value 16 is read from address 4 of the P/B MEMORY area 2 (see Part 6 of Table L) and the value is stored in register RI The M l address counter is counted up to address 5 and the NP counter is counted down to O 65 153 153 1,570,344 B 53 of the flow is now entered The 8 mid value 16 is still stored in register RII and, as explained above, the ALU forms the difference between the contents of registers RI and RII ( 16-16) and the difference, a 0, is stored into the D register and subsequently added to the I contained in the S register Thus the S register now contains dmin, the sum of offsets 5 During B 54, the ALU subtracts the difference between the a value 16 in register Ri and the min event time value 13 in register MIN The difference value, 3, is subsequently stored in the D register and is subsequently added to the value 2 already contained in the Do register, causing the value 5 to be stored in the Do register Thus the D, register at this time contains the sum of offsets value do for the 10 CP value 14 stored in address 0 of P/B MEMORY area 2 (see Part 6, Table 41). At this point, B 51 of the flow is reentered The NP counter has been counted down to 0, indicating that all of the 8 values for the entry in addresses 0 through 4 have been processed Accordingly, a true signal is now formed at the NP, output of counter NP and a true signal is formed at the P 32 output At the following CLK 15 pulse, the logic P 32 NPO is true, causing the P 33 flip flop to be set to a 1 state and the P 32 flip flop is reset to a 0 state, causing B 55 to be entered. The beginning delimiter 10 is now stored in register DI The true signal at the P 33 output causes a true signal at the B 13 output of the BRIGHTNESS MODULE which in turn calls the operation of the MEMORY MODULE The MEMORY 20 MODULE writes the beginning delimiter 10 in area 3 at the location specified by address 0 in the M 3 address counter as indicated in Part 7 of Table L A true signal is now formed at the B 13 CLK output, causing the M 3 address counter to count up to address 1 The true signal at the P 33 output also causes the P 34 flip flop to be set to a I state and the P 33 flip flop to be reset to a 0 state at the following CLK pulse 25 During B 56, the # of hits value, 2, is contained in the N counter The true signal at the P 34 output causes another true signal at the B 13 output of the BRIGHTNESS MODULE, thereby causing the MEMORY MODULE to again be called and write the # of hits value 2 at address 1 of area 3 as specified by the address counter M 3 The true condition of logic B 13 CLK again causes the M 3 30 address counter to be counted to address 2 The true signal at the P 34 output of the P 34 flip flop causes flip flop P 35 to be set to a 1 state and flip flop P 34 to be reset to a 0 state at the following CLK pulse, thereby causing B 57 of the flow to be entered. The S register now contains the sum of offsets to 8 mid, referred to as the dmn value, a value of 1 The true signal at the P 35 output causes a true signal at the B 13 35 output of the BRIGHTNESS MODULE, causing the MEMORY MODULE to write the din value 2 in address 2 of area 3 (using the M 3 address counter) and the M 3 address counter is counted up to address 3 The true signal at the P 35 output of flip flop P 35 causes the P 36 flip flop to be set to a 1 state and flip flop P 35 to be reset to a 0 state at the following CLK pulse, thereby causing B 58 of the flow to be 40 entered The sum of offsets to the first event of the response, do, is now stored in the D, register The true signal at the P 36 output again causes a true signal at the B 13 output, causing the MEMORY MODULE to write the do value 5 at address 3 using the M 3 register and the M 3 address counter is counted to address 4 At this point, the MEMORY MODULE area 3 contains the values indicated for addresses 0 45 through 3 depicted in Part 7, Table 41. During B 44, in the manner described above, the P/B MEMORY area 2 reads out of address 5 (using the M 1 address counter) and the new CP value 7 is stored into register RI Additionally, the address counter M l is incremented to address 6. During B 45, the register RII does not contain the end of field value 1, 50 accordingly, B 46 is entered During this pass through B 46, the CP value 7 in register RII is found to be < the beginning delimiter value 10 in register DI. Accordingly, a true signal is formed at the L output of the ALU This causes B 47 of the flow to be entered. During B 47 of the flow, the logic P 22 L CLK becomes true, causing a true 55 signal at the B 6 output of the BRIGHTNESS MODULE This in turn causes the DECODE II MODULE to read out the next lower beginning delimiter value 8 The true signal at the P 22 output causes the delimiter value 8 to be coupled through the DI register to its output. B 6 of the flow is reentered where the CP value 7 in register RII is compared 60 with the beginning delimiter value 5 in register DI and the former is found to be the larger Accordingly, the ALU causes a true signal at the L output of inverter 1140 causing the logic P 22:E to become true as discussed above, thereby causing B 48 of the BRIGHTNESS MODULE flow to be reentered. 154 1,570,344 154 The operation of the BRIGHTNESS MODULE continues similar to that described above as depicted below in symbolic notation. B 48 S, DO O Read MIN P/B MEMORY ( 6) B 49 Read N, NP P/B MEMORY ( 2) B 50 T -MI( 8) + NP/2 ( 1) = T ( 9) Read RII P/B MEMORY ( 10) B 51 NP:0 B 52 Read RI P/B MEMORY ( 8) NP NP ( 2)1 = NP ( 1) B 53 D = I RII ( 10) RI ( 8)l = D ( 2) S = S ( 0) + D ( 2) = S ( 2) B 54 D RI ( 8)MIN ( 6) = D ( 2) DO = DO ( 0) + D ( 2) = DO ( 2) B 51 NP O B 52 Read RIIP/B MEMORY ( 10) NP NP( 1) 1 =NP( 0) B 53 D = I RII( 10)-RI( 10)l = D( 0) S S ( 2) + D ( 0) = S ( 2) B 54 D RI ( 10)MIN ( 6) = D ( 4) DO = DO ( 2) + D ( 4) = DO ( 6) B 51 NP= O '. B 55-B 58 Write following in addresses 4-7 of MEMORY MODULE area 3: DI= 5 N= 2 S= 2 B 5 Do= 6 B 44 Read RII, P/B MEMORY ( 4) B 45 RII( 4)> 1 = B 46 RII ( 4) < DI ( 5) B 47 Call DECODE II MODULE DI DO 2 ( 0) B 46 B 48 B 49 B 50 B 51 B 52 B 53 B 54 B 51 B 52 B 53 B 54 B 51 B 53 RII( 4) > DI( 5) S, DO O Read MIN P/B MEMORY ( 1) Read N, NP P/B MEMORY( 3) T + M l ( 13) + NP/2 ( 1) = T ( 14) Read RII P/B MEMORY ( 5) NP O Read RI P/B MEMORY ( 2) NP NP ( 1) I =NP( 2) D I RII ( 5) RI ( 2)1 S -S ( 0) + D( 3) = S ( 3) D ( 1), RI ( 2) MIN ( 1) = D ( 1) DO DO( 0) + D ( 1) = DO (I) NP O Read RI P/B MEMORY ( 5) NP NP( 2) 1 =NP(I) D = I RII ( 5) RI ( 5)1 = D ( 0) S S ( 3) + D ( 0) = S ( 3) D RI( 5) MIN ( 1) = D ( 4) DO DO ( 1) + D( 4) = Do ( 5) NP#0 Read RI P/B MEMORY ( 7) NP NP ( 1) I =NP( 0) D RII ( 5) RI ( 7)1 = D ( 2) S S( 3) + D ( 2) = S ( 5) D,-RI ( 7) MIN ( 1) = D ( 6) Do, DO( 5) + D( 6)=D ( 11) compute 8 midpoint address read midpoint 8 value read beginning delimiter of last entry in response read 8 MID 1,570,344 B 54 156 1,570,344 156 B 51 NP= 0 B 55-B 48 Write following in addresses 8-11 of MEMORY MODULE area 3 DI= = O N= 3 S= 5 Do= 11 B 44 read RII P/B MEMORY (-1); end offield 10
After B 44 of the flow, B 45 is entered During B 45, the register RII contains the end of field delimiter 1 Accordingly, the logic B 9 (P 22 SRII) causes the
BRIGHTNESS MODULE to exit.
At this point, the MEMORY MODULE area 3 contains the field of information depicted at addresses 0 through 11, Part 7 of Table 41 The 15 BRIGHTNESS MODULE forms a true signal at the FC (BMEND) output, signalling to the MINI COMPUTER that it has completed its brightness function.
The MINI COMPUTER then takes the field of information depicted at Part 7,
Table 41, and computes the following scatter values for each entry as illustrated below in equation form 20 Sentry I = do-dmn = 5 1 = 50 (TEST) do + (LNRQ -N) LNRQ 5 + ( 3-2) 3 S entry 2 = 6 2 = 444 (IS) 6 + ( 3-2) 3 S entry 3 11-5 = 5454 25 (THIS) 11 + ( 3-3) 3 From the above, it will be seen that the scatter value for entry 3 corresponding to the word “THIS” is closest to unity and accordingly would most likely be selected as the response for the request word “SIT” The MINI COMPUTER also computes the length factor L, using the equation given above, together with the 30 length of request LNRQ stored in IPRF and the length of the response for each entry as follows:
L Q NV 3 ( 3 4)) 3 L entry 1 1 ( 63 LNRQ 3 3 (TEST) 1 ( 63) 3 = 99 L entry 2 = 63 3 2) (IS) = 1 ( 63 1/3) = 99 L entry 3 = 1 ( 63 3) 3 (THIS) = 1-0 = 99 =.99 157 1,570,344 157 The MINI COMPUTER under program control then computes the brightness value B for each of the entries as follows:
B, = L, S, = 99 x 50 = 495 (TEST) B 2 = L 252 =99 x 444 = 437 5 (IS) B 3 = L 3 53 = 99 x 5454 = 5499 (THIS) From the above example it will be seen that the word “THIS” has the highest brightness value B of 5499 and based thereon, would be selected as the best word 10 from the data base which is a response to the request word ‘SIT”.
XVII DPM INTERFACE MODULE The DPM INTERFACE MODULE of Fig 1 acts similar to a conventional I/O peripheral to the MINI COMPUTER The DPM INTERFACE MODULE is initialized by the MINI COMPUTER The DPM INTERFACE MODULE then 15 stores information from the MINI COMPUTER or, upon completion of a desired function by the delta processing machine (DPM), the results are read by the MINI COMPUTER from the DPM INTERFACE MODULE.
Three groups of information are necessary to run the DPM as follows: ( 1) input information such as the isoentropicgram width (HW); length of data in 20 memory area (i e, LNI, LN 2), length of request (LNRQ); line number (LINE #); top limit (TL), and bottom limit (BL), internal (IR) and pipe width (PW) The input information is placed into the IPRF shown in Fig 52 by the MINI COMPUTER.
( 2) Output information such as new line number of seed, seed length, etc, all of which have been pointed out in connection with each module ( 3) Memory 25 information which is written and read in the MEMORY MODULE or the P/B MEMORY by the MINI COMPUTER.
The DPM INTERFACE MODULE provides the necessary circuitry to handle the input/output interface in between the MINI COMPUTER and the DPM.
Reference is now made to Fig 51 through Fig 53, showing block and schematic 30 diagrams of the DPM INTERFACE MODULE Heavy lines are used to depict multiple lines for carrying multiple bits of data in parallel Logical equations are used to represent gates used to control the operation of the system A parallel I/O bus 1210 provides the interconnection between the MINI COMPUTER and the rest of the circuitry in the DPM INTERFACE MODULE As the module is 35 disclosed, the necessary connections will be presented to show how this INTERFACE MODULE would be set up as an interface to a Digital Equipment Corporation PDP-1 1 computer.
The I/O bus 1210, as depicted in Fig 54, is made up of three groups of lines referred to as the “data lines”, the “address lines” and the “bus control lines” 40 Considering first the address lines, the MINI COMPUTER places addresses on the address lines The address signals are the addresses of peripheral units external to the MINI COMPUTER with which the MINI COMPUTER is to communicate.
The addresses for the INTERFACE MODULE are of the following type:
XXXXXYYY 45 where XXXXX uniquely identifies the desired peripheral with which the MINI COMPUTER is to communicate, the YYY identifies the register within the peripheral with which the MINI COMPUTER is to communicate.
Referring to Fig 1, the DPM INTERFACE MODULE contains interface logic unit 1204 The details of this unit which are of importance to the present 50 invention are disclosed in connection with Figs 51 through 53 Generally speaking, the interface logic 1204 is responsible for gating data to and from the I/O bus 1210.
The unit 1204 also handles the handshaking steps of forming the signals at the READY and BDONE lines of the bus control lines as discussed in more detail hereinabove Additionally, the unit 1204 monitors a STATUS register depicted in 55 Fig 53 and depending on the status of various flip flops in the STATUS register, notifies an interrupt control module 1206 when interrupt operations are to be handled.
In the present system, the only peripheral of interest is the DPM INTERFACE MODULE The specific registers within the DPM INTERFACE MODULE with which communication takes place are disclosed in more detail in connection with Fig 51.
The data lines carry the data which is being communicated between the MINI 5 COMPUTER and the DPM INTERFACE MODULE Data may be placed on the lines, either by the MINI COMPUTER or the DPM INTERFACE MODULE The bus control lines carry control signals for controlling the transfer of information in between the MINI COMPUTER and the DPM INTERFACE MODULE.
Consider now the sequence of operation and timing for an I/O bus “output” 10 operation from the MINI COMPUTER to the DPM INTERFACE MODULE.
Fig 55 contains a timing diagram illustrating the sequence of operation First, the MINI COMPUTER applies address signals on the address lines as indicated at 1.
Next, the MINI COMPUTER applies data signals on the data lines as depicted at 2.
After transient conditions have settled on the address and data lines (such as after a 15 predetermined time delay), the MINI COMPUTER forms a true signal on the READY line in the bus control lines A true signal on the IN/OUT line indicated an output transfer from the MINI COMPUTER to the DPM INTERFACE MODULE, whereas a false signal indicates an input transfer to the MINI COMPUTER Around the same time that data is applied on the data lines, the MINI 20 COMPUTER applies a true signal on the IN/OUT line indicating that this is to be an output transfer After the true signal at the READY control line, the DPM INTERFACE MODULE reads the data applied on the data lines After the DPM NTERFACE MODULE completes its reading operation, the DPM INTERFACE MODULE applies a true signal on the BDONE line of the bus control lines The 25 true signal on the BDONE line signals the MINI COMPUTER that the output operation is complete, and therefore the MINI COMPUTER then removes the signals it applied to the READY line, the address line, the data lines, and the IN/OUT line Subsequently, the DPM INTERFACE MODULE removes the true signal on the BDONE line This cooperative signalling of ready and done on the 30 READY and BDONE lines is referred to in the computer art as handshaking and is a well known technique requiring no further explanation.
Consider now the sequence of operation and timing for an I/O bus “input” operation to the MINI COMPUTER from the DPM INTERFACE MODULE, as depicted by the timing diagram of Fig 56 Initially, as indicated at 1, the MINI 35 COMPUTER applies addresses on the address lines of the bus 1210 Also, the MINI COMPUTER maintains the signal on the IN/OUT line false, indicating that this is an input operation to the MINI COMPUTER from the DPM INTERFACE MODULE The MINI COMPUTER then forms a true signal at the READY line of the bus control lines after the signals on the address lines have settled (such as after 40 a prefixed delay) The DPM INTERFACE MODULE then responds by applying data signals onto the data lines as indicated at 2 The DPM INTERFACE MODULE then forms a true signal at the BDONE line of the bus control lines, signalling that the operation is complete Subsequently, after a prefixed delay, the MINI COMPUTER reads the data on the data lines The MINI COMPUTER 45 responds to the true signal at the BDONE line by removing the signals on the READY and the address lines, as indicated at 1, 2, and 3 Subsequently, the DPM INTERFACE MODULE removes the true signal at the BDONE line and the data lines, completing the input operation.
The foregoing input and output sequences are repeated for each transfer of 50 data in between the MINI COMPUTER and the DPM INTERFACE MODULE.
Refer now to the general block diagram of Fig 1 The DPM INTERFACE MODULE contains an address selector 1202 The address selector 1202 has inputs connected to the address lines and the IN/OUT control line of the I/O bus 1210.
The address selector 1202 contains address recognition circuits (not shown), well 55 known in the computer art, for recognizing the X X X X X portion of the address signal on the address lines which designate the DPM INTERFACE MODULE In addition, an address decoder (not shown) is contained in the address selectors 1202 for converting the coded signals in the YYY portion of the address on the address lines to a true signal on one of the output lines SO, SI and 52 To be explained in 60 more detail, with respect to Fig 51, true signals at the SO output selector either a DATAO output gate or a DATAI input register, and true signals at the 51 and 52 outputs select the AI and STATUS registers, respectively (see Fig 51) Thus, the address decoder (not shown) in the address selector 1202 forms a true signal at one, 158 I 1,570,344 158 and only one, of the output lines SO, SI and 52, depending on the coded signal in the address portion YYY of the signals on the address lines.
The address selector 1202 also contains a decoder (not shown) which is responsive to a true signal on the IN/OUT bus control line for forming a true signal on an IN output line and is responsive to a false signal on the IN/OUT bus control 5 line for forming a true signal at an OUT line The IN line and the OUT line are outputs depicted for the address selector 1202.
It will be understood that the address selector 1202 will contain other logic, timing, and control which are not important to an understanding of the present invention and therefore need not be described for a complete understanding 10 thereof.
Refer now in more detail to the portions of the circuitry of the address selector 1202 and the interface logic 1204 depicted in Figs 51 through 53 In Fig 51 there are depicted three registers that are addressable by the MINI COMPUTER These registers and their functions are as follows 15 DATAO register is an output register responsive to the logic 50 OUT to store 8 bits of information from the data lines of the I/O bus 1210 Register DATAO handles the transfer of information from the MINI COMPUTER to the IPRF, the MEMORY MODULE, or the P/B MEMORY.
The DATAO register can be represented as a PDP-11 interface register by 20 using a M 1502 bus output interface as disclosed on page 198 of the Digital Equipment Corporation manual PDP-1 1 INTERFACE MANUAL The following connections must be made Note only low order 8 bits of UNIBUS are used Bus signal BOO-B 07 are connected to M 1502 pines BEI, BF 2, BH 2, BD 2, BE 2, BEI, BHI, and BDI respectively to form the connection from the I/O bus to 25 the register To get from the register to data selector D 53 the M 1502 pins BUI, BR 2, B 52, BSI, BRI, BMI, BLI, and BL 2 are connected to bits 0-7 of the data selector D 53 Additionally, bus signal INIT is connected to M 1502 pin AEI while pin A Pl is grounded INTERFACE signal SO is attached to AMI and out to AAI forming the clock input for DATAO 30 AI register is an output register that is responsive to the logic P 2 CLK SI for storing an 8 bit address from the data lines of the I/O bus 1210 provided by the MINI COMPUTER.
This register is used only as an output register and is designed as disclosed below The register picks only the low order 8 bits from the UNIBUS and is 35 clocked when the signals Sl OUT are asserted by the address selector The register can be reset by asserting the INIT control line on the UNIBUS Note that the AI register is a counter Therefore, loading AI is normally a two step process During the first step the information is clocked from the bus into a register This is shown on the design as an enable pulse Secondly, after the information settles in the 40 registry it is loaded into the co-nter AI This is shown as the load pulse The signal which clocks the interface register is delayed to allow the outputs of the M 1502 register to settle out Then the AI counter is loaded with the value in the M 1502 register The rest of the operation is as described in the DPM interface module.
The UNIBUS input connections to M 1502 module in the AI register are the same 45 as disclosed for the DATAO register The output pin connections on the M 1502 registor only now they are attached to bits 0-7 of the AI counter Additionally, the INIT signal from the UNIBUS is applied to pin AEI of the M 1502 while pin A Pl is grounded The signal Sl is applied to pin AAI while the OUT signal is applied to the AMI pin These form the strobe pulse that strobs information into the M 1502 50 This signal is delayed until the lines in the M 1502 settle out Then the contents of the 1502 are loaded into the counter AI The AI register is an address register used to select a particular register in the DPM to address in the MEMORY MODULE or to address in the P/B MEMORY where information is to be written or from which information is to be read To this end, the AI register is connected to a decoder 55 DCI and to a data selector D 54 From D 54, the information is gated to a data selectors DSI-D 53 of the MEMORY MODULE or to data selectors DSI-D 52 of the P/B MEMORY.
The action of the AI register in controlling the DS 1 to D 53 selection circuits in the MEMORY MODULE or selection circuits DSI-D 52 of P/B MEMORY will 60 be explained in more detail in connection with the MEMORY MODULE description The decoder DCI is a conventional decoder that is responsive to the rightmost 4 bits of binary coded address information in register AI and forms an output signal on one of ten output lines designated D I through D 10, responsive to a true enable signal atl T Although the 4 bits give 16 possible combinations, only 10 65 159 I 1,570,344.
159 1,570,344 160 combinations are used In this manner, the register AI selects and causes a true signal on one of the output lines Dl through D 10 Also, at a different time, the signals on the lines Dl through D 6 are used for controlling a D 52 selection circuit which couples the output of registers in the SEED MODULE and the OUTPUT MODULE into the DPM INTERFACE MODULE Also, at still a different time, 5 the outputs Dl through D 9 from the DCI decoder are operative to select one of the registers of the IPRF into which information is to be stored from the DATAO register.
The STATUS register is an input/output register that is responsive to the logic (IN + OUT) 52 for storing control information applied on the data lines of the I/O 10 bus 1210 by the MINI COMPUTER The information stored in the STATUS register performs a number of functions, including initiation or setting of certain flip flop conditions needed in execution of the various DPM modules and the selection of modules to be used for various operations.
The STATUS register is an INPUT/OUTPUT register and thus to convert it to 15 the UNIBUS of a PDP-11 would require a M 1501/M 1502 register pair The M 1501 would be used as the input portion of the register and the M 11502 is used as the output portion of the register The full 16 data bis of the UNIBUS are used The connection of pins would be done as below indicated.
M 1502 OUTPUT portion Bus bit BOO is connected to pins BEI ,, B 01,,,,,,,, B 172 B 02,,,,,, ,, BH 2 B 03,,,,,, ,, BD 2 25,, ,, B 04 ,, ,, ,, ,, BE 2 25 B 05,,,,,, ,, BFI B 06,,,,,, ,, B Hi B 07,,,,,, ,, HI ofthe M 1501 B 08,,,,,, ,, BKI 30,, ,, B 09 ,, ,, ,,,, BJI 30 B 10,,,,,, ,, BCI ,, B 11, ,,, ,, BB I ,,B 12,,,,,,BVI B 13,,,,,, ,, ACI 35,, ,, B 14 ,, ,, ,, ,, ADI 35 B 15,,,,,, ,, BT 2 Additionally the INIT signal from the UNIBUS is connected to AEI pin of the M 1502 module while pin A Pl is grounded The signal 52 from the address selector is applied to pins AAI and ABI while the OUT signal is applied to pin AMI forming the load strobe for the M 1502 register Note that bus bit B 07 was 40connected to input pin Hl of the input module M 1501 This bit (BDONE) to be explained later must have the capability that it can be asynchronously set and reset.
The in put portion of the STATUS register is designed for the UNIBUS of the PDP-11 by using an M 1501 Bus input Interface as disclosed on Pages 196 and 197 of the above referenced manual The UNIBUS connection needed to complete this 45 design would be as follows:
161 1,570,344 161 Pin P 2 of STATUS register bit 0 is connected to the UNIBUS bit BOO N 2 1 BOI Ml 2 B 02 LI 3 B 03 KI 4 B 04 5 Jl 5 B 05 L 2 6 B 06 M 2 7 B 07 Si 8 B 08 RI 9 B 09 10 U 2 10 Bl O Pin T 2 of STATUS register bit 11 is connected to the UNIBUS bit Bl I 52 12 B 12 R 2 13 B 13 NI 14 B 14 15 Pl 15 B 15 Additionally the signals 52 and IN from the address selector are connected to pins K 2 and J 2 respectively and form gating signals which gate the information in the STATUS register onto the UNIBUS Again bit 7 must be handled specially in that it feeds from pin AI of the M 1501 module to pin DD and from there onto the 20 UNIBUS.
Fig 53 shows a schematic and block diagram of the STATUS register as well as a block diagram of the decoder 1218 which is connected to the output of the STATUS register The STATUS register includes three flip flops labelled fl, f 23 and f 3 which are connected to the input of a decoder DC 2 The decoder DC 2, 25 responsive to the combination of bits stored in flip flops fl, f 2 and f 3, forms, at any one time, a control signal at one and only one of the output circuits DIGO, SMGO, CMGO, OMGO, PMGO, and BMGO It will be recognized that the foregoing outputs are the control lines which call the operation of the DECODE I, SEED, CHANGE, OUTPUT, PIPE and BRIGHTNESS MODULES 30 The STATUS register has two flip flops identifid as m, and m 2 which are connected to the input of a decoder DC 3 and the input of an OR gate 1220 The flip flops m, and m, have a total of four possible combinations of states When either flip flop m, or m 2 is in a 1 state, the OR gate 1220 forms a true signal at the M output This indicates that the area in the MEMORY MODULE or P/B 35 MEMORY is being selected by the m, and m 2 flip flops The STATUS register also has a flip flop PBM and when in a 0 state, the outputs of decoder DC 3 are used to address the MEMORY MODULE, and when in a 1 state, the outputs of the decoder DC 3 are used to address the P/B MEMORY.
Table 42 depicts the state of the flip flops m 1 and m 2 and the corresponding 40 outputs Mle, M 2 e, and M 3 e which receive a true signal when the PBM flip flop is 0 Table 43 depicts the state of the m, and m 2 flip flops and the corresponding outputs M Ie and M 2 e receiving true signals when the PBM flip flop is a 1 AND gates 1232, 1234 and 1236 have one input coupled to the outputs of the decoder DC 3 to the input of the MEMORY MODULE when the flip flop PBM is in a 0 45 state AND gates 1238 and 1240 couple only the outputs Mle and M 32 e to the P/B MEMORY when the flip flop PBM is a 1 The outputs Mle, M 2 e, and M 3 e, in turn, control the DSI, D 52 and D 53 selection circuits in the MEMORY MODULE for areas 1, 2 and 3, respectively, or DSI or D 52 of the P/B MEMORY The decoder DC 3 has an enable input which is connected to the M output of the OR gate 1220 The decoder DC 3 only; forms a true signal at one of its three outputs when the signal at the M output is true The OR gate 1220 also has its output connected through a logical signal inverter 1222 to the M output Theb T output has 5 a signal which is complementary to that of the signal at the M output.
The STATUS register also has five flip flops identified as DELOP, FIRST, LAST, PBM, DIINIT and DPM The aforementioned five flip flops are used to provide control signals from the DPM INTERFACE MODULE to other modules in the DPM Using the same system of notation described above, the primed and 10 unprimed outputs of the flip flops are shown as outputs at the bottom of Fig 53.
Looking more specifically at these flip flops, flip flops FIRST and LAST are used to control the 1 and 0 states of flip flops Bl FIRST and PFIRST in the BRIGHTNESS and PIPE MODULES The unprimed output of the PBM flip flop is used as one input to an AND gate 1231 for forming the PBWE signal, a write 15 enable signal to the P/B MEMORY If the PBM flip flop is in a I state, a read operation takes place to the P/B MEMORY If the PBM flip flop is in state 0, no operation takes place in the P/B MEMORY.
The DELOP flip flop has its unprimed output connected to the OUTPUT MODULE The OUTPUT MODULE also has a DELOP flip flop The DELOP flip 20 flop is used to set the DELOP flip flop in the OUTPUT MODULE.
The DIINIT flip flop has its unprimed output connected to the DECODE I MODULE This flip-flop is used to prime the DECODE I MODULE prior to calling said module from the DPM INTERFACE MODULE The DPM flip flop has its unprimed output connected as a control input to the decoder DC 2 25 (Fig 53) as explained in more detail hereinafter.
Two flip flops are contained in the STATUS register to control the movement of information across the I/O bus 1210 and will now be described The interrupt enable flip flop (bit 6 of the output portion of the STATUS REGISTER) is set to a true (or one) state if upon completion of the called module, an interrupt is to be 30 generated If an interrupt is not desired, then the completion of the called module can be monitored by testing the second flip flop, the BDONE flip flop (STATUS REGISTER bit 7) As long as BDONE is set to 0 this indicates that the called module has not completed Upon completion the called module sets the BDONE flip flop to a value 1, thus indicating to the MINI COMPUTER that the operation 35 is complete The BDONE flip flop can be designed for a PDP-1 1 interface by considering the design of Fig 56 A.
BDONE is affected in the above described PDP-1 Ll 1 interface modules by attaching UNIBUS data line B 07 to M 1501 pin H I; the asynchronous set (s) input is attached to pin bl; the clock input, to pin D 2; the asynchronous reset (R) to pins 40 Cl and Fl; and attaching output pin Al to pin DD All the pins mentioned above deal with the flip flop labeled RQE in the M 1501 module.
Logic and control cirucit 1252 are provided for controlling the state of the BDONE flip flop and for the generation of interrupts If the circuit P 2 CLK + SMEND + CMEND + OMEND + DIEND + BMEND + PIPEND is set to 1, and 45 the interrupt enable bit is set module 1252 will generate an interrupt to the MINI computer The interrupt control module can be made to interface with a PDP1 11 by using the module M 782 Interrupt Control Module as disclosed on Pages 317 and 318 of the above referenced manual In Fig 53 this would mean that the completion circuit would be attached to pin Ul of the module while the interrupt 50 enable signal would attach to pin Ul The M 782 module would then proceed to obtain control of the UNIBUS and generate an interrupt from pin Ml The interrupt vector address in the M 782 module would be gated onto the UNIBUS through pins E 2, Ll, N 2, Fl, F 2, and Hl.
Referring back to Fig 51, and I register is connected to the output of a DSI 55 selection circuit which in turn has three data inputs connected to the output of the D 55 selection circuit in the MEMORY MODULE, the D 52 selection circuit in the DPM INTERFACE MODULE, and the D 56 selection circuit in the P/D MEMORY The DS 2 selection circuit in turn has six data input circuits connected to the outputs of the registers SLINE, SLN, ONOC, and OAR of the SEED 60 MODULE, the registers OAR and OLN of the OUTPUT MODULE, register DOI in the DECODE I MODULE, and the STATUS register The D 52 selection circuit is of the same type described hereinabove in connection with the ENCODE MODULE and has six control circuits with the corresponding numbers to those 162 1,570,344 162 used for the DATA input circuits When one of the control input circuits (i e, I) receives a true signal, the correspondingly numbered data input circuit (i e, I) is connected through the D 52 selection circuit to the input of the D 52 selection circuit The DSI selection circuit is of the same type as the D 52 selection circuit and has control inputs at the sides thereof, labeled the same as the corresponding data 5 inputs The DSI selection circuit couples a data input to its output when the corresponding control input, shown along its side, receives a true signal.
The address selector 1202 is shown in the left hand corner of Fig 51 As shown the address of a desired DPM register is gated from the bus into the address selector The selector decodes the address and asserts one of the three signals SO, 10 SI or 52 Additionally the control lines from bus are also gated into the address selector They are decoded into an IN signal if data are to be input into the MINI; an OUT signal is generated if data are to be output from the MINI to the DPM.
Finally the P 2 CLK pulse is used to generate the DONE signal to the I/O bus 1210 indicating that the requested operation is complete 15 The address selector 1202 shown in Fig 51 can be interfaced to a PDP-11 by using an M 105 address selector as disclosed in pages 311 and 312 of the above referenced manual Bus lines A 01 -A 017 are attached to pins H 2, HI, Fl, V 2, U 2, Ul, UI, P 2, N 2, RI, PI, Ll, Cl, K 2, KI, D 2, E 2, and Dl respectively Additionally control lines CO, Cl from the UNIBUS are attached to pins F 2, J 2 of the M 105 20 module Pins M 2, and Nl are OR’ed together to give the OUT signal while pin M l gives the IN signal Also, pins 52, T 2, and R 2 give the signals SO, Si and 52 respectively The SSYN signal on the M 105 is grounded and the P 2 C Uk supplies the SSYN signal (DONE) to the UNIBUS.
A control counter 1213 has two flip flops Pl and P 2 These flip flops are also 25 edge trigger flip flops of the type disclosed above An OR gate 1226 is connected to the unclocked reset to O inputs of the flip flops Pl and P 2 The OR gate 1226 has its input connected to MINIT and the circuit P 2 CLK.
The control counter 1213 also has an AND gate 1228 The AND gate 1228 has one input connected to the M output of the DPM flip flop and another input 30 connected to the output CLK of a source of clock pulses CLK and CLK A source of clock pulses forms a series of recurring true pulses at the CLK and C output thereof as depicted in Fig 51.
Fig 52 is a block diagram of the IPRF The IPRF includes a group of nine registers, each of which has 8 flip flops for storing 8 binary bits of coded 35 information The registers in the IPRF each have a data input connected together in parallel to the data output of the D 53 selection circuit of Fig 51 Each of the registers of the IPRF is of type SN 74175 disclosed in the above TTL book and has an L input connected to one of gates 1230-1 to 1230-9 When one of the L inputs receives a true signal, the corresponding register stores the binary coded data from 40 the output of the D 53 selection circuit The gates 1230-I and 1320-9 are AND gates with one input connected to the output of an AND gate 1232 and the other input connected to one of the outputs Dl through D 9 of the decoder DCI of Fig.
51 The AND gate 1232 has three inputs connected to the outputs Pl of the Pl flip flop, CER of the source of clock pulses, and OUT of the I/O control 1216, all of 45 which are shown in Fig 51 Table 43 depicts the five outputs from the I/O control 1216 along with the indication of the meaning of a true signal at the corresponding output.
With the above general discussion of the DPM INTERFACE MODULE in mind, consider the actual operation The control counter 1213 has three states 50 When the DPM INTERFACE MODULE is not in operation, both the Pl and P 2 flip flops are in 0 states Both of the flip flops Pl and P 2 become true, sequentially, when data is being stored into the DATAO register from the I/O bus 1210, or when data is being read out of the I register onto the I/O bus 1210 Otherwise, only flip flop P 2 becomes true The control counter 1213 is always reset to 0 whenever an 55 operation completes after the interface of the DPM INTERFACE MODULE has been selected by the MINI COMPUTER or a MINIT signal has been formed indicating system initiation The output of OR gate 1223 is set to a 1 state whenever the DPM INTERFACE MODULE is requested, i e, SO, Si or 52 is set It should be noted that the output of the OR gate 1223 is the control for gate 1228 which 60 allows the clock pulses to be applied through the gate 1228 to the Pl and P 2 flip flops of the control counter 1213.
Following is an example of the sequence of an output operation for writing a word of information from the MINI COMPUTER into the IPRF.
The sequence of operation similar to that depicted in Fig 55 is followed 65 163 1,570,344 163 Consider the operation of writing a status word into the STATUS register To this end, the MINI COMPUTER forms an address on the address lines of the I/O bus 1210 and the status word is applied on the data lines As discussed above, a true signal is subsequently formed at the output of gate 1223 causing the clock to be enabled The proper address is decoded by the address selector 1202 which forms a 5 true signal at the 52 output The logic (IN + OUT) 52 is now true, causing a true signal at the load input of the STATUS register to store the control word applied on the data lines of the I/O bus 1210 by the MINI COMPUTER.
* The true signal at the output 1223 causes the gate 1228 to couple the CLK pulses to the clock inputs of the Pl and P 2 flip flops Since both of flip flops Pl and 10 P 2 are in a 0 state, the signals at the Pl and P 2 outputs are false Also since a true signal is not formed at the SO output, a true signal is formed at the SO output As a result, the logic (Pl + P 2) 50 is true, causing the P 2 flip flop to be set to a I state at the following CLK pulse The logic P 2 CEK becomes true which in turn is applied to the logic and control circuit 1206, causing it to set the BDONE flip flop bit 7 of 15 STATUS) to a 1 state, causing a true signal on the BDONE line The P 2 CEK also is applied to address selector 1202 thereby causing the bus to be free for other operations When P 2 CEKis set to a 1 state, gate 1226 forms a true signal and flip flops Pl and P 2 reset.
Next consider the sequence of operation that allows for the outputing of 20 information to the AI register The sequence of operation is somewhat similar to that described for the STATUS register.
Initially the address of the AI register is put onto the bus 1210 by the MINI COMPUTER This address is received and decoded by the address selector 1202 and as a result the S I and OUT lines of the circuit are asserted The S I signal causes 25 gate 1223 to fire thereby initializing the clock enable gate 1228 Since 51 is asserted, the circuit (P Tl+ 2) SO is true and on the first CLK pulse the P 2 flip flop is set to a 1 state.
Initially, recall that lines S I and OUT were asserted These are OR’ed together and form a true pulse at the enable input of the AI register Recall that this enable 30 pulse clocks the information from the bus into a storage register The pulse P 2.SL OUT C loads the information from this register into the counter AI The P 2.CLK signal causes control counter 1213 to be reset to 0 Additionally the P 2.CLK pulse is applied to 1202 address selector which in turn supplies a done signal to the bus The MINI COMPUTER responds by freeing the bus for future 35 operations.
It should be noted here that the output of the AI register is used as an address into the IPRF, the DPM MEMORY MODULE, or the P/B MEMORY MODULE.
Once the AI register is loaded initially all subsequent output operations to the DATAO register cause the AI counter to be counted up by one This is so since the 40 circuit P 2 CLK SO would then be true This design is simply a means whereby a sequence of consecutive memory locations can be filled by placing a starting address into AI and then repeatedly writing to the DATAO register.
Next, the MINI COMPUTER provides a data word which is to be stored into the DATAO register and subsequently transferred to the IPRF To this end, the 45 MINI COMPUTER again follows the sequence of operation depicted in Fig 55.
Thus, the MINI COMPUTER applies an address on the address lines and a data word on the data lines and a true signal on the IN/OUT line, indicating that an output operation is taking place by the MINI COMPUTER The address on the address lines causes the address selector 1202 to form a true signal at the SO output 50 and the true signal on the IN/OUT line causes a true signal at the OUT output of the address selector 1202 Therefore, the logic (Pl + P 2) m 5 becomes true Thus, during the operation of the control counter 1213, the Pl flip flop is set to a I state rather than the P 2 flip flop The logic SO OUT also becomes true, causing the DATAO register to store the data word applied on the I/O bus 1210 by the MINI 55 COMPUTER.
Referring now to the STATUS register, both the m, and m 2 flip flops are 0 since information is not being written into the MEMORY MODULE or P/B MEMORY Accordingly, a true signal is formed at the M Woutput of the inverter 1222 Accordingly, the logic Pl M is now true, causing the D 53 selection circuit to 60 couple the content of register DATAO through to the input of the IPRF registers shown in Fig 52 The address word stored in register AI causes the decoder DC 1 to form a true signal at one of the outputs D 1 through D 9 which in turn selects the one of the registers in the IPRF into which the word contained in register DATAO is to be stored Assume for purposes of explanation that the address in register AI 65 164 1,570,344 164 1,570,344 165 16 causes a true signal at the D I output corresponding to the TL register A true signal is being formed at the OUT output and the source of clock signals forms a true signal at the CL-K output True signals are now formed at the outputs PI, CLK and OUT, causing the AND gate 1232 to form a true signal The true signal at the output of AND gate 1232 in combination with the true signal at the DI output of the decoder DC 1 5 causes AND gate 1230-1 to apply a true signal to the TL register, causing the contents of DATAO to be loaded into the TL register On the next CLK pulse flip flop Pl is reset to O and flip flop P 2 is set to 1 When the P 2 ELK pulse is formed the address selector send a DONE pulse to the bus indicating to the MINI COMPUTER that the operation of the DPM INTERFACE MODULE is 10 complete The MINI COMPUTER responds to the true signal at the DONE control line and drops control of the bus.
An input operation for reading information from the DPM to the MINI COMPUTER will now be described.
Information is read from one of the registers SLINE, SLN, ONOC, OAR of the is SEED MODULE or one of the registers OAR and OLN of the OUTPUT MODULE D 13 from the DECODE 1 MODULE, or from the STATUS register.
Initially, the MINI COMPUTER stores a control word in the STATUS register as described above Also, an address word is stored in register AI as described above.
Next a word is to be sent over the data lines of the I/O bus 1210 from the DPM 20 INTERFACE MODULE to the MINI COMPUTER Following the operation depicted in Fig 56, the MINI COMPUTER initially applies an address on the address lines and after the signals have been settled, forms a true signal on the IN line and on the SO line The true signal at SO causes OR gate 1223 to fire which causes the AND gate 1228 to a ply CLK pulses to the clock input of the Pl and P 2 flip 25 flops The logic (‘PI P 2) SO is true, causing the Pl flip flop to be set to a 1 state, thereby forming a true signal at the Pl output The control word stored in the STATUS register causes both m, and m, flip flops to be in a 0 state and accordingly a true signal is formed by the inverter 1222 at the Woutput The true signal at the Woutput enables the decoder DCI to form a true signal at one of the outputs Dl 30 through D 6 corresponding to the address contained in register Al Additionally, the address selector 1202 forms a true signal at the IN output The true signal at the IN output in combination with the true signal of one of the outputs Dl through D 7 causes the D 52 selection circuit to couple one of the registers from the SEED MODULE or the OUTPUT MODULE or the DECODE I MODULE or the 35 STATUS register through to the input of the DSI selection circuit Additionally, the logic Pl Mi is true, causing the D Sl selection circuit to couple the same register through to the input of the I register.
The logic P 1 E becomes true, causing the I register to load the data from the selected register into the I register The true signal now formed at the Pl output 40 of the Pl flip flop and the following CLK pulse causes the P 2 flip flop to be set to a 1 state and the Pl flip flop to be reset to a 0 state, causing a true signal at the P 2 output The true signal at the P 2 output causes the logic P 2 CLK to become true.
The logic 50 P 2 CLK IN is now true, causing the DATAI gate to gate the data in the I register onto data lines of the I/O bus 1210 Additionally, the logic and control 45 circuits 1206 set the BDONE flip flop to a 1 state, causing a true signal on the BDONE control line of the I/O bus 1210, thereby signalling the MINI COMPUTER that a data word is available for reading The true signal at the P 2.CLK output causes the OR gate 1226 to reset the Pl and P 2 flip flops to a 0 state, thereby terminating the operation of the DPM INTERFACE MODULE 50 Consider now the way in which the information is written to the MEMORY MODULE by the MINI COMPUTER In the manner discussed above, the MINI COMPUTER causes a control word to be stored in the STATUS register, an address word to be stored in the AI register, and a data word to be stored in the DATAO register It should be noted that the control word now stored in the 55 STATUS register causes the DPM flip flop to be in a 0 state, the PBM flip flop to be in a 0 state (selecting the MEMORY MODULE), and either or both of the m 1 or m 2 flip flops to be in a I state (selecting memory area 1, 2 or 3 in the MEMORY MODULE) As a result, the OR gate 1220 forms a true signal at the M output The true signal at the M output causes the decoder DC 3 to be enabled and it forms a 60 true signal at one of the outputs Mle, M 2 e, or M 3 e, depending upon the states of flip flops m, and m 2 as depicted in Table 42.
After the MINI COMPUTER has stored a data word into the DATAO Gating circuits are depicted by logical equations using the outputs of other modules, flip flops, etc, as to designate terms in the equations 65 1,570,344 selection circuit to couple the DATAO register to the input of the D 54 selection circuit of the MEMORY MODULE Additionally, the MINI COMPUTER applies a true signal on the IN/OUT line on the I/O bus, causing a true signal at the OUT output Thus, each of the signals PI, M PBM and OUT are now true, causing the AND gate 1230 to form a true signal at the IWE output The true signal at the IWE 5 output is a write enable pulse for the MEMORY MODULE The true signal at the IWE output causes the data word in the DATAO register to be written into the address and the memory area of the MEMORY MODULE specified by the Al register.
The P 2 flip flop is subsequently set to a 1 state in the manner discussed above 10 which again causes the Al register to be incremented, thus allowing the next memory location in the MEMORY MODULE to be selected for writing In this manner, it is possible to write into consecutively addressed addresses in one of the memory areas of the MEMORY MODULE with one write to the Al register and a series of writes to the DATAO register 15 Consider now the way in which an input operation takes place from the MEMORY MODULE to the MINI COMPUTER The sequence of operation is as depicted in Fig 56 The STATUS register and AI register are loaded with a control word and an address word, respectively, as discussed above One or both of the flip flops m 1 and m 2 is now true, causing a true signal at the M output of the OR gate 20 1220 Thus, the decoder DC 3 and associated circuitry (Fig 52) are also enabled to form a true signal at one of the outputs Mle (DSI MEMORY MODULE), M 2 e (D 52 MEMORY MODULE), and M 3 e (D 53 MEMORY MODULE), selecting DSI, D 52 or D 53 for memory areas 1, 2 and 3 of the MEMORY MODULE It should be noted that should a read be taking place from the P/B MEMORY, a true 25 signal would be formed at PB M and a signal would be formed instead at one of the outputs Mle (D 52 P/B MEMORY) or M 2 e (DSI P/B MEMORY).
Returning to the example, once enabled, the MEMORY MODULE reads out from the memory location specified by the address contained in the register AI.
The logic Pl M PM Fis now true, causing the DSI selection circuit to couple the 30 information read out from the addressed location in the MEMORY MODULE to the input of the I register The logic Pl CLK becomes true, causing the I register to store the word from the MEMORY MODULE.
The true signal at the Pl output causes the P 2 flip flop to be set to a 1 state and the Pl flip flop to be reset to a 0 state at the following CLK pulse, causing a true 35 signal at the P 2 output The logic P 2 CLK again becomes true, causing true signals at output BDONE and causing the input operation to terminate.
The address selector is forming a true signal at the SO output, causing the logic SO.P 2 CECWIN to become true and causing the DATAI gate to gate the data stored in the I register onto the data lines of the I/O bus 1210 The true signal at the 40 BDONE control line causes the data to be read by the MINI COMPUTER.
Subsequently, the P 2, BDONE, and Pl flip flops are reset as discussed above, causing the operation to terminate.
Again, consecutive memory locations may be read from the MEMORY MODULE, using only one write into the Al register, simply by incrementing the 45 address as discussed above.
Specific DPM functions such as the operation of the SEED MODULE, the CHANGE MODULE, the OUTPUT MODULE, the DECODE 1 MODULE, the PIPE MODULE, and the BRIGHTNESS MODULE are also initiated and controlled by the DPM INTERFACE MODULE These operations are initiated 50 by ( 1) writing the proper information into the MEMORY MODULE; ( 2) writing appropriate information into the registers of the IPRF; and ( 3) writing a control word into the STATUS register, thereby setting the proper combination of function flip fips f I, f 2, and f 3, and setting the DPM flip flop to a 1 state, enabling the decoder DC 2 to form a true signal at one of the outputs SMGO, CMGO, Dl GO, 55 OMGO, PMGO, and BMGO, thereby calling operation of the corresponding SEED, CHANGE, OUTPUT, PIPE and BRIGHTNESS MODULES This then starts the proper function and operation in the DPM The MINI COMPUTER monitors the operation waiting for a “finished” signal to be formed, at one of the outputs SMEND, CMEND, DIMEND, OMEND, PIPEND, or BMEND by the 60 SEED, CHANGE, DECODE 1, OUTPUT, PIPE and BRIGHTNESS MODULES, respectively.
With reference to the I/O control 1216, it will be seen that a true signal at any one of these outputs causes the I/O control 1216 to apply a true signal to the MINI COMPUTER via the I/O bus 1210 which in turn causes the MINI COMPUTER to 65 166 1,570,344 166 interrupt its operation and subsequently read the appropriate results from the DPM Reading of the results from the DPM involves reading the data from the registers SLINE, SLN, ONOC and OAR of the SEED MODULE or registers OAR and OLN from the OUTPUT MODULE as discussed above Alternatively, or in addition, information may be read from the proper MEMORY MODULE area 5 It should be emphasized that the DPM INTERFACE MODULE shown hereinabove is not the only way in which the interface module might be constructed, but is shown by way of example.
XVIII MEMORY MODULE 10 Fig 57 is a schematic diagram of the MEMORY MODULE On the right of Fig 57 are shown the input/output control lines used for controlling the MEMORY MODULE and the information input/output lines Heavy lines are used to designate multiple signal data lines.
The MEMORY MODULE includes three random access memories 1310, 1312 and 1314 forming MEMORY MODULE areas 1, 2 and 3, respectively The 15MEMORY MODULE areas 1, 2 and 3 are TTL RAM type SN 7489, disclosed at page 220 of the above TTL book Each memory has 256 memory locations, each of which contains 8 binary coded bits The aforementioned type of memory is only used herein by way of example and, within the scope of the present invention, may be of different sizes and types, depending upon the particular application In most 20 applications it may be desirable to replace the TTL RAM memories with one or more disc files to give greater storage capacity.
Associated with each of the memories 1310, 1312 and 1314 are address decoders 1316, 1318 and 1320, respectively Each address decoder receives a composite binary coded signal and decodes it into signals suitable for addressing 25 memories 1310, 1312 and 1314.
Also within each of the memories 1310, 1312 and 1314 is a memory information register (MIR) Each memory information register has its input connected to the output of a D 54 selection circuit from which it receives 8 binary bits of information for storage in one of the memory locations of the corresponding 30 RAM memory Each of the MIR registers forms a part of the RAM memory disclosed in the above TTL book Also included in each of the memories 1310, 1312 and 1314 is an MDR which forms the information output for the corresponding RAM memory 8 binary coded bits are applied as output at each of the MDR circuits when information is being read out of the corresponding memory 35 Writing takes place in one of the memories 1310, 1312 and 1314 by applying an information word to the corresponding MIR and an address word to the corresponding address decoder After the signals have stabilized at the foregoing inputs, a true write enable signal is applied at the WRITE ENABLE input to the memory, causing it to write the information word applied at the MIR input to the 40 address specified by the address word applied to the address decoder Reading takes place in a memory merely by applying the address of the desired location to the address decoder for the memory, thereby causing the word at the corresponding address to be read out and applied at the MDR output of the memory 45 Selection circuit DSI through D 55 are used for gating address and data into and out of the MEMORY MODULE The selection circuits DSI through D 55 are data selectors of the type disclosed above Connected to each data selector are heavy lines to designate information lines and thin lines to designate control signal lines Each heavy (information) line is numbered and has a correspondingly 50 numbered thin (control) line A true signal at the control input line causes signals applied at the corresponding information lines to be coupled through to the output of the data selector Thus, for example, selection circuit D 51 couples information input I to its output responsive to a true control signal at the control input 1 shown on the left side 55 A WRITE ENABLE circuit 1322 generates write enable signals at its WE output The WRITE ENABLE circuit 1322 has a control input line MEMGO connected to an OR gating circuit 1324 and another input connected to the MINIT output of the MINI COMPUTER One-shot multi-vibrators Ml and M 2 have outputs using the same symbols as the corresponding multi-vibrator The primed 60 output receives a true signal when the one-shot multi-vibrator is in a 0 state and the unprimed output receives a true signal when the multi-vibrator is in a 1 state The one-shot multi-vibrators are normally in a 0 state and when 1,570,344 167 167 168 1,570,344 168 a true signal is applied on the line MEMGO, the multi-vibrators are triggered to a 1 state where the true signal is removed at the primed output and a true signal is applied at the unprimed output To be explained in more detail, the one-shot multi-vibrators automatically reset to a 0 state a prefixed time interval after being triggered to a 1 state The delay time for the one-shot multivibrator M 2 5 is longer than that of the M l for the reasons explained hereinafter Also included in the WRITE ENABLE circuit 1322 is a flip flop FF The flip flop FF is of type SN 7474 disclosed in the above TTL book The flip flop FF has I and 0 states with outputs FF and FF’ (the latter not shown) which receive true signals when the flip flop is in I and 0 states, respectively The flip flop FF has two inputs for controlling 10 the setting and resetting thereof, and a clock input The clock input is shown on the lower left hand side of flip flop FF The upper left hand input of the flip flop FF is connected to a source of voltage (Vcc), not shown, which always applies a true signal at the corresponding input at all times The upper left hand input of the flip flop FF causes the flip flop to be set to a I state when a clock signal is applied at the is lower left hand side input of the flip flop The input shown along the bottom side of flip flop FF resets the flip flop FF to a 0 state without clock.
Also included in the WRITE ENABLE circuit 1322 are AND gates 1326 and 1328 and an OR gate 1330 AND gates 1330, 1332 and 1334 apply the control signals to the WRITE ENABLE input on the memories 1310, 1312 and 1314, respectively 20 The modules which communicate with the MEMORY MODULE of Fig 57 and whether information is read out from the MEMORY MODULE and/or written into the MEMORY MODULE, are summarized as follows:
DECODE I MODULE read DECODE II MODULE read 25 ENCODE MODULE -write (EWI) PIPE MODULE -write (P 19) B RIGHTNESS MODULE write (B 13) DPM INTERFACE MODULE read and write (IWE) 30 The sequence of operation of the MEMORY MODULE during a write operation in one of the memories 1310, 1312 and 1314 will now be described with reference to the timing diagram of Fig 58 A write operation is initiated or called by the DPM INTERFACE MODULE or the PIPE MODULE or the 35 BRIGHTNESS MODULE or the ENCODE MODULE The calling signal is applied on the output control line shown in parentheses after the name of each module above and being shown as input to the OR gate 1324 The calling module applies a calling signal to the OR gate 1324 It in turn applies a true signal at the MEMGO output which triggers the one-shot multi-vibrators Ml and M 2 to a 1 40 state In addition, the true signal at the M l output of the M l multivibrator causes a true signal to be applied at the clock input of the FF flip flop, acting as a clock, causing the FF flip flop to be set to a I state The time delay built into the M l multivibrator is sufficient to allow the signals on the address lines to the DSI-D 53 selection circuits and on the information lines to the D 54 selection circuit to settle 45 out After the one-shot multi-vibrator M l resets to a 0 state, a true signal is formed at the M 1 output thereof Additionally, the FF flip flop is still in a 1 state, and therefore both inputs to the AND gate 1328 receive a true signal and form a true signal at the WE output The true signal at the WE output is applied to the inputs of AND gates 1330-1334 Each of the AND gates 1330-1334 has a second input 50 which controls the particular one of the memory areas 1, 2 and 3 into which information is to be written from the selection circuit D 54 To be explained in more detail, the signals from the SWITCH MATRIX of Fig 59 or from the DPM INTERFACE MODULE determine which of the RAM areas into which information is to be written 55 Thus, a true signal at the IWE output of the DPM INTERFACE MODULE causes the second input of each of the AND gates 1330-1334 to be true, thereby causing each of the AND gates to apply a WRITE ENABLE signal to the corresponding RAM memory Thus, the word of information applied at the output of the D 54 selection circuit is written into each of the memory areas 1, 2 and 3.
Normally, writing into the memory areas 1, 2 and 3 is controlled by the 5 SWITCH MATRIX To be explained in more detail, the area into which writing is to take place from the ENCODE MODULE is determined by true signals at the 531, 532 and 533 outputs of the correspondingly labeled flip flops of the SWITCH MATRIX Thus, a true signal at the 531 output causes AND gate 1330 to receive true signals at both inputs and thereby apply a WRITE ENABLE circuit to the 10 memory area 1, causing a write operation only in that memory area Similarly, true signals at the 532 and 533 outputs of the SWITCH MATRIX cause writing to take place in the memory areas 2 and 3, respectively However, it should be noted that a write operation from the interface module does not use the SWITCH MATRIX.
This is shown by the addition of IWE to the WRITE ENABLE gates 1330, 1332 and 15 1334.
In summary then it should now be understood that the outputs of EOP from the ENCODE MODULE of D 53 from the PIPE MODULE, of D 53 from the BRIGHTNESS MODULE, and of D 53 from the DPM INTERFACE MODULE, are coupled to the inputs of the D 54 selection circuit A true signal at the EWI, 20 P 19, B 13, or IWE outputs from the ENCODE, PIPE, BRIGHTNESS, and DPM INTERFACE MODULES, respectively, causes the D 54 selection circuit to couple outputs from the corresponding modules through to the MIR input of the memory areas 1, 2 and 3, respectively The DSI, 2 and 3 selection circuits couple the addresses to the inputs of the corresponding address decoders 1316, 1318 and 1320 25 By way of example, a true signal at the DMI 1 output of the DECODE I MODULE, and a true signal at the 511 output of the SWITCH MATRIX cause the D 51 selection circuit to couple the output of register MARI of DECODE I MODULE to the input of address decoder 1316.
The D 55 selection circuit couples the information being read out of the 30 memory areas 1, 2 and 3 to the inputs of the DECODE I, II and DPM INTERFACE MODULES By way of example, a true signal from the Mi E output of the DPM INTERFACE MODULE or from the output DM 11 from the DECODE I MODULE, in combination with a true signal at the S 11 output of the SWITCH MATRIX, or a true signal at the D 521 output of the DECODE II 35 MODULE, in combination with a true signal at the 521 output of the SWITCH MATRIX, will cause the information from MDR of memory area I to be coupled through to the output of the D 55 selection circuit.
After sufficient time for the signals to be applied at the output of the D 55 selection circuit are stabilized to the input of the modules receiving the signals, the 40 M 2 multi-vibrator automatically resets to a 0 state, causing a true signal at the M 2 output, which in turn causes both inputs of the AND gate 1326 to be true and thereby apply a true signal to one input of the OR gate 1330 The OR gate 1330 in turn applies a true signal to the reset input of the flip flop FF causing it to be reset to a 0 state, thereby removing the true signal at the FF output This, in turn, causes 45 the AND gate 1328 to terminate its true signal at the WE output, terminating the WRITE ENABLE signal to the memory areas 1, 2 and 3.
XIX SWITCH MATRIX The SWITCH MATRIX of Fig 59 has nine flip flops designated S 1-513, 521-523, and 531-533 The flip flops are set to allow the DECODE 1, DECODE 50 II and ENCODE MODULES to read and write in the proper MEMORY MODULE areas (Fig 57) The flip flops are labeled as follows: Sij where i = I designates DECODE I; i = 2 designates DECODE II; i = 3 designates ENCODE, and where j = 1 identifies MEMORY MODULE area 1; j = 2 designates MEMORY MODULE area 2, and j = 3 designates MEMORY MODULE 55 area 3 With reference to the SWITCH MATRIX of Fig 59, and the description of the DECODE I, DECODE II and ENCODE MODULES, it will be recalled that the DECODE I and II MODULES always read from memory, whereas the ENCODE MODULES always writes in memory Thus, when flip flop Sl l is in a 1 state, it designates that DECODE I MODULE is to read 60 from MEMORY MODULE area 1 If flip flop 521 is in a I state, it designates that the DECODE II MODULE is to read from MEMORY MODULE area 1, and if the 1,570,344 169 169 531 flip flop is in a I state, it designates that the ENCODE MODULE is to write in MEMORY MODULE area 1 In addition to the flip flops, the SWITCH MATRIX has gates 1410 through 1440, signal inverters 1442 and 1444, and an SP flip flop which controls the setting and resetting of the above-mentioned flip flops responsive to control signals from the rest of the system The input/output control signals for controlling the operation of the SWITCH MATRIX are shown along the right hand side of Fig 59, along with the modules from which the signals originate.
The flip flops are all of type SN 7474 having the characteristics disclosed above.
Consider now generally the operation of the SWITCH MATRIX As mentioned above, the SWITCH MATRIX is used for controlling the operation of the 10 MEMORY MODULE Normally, the MEMORY MODULE will be used in manipulation of seeds A seed must be read, acted upon, and written out since there is no guarantee that the output length of a new seed will be less than the input length of the current seed There must be at least two memory areas for reading and writing the seeds Additionally, in accordance with preferred embodiment of 15 the present invention, the “best seed” (i e, the one with the shortest physical length) is always retained during the course of locating the seed This is advantageous since it saves regeneration time upon completion of the seed finding process By virtue of the last mentioned feature, a third memory area was added to the MEMORY MODULE system During the operation of the DPM SYSTEM, 20 the normal method of reading and writing in the memory area is through the DECODE I and DECODE II MODULES and the ENCODE MODULE The routing of these modules to the proper memory areas is accomplished under control of the SWITCH MATRIX.
Turning now more specifically to the SWITCH MATRIX but still speaking 25 generally of its operation, initially the proper flip flops S 11-513, 521523, and 531-533 are set by the calling modules (SEED, CHANGE, OUTPUT, PIPE, REVOLVE, and BRIGHTNESS MODULES) The SWITCH MATRIX is set up so that when it is clocked (by a signal through gates 1410 and 1412-1416), the MEMORY MODULE area last written into from the ENCODE MODULE will be 30 enabled for reading out information to the DECODE I and DECODE II MODULES This is done by setting the proper one of the flip flops 511-513, 521-523, and 531-533 The flip flops 531, 532 and 533 which control writing from the ENCODE MODULE, have control circuitry for appropriately setting these flip flops so that if the current write area contains the best seed, it is not 35 overwritten at a later time.
The SP flip flop indicates whether the area just read contains the sced If in a 0 state it indicates that the area just read does not contain the seed and can be overwritten If the SP flip flop is in a 1 state, it indicates that the area just read contains the seed and can not be overwritten For example, assume flip flop SP is in 40 a 0 state and reading is taking place in area 2 and writing in area I of the MEMORY MODULE Flip flops 531, 512 and 522 are in a 1 state The following clock from gate 1410 causes flip flops 532, Sll and 521 to be set to 1 (and flip flops 531, 512 and 522 to be reset to 0), causing a read from area 1 and a write in area 2 of the MEMORY MODULE Assume now for example that the SP flip flop is in a 1 state 45 and reading is taking place in area 2 and writing in area I of the MEMORY MODULE Flip flops 531, 512 and 522 are again still in a 1 state The following pulse from gate 1410 now does not reach flip flop 532, it being blocked by gates 1430 and 1438 due to the false signal at SP Insteadthe pulse from gate 1410 in combination with true signals at outputs SP, 53 Tand 523 causes the gates 1426 and 50 1436 to set flip flop 533 to a 1 state, causing writing, not in area 2, but area 3 of the MEMORY MODULE Additionally, flip flops Sl I and 521 are set to 1 states, again causing reading in area 1 As a result, writing takes place in area 3 and the seed in MEMORY MODULE area 2 is not overwritten but is saved.
In summary then, the DECODE I and II MODULES read from MEMORY 55
MODULE area (e g, area 2); the ENCODE MODULE writes to some other MEMORY MODULE area (e g, area 1) and the area in which reading and writing take place is determined by the states of the flip flops Sll-531, 512-532, 513-533.
Gating circuits are depicted by logical equations using the outputs of other 60 modules, flip flops, etc, as to designate terms in the equations.
Consider now an actual example of the operation of the SWITCH MATRIX of Fig 59 and the MEMORY MODULE of Fig 57 Table 44 shows an example of an iso-entropicgram and will be used in illustrate the operation of the system Table 45 indicates the sequence of operation while performing the revolve operation 65 I 1,570 344 1711,7,411 indicated along the right hand side of Table 44.
Initially, the MINI COMPUTER and DPM INTERFACE MODULE store line 0 of the iso-entropicgram in MEMORY MODULE area I as described above.
Line 0 is depicted at the beginning of Table 44 The SEED MODULE is then called by the MINI COMPUTER A true signal is formed at the SM I output of the SEED 5 MODULE, causing the flip flops S I I, 531 and 522 of the SWITCH MATRIX to be set to a I state The SEED MODULE then calls the operation of the DECODE I MODULE The DECODE I MODULE forms a true signal at the DMI 1 output, causing the logic DM 1 Il SI I to become true, thereby causing the DSI selection circuit to couple the output of the D 54 selection circuit to the input of the address 10 decoder 1316 and causing the D 55 selection circuit to couple the output MDR in MEMORY MODULE area I to its output Thus, the DSI selection circuit gates the address in the MARI register of the DECODE I MODULE to the address decoder of MEMORY MODULE area 1 and the D 55 selection circuit gates out from MEMORY MODULE area 1 back to the calling module (the DECODE I 15 MODULE) Since a one line revolve operation takes place, the SEED MODULE forms a true signal at the SM 5 output (asserts SM 5), thereby indicating that MEMORY MODULE area I contains the best seed so far and then calls the operation of the REVOLVE MODULE.
The REVOLVE MODULE then forms a true signal at the RM 8 output 20 thereof, causing gates 1410 and 1412-1416 in the SWITCH MATRIX to form a clock pulse which sets flip flops S I I, 521 and 532 to a true state and resets flip flops 522 and 531 to a 0 state The REVOLVE MODULE then forms a true signal at the RM 12 output while the true signal is still formed at the SM 5 output This causes the Z 5 SP flip flop to be set to a I state The REVOLVE MODULE then forms line I of the 25 iso-entropicgram as depicted in Table 44 during which the DECODE I MODULE and the DECODE II MODULE both read from MEMORY MODULE area 1, under control of SWITCH MATRIX flip flops Si I and 521 and the ENCODE MODULE writes into MEMORY MODULE area 2, under control of the 532 flip flop Upon completion of this operation, control returns to the SEED MODULE 30 The SEED MODULE then forms a true signal at the SMI I output, which causes the signal inverter 1442 in the SWITCH MATRIX to apply a false or inhibit signal to the clock gates 1412-1416 The SEED MODULE also forms a true signal at the SM 12 output, causing the OR gate 1410 to apply its clock signal to the gates 1412-1416 but it is ineffective because of the inhibit signal from inverter 1442 35 Since line I of the iso-entropicgram (Table 44) is shorter than line 0, the SEED MODULE again forms a true signal at the SM 5 output, indicating that line I in MEMORY MODULE area 2 is to be saved.
The SEED MODULE now forms a true signal at the SM 12 output but since the gates 1412-1416 are inhibited, only the flip flops S l, 512 and 513 receive a 40 clock signal Also, since the flip flop 532 is in a I state, the clock signal causes the flip flop 51 2 to be set to a I state and the flip flop SI I is reset to a 0 state Thus, at this juncture the flip flops 512 521 and 532, as well as the flip flop SP, are in a 1 state as indicated in Table 45.
The SEED MODULE now reads, using the DECODE I MODULE from 45 MEMORY MODULE area 2 and determines that the system is to revolve down two lines in the iso-entropicgram and therefore calls the REVOLVE MODULE.
The REVOLVE MODULE now forms a true signal at the RM 8 output, causing the gate 1410 to apply a clock signal to the flip flops S 1, 512 and 513 and to the gates 1412-1416 At this point the SP flip flop is still in a 1 state because in this last cycle 50 it was established that area I was not to be overwritten A true signal is now formed at SM 5 because line I in area 2 is the shortest and now the possible seed and is not to be overwritten Therefore the clock signal causes the flip flops S 12, 522 and 533 to be set to a I state.
The REVOLVE MODULE now forms another signal at the RM 12 output and 55 since a true signal is still formed at the SM 5 output, flip flop SP still remains in a I state This time the I state of the SP flip flop indicates that MEMORY MODULE area 2 containing line 1 is to be saved as the best seed line to this point The REVOLVE MODULE then proceeds to revolve down two lines in the isoentropicgram After the revolve is complete, MEMORY MODULE area 3 60 contains line 3 of the iso-entropicgram Control now returns to the SEED MODULE The SEED MODULE now forms true signals at the SM 11 and SM 12 output, causing the gates 1412-1416 to be inhibited and therefore only flip flops S I, 512 and 513 receive clock signals This causes flip flop 513 to be set to a 1 state The SEED MODULE then determines that a revolve of two lines is to take 65 1,570,344 171 171 place It also determines that line 3 of the iso-entropicgram now contained in MEMORY MODULE area 3 is no shorter than line I and therefore the true signal at the SM 5 output is removed by the SEED MODULE The REVOLVE MODULE is then called, causing the revolve operation to take place.
The REVOLVE MODULE forms a true signal at the RM 8 output, causing OR 5 gate 1410 to provide clock signals to all of the flip flops in the SWITCH MATRIX.
As a result, the flip flops 513, 523 and 531 are set to a 1 state and flip flops 522 and 533 are reset to a 0 state Thus, MEMORY MODULE area 2 containing line I of the iso-entropicgram is saved The REVOLVE MODULE also forms a true signal at the RM 12 output and since a true signal is not being formed at the SM 5 output, 10 the flip flop SP is reset to a 0 state The REVOLVE MODULE now revolves line 3 down to line 5 of the iso-entropicgram and line 5 is stored into MEMORY MODULE area 1 During this revolve process, the REVOLVE MODULE calls the DECODE I MODULE, which in turn calls the MEMORY MODULE, and forms a true signal at the DMII output Since the flip flop 513 is in a 1 state, the logic 15 S 13 DM 11 is true, thereby causing the D 53 and D 55 selection circuits to couple the address to the MEMORY MODULE area 3 and couple the information read out of MEMORY MODULE area 3 via the D 55 selection circuit back to the calling module Additionally, the REVOLVE MODULE calls the DECODE II MODULE which in turn forms a true signal at the DM 21 output Since the flip flop 523 is in a 1 20 state, the logic 523 DM 21 is true, causing the gate D 53 to couple the address from the MAR 2 register of the DECODE II MODULE to the MEMORY MODULE area 3 and causing the information read out of the address location to be coupled through the D 55 selection circuit back to the DECODE II MODULE.
Finally in its output operation, the REVOLVE MODULE calls the ENCODE 25 MODULE which writes into MEMORY MODULE area 1 To this end, the ENCODE MODULE forms a true signal at the EWI output, and since the flip flop 531 of the SWITCH MATRIX is in a 1 state, the logic 531 EWI is now true, causing the DS I selection circuit to couple the address in register MAR 3 of the ENCODE MODULE through to the MEMORY MODULE area 1 Additionally, the true 30 signal at EWI causes the D 54 selection circuit to couple the output from the ENCODE MODULE through the D 54 selection circuit to the MIR input to the MEMORY MODULE area 2 The write enable circuit 1322 forms a true signal at the WE output as described above, and true signals at WE and IWE cause the AND gate 1330 to apply a write enable signal to MEMORY MODULE area 1, 35 causing it to write the output from the ENCODE MODULE Control then returns to the SEED MODULE.
The rest of the operation, while revolving through the iso-entropicgram of Table 44, may be followed with reference to Table 45.
XX P/B MEMORY 40 The P/B MEMORY depicted in Fig 60 has two memory areas 1 and 2 identified at 1514 and 1516, respectively These memory areas are RAM type memories of the same type as that disclosed hereinabove with respect to the MEMORY MODULE The memory areas are used as a read/write scratch pad while executing the PIPE and BRIGHTNESS MODULE functions The only 45 rpodules in the system with which the P/B MEMORY must interface are the PIPE, BRIGHTNESS, and DPM INTERFACE MODULES.
The P/B MEMORY has a switching flip flop SM which designates the proper read/write areas between area 1 and area 2 Thus when flip flop SM is in a 1 state, a read takes place from area 1 and a write takes place in area 2 50 Gating circuits are depicted by logial equations using the outputs of other modules, flip flops, etc, as to designate terms in the equations.
DSI and D 52 selection circuits are data selectors of the same type as that described above with respect to the MEMORY MODULE which route the signals from the PIPE and BRIGHTNESS MODULES to the proper memory address 55 decoders 1515 and 1517 Referring to the DS I and D 52 selection circuits, it will be noted that each of the logic indicated contains a term from either the PIPE MODULE or BRIGHTNESS MODULE and each of the control inputs, except for control input 5 of the DSI selection circuit, has a second term from one of the outputs from the SM flip flop In this manner, the SM flip flop is able to switch the 60 areas being used between area 1 and area 2, depending on its state If flip flop SM is in a 1 state, OR gates 1510 and 1512 cause the PIPE and BRIGHTNESS MODULES to read from P/B MEMORY area 1 and write to P/B MEMORY area 1,570,344 172 172 2 If flip flop SM is in a 0 state, OR gates 1510 and 1512 cause the PIPE and BRIGHTNESS MODULES to write in P/B MEMORY area I and read from P/B MEMORY area 2 In this connection, the addresses for reading are coupled by DSI and D 52 from the DSI selection circuit in the BRIGHTNESS memory and from the M l register in the PIPE MODULE, whereas, the addresses for writing are 5 received from the M 2 register in the BRIGHTNESS MODULE and register M 2 in the PIPE MODULE and the D 54 selection circuit in the DPM INTERFACE MODULE.
The data selector D 55 gates the data to be written into the MIR input of the P/B MEMORY areas 1 and 2 10 The data selector D 56 in the P/B MEMORY gates the information read out of memory areas 1 and 2 to the PIPE and BRIGHTNESS MODULES.
The write enable circuit 1522 is identical to the write enable circuit 1322 described hereinabove for the MEMORY MODULE Fig 58 Similar to the MEMORY MODULE, the write enable circuit 1522 has an OR gate 1524 15 (corresponding to gate 1324) which forms a true signal at the P/B GO input to the write enable circuit 1522 The P/B GO input corresponds to input labeled MEMGO in th MEMORY MODULE The OR gate 1524 has the designated inputs from the PIPE, BRIGHTNESS and DPM INTERFACE MODULES, which call the operation of the P/B MEMORY, similar to that described hereinabove with 20 respect to gate 1324 of the MEMORY MODULE.
The operation of the P/B MEMORY is similar to that described hereinabove for the MEMORY MODULE and need not be set out in detail for a complete understanding of the invention.
The input and output control signals used to control the operation of the P/B 25 MEMORY, as well as the information inputs/outputs (designated by heavy lines) are shown along the right hand side of F Ig 60 Arrows to the left indicate incoming signals and arrows to the right indicate outgoing signals with respect to the P/B MEMORY.
XXI GENERAL ORGANIZATION OF ALTERNATE DPM SYSTEM 2 A General Discussion The general organization of the alternative DPM SYSTEM of Fig 61 involves the fast seed finding method described hereinabove The alternative DPM SYSTEM of Fig 61 includes the MINI COMPUTER, the DPM INTERFACE MODULE, the DECODE I and II MODULES, and the ENCODE MODULE, all 35of which have been disclosed and described hereinabove.
Especially provided for this preferred embodiment of the invention are the following new modules: DELTA 2 MODULE, REVOLVE 2 MODULE, REVOLVE 3 MODULE, SEED 2 MODULE, OUTPUT 2 MODULE, MEMORY 2 MODULE, AUXILIARY MEMORY II MODULE, and SWITCH MATRIX 2 40 MODULE The REVOLVE 2 MODULE in conjunction with the other portions of the system depicted in Fig 61 forms a revolver for generating various lines of an iso-entropicgram, given an input line, without generating the intermediate lines of the iso-entropicgram The REVOLVE 3 MODULE is a modified version of the REVOLVE 2 MODULE which only generates the largest two or last two actual 45 occurrence values for a line of the iso-entropicgram It will be recalled that the largest two occurrence values are the ones need to determine the next line in the iso-entropicgram which is to be generated in the process of locating the seed To be explained in more detail, the DELTA 2 MODULE differs from the DELTA MODULE in that the DELTA 2 MODULE generates any line of the Delta 50 depicted, by way of example, in Table 6 The DELTA MODULE also rightshifts lines of the Delta causing shifted Delta values to be formed These shifted Delta values are provided as inputs to the REVOLVE 2 MODULE and the REVOLVE 3 MODULE and are used by these modules in their process of generating subsequent lines of the iso-entropicgram The specific implementation of these modules will be 55 described in more detail in connection with each module.
However, the method of operation of the fast seed finding implementation can be briefly summarized as follows:
1 Read the largest two actual occurrence values (Nl, N 2).
1,570,344 173 173 or 2 Compute T = MAX (HW -N 1, NI N 2) where HW = the isoentropicgram width.
3 If the system has completely revolved through the iso-entropiefgram then go to Step 6 below; otherwise go to Step 4 below.
4 Call REVOLVE 3 MODULE causing it to return N 1, N 2 of the next line in 5 the iso-entropicgram The REVOLVE 3 MODULE revolves a line of an isoentropicgram by the number of lines specified by the value T but only returns NI and N 2 of that line, not the entire line.
If NI is less than the largest occurrence value of the current seed line, store an identification of the current seed line and return to Step 2 10 6 Call REVOLVE 2 MODULE causing a revolve by the number of lines specified by T and generate the entire resultant seed line.
7 Halt.
A more complete understanding of the present invention will be had with is reference to the following discussion 15 The DECODE I and II MODULES and the ENCODE MODULE used for this alternative implementation are essentially identical in design to the DECODE and ENCODE MODULES of the first disclosure However, due to the nature of the second design, the calling sequences to these modules differ Hence the altered version of these modules appear in Figs61 A 61 H 20 As mentioned above this alternative implementation forces a different calling sequence on the DECODE and ENCODE MODULES It can be stated that this alternative implementation generates lines of the iso-entropicgram directly at the expense of using auxiliary storage while the first implementation generated a new line by revolving down by component powers of 2 while not using any auxiliary 25 storage Because the new lines are generated directly, there is no switching back and forth of control to the DECODE I and II MODULES Hence the loading or initializing circuits of these modules are somewhat shortened Also the CHANGE 2 MODULE must perform the merging of the revolved change line with the seed line This necessitates its calling on all three modules Additionally, the OUTPUT 2 30 MODULE writes its output directly to the MEMORY MODULE area 3 It, therefore, does not call ENCODE Finally, it should be noted that in this implementation the situation does not exist in which both DECODE I and DECODE II read from the same DPM MEMORY MODULE area What follows is a brief description of these three modules and the circuit changes that are 35 necessitated.
B Revised ENCODE MODULE In the previous system the ENCODE MODULE was called by the SEED, REVOLVE, and OUTPUT MODULES In the revised ENCODE MODULE for the alternative implementation only the REVOLVE 2 and CHANGE 2 MODULES 40 call the ENCODE MODULE REVOLVE 2 must call the ENCODE MODULE when it is generating a line of the iso-entropicgram; CHANGE 2 calls ENCODE during the process which merges the revolved change line and the seed line.
Since the OUTPUT 2 MODULE does not call the ENCODE MODULE, the clipping function is not performed Hence, there is no need for data selectors ED 54 45 and ED 55 As can be seen in Fig 61 A they have been omitted Now the appropriate IPRF registers are fed directly to EBL and ETL Note that the initial loading circuits of the registers EBL, ETL, and EHW have been changed to A 2 R 2 + A 2 C 5 These pulses originate in the REVOLVE 2 and CHANGE 2 MODULES respectively 50 In Fig 61 B it can be seen that the first input to data selector ED 56 has been changed from the OUTPUT MODULE to the DSI output of the CHANGE 2 MODULE The second input now comes from RI of the REVOLVE 2 MODULE.
The enabling lines of ED 56 have been changed to A 2 R 8 and A 2 C 9 Likewise the inputs to OR gate 109 has been changed to reflect clocking pulses from the 55 REVOLVE 2 and CHANGE 2 MODULES The load (L) input of the EIR register has been changed to A 2 R 2 + A 2 C 5 Additionally on Fig 61 B the input/output signals have been changed to reflect only those control and data signals that are 174 1.570 344 1741 needed Note that these signals come only from the REVOLVE 2 and CHANGE 2 MODULES.
In Fig 61 C the following circuits of the ENCODE MODULE have had their input circuits revised: OR gate 105, 106, and 107 have been altered to reflect the proper signals from the REVOLVE 2 and CHANGE 2 MODULES Additionally 5 the input to flip flop Pl is grounded This indicates that the Pl-P 4 portion of the counter is not used Flip flops PI-P 4 had performed the clipping function for OUTPUT MODULE This function is not needed for the alternate implementation.
This completes a discussion of the revised ENCODE MODULE for the 10 alternative implementation The above revisions pertain to the ENCODE MODULE as it is called from the REVOLVE 2 and CHANGE 2 MODULES.
C Revised DECODE I MODULE The revised DECODE I MODULE is called by the DPM INTERFACE, REVOLVE 2, REVOLVE 3, SEED 2, CHANGE 2, and OUTPUT 2 MODULES 15 Only the initialization circuits have been changed to reflect the control and data signals from these alternate modules.
The input selection circuit to register MLNI has been revised to reflect the fact that the switching back and forth of MEMORY MODULE areas is only done in this implementation in connection with the CHANGE MODULE Therefore, 20 AND gate 222 is omitted from the design The enabling circuit on AND gate 220 which enables MLN 3 from ENCODE to MLN 1 consists of the circuit A 2 S 10 CNG + A 2 V 5 The A 2 C 5 signal is from the CHANGE 2 MODULE and is used to enable the length of the revolved change line into MLNI The A 2510 CNG comes from the SEED 2 MODULE when that module is called from the CHANGE 2 25 MODULE AND gate still gates information from the IPRF to MLNI The enable circuit is essentially the same as for the original DECODE 1 MODULE; only the names of the signal have chapged NOTE that if the SEED 2 MODULE is called directly the signal A 2510 CNG gates the information from the OPRF to MLNI rather than from MLN 3 30 OR gate 228 whose output initializes the DIFST flip flop has as input signals from the alternate modules in addition to those signals from the INTERFACE, PIPE and BRIGHTNESS MODULES.
ON Fig 61 E the input/output signals have been modified to reflect the signals from the alternative implementations of the new modules In addition the 35 activating gate 230 has had its inputs changed to reflect the calls from the new modules.
D Revised DECODE II MODULE The revised DECODE II MODULE shown in Figs 61 F-61 H reflects the fact that in the alternative implementation DECODE 11 is called only by the CHANGE 40 2, OUTPUT 2, PIPE, and BRIGHTNESS MODULES As a result portions of its initializing circuits have been considerably reduced.
In Fig 61 F the input to data selector DDSI has been reduced from seven inputs TO three inputs In the revised module only the inputs from the OPRF, PIPE, and BRIGHTNESS are needed The enabling circuits have been similarly 45 modified to reflect these changes Likewise, the load circuit has been modified to reflect the fact that the CHANGE 2 and OUTPUT 2 MODULES are the only alternate modules which call DECODE II Additionally, on Fig 61 F the input to the D 2 FST flip flop asynchronoies set circuit have been modified, i e the inputs to OR gate 228 ‘ have been changed 50 In Fig 61 G only the module activating signals input to gate 230 ‘ are changed.
Finally, on Fig 61 H the input control and data signals have been modified to reflect the signals and data originating from the alternative modules, CHANGE 2 and OUTPUT 2.
These are the revisions that must be made to the DECODE I and II and 55 ENCODE MODULES in order to incorporate them into the alternative implementation It should be noted that the circuits changed dealt mainly with initializing and activating circuits, i e those circuits which interface directly with the calling modules.
E PIPE and BRIGHTNESS MODULES 60 The PIPE and BRIGHTNESS MODULES are incorporated into the alternative implementation but they are revised slightly They must be revised in 1,570,344 176 l 734 1 7 that the signals that now are used between the PIPE and BRIGHTNESS MODULES and the P/B MEMORY MODULE are now connected to the AUXILIARY MEMORY MODULE II The P/B MEMORY MODULE is not used in this alternative implementation Note also that the changed signals represent a 1-to-I change Signals are neither added nor dropped from the 5 modules in question.
XXII DELTA 2 MODULE A General Description
The DELTA 2 MODULE differs from the DELTA MODULE in the DPM SYSTEM of Figs 1-60 The DELTA MODULE merely breaks a number 10 provided thereto designating the number of lines to be revolved, into its component powers of 2 The DELTA 2 MODULE differs from the DELTA MODULE in that the DELTA 2 MODULE generates any line of the delta, depicted by way of example in Table 6 The DELTA 2 MODULE is also capable of right shifting any line of the delta any specified number of possible occurrence values These two is features of the DELTA 2 MODULE enable any line of the iso-entropicgram for a given line to be generated without being required to generate the intermediate lines of the iso-entropicgram This technique has been generally discussed hereinabove under I B Iso-Entropicgram Techniques.
In addition, the DELTA 2 MODULE utilizes a special technique for 20 generating any row of the delta Note that a delta of the same width as the isoentropicgram for the given line is required Table 6 depicts a delta of 8 possible occurrence values The special technique is as follows: If an isoentropicgram has a width of N, any line M of the delta can be generated utilizing the implies function for the column (possible occurrence values) going from O to N and the line number 25 M This function is depicted by the following:
F = C implies R is the same as (C -+ R).
F=Uor R.
The implies function is therefore applied between any column (possible occurrence value) value C and any line value R, where C is the number of the column (or 30 possible occurrence value) of the delta and R is the number of the line of the delta which is to be generated The result of the equation F =C or R is taken and the bits are serially AN Ded together If the result is a 1, then there is an occurrence value in the column (possible occurrence value) of interest and the line of interest of the delta If on the other hand the result is 0, the column of interest in the line of 35 interest in the delta does not contain an occurrence value.
The above concept can be more easily understood with reference to the example of Table 48 To be explained in more detail in connection with the DELTA 2 MODULE, the possible occurrence value of interest is stored in a register DELCOL whereas the line number value of interest is stored in the register 40 DELRO For purposes of illustration, the isoentropicgram is assumed to be 8 values wide and it is assumed that it is desired to generate delta line 5 Referring to Table 48, the line number value is constant at 5 ( 101) whereas the possible occurrence value varies between 0 ( 000) and 5 ( 101) Considering the implies function for possible occurrence value 0 ( 000) using the F = ‘+ R implies function 45 results in the following: F= 000 + 101 = l l l + 101 = 111 The foregoing is depicted at 0 of Table 48 Repeating the implies function for each of possible occurrence values 1 through 5 results in the binary equivalent of decimal values 775577 depicted in Table 48 Doing a bit wise AND, as explained above, on the binary so equivalent results in 110011 as depicted in the next to last column of Table 48 50 This represents possible occurrence values 0, 1, 4 and 5 which is delta line 5 (see Table 6).
In summary then and of importance to this implementation of the DELTA 2
MODULE, whenever the result of the bit wise AND is a 1, then the corresponding possible occurrence value is outputted since it designates the presence of that 55 occurrence value in the desired line of the delta If the result is a 0, then the possible occurrence value is not outputted since there is no occurrence value in that column It will also become apparent in the following discussion of the DELTA 2 MODULE that is necessary to shift the possible occurrence values of the delta values to the right by some specified number N This is simply done by adding 60 the value N to the possible occurrence value and outputting that result For 176 1,570,344 176 example, the right hand list of occurrence values depicted in Table 48 is shifted to the right by three merely by adding three to each value.
Several additional features of the alternative DELTA 2 MODULE should be noted First, it is not necessary to form the values of the delta moving from left to right beyond the point where the remaining values to the edge of the iso 5 entropicgram are O ‘s For example, if the iso-entropicgram width is 256 occurrence values wide and line 2 of the delta is being generated, there is no need to generate values beyond possible occurrence value 2 because all values beyond possible occurrence value 2 are O ‘s In this regard, once the possible occurrence value has exceeded the line number of interest, all succeeding values are 0 Thus, it is 10 possible at this point to merely form an indication that the entire line of the delta has been generated.
Additionally, the DELTA 2 MODULE shifts lines of the delta a specified number of places to the right As a result, it is possible that the shifted line may extend beyond the iso-entropicgram width Those values beyond the edge of the 15 iso-entropicgram need not be generated To this end, an overflow indication is generated, whenever a value is formed, in the process of shifting, beyond the isoentropicgram width.
B Components.
The DELTA 2 MODULE is depicted in Fig 62 and contains registers 20 DELCOL, DELRO, DELV and DELHW The purpose of each of these registers is depicted in Table 49 Each of the registers has eight bits for storage and are of the following type.
A true signal applied at the L input of the DELRO and DELHW and DELRO registers causes each of these registers to store the eight binary bits applied at the 25 input thereof The DELCOL and DELV registers count up one state responsive to each true signal applied at the C input thereof The register DELCOL is reset to 0 responsive to a true signal at the CLR input.
In addition, the DELTA 2 MODULE has DSI, D 52 selection circuits The selection circuits are of the same type disclosed hereinabove 30 Also provided are flip flops, Pl through P 5 which form a control counter 1613.
Flag flops DELFST, DELEND and DELOVL are present and their purpose is set forth in Table 49 The flip flops are each of the leading edge trigger type disclosed hereinabove.
In addition, conventional OR gating circuits, 1620,1622 and 1624 are provided A 35 conventional logical signal inverter circuit 1626 forms the logical inversion at LT of the signal at the LT output.
The unprimed outputs of the eight flip flops in each of the DELCOL and DELRO registers are depicted in Fig 64 by lines labled 0 through 7 Only lines 0 and 7 depicting the least significant and most significant flip flops are shown in Fig 40 64, the rest being indicated by dashed line.
Eight logical signal inverter circuits 1640 are connected to the unprimed outputs 0 through 7 of the register DELCOL The inverter circuits 1640-0 through 1640-7 (only 1640-0 and 1640-7) are shown) are connected to the outputs 0 through 7 of the DELCOL register Seven OR gating circuits 1642 labled 1642-0 45 through 1642-7 (only 1642-0 and 1642-7 being shown) are associated with the correspondingly numbered outputs of the DELCOL and DELRO registers Thus, OR gate 1640-0 has one input connected in turn is connected to the 0 output of the DELCOL register and a second input is connected directly to the 0 output of the DELRO register Each of the other OR gates 1642-1 through 1642-7 also so have two inputs, one of which is connected through one of the correspondingly numbered inverter circuit 1640 to the correspondingly numbered output of the DELCOL register and the other of which is connected directly to the correspondingly numbered output of the DELRO register The outputs of each of the OR gating circuits 1642-0 through 1642-7 are all connected as an input to the 55 AND gate 44 The output of the AND gate 44 is connected to the clocked input at the upper side of the S flip flop.
The S flip flop has its clocked input at the lower portion of the left hand side connected to a gate represented by the logic P 4 CLK Also, the reset input is connected to the VCC output of the DPM INTERFACE MODULE and the upper 60 unclocked set to one input is connected to the P 3 output of the P 3 flip flop in the control counter 1613 (Fig 62).
The clock control for the DELTA 2 MODULE is the generalized clock control 700 disclosed hereinabove It should be noted that the CS input is 1,570,344 177 177 connected to ground thereby providing a permanent false input the CS input which disables the clock suspension feature.
Also provided are comparitors, C-I and C-2 The comparitor C-I compares the content of the registers DELCOL and DELRO and forms true signals at the GT and LT outputs responsive to the content of register DELCOL being the 5 larger and the smaller respectively The comparitor C-2 compares the content of registers DELV and DELHW and forms true signals at the G, L and E outputs responsive to the content of register DELV being the larger, the smaller and equal respectively.
Circuit 1628 forms an implies circuit The implies circuit is a logical gating 10 circuit which OR’s corresponding bits in registers DELCOL and DELRO and then does a bit wise AND on the result to produce a true signal at the S and Soutputs responsive to the result being 1 and 0 respectively.
Fig 64 shows the details of the implies circuit 1628 shown generally in Fig 62.
As indicated, there are logical signal inverters 1640-0 through 1640-7, OR gates 15 1642-0 through 1642-7 and an AND gate 1644 A leading edge type trigger flip flop S is also included and is of the same type disclosed hereinabove.
The information input/output lines are depicted by heavy line and the control input/output lines are depicted by thin line along the right hand side by Fig 62.
C Detailed Description 20
Consider first the general sequence of operation of the DELTA 2 MODULE with reference to the flow diagram of Fig 63 Various blocks of flow diagram are identified by the symbols DM followed by a number (i e DMI) and the corresponding state of the control counter 1613 is indicated by a P followed by a numeral (i e P 1) identifying the one of the flip flops of the control counter 1613 25 then in a one state Initially each of the flag flip flops DELFST, DELEND and DELOVL are reset to 0 as are the control counter 1613 flip flops and then the DELTA 2 MODULE is called Initially, a true signal is formed at one of the outputs A 201 by the SEED 2 MODULE or the output A 251 of the SEED 2 MODULE causing a width value for the iso-entropicgram to be stored from the 30 HW register of the IPRF into register DELHW Additionally, a true signal is formed at the output A 2 R 4 or A 3 R 4 by the REVOLVE 2 MODULE causing a shift value to be applied to the input of the register DELV from the DO I output of the DECODE 1 MODULE or a true signal is formed at the A 208 output of the OUTPUT 2 MODULE causing a shift value formed at its OP output to be applied 35 at the input of the DELV register by the D 52 selection circuit Subsequently, a true signal is formed at the C input of the DELV register at one of the following outputs:
A 2 R 5 and A 3 RS from the REVOLVE 2 MODULE or the A 209 of the OUTPUT 2 MODULE The true signal at the C input of the DELV register causes the shift value to be stored into the DELV register 40 Also, initially a true signal is formed at one of the following outputs: A 3 R 1 and A 2 R 1 of the REVOLVE 2 MODULE and the A 205 output of the OUTPUT 2 MODULE causing a true signal at the 1, 3 and 2 inputs of the DS 1 selection circuit.
True signals at the 1, 3 and 2 inputs of the DS I selection circuit cause the line value to be applied from the RIL output of the REVOLVE 3 MODULE, the RIL output 45 of the REVOLVE 2 MODULE and the OP output of the OUTPUT 2 MODULE, respectively, to the input of the DELRO register A true signal at the A 2 R 2 output of the REVOLVE 2 MODULE or the A 206 output of the OUTPUT 2 MODULE or the A 3 R 2 output of the REVOLVE 3 MODULE causes the DELRO register to store the line value 50 The OR gate 1622 triggers the DELFST flip flop into a one state on the first call to the DELTA 2 MODULE responsive to a true signal of any one of the following outputs: A 3 RI, A 3 RI of the REVOLVE 3 MODULE A 2 R 1 and A 2 R 1 from the REVOLVE 2 MODULE and A 201 from the OUTPUT 2 MODULE.
With the storage of the aforegoing information, the DELTA 2 MODULE has 55 now been initialized The DELTA 2 MODULE is incalled by forming a true signal at one of the following outputs: A 2012 from the OUTPUT 2 MODULE; A 3 R 6 of the REVOLVE 3 MODULE and the A 2 R 6 output of the REVOLVE 2 MODULE.
A true signal at any one of these outputs causes the OR gate 1620 in the DELTA 2 MODULE to form a true signal at the output thereby triggering the generalized 60 clock control 700 into operation causing clock pulses to be applied at CLK and CLK to the DELTA 2 MODULE to thereby sequence its operation.
With the DELFST flip flop in a one state, the call on the DELTA 2 MODULE causes DM 2 to be entered following DMI.
178 1,570,344 178 During DM 2 the followin’g takes place: The DELFST flip flop is reset to 0.
Additionally, the DELEND flip flop is reset to 0.
DM 10 is entered following DM 2 During DM 10 the occurrence value (possibly a shifted occurrence value) is to be stored from the DELV into the DELO register for output c Following DM 10, the operation of the DELTA 2 MODULE is exited awaiting a subsequent call All future calls to the DELTA 2 MODULE, simply call the module and the module uses those values previously placed therein as described above.
The second call to the DELTA 2 MODULE occurs with the DELFST flip flop 10 in a zero state Accordingly, DM 3 is entered following DM 1 During DM 3, a check is made to determine whether the module has generated a complete desired line of the delta To this end, the current possible occurrence value contained in register DELCOL is checked to see whether it is greater than or equal to (>) the line value initially stored in register DELRO If greater, flip flop DELEND is set to a one is state to indicate that the module has completed its operation and clock control 700 ceases operation exiting to the calling module.
If the current possible occurrence value in register DELCOL is less than (L) the line number value in register DELRO, DM 5 is entered During DM 5 the current possible occurrence value in DELCOL and the possible occurrence value 20 in register DELV are incremented by 1 Following DM 5, DM 6 is entered where a check is made to see whether the shift represented by counting up the possible occurrence value in register DELV has resulted in a value which is beyond the width of the iso-entropicgram To this end, the iso-entropicgram width value contained in register DELHW is compared with the content of register DELV If 25 the possible occurrence value in DELV is greater than the isoentropicgram width, DM 7 is entered where the DELOVL flip flop is set to a one state and the operation of the clock control 700 is to exit to the caller.
If on the other hand the comparison during DM 6 reveals that the possible occurrence value in register DELV is less than the iso-entropicgram width value in 30 register DELHW, DM 8 is entered.
During DM 8, the implies function is applied to the content of the DELCOL and DELRO registers The relationship set forth above is F = C + R and in terms of the possible occurrence value in register DELCOL and the line value in register D ELRO, the relation can be rewritten as F = S = DEIXOL + DELRO If the 35 implies function results in a 0, then following DM 9, DM 5 is re-entered and the possible occurrence value in registers DELCOL and DELV are increased by one value as discussed above The loop through DM 6 and DM 8 is repeated until the possible occurrence value in register DELV is larger than the isoentropicgram width value in register DELHW or until the implies function performed during 40 DM 8 results in a 1 (S = 1) When this occurs, a true signal is formed at output S and DM 10 is entered where the possible occurrence value in register DELV is transferred to the output register DELO for output to the caller.
Summarizing then, possible occurrence value (or column) has been shifted along Register DELV monitors the shifting process by incrememting its value by 1 45 for each shift Whenever a 1 is encountered (S = I) in the implies function, the possible occurrence value in DELV is loaded into the register DELO for output.
With the general description of the flow diagram of Fig 63 in mind, consider in more detail the DELTA 2 MODULE as depicted in Fig 62 Assume that the DELTA 2 MODULE has been initialized as discussed above The control counter 50 1613 including all of flip flops Pl through P 5 are reset to 0 by a true signal at the MR output of the generalized clock control 700 Clock signals are then formed at CLK by the generalized clock control 700 Since the flip flops Pl through P 5 are initially all in a 0 state, the logic P 1 P 2 P 3 is true Therefore, the first upswing of the pulse at CLK causes flip flop Pl to be set to a one state thereby causing DM 1 of 55 the flow to be entered At this point, the flip flops Pl and DELFST are both in a one state cuasing a true signal at the Pl DELFST logic Accordingly, the following CLK pulse causes the flip flop P 5 to be set to a one state and flip flop Pl to be reset to a 0 state The logic P 5 DELFST CLK is now true since the P 5 flip flop is in a one state and therefore at the CLK pulse flip flop DELFST is reset to a 0 state 60 Additionally, the true conditions of logic P 5 CLK causes the possible occurrence value contained in register DELV to be stored into the DELO register This same logic causes a true signal at the MT input of the generalized clock control 700 causing a true signal to be formed at the FC output of the generalized clock control 700 which in turn causes a true signal at the DMEND output of the DELTA 2 65 179 I 1,570,344 179 MODULE thereby terminating further operation of the DELTA 2 MODULE thereby causing an exit.
On the next cal to the DELTA MODULE, i e the next true signal formed bythe OR gate 1620, flip flop Pl is again set to a one state However, since DELFST has been reset to a 0 state, nothing takes place during the one state of flip flop P 1 5 The following CLK pulse causes flip flop P 2 to be set to a one state and flip flop Pl to be reset to a 0 state thereby enabling DM 3 of the flow to be entered The one state of flip flop P 2 causes a true signal at the P 2 output causing the comparator C-I to be enabled and thereby compare the content of the possible occurrence value in register DELCOL against the line number contained in register DELRO 10 If the possible occurrence value in register value DELCOL is not less than the line number in register DELRO, the comparitor C-I forms a false signal to the LT output causing the inverter 1626 to form a true signal at the LT output.
Accordingly, at the following CLK pulse, the logic P 2 LT CLK becomes true setting the DELEND flip flop to a one state to indicate that the entire desired line is of the delta has been generated by the DELTA 2 MODULE Additionally, the comparitor C-I forms a true signal at the GT output and the logic P 2 GT is true causing a true signal at the MT input of the generalized thought control 700 which forms a true signal at the DMEND output signalling that the operation of the DELTA 2 MODULE has been completed and is being exited 20 If on the other hand the possible occurrence value in the DELCOL counter is less than the line number in register DELRO, the comparitor C-I forms a true signal at the LT output causing the logic LT P 2 to be true which causes flip flop P 3 to be set to a one state and flip flop P 2 to be reset to a 0 state at the following CLK pulse This causes DMS of the DELTA 2 MODULE flow to be entered The true 25 signal at the P 3 output causes the DELCOL and DELV counters to count the possible occurrence values therein up one The true signal at the P 3 output of the P 3 flip flop causes flip flop P 4 to be set to a one state and flip flop P 3 is reset to a 0 state at the following CLK pulse thereby causing DM 6 of the flow to be entered A true signal is now formed at the P 4 output of the P 4 flip flop causing the comparitor 30 C-2 to compare the possible occurrence value in counter DELV with the isoentropicgram width value in register DELHW If the possible occurrence value in DELV is the greater or is equal to the width value, the comparitor C-2 forms true signals at the G and E output respectively, either of which causes the OR gate 1624 to form a true signal at the GE output At the following CLK pulse, the logic 35 P 4.GE CLK then becomes true causing the DELOVL flip flop to be set at a one state and causing a true signal at the MT input of the generalized clock control 700 which terminates the operation ofthe DELTA 2 MODULE causing a true signal at the DMEND output.
If on the other hand the width value in register DELHW is larger than the 40 content of DELV, the comparitor C-2 forms a true signal at the L output at the following C Ypulse The logic P 4 CLK becomes true, causing the implies circuit 1628 to perform its function If the implies function as applied to the DELCOL and DELRO registers results in a one (s = 1), a true signal is formed at the S output whereas if it is a 0, a true signal is formed at the output A true signal at the S 45 output causes the logic P 4 LS to become true thereby setting flip flop P 3 to a one state and allowing flip flop P 5 to be reset to a 0 state at the following CLK pulse thereby causing DM 5 of the flow to be entered It on the other hand the S output of the implies circuit 1628 receives a true signal, the logic P 4 L S becomes true causing flip flop P 5 to be set to a one state and flip flop P 4 is reset to a 0 state at 50 the following CLK pulse thereby causing DM 10 of the flow to be entered.
During DM 10, a true signal is formed at the P 5 output Therefore, the following pulse at CLK causes the logic P 5 CLK to become true The true condition of this logic causes the register DELO to store the possible occurrence value from DELV as the output and causes the generalized thought control 700 to 55 terminate the operation of the module and form a true signal at the DMEND output returning control back to the calling module.
D Example of Operation.
Consider now an actual example of the operation of the DELTA 2 TMODULE making reference to the flow diagram of Fig 63 and the schematic and block 60 diagram of Fig 62.
As a first example, assume that line 5 of the delta is to be generated Also assume that there is to be a 0 shift Since there is a 0 shift, a shift number value of 0 1,570,344 is stored in the DELV register and a line number value of 5 is stored in the DELRO register.
Also, initially the DELEND flip flop is set to a one state indicating that this is about to be the first call on the DELTA 2 MODULE.
The first call on the DELTA 2 MODULE causes DM 1 and DM 2 of the flow to 5 be entered During DM 2, the DELEND and DELOVL flip flops are reset to 0.
Additionally, register DELCOL is set to 0 corresponding to a possible occurrence value (column) of 0.
DM 10 of the flow is entered and the possible occurrence value of 0 in register DELV is transferred to the DELO register for output and the DELTA 2 MODULE 10 exits its operation.
On the second call to the DELTA 2 MODULE, control goes from DMI to DM 3 of the flow since the DELEND flip flop is now in a 0 state During DM 3 the possible occurrence value of 0 contained in register DELCOL is compared with the line number value of 5 in register DELRO by the comparitor C-1 Since the is content of register DELCOL is less than that of register DELRO, DM 5 of the flow is entered.
During DM 5 the possible occurrence values of 0 stored in registers DELV and DELCOL are counted up to one.
During DM 6 of the flow, the iso-entropicgram width of 8 stored in register 20 DELHW is compared with the possible occurrence value of one stored in register DELV Since the iso-entropicgram width in register DELHW is the larger, DM 8 of the flow is entered.
During DM 8 of the flow the implies function now takes place on the content of register DELCOL and DELRO Considering the relation S = DELCOL + 25 DELRO =T+ 5 = 6 + 5 = 7 doing a bit wise and of the binary equivalent of the decimal number 7, the result is a one Therefore S = 1 Therefore, the DELTA 2 MOLULE goes from DM 9 to DM 10 During DM 10 the possible occurrence value of one in register DELV is transferred to the DELO register for output and again the operation of the module is exited 30 On the third call to the DELTA 2 MODULE, DM I through DM 3 is entered.
The possible occurrence value in register DELCOL is still less than the line number value in register DELRO and therefore DMS is entered During DM 5, the possible occurrence values of one in registers DELV and DELCOL are both counted up by one to values of 2 DM 6 of the flow is then entered where the possible occurrence 35 value of 2 in the DELV register as compared with the width value of 8 in the DELHW register and the former is found to be the smaller Accordingly, D 1 M 8 is entered where the implies function is repeated causing the following computation:
T+ 5 = 6 + 5 results in a 0 (S = 0) Accordingly, control returns to DM 5 During DM 5 the DELV and DELCOL registers are both incremented by one to possible 40 occurrence values of 3 DM 8 is re-entered where the implies function is applied to the values of 3 and 5 in the DELCOL and DELRO registers resulting in S = 0.
Accordingly, DM 5 is re-entered The possible occurrence values in the DELV and DELCOL counters are counted up from 3 to 4.
During DM 8 the implies function is again applied to the values of 4 and 5 in 45 the DELCOL and DELRO registers resulting in S = 1 Accordingly, DM 10 is entered where the possible occurrence value of 4 in register DELV is shifted to the DELO register for output.
On the fourth call to the DELTA 2 MODULE, DMI and DM 3 are entered.
The possible occurrence value of 4 in register DELCOL is still smaller than the line 50 number 5 in register DELRO Accordingly, DM 5 is entered During DM 5, the possible occurrence values in register DELV and DELCOL are counted up from 4 to 5.
During DM 6 the width value of 8 in the DELHW register is still greater than the possible occurrence value of 5 in register DELV Accordingly, DM 8 is re 55 entered where the implies function is performed and results in S = 1 DM 10 is accordingly re-entered where the possible occurrence value of 5 in DELV is transferred to the DELO register for output and an exit is taken.
On the 5th call to the DELTA 2 MODULE, DMI to DM 3 are entered During DM 3 the possible occurrence value of 5 in register DELCOL is found equal to the 60 line value of 5 in register DELRO Accordingly, DM 4 is entered where the DELEND flip flop is set to a one state and the operation of the DELTA 2 MODULE is exited.
It should now be noted that the values that have been outputted in the DELRO register have been the possible occurrence values of 0, 1, 4 and 5 These 65 181 1,570,344 181 182 1,570,344 182 are the possible occurrence values (or columns) in which an occurrence appears in line 5 of the delta (Table 6).
Consider a second example of the operation for the DELTA 2 MODULE In this example, assume that is is desired to shift the delta line 3 places to the right.
Again, assume that the line of the delta to be generated is 5 Under these 5 conditions, preliminary to calling the DELTA MODULE, register DELFST is set to a one state Register DELRO is loaded with line number value 5 and the register DELV is loaded with the shift value of 3.
On the first call, DELFST is in a one state Accordingly, DM 2 is entered where DELFST, DELEND and DELOYL are all reset to 0 Additionally, the to register is reset so that it represents a possible occurrence value of 0 DM 10 is next entered where the DELO register is loaded with the possible occurrence value (equal to shift value) of 3 in register DELV Accordingly, the possible occurrence value of 3 is outputted in register DELO and the DELTA 2 MODULE operation is exited 15 On the second call to the DELTA 2 MODULE the DELFST register is in a 0 state Accordingly, DM 1 and DM 3 are entered During DM 3, the possible occurrence value of 0 in the DELCOL register is compared to the line number 5 in the DELRO register and the former is found not to be greater Therefore, DM 5 of the flow is entered 20 During DM 5 the DELV register is incremented from occurrence value 3 to 4 while the DELCOL register is incremented from possible occurrence value 0 to 1.
During DM 6 of the flow, the width value in the DELHW register is compared to the possible occurrence value of 4 in the DELV register and the former is found to be the greater Therefore, DM 8 is entered where the implies function is 25 performed resulting in S = 1 Accordingly, a true signal is formed at the S output causing DM 10 to be entered During DMIO the incremented occurrence value of 4 is loaded in the DELO register for output and an exit is taken.
The third call to the DELTA 2 MODULE causes DM 1 to DM 3 to again be entered During DM 3, the occurrence value of 1 in the DELCOL register is 30 compared to the line number 5 in the DELRO register and the first is found to be less Therefore, DM 5 is entered During DM 5, the occurrence value of 1 in the DELCOL register is incremented by I to 2 and the possible occurrence value of 4 in the DELV register is incremented by 1 to 5 During DM 6, the incremented possible occurrence value of 5 in the DELV register is found less than the width 35 value in DELHW Accordingly, DM 6 through DM 8 is entered where the implies function is performed resulting in S = 0 Accordingly, DM 5 is re-entered where the possible occurrence values of 5 to 2 in the DELV and DELCOL registers are incremented to 6 and 3 respectively The possible occurrence value of 3 in the DELCOL register is not greater than the width value in the DELHW register 40 Accordingly, DM 8 is entered During DM 8, the implies function is applied on the values of 3 and 5 in the DELCOL and DELRO registers resulting in S = 0.
Accordingly, DM 5 is re-entered During DM 5, the occurrence values in the DELV and DELCOL registers are increased from 6 to 7 and 3 to 4 respectively During DM 6, it is found that the width value 8 in the DELHW register is greater than the 45 occurrence value 7 in the DELV register Therefore, DM 8 is re-entered where the implies function is again applied to the values 4 and 5 in the DELCOL and DELRO registers resulting in S = 1 causing DM 10 to be entered The occurrence value 7 in the DELV register is loaded into the DELO register for output and the operation of the module is exited 50 The fourth call on the DELTA 2 MODULE causes DMI through DM 3 to be entered The occurrence value of 4 in the DELCOL register is compared to the line number value 5 in the DELRO register and is found to be less Accordingly, DM 5 is entered During DM 5, the occurrence values 7 and 4 in the DELV and DELCOL registers are increased to 8 and 5 respectively and DM 6 is entered During DM 7, 55 the occurrence value 8 in the DELV register is found equal to the width value in the DELHW register Accordingly, DM 7 is entered where the DELOVL flip flop is set to 1 indicating that there is no need to generate further shifted occurrence values in the DELV register since the rest would be beyond the edge of the isoentropicgram and therefore meaningless 60 Accordingly, what has been generated out of the output register DELO are the occurrence values 3, 4 and 7 With reference to Table 6, it would be seen that line 5 of the delta shifted three places to the right would be occurrence values 3, 4 and 7.
182 1,570,344 182 XXIII REVOLVE 2 MODULE.
A General Description.
The REVOLVE 2 MODULE in conjunction with the other portion of the systems depicted in Fig 61 depict a revolver for generating various lines of an isoentropicgram, given an input line, without generating the intermediate lines of the 5 iso-entropicgram Generally the operation, in binary values, involves the following:
1 Determining the number of lines N separating the given line (called input line) from the desired line in the iso-entropicgram; 2 At least partially generate line N of the delta once for each actual occurrence value in the input line, 3 Shift the values of each generated delta line N by the amount designated by the value of the corresponding actual occurrence value in the input line and exclusive OR the resultant shifted occurrence values.
Table 51 gives an example of an iso-entropicgram for the given line depicted at line 0 Thus, there are occurrence values (or l’s in columns 0, 2, 3, 5) Assume it is 15 desired to generate line 3 of the isoentropicgram of Table 51 Following the aforegoing method will result in a sequence of operation as depicted in Table 52.
It should be noted that although the values of the occurrence value are selected from right to left in the embodiment of the invention disclosed herein, and that this is a preferred order for selecting the occurrence values, the process could 20 be reversed and the occurrence values selected in the opposite order from smallest to largest within the broader scopes of the present invention.
Several features involving implementation of the present invention should be noted in connection with the example of Tables 51 and 52 and therefore this example will now be examined in more detail in connection with these features 25 First, as indicated above, the occurrence values of the input line are scanned and selected from largest to smallest, i e right to left in Table 52 The first occurrence value selected in five, the DELTA 2 MODULE is then called causing it to generate line 3 of the delta shifted (or incremented) five places to the right resulting in an intermediate result consisting of possible occurrence values 5, 6 and 7 The 30 remaining possible shifted occurrence value is the 8, but it is equal to the width of the iso-entropicgram and is disregarded Thus, only values 5, 6 and 7 form the first intermediate value and are stored in a AM II MEMORY area II The next step is to pick up occurrence value 3 from the input line and subsequently generate line 3 of the delta offset by 3 resulting in occurrence values 3, 4, 5 and 6 The next step is to 35 XOR the stored line and the newly generated line 3 of the delta offset resulting in a second intermediate value with occurrence values of 3, 4 and 7 The second intermediate result is stored in AM II MEMORY are 1 Subsequently, the next occurrence value in the input line, namely, occurrence value 2, is picked up and line 3 of the delta right shifted by 3 is generated and XO Red forming the third inter 40 mediate results 34 and 7 resulting in an intermedial result of 2, 5 and 7 The third intermediate result is stored in AM II MEMORY area 2 Finally, delta line 3 unshifted is XO Red with the third intermedial result resulting in the final line 3 of the isoentropicgram as depicted at the bottom of Table 52.
Returning again to the first step depicted in Table 52, once all of the 45 occurrence values to the right of possible occurrence 6 have been processed, those occurrence values to the right of possible occurrence 6 can be output Thus, occurrence value 7 can be output which in the present embodiment is an output to the ENCODE MODULE which in turn encodes the value to hybrid form for storage in the MEMORY MODULE Therefore, the intermediate results that are stored in 50 AM II MEMORY can be minimized by storing the occurrence values that have been completely processed in permanent storage in the MEMORY MODULE, without need of storing them in the intermediate storage in AM II MEMORY In this same connection, it will be noted that in cycle III all occurrence values to the right of possible occurrence value 3 has been completely processed and therefore 55 can be stored into the permanent storage of the MEMORY MODULE without need of storing into the intermediate storage of the AM II MEMORY.
This concept can generally be defined by saying that once it is determined that the shifted delta line does not extend beyond the iso-entropicgram width, all those possible occurrence values which lie between the end of the occurrence value from 60 the DELTA 2 MODULE and the end of the previous intermediate results are “passed to the calling module” or more specifically sent to the MEMORY MODULE for permanent storage, via the ENCODE MODULE.
1,570,344 183 183 B Components.
Referring to Figs 65 and 66, the REVOLVE 2 MODULE contains the following eight bit registers, RI, R 11, WAP, WAS, WAT and RIL In addition, the REVOLVE 2 MODULE contains the following flip flops, GT, ET, LT, HFF and Pl through P 10 Each of these flip flops are of the leading edge triggered type discus 5 sed above The purpose of the flip flops and registers listed above are set forth in Table 53 and should be referred to form a better understanding of the purpose of registers and flip flops.
Selection circuits DS l through D 55 are provided for gating eight binary coded bits of information from the inputs shown along the upper side to a single eight 10 binary bit output along the lower side The selection circuits are of the same type discussed hereinabove and need not be considered in more detail at this point.
A conventional OR gating circuit 1726 is provided In addition, logic is used to represent logical gating circuits as discussed in more detail hereinabove A clock suspension logic circuit 1722 provides signals to the CS input of a generalized clock 15 control 700 for suspending the operation in the manner discussed in more detail hereinbelow.
Switches 1740 and 1742 are provided for forming binary code of signals representing the value 255 The switches 1740 and 1742 may be conventional, mechanical or electronic switches which permanently provide these signals at their 20 output or other circuitry well-known in the computer art for this purpose.
Input/output control lines and information input/outputs are shown along the right hand side of Figs 65 and 66 Single lines are depicted by the thin line whereas multiple lines for carrying eight binary bits of information are depicted by solid line 25 C Detailed Description.
Consider now the REVOLVE 2 MODULE in more detail making reference to the schematic and block diagram of Fig 65 and Fig 66 and a flow diagram of Fig.
67 A better understanding of the REVOLVE 2 MODULE can be also be obtained by making reference to Tables 53 and 54 which give the principal registers, 30 counters and flip flops and the principal inputs and outputs of the REVOLVE 2 MODULE At the outset, it should be noted that the system, in general processes event occurrence vectors from largest to smallest values therein However, it should be noted that the DELTA 2 MODULE provides the occurrence values from lines of the delta in reverse order from smallest to largest value, i e from left to 35 right Also, the intermediate results referred to in connection with Table 52 are stored in order from lowest to largest value However, when writing out the occurrence values representing the new line the iso-entropicgram, the occurrence values are desirbaly written out to the MEMORY MODULE, via the ENCODE MODULE, largest to smallest value to be consistent with the rest of the system 40 In this connection, the REVOLVE 2 MODULE has two registers, WAP and WBP, which are the read and write pointers respectively for the AM II MEMORY.
A reverse read register WAS is provided for storing the address of the largest occurrence value written into the AM II MEMORY after one complete line for the delta has been provided by the DELTA 2 MODULE Additionally, a register WAT 45 is provided for storing the number of entries, i e occurrence values, in the corresponding area of the AM II MEMORY On the subsequent cycle, the occurrence values from the intermediate result contained in the AM II MEMORY are read from smallest to largest occurrence (left to right), and each time the WAT register is counted down by one value as the DELTA 2 MODULE provides it value 50 to the REVOLVE 2 MODULE When the DELTA 2 MODULE reaches the occurrence value for a delta line, it forms a true signal at the DELEND output which is an input to the REVOLVE 2 MODULE Using the WAS register as a pointer to the area of the AM II MEMORY containing the rest fot he intermediate result, the previously stored intermediate result is read out moving from largest to 55 smallest occurrence value Each time a value is read out, the WAT counter is also counted down by one value until it reaches 0 Each occurrence value of the intermediate result read out is provided to the MEMORY MODULE for storage via the ENCODE MODULE In this manner, the REVOLVE 2 MODULE provides the final occurrence values for the desired line of the iso-entropicgram to the 60 MEMORY MODULE for storage in decreasing value order.
Refer now more specifically to the schematic and block diagram and flow diagram of the REVOLVE 2 MODULE shown in Figs 65, 66 and 67 Considering the general operation, initially one of the calling modules SEED 2 or OUTPUT 2 184 1,570,344 184 1,570,344 185 cause the number of lines to be revolved value to be stored into the input of the RIL register The number of lines to be revolved value is received either from the SLINE register of the SEED 2 MODULE or the OP output from the OUTPUT 2 MODULE During RM 2-1 of the flow, register DELRO of the DELTA 2 MODULE stores the number of liners to be revolved value from the RIL register 5 of the REVOLVE 2 MODULE Additionally, during RM 2-1 the pointer registers WAT, WBP, WAP and WS are all reset to 0 and the initialization flip flops for the DECODE I MODULE, the DELTA 2 MODULE and the ENCODE MODULE are all reset to 1 In this connection, the DIFST flip flop of the DECODE I MODULE and the EFIRST flip flop of the ENCODE MODULE and the DELFST 10 flip flop of the DELTA 2 MODULE are all set to 1 states Additionally, the SM flip flop in the AM II MEMORY is set to I causing memory area 1 I to be the initial area for writing in the AM II MEMORY.
During RM 2-2, pointer register WAS is counted down by 1 The purpose of is this step is now explained The first time through the flow, this operation has 15 no useful purpose However, in later stages of the operation, register WAS is loaded with the content of the WBP write pointer register The WBP write pointer register now is pointing to the next address in the AM II MEMORY to be written following the end of writing one of the intermediate results in the AM 1 I MEMORY Therefore, it is necessary to decrease the value therein by 20 1 so that it actually contains the address of the last occurrence value written into the AM II MEMORY of an intermediate result.
Also during RM 2-2, the DECODE 1 MODULE is called causing it to provide the next occurrence value, in order from largest to smallest, of the event occurrence vector representing the input line which is to be revolved The 25 DECONDE I MODULE provides the occurrence valued in absolute code and it is first stored in the D Ol register of the DECODE 1 MODULE and then transferred to the DELV register of the DELTA 2 MODULE This value in DELV then becomes the shift value specifying the number of occurrence values by which each of the occurrence values from the line of the delta are to be incremented or shifted 30 The EOFI flip flop when in a O state indicates that the DECODE I MODULE has not reached the end of the field of the input line Asuming the EOFI flip flop is in a
0 state, RM 2-3 through RM 2-6 are then entered.
During RM 2-3 through RM 2-6 a determination is made as to whether there is anything in the current read area of the AMII MEMORY to be read If the WAT 35 pointer register, which is an indication of the number of occurrence values remaining to be read is O (W), as it is the first time through the REVOLVE 2 MODULE, RM 2-4 is entered If WAT pointer is not 0 (W), RM 2-6 is entered where the occurrence value of the intermediate result contained in AM 11 MEMORY at the location specified by the read pointer register WAP is read out 40 and stored into the RI register and the read pointer register WAP is decreased by I address, RM 2-7 of the flow is then entered.
If the WAT pointer is 0 indicating that all occurrence values have been read from the intermediate value and RM 2-4 is entered, the DELOVL flip flop is checked to see whether an overflow has occurred in the DELTA 2 MODULE If 45 an overflow has occurred, i e, a shifted occurrence value has been formed which is beyond the width of the iso-entropicgram, the DELOVL flip flop will be in a I state and RM 2-19 of the flow will be entered which starts another cycle of operation.
Another cycle of operation is started by entering the RM 2-19 whenever all of the intermediate values stored in a read area of the AM II MODULE have been read 50 and all of the shifted values (within the width of the iso-entrogicgram) have been provided from the DELTA 2 MODULE.
Returning back to RM 2-4, if the overflow flip flop DELOVL is in a 0 state indicating an overflow has not occurred in the DELTA 2 MODULE, RM 2-5 is entered where the maximum possible occurrence value for the cight bit wide 55 register structure of the machine is stored into the RI register To be explained in more detail in the subsequent operation, the maximum value of 255 is used to properly sequence the operation of the machine RM 2-7 is now entered.
During RM 2-7, the DELTA 2 MODULE is called by the REVOLVE 2 MODULE during which the operation of the REVOLVE 2 MODULE is 60 suspended If the DELTA 2 MODULE detects an overflow condition and sets the DELOVL flip flop, the maximum value of 255 is stored into the register RII If no overflow condition is detected and flip flop DELOVL is not in a 1 state, and if the last occurrence value of the delta line being formed by the DELTA 2 MODULE is not presently being formed, the DELEND flip flop will be in a 0 state causing a true signal at the DELEND output and causing the next occurrence value of the delta line being formed in DELO by the DELTA 2 MODULE to be transferred into register RH of the REVOLVE 2 MODULE and RM 2-8 of the flow is entered. During RM 2-8 through RM 2-13 of the flow, the exclusive or (XOR) 5
operation is performed by the REVOLVE 2 MODULE To this end, during RM 2-8, the content of the RI and RII registers are compared Register RI at this point stores the intermediate occurrence value from the AM II MEMORY whereas the register RH normally stores the delta line occurrence value from the DELTA 2 MODULE If the intermediate occurrence value in register RI is 10 greater, since information is being read in increasing order, RM 2-9 of the flow is entered where the delta line occurrence value from the RII register is stored into the write area of the AM II MEMORY, at the location specified by write pointer register, and the WBP register is incremented by one address Then following RM 2-9, RM 2-7 of the flow is re-entered where the DELTA 2 MODULE is 15 again called causing it to provide the next higher occurrence value from the delta line.
Returning to RM 2-8, assume that the comparison indicates that the contents of registers RI and RII are equal It will be recalled that under these conditions, the exclusive OR function requires that both values be detected from the result To this 20 end, RM 2-14 of the flow is entered where the pointer register WAT is counted down one to reflect that there has been one value read from the AM II MEMORY and RM 2-3 of the flow is entered repeating the subsequent process of the flow.
Returning to RM 2-8, assume that the content of register RI is smaller than that of register R 11 This indicates that the occurrence value from the intermediate 25 result in AM II MEMORY is less than the new occurrence value obtained from the delta line and accordingly the occurrence value in register RI is written into the write area of the AM II MEMORY and the write pointer register WBP is increased by one so that it points to the next memory location in the write area of -30 the AM II MEMORY into which an occurrence value is to be written 30 RM 2-11 of the flow is now entered where the state of the WAT pointer register is checked to see if there are any more entries to be read from the AM II MEMORY read area If the WAT pointer register is not in a 0 state, a true signal is formed at the W output thereof causing RM 2-13 of the flow to be entered where the next larger occurrence value from the AM II MEMORY read area is 35 read and the WAP pointer register is increased by one.
Returning to RM 2-1 1, if the WAT pointer is 0, a true signal is formed at the W output, indicating that all occurrence values in the intermediate result have been read from the read area of the AM II MEMORY and RM 2-12 of the flow is entered where the maximum value of 255 is stored into the RI register Following 40 either RM 2-12 or RM 2-13, RM 2-8 of the flow is re-entered where the exclusive OR process is repeated The loop through RM 2-3 to RM 2-14 is repeated until one of two possible exits from the loop occur.
, The first possible exit is at RM 2-4 If there are no further occurrence values in the delta line which fall within the width of the iso-entropicgram, an overflow 45 condition exists, the DELOVL flip flop is in a I state and under these conditions, RM 2-19 of the flow is entered where the current state of the write pointer WB P is transferred to the WAS and WAT pointer registers for the purpose discussed above Also, the content of the WAP and WBP pointer registers are reset to 0 and the SM flip flop in the AM II MEMORY is complemented so that the previous 50 read area becomes the current write area and the previous write area becomes the current read area Subsequently, RM 2-2 of the flow is re-entered.
Returning to a point made at the beginning of the present discussion, during RM 2-2 the WAS pointer is now decreased or counted down 1 so that is contains the actual address of the last occurrence value written into the previous write area 55 of the AM II MEMORY.
f Consider now the other exist from the loop RM 2-3 through RM 2-14 The second exit occurs from RM 2-7 when the DELTA 2 MODULE has formed its last shifted occurrence value of a delta line When this occurs, a true signal is formed at the DELEND output of the DELEND flip flop causing RM 2 -15 of the 60 flow to be entered where a check is made to determine whether there are any values of an intermediate result remaining to be read from the read area of the AM II MEMORY If values remain to be read, these values then lie above, or to the right of the last occurrence value generated by the DELTA 2 MODULE, and as discussed above are to be sent as output to the MEMORY MODULE via the 65 186 1,570,344 186 ENCODE MODULE To this end, if the WAT pointer register is not 0, RM 2-16 of the flow is entered and the occurrence value in the AM II MEMORY specified by the WAS pointer register is read out and stored into the RI register.
Additionally, the number of entries remaining to be read specified by the WAT pointer is decreased by I and the reverse read pointer register WAS is decreased by 5 1 pointing to the next lower occurrence value of the intermediate result which is to be read from the AM II MEMORY The ENCODE MODULE takes the occurrence value that has been output and converts it into hybrid coded form for storage in the MEMORY MODULE as discussed hereinabove in connection with the DPM system The loop from RM 2-15 to RM 2-17 is repeated as long as there 10 are values from the intermediate result in AM II MEMORY remaining to be read (i.e the WAT register is not 0).
When all of the values of the intermediate result from the read area of the AM II MEMORY have been read, the WAT pointer register is O and a true signal is formed at the W output This causes RM 2-18 to be entered following RM 215 15 where a check is made to determine whether the DECODE I MODULE has reached the last occurrence value in the event occurrence value representing the input line If the last occurrence value has been reached, the EOFI flip flop is in a I state causing a true signal at the EOFI output and flip flop ELAST in the ENCODE MODULE is set to a 1 state indicating this is the last occurrence value to be 20 encoded following which the ENCODE MODULE is called causing it to write the last occurrence value of the result into the MEMORY MODULE in hybrid coded form Subsequently, the operation of the REVOLVE 2 MODULE is exited.
However, if during RM 2-18 the EOF 1 flip flop is not in a 1 state indicating that the last occurrence value of the event occurrence vector representing the 25 input line has not been provided by the ENCODE MODULE, RM 2-19 of the flow is reentered for another cycle.
With the aforegoing general description of the operation for the REVOLVE 2
MODULE, consider the details of the system depicted in Figs 65 and 66 making reference to the flow diagram of Fig 67 Initially, before operation starts, the DPM 30 INTERFACE MODULE forms a true signal at the MINIT output causing a true signal at the input IN to the generalized clock control 700 This in turn causes a true signal at the MR output of the generalized clock control 700 resetting each of the flip flops Pl through P 10 of the control counter 1713 to 0.
Also initially, MEMORY MODULE area 1 is loaded with an event occurrence 35 vector, in hybrid coded form, representing the input line which is to be revolved.
* The REVOLVE 2 MODULE operation is then called by the SEED 2 MODULE or the OUTPUT 2 MODULE by forming a true signal at the A 256 or A 207 output, respectively Either causes the OR gate 1720 to form a true signal at the IN input of the generalized clock control 700 which in turn causes the clock 40 signals to commence at the CLK and CLK outputs of the clock control 700 and the inverter 1730 respectively Since all of the flip flops Pl through P 10 are in a O state, the logic Pl + P 2 + Pl O causes the Pl flip flop to be set to a 1 state at the following CLK pulse thereby causing RM 2-1 of the flow to be entered In addition, the SEED 2 MODULE or OUTPUT 2 MODULE forms a true signal at 45 the A 256 or A 203 output causing the D 53 selection circuit to couple the number of lines to be revolved value from the SLINE register of the SEED 2 MODULE or from tfie d P output of the OUTPUT 2 MODULE to the input of the RIL register.
The true signal at the A 257 and A 204 outputs of the SEED 2 MODULE and the OUTPUT 2 MODULE respectively caused the RIL register to store the number of so lines to be revolved value from the SEED 2 MODULE and the OUTPUT 2 MODULE respectively The true signal at the Pl output causes a true signal at the A 2 RI output of the input/output control lines which in turn sets the DIFST flip flop in the DECODE I MODULE and the EFRST flip flop in the ENCODE MODULE to 1 states, thereby indicating the first call on these modules In 55 addition, the true signal at A 2 R 1 sets the SM flip flop in the AM II MEMORY to a I state causing the following write to take place in area 2 of the AM II MEMORY.
The true signal at the A 2 RI output causes the selection circuit DSI in the DELTA 2 MODULE to couple the number of lines to be revolved value from the RIL register of the REVOLVE 2 MODULE to the input of the DELRO register of 60 DELTA 2 MODULE and at the following CLK pulse, the logic Pl CLK becomes true causing a true signal at the A 2 R 2 output of the input/output control lines of the REVOLVE 2 MODULE which in turn causes the number of lines to be revolved value to be stored from the RIL register into the DELRO register In addition, the true condition of the logic Pl CLK causes a true signal at the A 2 R 3 output of the 65 187 I 1,570,344 187 188 1,570,344 188 REVOLVE 2 MODULE which in turn triggers the DIGO multivibrator in the DECODE I MODULE calling, for the first time, its operation.
Each time the DECODE 1 MODULE or the DELTA 2 MODULE or the ENCODE MODULE are called, clock suspension logic 1722 applies a true signal at the CS input of the generalized clock control 700 causing it to temporarily inhibit 5 further clock pulses and thereby suspend the operation of the REVOLVE 2 MODULE until the called module has completed its operation.
To this end, the D IMEND signal from the DECODE I MODULE is now true and accordingly when the K pulse occurs, the logic DIMEND PL CLK becomes true applying a true signal to the CS input of the generalized clock control to 700 thereby suspending its operation until the DECODE 1 MODULE has provided the first occurrence value from the event occurrence vector of the input line which is being revolved When the DECODE I MODULE has formed the first occurrence value in DOI the DTMEND output from the DECODE 1 MODULE becomes false, thereby causing a false signal at the CS input to the generalized 15 clock control 700 which in turn causes the clock pulses to be formed again at the CLK and CLK output.
In addition, the true signal at the Pl output of the Pl flop flop causes the CLR input of the WAP, WBP, WAS and WAT pointer registers to be true and thereby reset each to a O state 20 If the EOFI output of the DECODE 1 MODULE is true, it indicates that the end of file has not yet been reached by the DECODE 1 MODULE Under these conditions, the logic Pl EOFI is now true and the following CLK pulse causes the flip flops Pl and P 2 to be set to 0 and I states respectively If on the other hand the end of file has been reached by the DECODE 1 MODULE, a true signal is formed 25 at the EOF 1 output thereof causing the logic Pl EOFI to become true which in turn causes P 8 to be true which in turn causes the P 8 or P 10 flop flop to be set to a I state instead of the P 2 flip flop depending upon whether the WAT register has been counted down to 0 However, this operation will be described in more detail subsequently 30 Assuming that the P 2 flip flop has been set to a 1 state and RM 2-2 of the flow is entered, the true signal at the P 2 output of the P 2 flip flop causes a true signal at the C input of the WAS register causing the possible occurrence value (shift value) therein to be counted down by 1 and the HFF flip flop to be reset to 0 The true signal at the P 2 output causes a true signal at the A 2 R 4 output to the D 52 selection 35 circuit of the DELTA 2 MODULE causing the possible occurrence value from the DO I output of the DECODE 1 MODULE to be coupled to the input of the DELV register In addition, the =LR pulse causes the logic P 2 OK to become true which causes a true signal at the A 2 R 5 output which in turn clocks the occurrence value into the DELV register of the DELTA 2 MODULE The DELV register now 40 contains the number specifying the number of shifts required in the delta which is subsequently to be formed Assuming that overflow has not occurred in the DELTA 2 MODULE and the WAT read pointer register has not been counted down to 0, true signals are formed at the DELOVL and W O outputs causing the logic DELOVEWQ P 2 to become true and the following CLK pulse triggers the P 2 and 45 P 3 flip flops to 0 and 1 states, respectively, thereby causing the actions depicted in RM 2-3 and RM 2-6 to take place The logic P 3 W O now becomes true causing a true signal at the A 2 R 7 output of the REVOLVE 2 MODULE causing a read operation In addition, the true signal at the P 3 output causes the D 55 selection circuit to couple the address pointer in the WAT pointer register through to the 50 address input of the AM II MEMORY In addition, the true condition of logic P 3.W CLK causes the WAP read pointer register to be counted up by one address.
It should be noted, however, that if the WAT register were 0, it indicates that the last event occurrence value has been read from the AM II MEMORY read area 55 and accordingly a false signal is formed at the W,, output In this care, a read signal is not applied at the A 2 R 7 output of the REVOLVE 2 MODULE, nor is the WAP address pointer counted up RM 2-7 of the REVOLVE 2 MODULE flow is entered The true condition of logic P 3 CLK also causes a true signal at the A 2 R 6 output of the REVOLVE 2 MODULE calling the operation of the DELTA 2 60 MODULE.
The DELTA 2 MODULE at this time forms a true signal at the DMEND output causing the logic DMEND P 3 CLK to become true in the clock suspension logic 1722 thereby suspending the operation of the REVOLVE 2 MODULE, as discussed above, until the DECODE 2 MODULE provides the next occurrence 65 value corresponding to the line of the delta being formed When the DELTA 2 MODULE provides the occurrence value the DMEND signal goes false causing the generalized clock control 700 to start forming its clock pulses at CLK and CLK.
Assuming that the end of the line of the delta is not being formed, the logic P 3 DELENIY becomes true causing the P 4 flip flop to be set to a I state and the P 3 5 flip flop is reset to a 0 state at the following CLK pulse If the DELTA 2 MODULE has not detected an overflow, i e a shifted occurrence value greater than the isoentropicgram width, a true signal is formed at the DELOVL output causing the D 52 selection circuit to couple the occurrence value from DELO of the DELTA 2 MODULE to the input of the RII register and the true signal at the P 4 output 10 casues the occurrence value to be loaded into the RH register If on the other hand an overflow condition had occurred, the true signal is formed at the DELOVL output and the D 52 selection circuit couples the maximum value of 255 from the switches 1742 to the input of the RII register causing it to be stored instead.
Return now to RM 2-4 aiid RM 2-5 of the flow If during the true signal at 15 the P 3 output of the control counter 1713 the WAT read pointer register contains a 0, a true signal is formed at the W, output indicating that there are no intermediate values remaining in the read area of the AM II MEMORY to be read.
Accordingly, RM 2-4 is entered If the DECODE II MODULE does not detect an overflow and a true signal is formed at the UFTIOVL output, RM 2-5 is entered 20 following RM 2-4 where in the manner discussed above, the maximum value 255 is stored from the switches 1742 into the RII register If on the other hand during the true signal at the P 3 output an overflow condition is detected in the DELTA 2 MODULE and a true signal is formed at the DELOVL output, the control counter sets the P 10 flip flop to a 1 state causing RM 2-19 to be entered 25 Return now to the box RM 2-7 of the REVOLVE 2 MODULE flow and assume that the end of the delta line has not been reached and accordingly RM 2-8 of the flow is to be entered During RM 2-8 through RM 2-14, the exclusive OR function is performed by the REVOLVE 2 MODULE To this end, the true signal at the P 4 output of the P 4 flip flop in the control counter 1713 30 receives a true signal and the following CLK pulse sets the P 4 and P 5 flip flop into 0 and I states respectively The true signal at the P 5 output activates the comparitor 1750 causing it to compare the intermediate occurrence value from the AM II MEMORY and the delta occurrence value provided by the DELTA 2 MODULE which values are stored respectively in the RI and RII registers 35 Depending on the outcome of the comparison, the GT, ET or LT flip flops are set Thus, if the intermediate value contained in register RI is greater than, equal to or less than, the value in register RII, but signals are formed at the G E or L outputs respectively and at the following CLK pulse the GT, ET or LT flip flops, respectively, are set to a 1 state Note that following RM 2-8 whether RM 2-10 or 40 RM 2-14 is entered, the WAT read pointer register is counted down by one if the intermediate value in RI is not greater than the value in register RII Accordingly, the logic P 5: W O CLK causes the WAT register to be counted down by one address.
If the content of registers RI and RII are not equal_,a true signal is formed at 45 the E output of the inverter 1733 The logic true sign P 5 E is true and causes the P 5 and P 6 flip flops of the control counter 1713 to be set to O and 1 states respectively, thereby causing RM 2-10 of the flow to be entered The true signal at the P 6 output causes the output A 2 RI 1 of the input/output control lines to be true causing a write operation of the AM II MEMORY 50 However, in addition it should be noted that since during RM 2-10 the content of register RI is smaller than that of RII, the content of RI is to be written into the AM II MEMORY and accordingly the LT flip flop is now in a 1 state, Consider now RM 2-10 assuming the comparison during RM 2-8 as indicated that the intermediate occurrence value in register RI is the smallest The 55 LT flip flop is now in a 1 state Accordingly, the logic P 6 LT is true causing the P 6 and P 7 flip flops to be set to 0 and 1 states respectively, thereby causing RM 2-11 to be entered During RM 2-11, the state of the WAT register is checked to determine whether there is anything left in the read area of the AM II MEMORY.
To this end, if the WAT pointer register is 0, nothing is left to be read and a true 60 signal is formed at the WO output If on the other hand the WAT register is not at 0, a true signal is formed at the W, output Assume that the WAT pointer register is not 0 and a true signal is formed at the W, output and therefore there are additional intermediate occurrence values to be read from the read area of the AM 11 MEMORY RM 2-13 of the flow is entered, the logic P 7 Wo is now true causing 65 189 I 1,570,344 189 a true signal at the A 2 R 7 output of the REVOLVE 2 MODULE thereby causing the AM II MEMORY to perform a read operation using the address contained in the WAP register To this end, the true signal at the P 7 output causes the D 55 selection circuit to couple the address from the WAP register to the address input of the AM II MEMORY The logic P 7 W O CLK becomes true and causes the WAP pointer 5 register to count up the address therein by 1 so that it identifies the next location from which a read is to be affected from the AM II MEMORY At the same time, the true signal at the W, output causes the D 51 selection circuit to couple the occurrence value read out of the AM II MEMORY to the input of the register RI and the true condition of logic P 7 CLK causes the occurrence value to be stored 10 into the register RI If on the other hand the WAT pointer register were already at 0 and therefore no more occurrence values remained in the read area of AM II MEMORY, a true signal would be formed at the W O output causing the DSI selection circuit to apply the signals representing the value 255 to the input of the register RI in place of the output from the AM II MEMORY and accordingly the 15 maximum value 255 is stored into the register RI The true signal at the P 7 output causes the P 5 flip flop to be set to a 1 state and the P 7 flip flop is reset to a 0 state at the following CLK pulse thereby causing RM 2-8 to be entered following either RM 2-12 or RM 2-13.
Consider now the operation during RM 2-15 to RM 2-16 Flip flop P 8 is set 20 to a I state during the 1 state of any one of the following flip flops of the control counter, PI, P 3, P 6, P 9 or P 10 The 88 represents the logic end gating indicated at the upper left hand side of Fig 66 Note that RM 2-15 is entered and flip flop P 8 is set to a I state if either the end of the line of the delta has been reached by the DELTA 2 MODULE, as indicated by a true signal at the DELEND output of the 25 DELTA 2 MODULE, or the DECODE II MODULE has reached the end of field of the event occurrence vector representing the input line as indicated by a true signal at the EOFI output.
The purpose of RM 2-15 through the RM 2-20 is to determine whether there are remaining occurrence values in the read area of the AM II MEMORY to be 30 encoded by the ENCODE MODULE and written out into the MEMORY MODULE If the WAT read pointer register is not in a 0 state, a true signal is formed at the XW output indicating there are additional occurrence values in the AM II MEMORY read area to be sent to the ENCODE MODULE Under these conditions, RM 2-16 is entered where a read from the AM II MEMORY read area 35 is performed To this end, the true signal at the P 8 output causes a true signal at the A 2 R 7 output of the REVOLVE 2 MODULE causing the AM II MEMORY to perform a read operation at the location specified by the WAS pointer register In this connection the D 55 selection circuit responds to the true signal at the PS output and couples the address in the WAS pointer register to the address input of 40 the AM II MEMORY Additionally, the logic P 8 CLK becomes true causing the WAS pointer register to count the address therein down by one Additionally, the same logic counts the WAT pointer register down by one indicating that one additional value has been read from the read area of the AM II MEMORY As explained above, the D 51 selection circuit couples the intermediate occurrence 45 value from the AM II MEMORY to the input of the RI register where it is stored.
The logic P 9 W causes the P 8 flip flop to be set to a 1 state and the P 7 flip flip is reset to a 0 state at the following CLK pulse thereby causing RM 2-17 to be entered.
The logic P 9 CLK now becomes true causing a true signal at the A 2 R 9 output of the REVOLVE 2 MODULE thereby setting the ENGO multi-vibrator to a 1 state, 50 calling the operation of the ENCODE MODULE Additionally the occurrence value is coupled from the register RI to the input of the ENCODE MODULE and the ENCODE MODULE converts the occurrence value to hybrid code for storage into the MEMORY MODULE.
Return now to RM 2-15 and assume that the WAT pointer register is at 0 55 indicating that there are no remaining intermediate occurrence values in the AM II MEMORY read area A true signal is now formed at the W, output Accordingly, the logic P 9 WO sets the P 10 flip flop to a 1 state and resets the P 9 flip flop to a 0 state causing RM 2-18 to be entered If the EOFI flip flop is in a 0 state indicating that the end of the event occurrence vector representing the input line has not yet 60 been reached, then RM 2-19 is entered During RM 2-19, the logic P 10 EOFI CLK is true causing a true signal at the A 2 R 3 output of the REVOLVE 2 MODULE which in turn sets the D l GO multi-vibrator to a 1 state in the DECODE I MODULE causing the next event occurrence value of the input line to be provided Additionally, the true signal at the P 10 EOFI output causes the WAS and 65 190.
1,570,344 WAT pointer registers to store the address contained in the write address register WBP The logic PIO EOFI CLK becomes true causing the WBP and WAP write and read address registers to be reset to 0 The true signal at the P 10 output also causes the state of the SM flip flop to the AM II MEMORY to be complemented causing the read and write areas of AM II MEMORY to be interchanged during 5 the subsequent operation.
D Example of Operation Consider now the example of operation for the REVOLVE 2 MODULE depicted in Tables 51 and 52 and making reference to the schematic and block diagrams of Figs 65 and 66 and the flow diagram of Fig 67 Assume initially that 10 the event occurrence vector 0, 2, 3 and 5 depicted in Table 52 is stored into MEMORY MODULE area I by the MINI COMPUTER In the manner described hereinabove, the true signal at either the A 257 or the A 204 outputs of the SEED 2 MODULE or the OUTPUT 2 MODULE causes the register RIL to store the number of lines to be revolved from the SLINE register of the SEED 2 MODULE 15 or the OP output of the OUTPUT 2 MODULE The operation of the REVOLVE 2 MODULE is then called and flow block RM 2-1 is initially entered where: the number of lines to be revolved value is stored from the RIL register of the REVOLVE 2 MODULE into the DELRO register of the DELTA 2 MODULE; the address pointer registers WAT, WAP, WBP and WAS are initialized to O and the 20 DELFST, DIFST and EFIRST flip flops of the DELTA 2 MODULE, the DECODE 1 MODULE and the ENCODE MODULE are reset to O; and the SM flip flop in the AM II MEMORY is set so that area 2 will be the write area and area 1 the read area.
RM 2-1 of the flow is then entered where the DECODE I MODULE is 25 called Also address register WAS is counted down one value, however, this is of no consequence at this point in the operation The DECODE I MODULE then returns the first and largest occurrence value of the event occurrence vector This is a value 5 and it is transferred from the DOI register of the DECODE I MODULE into the DELV register of the DELTA 2 MODULE It will be recalled 30 that the value 5 stored into the DELV register of the DELTA 2 MODULE specifies a right shift of the delta line of 5.
RM 3 is entered where the WAT register is found to contain a 0 Accordingly, RM 2-4 of the flow is entered.
During RM 4, the DELTA 2 MODULE has not encountered an overflow and 35 accordingly the DELOVL input is not true causing RM 2-5 to be entered During RM 2-5, the maximum value of 255 is transferred through the DSI selection circuit and stored into the RI register indicating that there is nothing to be read in the current read area of the AM II MEMORY RM 2-7 is entered where the DELTA 2 MODULE is called The DELTA 2 MODULE computes the first value 40 of the delta line 3 (see Table 6) shifted five places to the right Referring to cycle 1 of Table 52, it will be seen that this will be an occurrence value of 5 and the occurrence value 5 is accordingly stored into the RII register.
RM 2-8 is now entered and the exclusive OR function is about to be performed During RM 2-8, the comparitor 1750 compares the content of 45 registers RI and RII and it is found that the maximum value of 255 in register RI is the larger Accordingly, RM 2-9 is entered where the smaller delta line value of 5 is stored into the AM II MEMORY area 2 at location O as specified by the address in the WBP pointer register Additionally, the address in the WBP register is counted up to address one so RM 2-7 is now entered where the operation of the DELTA 2 MODULE is called causing it to provide the second shifted delta occurrence value 6 for line 3.
The value 6 is stored into register RII RM 2-8 et sequence is again entered for the exclusive OR operation Again, the comparitor 1750 detects that the maximum value 255 in register RI is larger than the value 6 in register RII Accordingly ss RM 2-9 and RM 2-7 are again entered where the occurrence value 6 is writtenout into address I of the AM II MEMORY area 2 at address one as specified by the WBP address register Also, the WBP register is counted up to address 2 The DELTA 2 MODULE reads out the next shifted delta occurrence value 7 from the delta line 3 This value is stored into the register RII and subsequently RM 2-8 and 60 RM 2-9 are entered where the value of 7 is written from the register RII into the AM II MEMORY and the WBP counter is counted up to address 3.
During RM 2-7, the DELTA 2 MODULE detects the next occurrence value from the shifted delta line is 8 and is outside of the iso-entropicgram width.
191 1,570,344 191 192 1,570,344 192 Accordingly, it forms a true or overflow signal at the DELOVL output which causes the D 52 selection circuit to couple the maximum value 255 from the switches 1742 to the input of the register RH where the maximum value is stored.
RM 2-8 is now entered Since a true signal exists at DELOVL REGISTER RII stores the maximum value 255 and the contents of registers RI and RII are 5 found equal (both contain 255) causing RM 2-14 and RM 2-3 to be entered Since the WAT register now contains a 0 indicating there is nothing to be read from the AM II MEMORY, the true signal at the W output prevents the WAT counter from being counted down during RIM 2-14.
During RM 2-4, the DELOVL output is still true Accordingly, RM 2-19 is 10 entered.
During RM 2-19, the address 3 contained in the WBP write address register is transferred into the WAT and WAS registers, the WBP and WAP registers are reset to 0 and the SM flip flop in the AM II MEMORY is complemented causing the read and write areas to interchange and the DELFST mono-stable in the 15 DECODE I MODULE is set calling the operation of the DECODE 1 MODULE.
At this point in time, the AM II MEMORY contents, the WAS and WAT register contents and the output to the ENCODE MODULE are as follows:
AM II MEM-area 2 Output to 20 Address Contents ENCODEMODULE 0 5 6 WAS = 3 None 2 7 WAT= 3 Thus, the WAS register now contains address 3 which is one above the last address 25 in which a write occurred in the AM II MEMORY and the WAT register indicates that 3 intermediate values were written into the AM II MEMORY write area during the previous cycle RM 2-2 is now entered where the address in register WAS is counted down by I so that it now contains address 2 which is the last occurrence value of the intermediate values stored in the AM II MEMORY area 30 The memory area which was previously the write area is now the read area The second cycle of operation is now entered.
During RM 2-2 the DECODE I MODULE returns the next lower occurrence value of 3 from the event occurrence vector and the value of 3 is stored into register DELV of the DELTA 2 MODULE 35 RM 2-3 is entered and since the WAT register now contains a 3, it is not 0 and accordingly a true signal is formed at the W O output RM 2-6 is now entered where a signal goes out to the AM II MEMORY causing it to read out the value 5 contained in address 0 specified by the address register WAP and subsequently the WAP register is counted up by 1 address to address 1 The value of 5 is stored into 40 the register RI and subsequently RM 2-7 of the flow is entered.
During RM 2-7 the DELTA 2 MODULE is called and, with reference to Table 52, provides the shifted delta occurrence value of 3 The intermediate occurrence value of 5 in register RI from the read area of the AM II MEMORY is larger than the shifted delta line value of 3 in register R 11 Accordingly, the flow goes 45 through RM 2-8 to RM 2-9 where the smaller value 3 in register RII is written into address 0 of the write area in the AM II MEMORY.
RM-7 is now re-entered where the occurrence value 4 from line 3 of the delta is provided by the DELTA 2 MODULE and stored into register RII RM 28 is re-entered and the exclusive OR function is reperformed It is found that the 50 intermediate occurrence value 5 in register RI is greater than the shifted delta line value of 4 in register R 11 Accordingly, RM 2-10 is entered where the smaller value 4 is written into the AM II MEMORY at address I as specified by the write address register WBP Subsequently, the WBP write address register is incremented by 1 to address 2 55 Following RM 2-9, RM 2-7 is re-entered where the DELTA 2 MODULE provides the next shifted delta occurrence value of 5 and the value is stored into the register RII.
This time during RM 2-8, as the exclusive OR function is performed, it is found that the intermediate value 5 in register RI is equal to the shifted delta occurrence value 5 in register RI Accordingly, RM 2-14 is entered where these values are simply dropped by not writing them into the AM II MEMORY write area and by counting the WAT counter down by I value indicating that the number 5 of entries has now been decreased by 1.
RM 2-3 is now entered with WAT now containing address 2 Since WAT does not contain 0, a true signal is formed at the W O output causing RM 2-6 to be entered During RM 2-6, the next intermediate value of 6 is read from address I of the AM II MEMORY as specified by the WAP counter and the WAP counter is 10 incremented by I to address 2 The intermediate occurrence value of 6 is stored into the register RI RM 2-7 is now entered where the operation of the DELTA 2 MODULE is called causing the next higher shifted delta occurrence value 6 to be formed and stored into register RI.
RM 2-8 et sequence is now entered where the exclusive OR function is again 15 performed Again, it is found that the occurrence values of 6 in registers in RI and RII are equal Accordingly, RM 2-14 is entered where these values are deleted and the WAT counter is counted down by 1 to indicate that only 1 value remains in the AM II MEMORY read area.
RM 2-3 is re-entered and since WAT is not 0, a true signal is formed at the W O 20 output causing RM 2-6 to be re-entered where the last remaining intermediate value of 7 is read out from address 2 of the AM II MEMORY read area and the WAP register is counted up to address 3 The intermediate value of 7 is stored in the RI register.
RM 2-7 is re-entered where the DELTA 2 MODULE is recalled The 25 DELTA 2 MODULE has provided the last shifted delta occurrence value of the delta line 3 and accordingly a true signal is now being formed at the DELEND output thereof, causing RM 2-15 of the flow to be entered.
During RM 2-15, the WAT register contains a I and is therefore not 0, indicating that there is 1 value left to be read from the AM II MEMORY 30 Accordingly, RM 2-16 is entered where, using address 2 in the WAS address register, the AM II MEMORY read area is read This address contains the value 7 and it is stored into the register RI temporarily before it is transferred to the ENCODE MODULE Additionally, the WAS and WAT registers are counted down by 1 so that they contain a 1 and a 0 respectively RM 2-17 is now entered 35 where the intermediate value 7 contained in register RI is transferred to register EI of the ENCODE MODULE and the ENCODE MODULE operation is called causing the intermediate occurrence value of 7 to be encoded into hybrid coded form for storage into the MEMORY MODULE.
RM 2-15 is now re-entered This time the WAT register is found to be O 40 Accordingly, a true signal is formed at the W O output causing RM 2-18 to be entered Since the DECODE 1 MODULE has not reached the end of the event occurrence vector, atrue signal is formed at the EOF 1 output causing RM 2-19 to be re-entered At this point, the address of 2 contained in the write address register WBP is stored into the WAS and WAT registers and the WAP and WBP registers 45 are reset to 0 Additionally, the SM flip flop in the AM II MEMORY is; complemented causing the read and write areas to interchange Thus, the AM II MEMORY area 2 becomes the write area and area 1 becomes the read area At this point, the AM II MEMORY, the WAS and WAT registers and the output -to the ENCODE MODULE are as follows: 50 AM II MEM-area 2 Output to Address:Contents ENCODE MODULE 0 3 WAS = 2 7 1 4 WAT = 2 55 The third cycle of operation back through RM 2-19 and RM 12-2 et sequence is now entered During RM 2-2, the WAS register is counted down so that it now contains address I which, with reference to the data shown above, is the address in the AM II MEMORY area I where the intermediate occurrence value of 4 is stored Additionally, the DECODE 1 MODULE provides the next lower 60 193 193 194 1570344 1 GA occurrence value of 2 and it is loaded into the DELV register of the DELTA 2 MODULE causing delta line 3 to be formed shifted this time by only 2 occurrence values.
RM 2-3 is now entered and since the WAT register does not contain 0, the true signal at the W, output causes RM 2-6 to be entered During RM 2-6, the 5 AM II MEMORY area 1 has its address 0 read out and stored into register RI The value 3 is contained in address 0 Accordingly, register RI now contains the intermediate occurrence value of 3.
RM 2-8 et sequence is now entered where the exclusive OR function is performed During RM 2-8, it is found that the-shifted delta occurrence value of 3 10 contained in register RI is greater than the occurrence value of 2 provided from the event occurrence vector of the input line Accordingly, RM 2-9 is entered where the smaller value 2 is written out into the AM II MEMORY at address 0 and the WBP write address register is increased to 1.
RM 2-7 is now re-entered causing the operation of the DELTA 2 MODULE to 15 be called causing it to provide the next higher shifted delta occurrence value of 3 from the line 3 of the delta.
RM 2-8 et sequence is again entered for the exclusive OR operation At this point, registers RI and RII both contain a 3 and are therefore equal Accordingly, RM 2-14 is entered where the value of 2 in the WAT register is decreased by 1 and 20 thereby eliminating the occurrence value of 3 from the output RM 2-3 is reentered Register WAT now contains a 1 Accordingly, a true signal is formed at the W, output causing RM 2-6 to be entered During RM 2-6, the intermediate occurrence value 4 is read from the AM II MEMORY area 1 from address 1 and the value is stored into the register RI Additionally, the WAP read address is 25 counted up by I to address 2 RM 2-7 is re-entered where the DELTA 2 MODULE is called causing the next shifted delta occurrence value of 4 to be provided and stored into register RI.
The exclusive OR function is now performed and during RM 2-8 it is found that the values of 4 in registers RI RII are equal Accordingly, RM 2-14 is re 30 entered where the WAT counter is counted down to 0.
RM 2-3 of the flow is re-entered and there is found that the WAT register is 0.
Accordingly, RM 2-4 is entered During RM 2-4 an overflow condition does not exist in the DELTA 2 MODULE and, accordingly, a true signal is formed at the DYELOVL output Accordingly, RM 2-5 is entered where the maximum value of 35 255 is stored into the register RI RM 2-7 of the flow is now re-entered where the DELTA 2 MODULE is called causing the next higher shifted delta occurrence value of 5 to be provided and stored into the register RII.
During the exclusive OR function of RM 2-8 et sequence, it is found that the value in register RI is larger and therefore RM 2-9 is entered where the smaller 40 value of 5 in register RII is stored into the AM II MEMORY write area at address I RM 2-7 is now entered where the DELTA 2 MODULE is called Since the last shifted delta occurrence value has been provided, a true signal is formed at the DELEND output causing RM 2-15 of the flow to be re-entered 45 During RM 2-15, the register WAT contains a 0 Accordingly, a true signal is formed at the WO output causing RM 2-18 to be entered During RM 2-18, the EOFI flip flop is in a 0 state indicating that the DECODE 1 MODULE has not reached the end of the event occurrence vector for the input line Accordingly, RM 2-19 is re-entered 50 During RM 2-19, the WAT and WAS registers are loaded with the address 2 from the WBP register and the WAP and WBP registers are reset to 0; the SM flip flop is complemented in the AM II MEMORY causing the area 2 to be the new read area and area I to be the new write area At this point in time, the AM II MEMORY and the WAS and WAT registers and the output provided to the 55 ENCODE MODULE to this point are as follows:
AM II MEM -area 2 Output to Address Contents Encode Module 0 2 WAS = 2 7 60 WAT= 2 194 1,570,344 A I Cycle 4 is now entered.
During RM 2-2, the address in the WAS register is counted down by I so that it now contains address I which is the location of the last intermediate occurrence value contained in the read area 2 Additionally, the DECODE I MODULE is called causing it to provide the last occurrence value 0 from the event occurrence 5 vector of the input line The occurrence value 0 is stored into the DELV register of the DELTA 2 MODULE Therefore, the DELTA 2 MODULE will provide line 3 of the delta unshifted RM 2-3 is now entered and because the WAT register contains a value of 2, a true signal is formed at the W O output causing RM 2-6 to be entered During RM 2-6, the value of 2 is read from memory area 2 from address 0 10 (specified by the read address register WAP) and the WAP register is incremented to address 1.
During RM 2-7, the DELTA 2 MODULE is called causing the occurrence value 0 from line 3 of the delta to be formed and stored into the register R 11 The intermediate value 2 in register RI is greater than the value 0 in register R 11 15 Accordingly, RM 2-9 is entered where the value 0 is written into the address 0 of the write address area 2 of the AM II MEMORY and the WBP register is counted up to address 1.
RM 2-7 is re-entered causing the DELTA 2 MODULE to again be called.
The DELTA 2 MODULE now provides the occurrence value 1 from line 3 of the 20 delta and the value 1 is stored into register RII During the XOR operation of RM 2-8 et sequence, RI contains a value 2 and is therefore larger than the I contained in register RII causing RM 2-9 to be re-entered The value of I in register RII is now written out into the right area of the AM II MEMORY and the WBP register is increased by 1 The DELTA 2 MODULE is subsequently called 25 again causing the next higher shifted delta occurrence value 3 of line 3 to be stored into the register R 11 During the exclusive OR operation of RM 2-8 et sequence, it is found that the content of registers RI and RII are both 2 and therefore must be dropped Accordingly, the WAT counter is decreased from 2 to I and RM 2-3 is re-entered Since the WAT register still is not 0, RM 2-6 and 7 are reentered 30 where the intermediate value of 5 from address I of the AM II MEMORY is read and stored into the register RI and the DELTA 2 MODULE provides the next higher shifted delta occurrence value of 3 for storage in register RI.
During the exclusive OR operation of RM 2-8 et sequence, the value of 5 in register RI is the larger and therefore the value of 2 from register RII is stored into 35 the AM II MEMORY and the WBP write counter is increased to address 2.
RM 2-7 is re-entered where the DELTA 2 MODULE is again called However, at this point, the DELTA 2 MODULE has provided the complete line of shifted occurrence values from line 3 of the delta and a true signal is formed at the DELEND output of the DELTA 2 MODULE so indicated This causes RM 2-15 40 of the flow to be re-entered The WAT register now contains a value of 2 and therefore is not 0 causing a true signal at the W, output This causes RM 2-16 to be entered The WAS register now contains address 1 Accordingly, address 1 of the AM II MEMORY area 2 is read This address contains the value 5 and accordingly is stored into the register RII and subsequently during RM 217 is 45 provided to the ENCODE MODULE for encoding into hybrid form for storage into the MEMORY MODULE Additionally, the WAS and WAT registers are decreased by 1 so that both now contain a 0 RM 2-15 is now re-entered.
Since the WAT register now contains a 0, a true signal is formed at the W, output causing RM 2-18 to be entered During RM 2-18, the EOFI flip flop is in 0 50 state indicating that the end of the event occurrence vector for the input line has not been read by the DECODE 1 MODULE Accordingly, RM 2-19 is entered.
During RM 21-19, the address 3 contained in the WBP write address register is stored into the WAS and WAT registers and the WAP and WBP registers are reset to 0 Additionally, the SM flip flop in the AM II MEMORY is complemented 55 causing area 1 to become the new read area and area 2 to become the new write area Thus, at this point, the AM II MEMORY, the WAS and WAT register contents and the output to the ENCODE MODULE are as follows:
I 1,570,344 AM II MEM area 2 Output to Address Contents Encode Module 0 O WAS = 3 7 1 1 WAT= 3 5 5 2 3 During RM 2-2, the WAS register is reduced from 3 to 2 which is the address of the last intermediate value in the AM II MEMORY read area 1 The DECODE I MODULE now is called and since the last event occurrence vector has been provided, it returns a true signal at the EOFI output indicating that the end of field 10 of the event occurrence vector has been encountered Accordingly, RM 2-15 is entered The WAT counter contains a 3 and therefore forms a true signal at the W.
output Accordingly, RM 2-16 is entered where the value 3 identified by address register WAS is read from the AM II MEMORY and stored into the register RI and subsequently is transferred to the ENCODE MODULE for encoding in 15 hybrid coded form Additionally, the WAS address register is decreased from address 2 to 1 and the WAT register is decreased from 3 to 2.
RM 2-15 is re-entered and a true signal is still formed at the VW output causing RM 2-16 and RM 2-17 to be re-entered where the next lower intermediate value of I is read out, transferred to the ENCODE MODULE for 20 encoding the hybrid coded form and the WAS and WT registers are decreased to 0 and I respectively RM 2-15 is entered at this-point A true signal is still formed at the W output Therefore, RM 2-16 and RM 2-17 are re-entered 0 here the next lower intermediate value of 0 is read out from the AM II MEMORY read area I and transferred to the ENCODE MODULE for encoding 25 to hybrid coded form Additionally, the WAT register is decreased by 1 to 0.
RM 2-15 is now re-entered where the WAT register is found to contain a 0 and a true signal is formed at the W, output causing RM 2-18 to be entered The ENCODE MODULE has reached the end of the file Accordingly, a true signal is being formed at the EOF 1 output causing RM 2-20 to be entered During 30 RM 2-20, the logic P 1 EOF 1 is true, causing a true signal at the A 2 R 10 output which in turn causes the flip flop ELAST in the ENCODE MODULE to be set to a 1 state thereby calling the operation ofthe ENCODE MODULE for the last time causing it to completely encode the last occurrence value and provide it to the MEMORY MODULE for storage in hydrid coded form 35 At this point, the MEMORY MODULE contains the following occurrence values 7, 5, 3, 1, 0 The occurrence values of course are in hybrid coded form With reference to Table 52, it will be seen that this is the event occurrence vector of the input line revolved down by 3 lines.
XXIV REVOLVE 3 MODULE 40 A General Description
The REVOLVE 3 MODULE depicted in the schematic and black diagram of Figs 68 and 69 and the flow diagram of Fig 70 is quite similar to the REVOLVE 2 MODULE with the differences noted below The purpose of the REVOLVE 3 MODULE is to facilitate the fast seed finding operation of the SEED 2 MODULE 45 The structure and sequence of the fast seed finding process is presented in greater detail in connection with the SEED 2 MODULE However, for purposes of understanding the REVOLVE 3 MODULE, it should be noted that the SEED 2 MODULE has a fast seed finding procedure in which only the last two actual occurrence values in any line of an iso-entropicgram are used to determine the 50 number of lines by which a revolve is to take place to locate the next line in the process of locating the seed To this end the REVOLVE 3 MODULE starts generating a line specified by the SEED 2 MODULE until it has generated two actual occurrence values which will no longer be altered by XO Ring with a subsequent line provided by the DELTA 2 MODULE It has been pointed out in 55 connection with the REVOLVE 2 MODULE that the revolve takes place by generating a number of intermediate values and that the intermediate values are recorded into the AM II MEMORY Also those intermediate values to the right or at the largest end of the intermediate value are output to the ENCODE MODULE 196 1,570,344 196 if they are such that they will no longer be altered during XO Ring with subsequent lines provided by the DELTA 2 MODULE Once this condition is reached, the last two or largest two occurrence values in the line are sent to the calling module which is the SEED 3 MODULE: In contrast to the REVOLVE 2 MODULE, the values are now output to the ENCODE MODULE for hybrid coding and storage in the MEMORY MODULE.
The primary distinction between the REVOLVE 3 MODULE and the REVOLVE 2 MODULE will now be outlined With reference to the REVOLVE 2 MODULE flow diagram of Fig 67 it will be noted that following RM 3-8 and if a true signal is formed at output DELEND by the DELTA 2 MODULE (signaling 10 the last delta line value or shifted Delta line value is being formed by the DELTA 2 MODULE), RM 2-15 is entered The purpose for which the REVOLVE 2 MODULE entered RM 2-15 is to output to the ENCODER MODULE those occurrence values which will not be affected or changed in the exclusive OR operation by subsequent lines formed by the DELTA 2 MODULE However, in is the REVOLVE 3 MODULE, the values are not output to the ENCODE MODULE Instead, the REVOLVE 3 MODULE determines whether the WAT pointer content is greater than 2 If greater than 2, it indicates that there are two values in the AM II MEMORY and they are transferred to registers Nl and N 2 and subsequently transferred to the SEED 2 MODULE If there are less than two 20 values, the maximum value of 255 is stored into register RII and the REVOLVE 3 MODULE goes back to the exclusive OR operation depicted at RM 3-9 et seq In this manner, the REVOLVE 3 MODULE insures that every value in the read area is transferred over to the write area of the AM II MEMORY before the SM flip flop is complemented to interchange the read and write areas 25 Note inthe REVOLVE 2 MODULE flow diagram of Fig 67 that if the end of file is reached by the DECODE I MODULE, as indicated by the EOFI flip flop in a 1 state, RM 2-15 is entered for transferring occurrence values from the read area of the AM II MEMORY to the ENCODE MODULE for output However, in the REVOLVE 3 MODULE, if the EOFI flip flop is in a I state and the WAT pointer 30 is not greater than 2, the Nl register is set to 0 By the nature of the REVOLVE 3 MODULE, there is at least one value Therefore, if the WAT pointer is less than 2, it must be 1.
After register NI is set to 0, RM 3-21 is entered where an intermediate value is read from the AM II MEMORY and is stored into the N 2 register Exit is then 35 taken.
B Components Referring to Figs 68 and 69, the REVOLVE 3 MODULE contains the following 8 bit registers: RI RII NI, N 2, preferably of type SN 74100 disclosed in the above referenced TTL book WPB and WAP are up counters and form read 40 pointers WAS and WAT are respectively a read pointer and a counter to keep track of the number of items remaining to be read, and are both down counters.
In addition, the REVOLVE 3 MODULE contains the following flip flops: GT, ET, LT, and Pl through P 12 Each of these flip flops is of the leading edge trigger type discussed above The correspondingly labeled flip flops have generally the same 45 purpose as that designated in Table 53 for the REVOLVE 3 MODULE and will not be repeated herein.
Selection circuits DSI-D 55 are provided for gating 8 binary coded bits or information from any one of the inputs shown along the upper side to a single 8 so binary bit output shown along the lower side of each rectangular box The 50 selection circuits are of the same type discussed hereinabove and need not be considered in more detail at this point.
Switches 1840 form signals representing in binary code the decimal value 2, Switches 1842 and 1844 form signals representing, in binary code, the decimal value 255 The switches may be of conventional structure such as mechanical or 55 electronic switches, which permanently provide signals at their outputs.
Conventional OR gating circuit 1860 is provided for O Ring the signals at the G and E outputs of the compare circuit 1852 Conventional signal inverters 1856 and 1854 are provided for providing a logical signal inversion for the signal applied at their input 60 Clock suspension logic circuit 1822 provides signals to the CS input of a generalized clock control 700 for suspending the operation of the clock control 700 in the manner discussed in more detail hereinbelow and as discussed with respect to the generalized clock control 700.
197 1,570,344 197 Input/output control lines and information input-outputs are shown along the right-hand side of Figs 68 and 69 Single lines are depicted by thin lines, whereas multiple lines for carrying 8 binary bits of information are depicted by heavy solid lines.
C Detail Description 5
Consider now the general structure of the REVOLVE 3 MODULE as depicted in the schematic and block diagram of Figs 68 and 69 and the flow diagram of Fig.
Similar to RM 2-1 of the REVOLVE 2 MODULE flow, during RM 3-1 of the REVOLVE 3 MODULE flow the number of lines to be revolved value is transferred from the RII register to the DELRO register of the DELTA 2 10 MODULE and the WAP, WBP, WAS and WAT registers of the REVOLVE 3 MODULE are reset to 0 Additionally, the SM flip flop in the AM II MEMORY is set so that a write takes place in area 2 Additionally, the DELFST and D 1 FST flip flops of the DELTA 2 and DECODE I MODULES are set to 1 to indicate that the first call is about to be made on these modules It should be noted that the 15 DECODE I MODULE, as for the REVOLVE 2 MODULE, will be decoding the event occurrence vector of the input line stored in the MEMORY MODULE The ENCODE MODULE is not called by the REVOLVE 3 MODULE and therefore can be disregarded During RM 3-2 of the REVOLVE 3 MODULE flow, the reverse read pointer register WAS is reduced by 1 As for the previous module, this 20 can be disregarded during the first call on the REVOLVE 3 MODULE during RM 3-3, the DECODE I MODULE is called and one of the occurrence values from the input line provided by the DECODE I MODULE to the DELV register in the DELTA 2 MODULE It will be recalled that the DECODE 1 MODULE provides the occurrence values in order from largest to smallest value The 25 occurrence value stored in the DELV register becomes -the shift value for the DELTA 2 MODULE.
During RM 3-4, the content of the WAT register is checked to determine whether anything remains to be read from the read area of the AM-IL MEMORY If the WAT register is not 0, (w O is true) then RM 3-7 of the flow is 30 entered If the WAT register contains a 0, nothing remains to be read and RM 3-5 of the flow is entered.
If RM 3-5 of the flow is entered, the DELOVL (overflow) output and the DELEND output from the DELTA 2 MODULE are checked to see if either is true If neither one is true, i e, neither an overflow condition exists, nor has the end 35 of the line been reached by the DELTA 2 MODULE, RM 3-6 of the flow is entered where the maximum value 255 is stored into the RI register of the REVOLVE 3 MODULE which insures that during the exclusive OR operation, RM 3-10 is entered following RM 3-9 Following RM 3-6, RM 3-8 of the flow is entered 40 Returning to RM 3-5, if a true signal is formed at either the DELOVL or the DELEND output indicating that there is either an overflow or the end of the Delta line has been reached by the DELTA 2 MODULE, RM 3-22 of the flow is entered where the highest address written in the AM II MEMORY is stored into the WAS and WAT registers and the WAP and WBP registers are reset to 0 in a similar 45 manner and for a similar purpose as that discussed in connection with RM 2-19 ofthe REVOLVE 2 MODULE Also, the AM II MEMORY read write flip flop SM is complemented in interchange the read andwrite areas and the DELFST flip flop in the DELTA 2 MODULE is set to a 1 state to initialize for the next line requested from the DELTA 2 MODULE 50 Assume now that RM 3-8 of the REVOLVE 3 MODULE has been entered.
During RM 3-8, the DELTA 2 MODULE is called If the end of line has not been reached by the DELTA 2 MODULE and hence a true signal if formed at the DELOVL output, then the Delta line or Delta shifted line value is stored into register RII of the REVOLVE 3 MODULE from register DELO of the DELTA 2 55 MODULE If, on the other hand, an overflow condition has been sensed in the DELTA 2 MODULE and a true signal is formed at the DELOVL output, the maximum value 255 is stored into register RI.
RM 3-9 through RM 3-12 are provided for the exclusive OR operation similar to that dipicted and explained for the REVOLVE 2 MODULE at RM 2-8 60 through RM 2-10 Thus, if the two values in the registers RI and RII are equal, RM 3-11 and RM 3-4 are entered where the WAT read pointer register is decreased by 1 and RM 3-4 et seq is repeated thereby deleting the identical values in the registers RI and RII RM 3-12 and RM 3-10 insure that the smaller of the 198 1,570,344 198 values contained, in registers RI and RII is written out to the write area of the AM-II MEMORY Thus, during RM 3-10, the content of register RII is written as it is the smaller, whereas during RM 3-12, the content of register RI is written as it is the smaller Following RM 3-10, RM 3-8 of the flow is reentered During RM 3-12, the number in the read pointer register WAT is decreased by I unless it 5 has already reached 0 (i e W, is true) RM 3-13 through RM 3-15 are used to determine whether there is anything remaining to be read from the read area of the AM-IL MEMORY and if so, during RM 3-14 the value is read and stored into register RI and the read pointer register WAT is increased by 1 If the WAT register is 0 indicating that all values have been read from the read area of the 10 AM-II MEMORY, then RM 3-15 is entered following RM 3-13 where the maximum value 255 is stored into register RI, insuring that either RM 310 or RM 3-11 will be entered following the subsequent RM 3-9.
The loop through RM 3-8 can be terminated in one of two ways One of the ways is when the DELEND output from the DELTA 2 MODULE is true indicating 15 that the end of the Delta line has been reached thereby Under these conditions, RM 3-16 is entered following RM 3-8 of the flow During RM 3-16, a check is made to determine if the pointer register WAT contains a value less than 2 The value in register WAT can never be greater than 1 Therefore, if the value in register WAT is equal to 2, then RM 3-20 and RM 3-21 are entered WAT 20 containing a value of 2, indicates that there are 2 or more values in the AM-II MEMORY read area remaining to be read This also means that these two values are suffuciently large in reference to the remaining Delta lines that there is no possibility of their being altered or modified by the subsequent Delta lines.
Accordingly during AM-II MEMORY and stored in the Nl and N 2 registers of 25 the REVOLVE 3 MODULE and the WAS counter is decreased once for each value The operation is then exited The largest or rightmost occurrence value is stored in register Nl whereas the next largest is stored in register N 2.
Consider RM 3-16 again and assume that the value in register WAT is less than 2 If there are not at least two values remaining to be read from the read area 30 of the AM-I 1 MEMORY, RM 3-17 is entered where the maximum value 255 is stored into register RII and the exclusive OR portion of the flow is reentered By setting the maximum value 255 into the register RII, it insures that either RM 3-1 1 or RM 2-12 will be entered Hence, any remaining values in the AM-II MEMORY read area are read, stored in the register RII, and subsequently written 35 into the write area thereof Eventually, RM 3-11 will be entered, causing a return to RM 3-4 When this occurs, the content of register WAT will be 0 and the path RM 3-5, RM 3-22 to RM 3-2 will be entered.
Return now to the loop through RM 3-8 and consider the second way in which this loop is exited This occurs if the DECODE I MODULE has reached the 40 end of file of the event occurrence vector for the input line and hence a true signal if formed at the EOFI output A true signal at the EOFI output of the DECODE I MODULE causes RM 3-18 to be entered following RM 3-18 During RM 3-18, the content of the pointer register WAT is checked to see whether it contains a 2 or a value less than 2 If the WAT register contains a 2, 45 then it indicates that though the end of file for the input line has been reached by the DECODE I MODULE, that two occurrence values remain in the AM-II MEMORY read area and subsequently RM 3-20 and RM 3-21 are entered where the two values are stored in the NI and N 2 registers as discussed above Subsequently, the REVOLVE 3 MODULE is exited 50 If during RM 3-18 the value in the WAT register is less than 2, then a 0 value must be stored in the NI register However, there must be at least one occurrence value in each line of an iso-entropicgram and the occurrence value must be stored in the N 2 register Accordingly, RM 3-19 is entered where the 0 value is stored in register Nl an subsequently RM 3-21 is entered where the occurrence value in the 55 AM-II MEMORY read area is stored into the N 2 register and an exit is taken.
Consider now in more detail the specific circuitry in the REVOLVE 3 MODULE Making reference to the schematic and block diagrams of Figs 68 and 69, and the flow diagram of Fig 70, initially the DPM INTERFACE MODULE forms a true signal at the MINIT output resetting the generalized clock control 700 60 causing each of the flip flops in the control counter 1813 to be reset to 0.
Subsequently, the SEED 2 MODULE forms a true signal at the A 255 output causing the number of lines to be revolved value to be stored from T 3 of the SEED 2 MODULE into the RIL register A true signal at the A 255 output is also applied 199 1,570,344 199 to the I input of the generalized clock control 700 causing it and invertor 1830 to commence forming clock pulses at the CLK and the CLK outputs.
All flip flops in the control counter 1813 are now in a 0 state causing the logic Pl + P 2 P 12 to be true Accordingly, the first CLK pulse causes the Pl flip flop to be set to a 1 state The true signal at the Pl output of the Pl flip flop causes the 5 A 3 RI output of the input/output control lines for the REVOLVE 3 MODULE to receive a true signal The true signal at the A 3 RI output sets the DELFST flip flop in the DELTA 2 MODULE to a 1 state and enables the number of lines to be revolved value to be coupled to the input of the DELRO register in the DELTA 2 MODULE Additionally, the true signal at the A 3 RI output causes the SM flip flop 10 in the AM-II MEMORY to be set to a 1 state causing area 2 to be the write area.
The true signal at the Pl output causes the WAP, WAS, WAT and WBP pointer registers to be cleared or reset to 0 At the following CORK pulse, the logic P 1 CLK becomes true, causing true signals at the A 3 R 2 and A 3 R 3 outputs of the REVOLVE 3 MODULE The true signal at the A 3 R 2 output causes the number of is lines to be revolved value to be stored from register RIL into register DELRO The true signal at the A 3 R 3 output causes the DIGO multi-vibrator int he DECODE I MODULE to be set, calling the operation ofthe DECODE I MODULE (see RM 3-3 of the flow).
Assuming the end of file has not been reached by the DECODE I MODULE, 20 a true signal is formed at the Ed O Fl output causing the logic PL EOFI to be true.
The true condition of this logic causes the P 2 flip flop of control counter 1813 to be set to a I state and the flip flop Pl is reset to a 0 state at the following CLK pulse, thereby causing RM 3-2 of the flow to be entered During RM-3-2, the true signal at the P 2 output causes the address contained in the WAS pointer register to be 25 counted down by 1, in order to achieve the address of the highest value written into the write area of the AM-II MEMORY However, the counting down of the WAS register has no purpose during the first time through the flow of the REVOLVE 3 MODULE The true signal at the P 2 output and the true condition of logic P 2 CLK causes true signals at the A 3 R 4 and A 3 R 5 outputs fo the input/output control lines 30 for the REVOLVE 3 MODULE The true signal at the A 3 R 4 output enables the occurrence value from the input line provided by the DECODE I MODULE to be coupled as the shift value to the input of the DELV register in the DELTA 2 MODULE The true signal at the A 3 R 5 output causes this occurrence value (shift value) to be stored into the DELV register 35 If an overflow condition has not been detected or the end of Delta line has not been reached in the DELTA 2 MODULE, true signals are fomed at the DELOVI and DELEND outputs of the DELTA 2 MODULE Also, if the WAT pointer register has reached a O state, a true signal is formed at the w, output Under these conditions, the logic DELOVL DELEND w% is true (see input to P 3 flip flop) If 40 either the foregoing logic is true or the WAT counter is not 0, the logic P 2.(DELOVL DELEND W O + w%) is true and ai the following CLK pulse the P 3 flipflop is set to a 1 state Referring to the flow M it will be noted that when the P 3 flip flop is in a 1 state, either RM 3-5 or RM 3-7 is entered in the flow RM 37 is entered if the WAT pointer register is not 0 (wa) 45 During the first time through the flow, the WAT pointer register will contain a 0 Accordingly, RM 3-5 is entered If neither the DELOVL nor the DELEND is true, RM 3-6 is entered after RM 3-5 where the maximum value 255 is stored into the register RI.
Referring to Fig 68, it will be noted that a true signal at the W O output causes 50 the output of the switches 1844, which represent the maximum value 255, to be coupled through the DSI selection circuit to the input of the RI register.
Additionally, the logic P 31 LK becomes true and the maximum value 255 is stored into the register RI Since the output DELEND is true, the logic P 3 DELEND is now true and at the following CLK pulse the P 4 flip flop is set to a 1 state and the P 3 55 flip flop is reset to a 0 state causing RM 3-8 of the flow to be entered.
Returing to RM 3-4 and assuming that the WAT register does not contain a 0, a true signal is formed at the W O output and at this time the P 3 flip flop is in a 1 state.
Thus the logic P 3 CLK becomes true, causing a true signal at the A 3 R 6 output which in turn calls the operation of the DELTA 2 MODULE (Note that this action 60 is actually depicted, for ease of explanation, during RM 3-8 of the flow) In addition, the true condition of the logic wj P 3 causes a true signal at the A 3 R 7 output of the REVOLVE 3 MODULE which in turn causes a read operation in the AM-II MEMORY Referring to the clock suspension logic 1822, the logic A 3 R 6 D 1 JENU now becomes causing the generalized clock control 700 to suspend 65 1,570,344 201 1,570,344 201 operation pending the completion of operation of the DELTA 2 MODULE.
If during the true signal at the P 3 output the WAT register does not contain a 0 a true signal is formed at the W, output causing the DSI selection circuit to couple the output of the AM-II MEMORY through to the input of the RI register The true signal at the P 3 output causes the D 55 selection circuit to couple the address from the WAP pointer register to the address input of the AMIl MEMORY specifying the address from which the read for the RI register is made.
The true condition of the logic P 3 CK thus causes the value read from the AM-II MEMORY to be stored into register RI In addition, the logic H w C CLK becomes true causing the WAP pointer register to be counted up one address so 10 that it now contains the address fo the next available location in the AMII MEMORY write area.
The logic P 3 DELEND is also true during RM 3-7 After the DELTA 2 MODULE has completed its operation and the DMEND output thereof becomes true, and the logic A 3 R 6 DMEN U becomes false, the clock suspension logic 1822 is removes the true signal at the CS input causing the generalized clock control to again form its CLK pulses The following CLK pulse causes the P 4 flip flop to be set to a I state and the P 3 flip flop is reset to a 0 state causing RM 3-8 of the flow to be entered.
Consider now the operation during RM 2-8 If an overflow has not occurred 20 in the DELTA 2 MODULE, the output DELOVL is true Accordingly, the logic P 4.DELOVL is true causing the D 52 selection circuits to couple the Delta line value from the DELO register of the DELTA 2 MODULE to the input of the RII register The logic P 4 Cl K subsequently becomes true causing the Delta line value to be stored into register RIL However, if an overflow has occurred in the DELTA 25 2 MODULE, a true signal is formed at the DELOVL output thereof causing the logic P 4 DELOVL to be true which in turn causes the maximum value 255 to be coupled from the switches 1842 to the input of the register RII where it is stored.
The true signal at the P 4 output causes the P 5 flip flop to be set to a I state and the P 4 flip flop to be reset to a 0 state at the following CLK pulse thereby causing 30 RM 3-9 of the flow to be entered RM 3-9 through RM 3-12 carry out the exclusive OR operation similar to RM 2-9 through RM 2-12 of the REVOLVE 2 MODULE with a few exceptions.
Considering now in more detail the operation it will be noted that the lesser of the two values stored in the RI and RII registers is to be written out in the AM-Il 35 MEMORY But if the two values are equal then neither is to be written to the AM-II MEMORY.
The true signal at the P 5 output of the P 5 flip flop causes the comparator 1850 to compare the contents of the registers RI and RII.
Assume that the comparator 1850 detects that the content of registers RI and 40 RII are equal and therefore RM 3-11 is entered A true signal is fomed at the EQ output and the logic P 5 EQ,CLK becomes true, causing the ET flip flop to be set to a 1 state If the WAT counter is nut 0, W O is true and the logic P 5:N W O CLK becomes true, causing the WAT pointer to be counted down 1 The logic P 5 EQ(DELOVL DELEND wo + w,) now becomes true and at the following CLK 45 pulse, flip flop P 3 is set to a 1 state and flip flop P 5 is reset to a 0 state, causing RM 3-4 to be reentered Thus, it wil be seen that nothing is written into the AM-II MEMORY and the pointer register WAT is merely counted down by 1 during RM 3-11 after an equality is detected between RI and RII.
Returning now to RM 3-9 and assume that the content of register RI is less so than that of register RII The comparator 1850 forms a true signal at the M output of the signal inverter 1856 and a true signal at the LS output The logic P 5 LS CLK becomes true, causing the LT flip flop to be set to a 1 state and the logic P 5, EQ becomes true, cauing the P 6 flip flop to be set to a 1 state, and the P 5 flip flop is reset to a 0 state thereby causing RM 3-12 of the flow to be entered The logic 55 P 5.w O CLK is again true, causing the WAT pointer to be counted down by 1.
The logic P 6 LT is true, causing the D 54 selection circuit to couple the output of register RI to the input of the AM-II MEMORY The true signal at the P 6 output also causes a true signal at the A 3 R 9 output of the input/output control lines, causing the AM-II MEMORY to write the value from register RI 60 The logic P 6 LT is true, and at the following CLK pulse, flip flop P 7 is set to a 1 state and flip flop P 6 is reset to a 0 state causing RM 3-13 of the flow to be entered.
RM 3-13, RM 3-14 and RM 3-15 are provided similar to the REVOLVE 2 MODULE to check to see if there is anything more to be read from the read area of the AM-IL MEMORY and if so, to read the value for storage in register RI If 65 201 1,570,344 201 the WAT pointer has for some reason been counted down to 0, then during RM 3-13 the maximum value 255 is stored into register RI to so indicate rather than a value from the AM-II MEMORY Following eithere RM 3-15 or RM 3-14 RM 3-9 or the flow is reentered To this end, the true signal at the P 7 output causes the flop flop P 5 to be set to a I state at the P 7 output causes the flip 5 flop P 5 to be set to a I state and flip flop P 7 to be reset to a 0 state at the following CLK pulses.
Similarly, if the content of register RII is less than that of register RI, during RM 3-9 the comparator forms a true signal at the Ni output and the inverter 1856 forms a true signal at EQ Logic P 5 NX CLK is true and the flip flop GT is set to a 1 10 state The logic P 5,EQ is again true, causing the P 6 flip flop to be set to a I state, and flip flop P 5 is reset to a 0 state at the following CLK pulse, causing RM 3-10 of the flow to be entered.
During the signal at the P 6 output, the logic P 6 GT is true, causing the D 54 selection circuit to couple the lesser value in register RII to the input of the 15 AM-I 1 MEMORY Additionally, the true signal at the P 6 output causes a true signal at the A 3 R 9 output of the input/output control lines, causing the AM-II MEMORY to write the value from register R 11.
Additionally the logic P 6 CLK becomes true, causing the WPB pointer to be counted down by 1 so that it now contains the address of the next location in the 20 AM-II MEMORY at which writing is to take place Following RM 3-10, RM 3-8 is reentered If there is still output to be provided by DELTA 2 the DELEND output of the DELTA 2 MODULE is true Thus the circuit P 6.GT DEL ND is true causing the P 4 flip flop to be set to 1 Additionally the A 3 R 6 signal becomes true causing the DELTA 2 MODULE to be activated 25 Meanwhile the A 3 R 6 DMEND circuit becomes true causing the clock in the REVOLVE 3 MODULE to be disabled When the DELTA 2 MODULE completes, the REVOLVE 3 MODULE clock is enabled and the next CLK pulse causes the P 6 flip flop to be resent to 0 and the P 4 flip flop to be set to 1.
The above sequence of operation for RM 3-8 through RM 3-15 continues 30 until one of two exits occurs One exit occurs during RM 3-8 when the last shifted occurrence value is provided from a line of the Delta by the DELTA 2 MODULE.
Under these conditions, a true signal is formed at the DELEND output which causes RM 3-16 to be entered To this end, the true condition of logic P 6 DELEND causes to P 8 flip flop to be set to a 1 state, causing RM 316 to be 35 entered.
During RM 3-16, the content of the WAT pointer is checked to determine if it is less than 2 The true signal at the P 8 output causes the compare circuit 1852 to be enabled and forms a true signal at the GE and L outputs, respectively, if the content of the WAT pointer is greater than, equal to, or less than, value 2 40 (represented by the output signals from the switches 1840).
If the content of the WAT pointer is equal to or greater than 2, then the operation of the REVOLVE 3 MODULE is finished as there are at least two values in the AM-IL MEMORY which will no longer be modified by future XOR’s with occurrence values sent by the DELTA 2 MODULE When this occurs, the 45 compare circuit 1852 causes a true signal at the GE output of the OR gate 1860, causing the logic P 8 GE to be true At the following CLK pulse, the P 11 flip flop is set to a 1 state, and the P 8 flip flop is reset to a 0 state, causing RM 3-20 to be entered.
The true signal at the Pl 1 output causes the A 3 R 7 output of the input/output 50 control lines to be true, thereby causing the AM-II MEMORY to read the next value from the location specified by the WAS pointer Additionally, the true condition of logic Pl l CLK causes the WAS pointer to count down by 1 address.
The logic P 11 CLK also causes the value read from the AM II MEMORY to be stored into the NI register 55 The true condition of logic Pl 1 causes the flip flop Pl to be reset to a 0 state and flip flop P 12 to be set to a 1 state, thereby causing RM 3-21 to be entered The true condition of the P 12 output again causes a true condition at the A 3 R 7 output, causing the AM II MEMORY to read out the next value The true condition of logic P 12 CLK causes the N 2 register to store the current value from the AM II 60 MEMORY and the true condition of logic P 12 CLK causes the WAS pointer to count down by 1 additional address At this point in time the Nl and N 2 registers contain the rightmost and next to the rightmost occurrence values in the line of the iso-entropicgram being generated Subsequently the operation of the REVOLVE 3 MODULE is exited 65 202 1,570,344 202 Returing to RM 3-16, assume that the AM II MEMORY does not contain at least two values which will not remain unaltered Under these conditions WAT will contain a value less than 2 and the compare circuit 1852 forms a true signal at the L output, indicating that the content of the WAT register is less than the value 2 provided by the switches 1840, causing RM 3-17 to be entered The true condition 5 of the P 8 output causes the D 52 selection circuit to couple the maximum value 255 from the switches 1842 to the input of register Rll Additionally, the logic P 8.L CEK becomes true, and the maximum value 255 is stored into the register Rll Subsequently, RM 3-9 of the flow is reentered where the XOR operation is performed and pulse P 5 is reentered Since the maximum value 255 is contained in 10 register RII, it will be the maximum value and accordingly RM 3-12 through RM 3-15 will be entered where the value in register RI is stored into the AM II MEMORY The WAT pointer is counted down by 1, and the next value is read from the AM 11 MEMORY and stored into register RI When the WAT pointer has been counted down to 0, a true signal is formed at the w% ooutput, causing RM 3-15 15 of the flow to be entered Subsequently, RM 3-9 of the flow is reentered where the maximum value 255 stored in both registers RI and RII is found to be equal and hence RM 3-11 is entered, followed by RM 3-4 Pulse P 3 is in a 1 state Since the WAT pointer now contains a 0, a true signal is formed at the w output, causing RM 3-5 of the flow to be entered Since it is assumed that a true signal is formed at 20 the DELEND output of the DELTA 2 MODULE, indicating the last of the shifted occurrence values from a line of the delta, RM 3-22 is entered To this end, the true condition of the logic P 3 (DELEND+DELOVL) causes the flip flop P 10 to be set to a I state, causing RM 3-22 to be entered following RM 3-5 where the content of the WPB pointer is transferred to the WAS and WAT pointers and the 25 WAP and WPB pointers are reset to 0 Additionally, the SM flip flop in the AM II MEMORY is complemented, causing the read and write areas to interchange, and DELFST is triggered in the DECODE I MODULE, calling its operation, thereby causing the next actual occurrence value to be provided by the DECODE I MODULE from the original input line being processed 30 The sequence of operation subsequent thereto is similar to that described above.
Assume now that during RM 3-3, the last actual occurrence value of the original input line has been processed and the DECODE I MODULE provides a true signal at the EOFI output so indicating The flip flop P 10 in the control 35 counter 1813 is now true, and the logic P 1 O EOFI is true, causing the flip flop P 9 to be set to a 1 state, thereby causing the RM 3-18 to be entered During RM 3-18, the WAT pointer is again compared with the value 2, to determine if it is greater than or equal to 2, in which case RM 3-20 and RM 3-21 are entered, where the two values are read from the AM-II MEMORY and stored into the NI and N 2 40 registers as discussed above If, on the other hand, the content of the WAT pointer is less than 2, there are less than two values remaining to be read from the AM-I 1 MEMORY Under these conditions, WAT will always be 1 since there must be at least one actual occurrence value in any line of any iso-entropicgram A true signal is formed at the P 9 output thereby causing RM 3-19 to be entered During 45 RM 3-19 a true signal is formed at the P 9 output Since the content of the WAT pointer is less than 2, the compare circuit 1852 forms a true signal at the L output causing the logic P 9 L CK to be true, which in turn causes the NI register to be cleared to 0 The logic P 9 L is also true and at the following CLK pulse the flip flop P 12 is set to a 1 state and the P 9 flip flop is reset to a 0 state, thereby causing so RM 3-21 to be entered where the one remaining occurrence value in the AMII MEMORY is read and stored into N 2 register as discussed above.
Under the conditions discussed above where the WAT pointer is less than 2, this indicates that the rightmost possible occurrence value is 0, while the next to the rightmost possible occurrence value is not 0 This is quite important, as mentioned 55 above, since there is at least one occurrence value in any line of any isoentropicgram Setting Nl to 0 insures that the fast seed finding operation will halt If WAT is greater than or equal to 2 then RM 3-20 and RM 3-21 are entered as described above.
D Example of Operation 60 Assume now that the REVOLVE 3 MODULE is to revolve the input line of the iso-entropicgram depicted in Table 51, line 0, by three lines According to the fast seed finding operation, the REVOLVE 3 MODULE operates so as to generate the desired line of the iso-entropicgram starting with the largest occurrence value until 203 I 1,570,344 203 it has generated 2 occurrence values that will appear in the desired line In other words, the sequence of operation depicted at Table 52 is performed until two occurrence values are formed which will no longer be altered by future shifted lines of the Delta provided by the DELTA 2 MODULE Once the two occurrence values in the desired line are formed they are sent to the SEED 3 MODULE If the 5 desired line only has one occurrence value then, as mentioned above, there will only be one occurrence value and not two and the mechanism disclosed herein handles this condition.
Initially, T 3 of the SEED 2 MODULE is loaded with the value 3 which is the number of lines to be revolved The MEMORY MODULE area 1 is loaded with an 10 event occurrence vector (EO Vector) representative of the values 0,2,3,5 which is the input line of the iso-entropicgram depicted in Table 51 Initially, the SEED 2 MODULE forms a true signal at the A 255 output which causes the RIL register of the REVOLVE 3 MODULE to store the value 3 from register T 3 in the SEED 2 MODULE The EO Vector 0,2,3,5 is stored in the MEMORY MODULE and is accordingly the DECODE I MODULE is about to read and decode the EO Vector into absolute coded form The initial conditions are depicted, under this heading, in Table 55.
During the subsequent operation which will be referred to as Cycle 1, the DELTA 2 MODULE will form the occurrence values 5,6,7 which will be stored 20 into addresses 0,1 and 2 of the AM-II MEMORY area 2, and at the end the WAS and WAT pointers will contain the value 3 as depicted under the heading Conditions After Cycle 1 (Table 55).
Considering the operation, initially a true signal is formed at the A 255 output of the SEED 2 MODULE causing the generalized clock control 700 to commence 25 providing clock pulses to the control counter 1813 Subsequently, a true signal is formed at the A 3 R 1 output of the REVOLVE 3 MODULE, causing the DELFST flip flop in the DELTA 2 MODULE and the DIFST flip flop in the DECODE I MODULE to be set to 1 states, indicating that this is the first call on these modules.
Additionally, the true signal at the A 3 R 1 output enables the output of the RIL 30 register to be coupled through to the input of the DELRO register in the DELTA 2 MODULE.
Subsequently, a true signal is formed at the A 3 R 2 output which causes the DELRO register to store the value 3 from the RIL register of the REVOLVE 3 MODULE into the DELRO register of the DELTA 2 MODULE Additionally, the 35 true signal at the Pl output causes the WAT, WAS, WAP and WPB pointers to be reset to 0 Thus, all pointers are at 0 The true signal at Pl causes a true signal at theA 3 R 8 output which in turn sets the SM flip flop in the AM-II MEMORY so that the first write takes place in area 2.
RM 3-2 of the flow is now entered where a true signal is formed at the P 2 40 output which in turn causes the WAS pointer to be counted down by 1 value This has no particular meaning during this portion of the operation.
RM 3-3 of the flow is entered During the previous true signal at the Pl output the logic CLK Pl becomes true, causing a true signal at the A 3 R 3 output.
The true signal at the A 3 R 3 output called the operation of the DECODE I 45 MODULE causing it to provide the largest occurrence value from the EO Vector original input line Additionally, the true signal at the A 3 R 3 output causes the following logic to be true: A 3 R 3 DIMEND This causes the clock suspension logic 1822 to apply a true signal to the CS input of the generalized clock control 700, suspending its operation until the DECODE I MODULE returns the value 5 50 Dl MEND is now true re-enabling the block and, if EOFI is not set, Pl is reset to 0 and P 2 is set to 1 After the DECODE I MODULE has provided the value 5 from the input line, the D 1 MEND input becomes false, causing the clock suspension logic 1822 to apply a false signal at the CS input of the generalized clock control 700, enabling clock pulses to again be formed 55 Subsequently, a true signal is formed at the P 2 output and the logic P 2 CLK becomes true, causing true signals at the A 3 R 4 and A 3 R 5 outputs of the REVOLVE 3 MODULE The true signal at the A 3 R 4 output enables the aboslute coded value 5 from the output of the DECODE I MODULE to be applied to the input of the DELV register of the DECODE II MODULE and the A 3 R 5 signal 60 causes the value to be stored in the DELV register.
Since the end of the EO Vector original input line has not yet been reached by the DECODE I MODULE, the EOFI flip flop of the DECODE I MODULE applies a true signal at the EWI output Thus, following RM 3-3, RM 3-4 is entered Since the WAT pointer now contains a 0, RM 3-5 is entered Since the 65 204 1,570,344 204 DECODE II MODULE has not reached the end of the Delta line nor has an overflow occurred both of the outputs DELEND and DELOVL are false (i e.
1 DELEND and DELOVL are true) Accordingly, RM 3-6 of the flow is entered.
The true signal at the w, output and the true condition of logic P 3 CLK causes the maximum value 255 to be stored from the switches 1844 into the register RI 5 RM 3-8 of the flow is now entered The logic P 3 CUK being true causes a true signal at the A 3 R 6 output The true signal at the A 3 R 6 output calls the operation of the DELTA 2 MODULE causing it to provide the first occurrence value from line 3 of the Delta, offset by 5 (the occurrence value of the input line received from the DECODE I MODULE) With reference to the discussion in the REVOLVE 2 10 MODULE, it will be recalled that the first value in line 3 of the Delta is 0 which, added to the offset 5, results in the shifted Delta value of 5 The true condition of logic P 4 DELOVL and P 4 CLK causes the shifted Delta value 5 in register DELO of the DELTA 2 MODULE to be stored into register RII of the REVOLVE 3 MODULE 15 RM 3-9 of the flow is now entered where the shifted Delta value 5 in register RII is compared with the maximum value 255 contained in register RI Since the content of register RII ( 5) is the lesser, RM 3-10 of the flow is entered.
During RM 3-10, a true signal is formed at the P 6 output which in turn causes a true signal at the A 3 R 9 output of the REVOLVE 3 MODULE The logic P 6 GT is 20 true, causing the shifted Delta value 5 to be coupled from register R Il into the information input ofthe AM-IL MEMORY and the true signal at the A 3 R 9 output causes the AM-II MEMORY to write the shifted Delta value 5 into address 0 of the AM-II MEMORY area 2 as designated by the address register WPB The logic P 6 CLK also causes the WPB pointer to be counted up to address 1 25 Following RM 3-10, RM 3-8 is reentered where the DELTA 2 MODULE is again called so that it generates the next shifted Delta value of 6 (see Table 52).
RM 3-9 is reentered where the shifted occurrence value of 6 in register RII is found to be less than the maximum value 255 in register RI Accordingly, RM 3-10 is reentered where the value of 6 is stored at address I of the AM-II MEMORY 30 area 2 and the WPB pointer is again counted up by one address to address 2.
RM 3-8, RM 3-9 and RM 3-10 are again reentered where the DECODE II MODULE provides the next shifted occurrence value of 7 which is stored in register RII and subsequently written into address 2 of the AM-II MEMORY area 2, and the WPB pointer is counted up by I to address 3 At this point the AM-II 35 MEMORY area 2 is as depicted under Conditions After Cycle 1, Table 55.
RM 3-8 is reentered However, this time the iso-entropicgram width ( 8) has been exceeded Accordingly, the DELTA 2 MODULE forms a true signal at the DELOVL output The true signal at the DELOVL output causes the logic P 4 DELVOVL to be true Additionally, the logic P 4 CLK is true Therefore, during 40 RM 3-8 the maximum value 255 is stored from the switches 1842 into register R 11.
During RM 3-9, the comparator 1850 detects the same value, i e, 255, in both registers RI and RII and accordingly RM 3-11 is entered However, since the WAT pointer is already 0, it is not counted down.
RM 3-4 of the flow is reentered Since the WAT pointer is at 0 RM 3-5 is 45 reentered Since the DELOVL output of the DECODE II MODULE is true, RM 3-22 of the flow is entered At this time, a true signal is formed at the Pl O output Accordingly, the WAS and WAT pointers are loaded with the address 3 contained in the WPB pointer The true signal at the Pl O output also causes a true signal at the A 3 RIO output which toggles the SM flip flop in the AM-II 50 MEMORY and sets the DELFST flip flop in the DELTA 2 MODULE to a 1 state.
At this point Cycle 1 of the REVOLVE 3 MODULE is completed and all of the conditions depicted under the heading Conditions After Cycle 1 in Table 55 exist in the system.
During the second cycle of operation, the conditions depicted under the 55 heading Conditions After Cycle 2 are being generated.
RM 3-2 of the flow is reentered where the true signal at the P 2 output causes the WAS pointer to be counted down by 1 address to address 3.
RM 3-4 of the flow is now entered where the WAT pointer is checked to determine if it is 0 Since the WAT pointer now contains the value 3, it is not 0, and 60 accordingly RM 3-7 of the flow is entered rather than RM 3-5 as during Cycle 1.
During RM 3-7, the logic w; P 3 is true, causing a true signal at the A 3 R 7 output.
This causes the AM-II MEMORY to read the value 5 from AM-Il MEMORY area 2 from address 0 as specified by the WAT pointer The true condition of logic P 3 Wo CLK causes the WAP pointer to be counted up to address 1, so that it now 65 205 1,570,344 205 contains the address of the value 6 (see Conditions After Cycle 1, Table 55) The true signal at the P 3 output causes the logic P 3 CLK to become true which in turn causes a true signal at the A 3 R 6 output This in turn, as indicated during RM 3-8 of the flow, causes the DELTA 2 MODULE to start providing the next shifted line 3 of the Delta offset by 3 as designated by the RIL register Referring to Table 52, 5 line 3 of the Delta offset by 3 results in the values 3,4,5, and 6 Accordingly, the first shifted value 3 is now provided by the DELTA 2 MODULE.
Subsequently, the logic P 4 DELOVL becomes true, and the logic P 4 MTX becomes true, causing the shifted Delta value 3 to be stored into the register R 11.
RM 3-9 is now entered where the shifted Delta line value 5 (from AM-I 1 10 MEMORY area 2) stored in register RI is compared with the shifted line value 3 (from the DELTA 2 MODULE) contained in register RI.
: The value 5 contained in RII is found to be the larger and accordingly RM 3-10 is entered where the value 3 is stored in address 0 of the AM-IL MEMORY areal as specified by the WPB pointer The WPB pointer is then counted up I address to is address 1.
RM 3-8 is reentered where the DELTA 2 MODULE is again called, causing the next shifted Delta line value of 4 (see Table 52) to be provided and stored into register RI RM 3-9 is reentered where the shifted Delta value of 3 in register RI is found to be less than the shifted Delta line value of 4 in register R 11 Accordingly 20 RM 3-10 is reentered where the shifted Delta line value 4 is stored in address 1 of the AM-II MEMORY area 1 and the WPB pointer is counted up to address 2.
RM 3-8 is then reentered where the DELTA 2 MODULE is again called, causing the next shifted Delta line value of 5 to be read out and stored in register RI 25 RM 3-9 is then reentered Registers RI and RII now both contain shifted Delta line values of 5, and accordingly the equality causes RM 3-11 of the flow to be entered where the XOR operation takes place To this end, neither of the values in register RI or RII is stored Also, the logic P 5 Ni W O CLK becomes true, causing the WAT pointer to count down I address from 3 to 2 30 RM 3-4 of the flow is reentered where the WAT pointer is checked The WAT pointer at this point contains a 2, and is not 0; accordingly RM 3-7 is reentered During RM 3-7, the AM-II MEMORY area 2 address 1 (specified by the WAP pointer) is read With reference to Table 55 it will be noted that address 1 contains the value 6 and accordingly the value 6 is read and stored into register RI 35 and the WAP pointer is counted up 1 address to address 2.
RM 3-8 of the flow is reentered where the DELTA 2 MODULE is called causing the next shifted line value of 6 (see Table 52) to be provided and stored inmo register R 11.
RM 3-9 of the flow is reentered where registers RI and RI 1 are found to be 40 equal, causing RM 3-11 to be reentered where the two values in registers RI and RII are discarded During RM 3-11 the WAT pointer is counted down to 1.
RM 3-4 of the flow is reentered where the WAT pointer is found not to be 0 and accordingly RM 3-7 is reentered During RM 3-7, the address of the AMII MEMORY area 2 is read With reference to Table 55 it will be noted that the value 45 7 is read This value is stored into register RI The WAP pointer is counted up I address to address 3.
RM 3-8 is reentered However, the DELTA 2 MODULE had previously provided the last shifted Delta line value and accordingly a true signal is formed at the DELEND output of the DELTA 2 MODULE Accordingly, the D 52 selection 50 circuit causes the register RII to store the maximum value 255 from the switches 1842 and RM 3-16 is now entered rather than RM 3-9.
During RM 3-16 the WAT pointer contains a 1 and is therefore less than 2.
Accordingly, the compare circuit 1852 forms a true signal at the L output and the true condition of the output P 8 and the true condition of logic P 8 L CLK causes the 55 register RII to store the maximum value 255 from the switches 1842.
RM 3-9 of the flow is reentered where the value 7 in register RI is compared with the maximum value 255 in register RII Since register RI contains the smaller value, RM 3-12 is now entered During RM 3-12, the output P 6 is true, and accordingly a true signal is formed at the A 3 R 9 output of the REVOLVE 3 60 MODULE causing the AM-II MEMORY to write the value provided by the D 54 selection circuit Additionally the logic P 6 GT is true causing the D 54 selection circuit to couple the value 7 from register RI to the information input of the AM-II MEMORY The address 2 contained in the WPB pointer causes the 206 1,570,344 206 AM-II MEMQRY to store the value 7 at address 2 as depicted under Conditions After Cycle 2, Table 55.
The WAT pointer is counted down by I from I to O and RM 3-13 is entered.
Since the WAT pointer is now 0, RM 3-15 is entered where the true signal at the w O output and the true signal at the P 3 CLK output causes the maximum value 255 5 to be loaded into register RI from the switches 1844.
RM 3-9 is now reentered where it is found that both registers RI and RII contain the maximum value 255 and therefore are equal Accordingly RM 3-11 and RM 3-4 are reentered Since the WAT pointer is at 0, no decrement takes place During RM 3-4 it is found that the WAT pointer contains a O and a true 10 signal is being formed at the w, output Accordingly, RM 3-5 is entered.
During RM 3-5 a true signal is still being formed at the DELEND output of the DELTA 2 MODULE, causing RM 3-22 of the flow to be entered In the same manner discussed above, the address 3 contained in the WPB pointer is now loaded into the WAS and WAT pointers and the WAP and WPB pointers are reset to 0 15 Additionally, the flip flop SM is complemented and the DELFST flip flop in the DELTA 2 MODULE is set to 0 With the complementing of the flip flop SM, AM-II MEMORY area I will now be the new read area and area 2 the write area.
With reference to Conditions After Cycle 2, Table 55, the condition of the AM-Il MEMORY area 1 and the WAS and WAT pointers will be found 20 The third cycle of operation of the REVOLVE 3 MODULE is now entered where the information depicted under Conditions After Cycle 3, Table 55, are formed, starting with the initial conditions depicted under Conditions After Cycle 2.
To this end, RM 3-2 is reentered where the value 3 in the WAS pointer is 25 counted down to 2 During RM 3-3 the DECODE I MODULE is again called, causing it to provide the next actual occurrence value 2 of the EO vector for the input line stored in the MEMORY MODULE (see Table 52) The occurrence value 2 provided by the DECODE I MODULE is stored into the DELV register of the DELTA 2 MODULE During RM 3-4 it is found that the WAT pointer does 30 not contain a O and accordingly RM 3-7 is entered, where the value 3 is read from address O (specified by the WAP pointer) and is stored in register RI.
RM 3-8 of the flow is now entered where the DELTA 2 MODULE starts providing the shifting line values for line 3 of the Delta offset by 2, as indicated in Table 52 (With reference to Table 52 it will be seen that following Cycle 2, AM-I 1 35 MEMORY area 1 contains the actual occurrence values depicted “After First XOR” in Table 52) The first shifted Delta line value is a 2 (see Cycle 3 of Table 52), and the value is stored into register R 11 RM 3-9 is now entered where the value 2 in register RI 1 is found to be less than the value 3 in register RI Accordingly, RM 3-10 is entered where the smaller value 2 from register RH is stored into 40 address O of the AM-II MEMORY area 2, using address O contained in the WPB pointer Also, the WPB pointer is counted up by 1 to address I and RM 3-8 is reentered.
During RM 3-8, the DELTA 2 MODULE provides the next shifted Delta line value of 3 (see Cycle 3, Table 52) and the value is stored into register RI RM 3-9 45 is reentered where the value 3 stored in both registers RI and RII is detected as being equal and accordingly RM 3-l I is entered where both values are skipped over and the WAT pointer is counted down from 3 to 2 RM 3-4 and RM 3-7 are now reentered During RM 3-7 the next value, namely 4, is read from the AMII MEMORY area 1 (see Conditions After Cycle 2, Table 55) and the value is stored 50 into the register RI and the WAP pointer is counted up to address 2 RM 38 is now entered where the DELTA 2 MODULE provides the next shifted Delta line value of 4 During RM 3-9 the 4 in both of the registers RI and RII is detected as being equal and accordingly RM 3-11 is entered where both values are lost and the WAT pointer is counted down by 1 so that it now contains the value 1 55 RM 3-4 is reentered and since the WAT pointer is not 0, RM 3-7 is subsequently entered During RM 3-7, the value 7 is read from address 2 (specified by the WAP pointer) of the AM-II MEMORY area I and is stored into the register RI and the WAP pointer is counted up by 1 to address 3.
RM 3-8 is now entered where the DELTA 2 MODULE provides the next 60 shifted Delta line value of 5 (see Cycle 3, Table 52) Subsequently, RM 39 is entered where the value 5 in register RII is found to be smaller than the value 7 in register RI and accordingly RM 3-10 is entered where the value 5 is stored from register RII into address I (specified by the WPB register) of the AM-II MEMORY area 2 65 I 1,570,344 207 207 208 1,570,344 208 RM 3-8 is now reentered However, since the DELTA 2 MODULE has reached the end of the shifted Delta line value, a true signal is now formed at the DELEND output so indicating Accordingly, RM 3-16 is now reentered where the value I contained in the WAT pointer is found to be less than 2 and accordingly RM 3-17 is reentered where the maximum value 255 is stored into the register RI 5 During RM 3-9 the value 7 contained in register RI is found to be less than the maximum value 255 in register RII and accordingly RM 3-12 is entered where’ the value 7 is written into address 2 (specified by the WPB pointer) of the AM-II MEMORY area 2 Also, the WAT pointer is counted down by 1 to 0 and the WPB pointer is counted up by 1 to address 3 With reference to Table 55 it will be noted 10 that the Conditions After Cycle 3 are now present.
RM 3-13 is now entered where the WAT pointer is found to be 0 and accordingly RM 3-15 is entered where the maximum value 255 is stored into register RI RM 3-9, RM 3-11 and RM 3-4 are now successively reentered since the registers RI and RII now both contain the maximum value 255 However, the 15 WAT pointer contains a 0 and is unaltered Since the WAT pointer is at 0, RM 3-5 is entered following RM 3-4 The true condition of the output DELEND from the DELTA 2 MODULE causes RM 3-22 to be reentered where the value 3 contained in the WPB pointer is stored into the WAS and WAT pointers, where the WPB and WAP pointers are reset to 0, where the flop flip SM is complemented so 20 that in the AM-II MEMORY, area 2 becomes the read area and area 1 becomes the write area, and the DELFST flip flop in the DELTA 2 MODULE is set to 1.
This then becomes the end of Cycle 3 and the AM-II MEMORY area 2 and the WAS and WAT pointers contain the values depicted -under the heading Conditions After Cycle 3 in Table 55 25 At the beginning of Cycle 4, the conditions depicted under the heading Conditions After Cycle 3, Table 55, are present.
RM 3-2 is now entered where the WAS pointer is counted down from 3 to 2.
During RM 3-3 the DECODE I MODULE provides the next lower actual occurrence value of the input line, namely, the actual occurrence value 0 which is 30 stored into the DELV register of the DELTA 2 MODULE During RM 3-4 the WAT pointer contains the value 3, and accordingly is not 0, and RM 3-7 is entered During RM 3-7, the value 2 is read from address 0 (specified by the WAP pointer) of the AM-II MEMORY area 2, and the value 2 is stored into the register RI The WAP pointer is counted up from address 0 to address 1 During RM 38, 35 the DELTA 2 MODULE provides the first value from the shifted Delta line, offset by 0 (see Cycles 4, 5, Table 52) The first shifted Delta line value is 0 and this value is stored into register RI.
RM 3-9 is now entered where the value 0 contained in register RII is found to be less than the value 2 contained in register RI, and accordingly RM 310 is 40 entered where the value 0 is stored into address 0 of the AM-II MEMORY area 1, and the WPB pointer is counted up from 0 to 1.
RM 3-8 is reentered where the DELTA 2 MODULE provides the next shifted Delta line value of 1 (see Cycles 4, 5, Table 52) The value is now stored into register Rll During RM 3-9, the value 1 in register RII is found to be less than the 45 value 2 contained in register RI and accordingly RM 3-10 is reentered where the value I is written into the AM-II MEMORY area 1 at address 1 (specified by the WPB pointer) and the WPB pointer is counted up to address 2.
RM 3-8 is reentered where the DELTA 2 MODULE provides the next shifted Delta line value of 2 for storage in the register R 11 During RM 3-9, the value 2 50 stored in both registers RI and RII is detected as being equal and accordingly RM 3-11 is entered where these values are discarded and the WAT pointer is counted down by I from 3 to 2 RM 3-4 is reentered where the WAT pointer is found not to be 0; accordingly, RM 3-7 is reentered.
During RM 3-7 the value contained at address 1 (specified by the WAP 55 pointer) is read from the AM-II MEMORY area 2 and stored into register RI.
The WAP pointer is counted up by 1 to address 2 During RM 3-8 the DELTA 2 MODULE provides the next shifted Delta line value of 3 for storage in register Rll.
During RM 3-9, the value 3 in register RII is found to be the smaller and accordingly RM 3-10 is reentered where the value 3 is written into address 2 60 (specified by the WPB pointer) of the AM-II MEMORY area 1, and the WPB pointer is counted up by 1.
RM 3-8 is now reentered where the DELTA 2 MODULE is forming a true signal at the DELEND output indicating that the last of the shifted Delta line values has been provided Accordingly, RM 3-16 is entered 65 209 1,570,344 209 20 At this time, during RM 3-16 the content of the WAT pointer is found to be equal to 2 and accordingly the compare circuit 1852 forms a true signal at the E output, causing the OR gate 1860 to form a true signal at the GE output The WAS pointer at this juncture contains the address 2, pointing at address 2 of the AM-11 MEMORY area 2 (see Conditions After Cycle 3, Table 55) During RM 3-20, a 5 true signal is formed at the Pl 1 output which causes a true signal at the A 3 R 7 output of the REVOLVE 3 MODULE The true signal at the A 3 R 7 output causes the AM-Il MEMORY to read the value 7 from address 2 (specified by the WAS pointer) in the AM-II MEMORY area 2 The value 7 is provided at the input of the NI register of the REVOLVE 3 MODULE and the true condition of logic 10 Pl I CL 1 causes the value 7 to be stored into register NI The true condition of logic Pl I CLK causes the WAS pointer to be counted down 1 to address 1, and RM 3-21 is entered During RM 3-21, a true signal is formed at the P 12 output again causing a true signal at the A 3 R 7 output The AM-LI MEMORY reads out address I (specified by the WAS pointer) and the value 5 contained there is applied is to the input of register N 2 of the REVOLVE 3 MODULE The true condition of logic P 12 CLK causes the register N 2 to store the value 5 from the AMII MEMORY Additionally, the true condition of logic P 12 CLK causes the WAS pointer to count down from address I to address 0 At this point the operation of the REVOLVE 3 MODULE is exited At this point in time the NI and N 2 registers 20 contain the values 7 and 5, respectively With reference to Table 51 it will be noted that the values 7 and 5 correspond to the rightmost actual occurrence value and the nextmost actual occurrence value in line 3 of the iso-entropicgram.
XXV SEED 2 MODULE A General Description 25
According to this preferred embodiment of the invention special data processing means is provided for locating the desired seed in the isoentropicgram without the necessity of generating the entire line of each intermediate line used in locating the seed Advantageously, this increases the speed with which the seed is located in an iso-entropicgram Briefly, according to this embodiment the data 30 processing means goes from one line to a second line in the isoentropicgram by determining the difference between the largest two actual occurrence values in the first line and the difference between the width of the iso-entropicgram and the largest of the actual occurrence values in the first line The largest of these two differences indicates the number of lines by which the second line is displaced from 35 the first line in the iso-entropicgram Identification of the shortest line generated during this repeated process is retained The process stops when any subsequent line is found to be past the bottom end of the iso-entropicgram.
The right hand side of Table 4 B gives an abbreviated example of how this preferred embodiment of the present invention moves from one line to the next in 40 the iso-entropicgram while locating thc seed.
The SEED 2 MODULE is the principal control module in locating a seed The method involved is referred to herein as the fast seed finding method The SEED 2 MODULE in finding a seed calls the REVOLVE 2 MODULE and the REVOLVE 3 MODULE discussed hereinabove Briefly, the method involved gains speed by 45 generating only the largest two (or end two) actual occurrence values of any given line of an iso-entropicgram and based on these two values and the width of the isoentropicgram determines whether a seed line has been reached Once it has been determined that a seed line has been reached, the entire line is generated by the REVOLVE 2 MODULE 50 In addition to the control function of the SEED 2 MODULE, the SEED 2 MODULE receives the largest two occurrence values of the given line or input line of an iso-entropicgram from the DECODE I MODULE and determines the difference between these two values and the difference between the width of the iso-entropicgram and the largest occurrence value Subsequently the SEED 2 55 MODULE receives the largest two occurrence values provided by the REVOLVE 3 MODULE and determines the difference between these two values and the width of the iso-entropicgram in order to determine the number of lines by which a revolve must occur to locate the next line in the same iso-entropicgram in the process of locating the seed 60 These and other functions of the SEED 2 MODULE become clear in the detailed description.
The following discussion makes reference to the SEED 2 MODULE flow diagram depicted in Fig 73.
209 1,570,344 209 Briefly, the operation of the SEED 2 MODULE can be summarized as follows.
Initially the following parameters are clocked from the IPRF to the respective modules and registers as follows: The length of the seed is clocked into MLNI of DECODE I, line # is clocked into SMLI of SEED 2, iso-entropicgram width is clocked into SMHW of SEED 2 and EHW of ENCODE MODULES 5 The SEED 2 MODULE initially enters SB 2-1 responsive to a true signal at either of the outputs SM 2 GO or CM 2 formed by the DPM INTERFACE and CHANGE 2 MODULES, respectively.
Additionally, the seed line indicator register SLINE in the SEED 2 MODULE is reset to 0 and the T 3 position indicator is reset to 0 To be explained in more 10 detail, these two registers are reset to 0 since it is assumed that the SEED 2 MODULE is always starting from the 0 or input line of an isoentroipicgram in locating the seed line.
During SB 2-2 the DECODE I MODULE is called The DECODE I MODULE is now reading the given or input line of the iso-entrogicgram starting 15 with the largest occurrence value Accordingly the DECODE I MODULE first Drovides the largest occurrence value from the EO vector and this value is stored in the SN and TO registers of the SEED 2 MODULE Additionally the SEED 2 MODULE, using the ALU, determines the difference between the iso-entropicgram width value contained in register SMHW and the largest occurrence value 20 received from the DECODE I MODULE and the difference is stored in the TI register SB 2-3 is then entered where the next to largest occurrence value is provided by the DECODE I MODULE to the SEED 2 MODULE and ALU determines the difference between the largest (register TO) and the next to largest occurrence value and the result is stored in register TO At this point in time the 25 register TI contains the difference between the iso-entropicgram width value and the largest occurrence value from the given line of the iso-entropicgram and the register TO contains the difference between the largest and next to largest occurrence values of the same given line During SB 2-4 and SB 12-5, register Tl and TO are checked to see if register TI contains the largest and if not, the largest is 30 stored into register Tl.
During SB 2-6, the largest value contained in register T 1 is added to the content of register T 3 so that register T 3 contains the number of the next line of the iso-entropicgram which is to be formed.
During SB 2-7, the line number in register T 3 is compared with the width of the 35iso-entropicgram contained in SMHW and if the content of register T 3 is larger, the machine has revolved over the entire iso-entropicgram and accordingly, SB 2-12 through 52-16 are entered where the operation of the SEED 2 MODULE finally exits Returing to SB 2-7, if the content of register T 3 is the smaller, then SB 2-8 through SB 2-1 1 are entered where the largest and next largest occurrence values 40 of the next line in the iso-entropicgram are determined To this end, the SEED 2 MODULE calls the operation of the REVOLVE 3 MODULE during SB 2-8 and the desired line of the iso-entropicgram is transferred to register RIL of the REVOLVE 3 MODULE The REVOLVE 3 MODULE in turn returns the largest and next largest occurrence values from the new line of the isoentropicgram 45 SB 2-9 is used to determine whether the new line is shorter than the current seed line Initially it is assumed that the input line is the seed line and hence register SN was set to 0 during SB 2-2 For subsequent lines, the content of SN may not be 0 but will identify the line number of the shortest seed found to this point During SB 2-9 the SEED 2 MODULE determines whether the new line is shorter than 50 the current seed line by comparing the largest occurrence value contained in register Nl of the REVOLVE 3 MODULE with the content of register SN The seed line is defined as that line that has the largest number of O ‘s between the largest occurrence value and the edge of the iso-entropicgram The smaller of the values contained in registers SN and Nl will indicate the shortest line or possible 55 seed line If the new line of the iso-entropicgram is the shorter, register Nl will contain the smaller value and SB 2-10 will be entered where this length value will be stored into the SN register of the SEED 2 MODULE and the number of the new possible seed line now contained in register T 3 will be transferred to the SLINE register 60 If the presently assumed seed line is the smaller, then its largest occurrence value in register SN is smaller than the content of register NI of the REVOLVE 3 MODULE and SB 2-11 is entered after SB 2-9 where the difference between the iso-entropicgram width (SMHW) and the largest occurrence value (NI) is determined and stored into register Tl and the difference between the largest and 65 210 1,570,344 210 211 1,570,344 211 next largest occurrence values in registers NI and N 2 of the REVOLVE 3 MODULE is determined and stored into register TO Subsequently, control returns to SB 4 of the flow where the operation of SB 2-4 et seq is repeated Finally, during one of the passes through SB 2-7 it will be found that the number in register T 3 of the new line is larger than the width of the iso-entropicgram stored in register 5 SMHW and 5132-12 et seq will be entered.
During SB 2-12 the number of the seed line contained in register SLINE is transferred to the register RIL of the REVOLVE 2 MODULE and the operation of the REVOLVE 2 MODULE is called, causing the REVOLVE 2 MODULE to generate the designated line of the iso-entropicgram which is the seed line 10 During SB 2-13 the line number of the input line contained in register SMLI is added to the seed line number contained in register SLINE During SB 214 the width of the iso-entropicgram contained in register SMHW is compared against the value in register SMLI to see, if register SMLI contains the larger value This may occur if the SEED 2 MODULE is called by the CHANGE MODULE If the Is content of register SMLI is the larger, the iso-entropicgram width is subtracted from register SMLI during SB 2-15 Following the operation of the ENCODE 3 MODULE the new seed line will have been converted to hybrid code and stored in the MEMORY MODULE area 3.
Following SB 2-14 or SB 2-15, SB 2-16 is entered where the number of 20 actual occurrence values in the seed line is transferred from register ENOC of the ENCODE MODULE to register NOC of the SEED 2 MODULE and the length of the seed line contained in register MLN 3 of the ENCODE MODULE is transferred to register SLN of the SEED 2 MODULE.
The operation of the SEED 2 MODULE then exits leaving the seed line in 25 MEMORY MODULE area 3.
B Components Referring to Figs 71 and 72, the SEED 2 MODULE contains the following 8 bit registers: SN, TI, SMHW, TO, T 3, SMLI, NOC, SLN, and SLINE, all preferably of type SN 7400 disclosed in the above reference TTL book Also included are flip 30 flops CNG, SMB, and Pl through Pl 3 Each of these flip flops is of the leading edge trigger type discussed above Flip flops Pl through P 13 form a control counter 1913.
Selection circuits DSI through D 56 are provided for gating 8 binary coded bits of information from any one of the inputs shown along the upper side to a single 8 35 binary bit output shown along the lower side of each rectangular box The selection circuits are the same type discussed hereinabove and need not be considered in more detail at this point.
Conventional signal inverters 1930 and 1931 provide logical signal inversion for the signal applied at the respective inputs Boolean equations are used as 40 described hereinabove for depicting gating circuits required to control the various circuits of the SEED 2 MODULE.
Clock suspension logic 1922 is depicted using Boolean equations and provides signals to the CS input of the generalized clock control 700 for suspending the operation of the clock control 700 in the manner discussed in more detail herein 45 below and as discussed with respect to the generalized clock control 700 hereinabove.
An arithmetic logic unit (ALU) is provided for adding, subtracting and comparing the signals provided at the input shown along the upper side of the ALU The ALU is of the same type discussed hereinabove 50 Input/output control lines and information input/outputs are shown along the right hand side of Figs 71 and 72 Single lines are depicted by thin lines whereas multiple lines for carrying 8 binary bits of information are depicted in heavy solid lines.
C Detailed Description 55
Consider now the details of the SEED 2 MODULE The operation of the SEED 2 MODULE is called by the CHANGE 2 MODULE upon forming a true signal at the CM 2 GO output or by the DPM INTERFACE MODULE upon forming a true signal at the SM 2 GO output Either of these signals causes a true signal at the I input of the generalized clock control 700 which in turn causes clock 60 pulses to be formed at the CLK and CLK output Prior thereto the Pl through P 13 flip flops of the control counter 1913 were reset to 0 by a true signal at the MINIT 211 1,570,344 211 output of the DPM INTERFACE MODULE and accordingly are now in a 0 state.
Accordingly the logic P 1 + P 13 is now true and the following CLK pulse causes the Pl flip flop to be set to a 1 state thereby causing SB 2-1 of the flow to be entered The true signal formed at the Pl output sets the SMB flip flop to a 1 state, and clears the SLINE register to 0 The output Pl becomes true, causing the line 5 number of the input line to be gated through the D 54 selection circuit to the input of the SMLI register and the true condition of logic PL CULK causes the value to be stored into the SMLI register The true condition of the same logic Pl CLK causes the iso-entropicgram width to be stored into the SMHW register from the HW register of the IOPRF and resets the T 3 register to 0 The true signal at the Pl 10 output and the true condition of logic P 1 CLK also causes true signals at teh A 25 l and A 252 outputs The true signal at the A 2 SI output provides an enable signal to the following modules: DECODE I and II, ENCODE, SWITCH MATRIX 2 MODULES and sets the Dl FIRST flip flop of the DECODE I MODULE into a 1 state The true signal at the A 252 output causes the following to be stored into the 15 indicated registers: IR, TL, BL, HW, EIR, EBL, ETL, EHW of ENCODE MODULE, LNI to MLNI of DECODE I MODULE.
SB 2-2 of the flow is entered The true condition of logic P 1 CLK causes a true signal at the A 253 output which in turn calls the operation of the DECODE I MODULE, causing it to provide an occurrence value from the EO vector, in 20 MEMORY MODULE representing the given line of the iso-entropicgram which is about to be revolved to its seed During 51 82-2, the occurrence value provided by the DECODE I MODULE is the largest occurrence value in the given or input line By saving this value in register TO and by determining the difference between the iso-entropicgram width and the largest occurrence value, the given or input line 25 -is considered to be the current seed line.
The true condition of logic PI CLK DIMEND causes a true signal at the CS input of the generalized clock control 700 thereby causing it to suspend further clock pulses until the DECODE I MODULE provides its occurrence value When the DECODE I MODULE has provided its occurrence value in register DOI, the 30 output DIMEND of the DECODE I MODULE becomes false causing a false input at the CS input to the generalized clock control 700 The following CLK pulse sets the P 2 flip flop to a 1 state and resets the Pl flip flop to a 0 state The true signal at the P 2 output causes the DSI and D 53 selection circuits to gate the occurrence value in the D l register of the DECODE I MODULE to the input of the SN and TO 35 registers Additionally, the true signal at P 2 causes te D 55 and D 56 selection circuits to gate the iso-entropicgram width value from the SMHW register and the occurrence value from the DOI register of the DECODE I MODULE to the input of the ALU The true signal at the P 2 output causes the ALU to subtract the two values thereby forming, at the OP output therof, the difference between the largest 40 occurrence value of th given or input line and the width of the isoentropicgram.
The true signal at the P 2 output and the true condition of logic P 2 CLK causes the D 52 selection circuit to couple the difference value from the OP output to the input of the Tl register and causes it to be stored in the Tl register.
* The true signal at the P 2 CLK logic causes a true signal at the A 253 output 45 causing the DECODE I MODULE to be called a second time, causing the next to largest occurrence value of the given or input line to be stored in the DOI register to the DECODE I MODULE Similar to that described above, the logic P 2.MTK DTINEND causes the generalized clock control 700 to suspend its operation until after the DECODE I MODULE has provided the occurrence value so to register DOI After the DECODE I MODULE has completed this operation, the following CLK pulse causes the P 3 flip flop to be set to a I state and the P 2 flip flop to be reset to a 0 state in the control counter 913.
The true signal at the P 3 output causes the D 55 and D 56 selection circuits to couple the largest occurrence value in register TO and the next to largest 55 occurrence value contained in register DOI of the DECODE I MODULE to the input of the ALU The true signal at the P 3 output also causes the ALU to form the difference between the two values at the OP output thereof The true signal at the P 3 output in turn causes the D 53 selection circuit to couple the difference value to the input of the register TO and the true condition of logic P 3 CLK causes the 60 difference value to be stored in register TO.
Accordingly, at this time the register TI contains the difference between the iso-entropicgram width and the largest occurrence value, whereas the register TO contains the difference between the largest and next to largest occurrence value of the given or input line 65 212 1,570,344 2121 The true signal at the P 3 output also causes the P 4 flip flop to be set to a I state and the P 3 flip hop is reset to a 0 state at the following CLK pulse.
Briefly, during SB 2-4 and SB 2-5, the content of registers Tl and TO are compared and the larger of the two values is stored and ends up in register TI.
During SB 2-4, the true ‘condition at the P 4 output causes the D 55 and D 56 5 selection circuits to couple the content of registers Tl and TO to the input of the ALU and causes the ALU to compare the values The true signal at the P 4 output causes the D 52 selection circuit to couple the TO register to the input of register T I.
If the ALU detects that the content of register TI is less than that of re ister TO, a true signal is formed at the L output thereof causing the logic P 4 L to become 10 true which stores the content of register TO into register TI If the content of register Tl was originally the larger, or equal to that of register TO, SB 2-5 is skipped.
The true signal at the P 4 output causes the P 5 flip flop to be set to a I state and the P 4 flip flop is reset to a 0 state at the following CLK pulse, causing SB 2-6 of 1-5 the flow to be entered The true signal at the P 5 output causes the D 55 and D 56 selection circuits to couple the outputs of the TI and T 3 registers, respectively, to the input of the ALU The true signal at the P 5 output also causes the ALU to add the two values and form a sum at the output The register T 3 keeps a running tally of the number of lines by which the REVOLVE 3 MODULE has stepped through 20 the iso-entropicgram Since the larger difference value contained in register TI specifies the number of lines by which the REVOLVE 3 MODULE is to revolve for the next test, and the register T 3 contains the number of lines revolved to this point, the output of register OP now contains the total of the lines revolved The true signal at the P 5 output causes the logic P 5 CLK to become true and the output of 25 the ALU is stored into register T 3 The true signal at the P 5 output causes the P 6 flip flop to be set to a 1 state and the P 5 flip flop is reset to a 0 state at the following CLK pulse, thereby causing SB 2-7 to be entered.
During SB 2-7 the iso-entropicgram width value contained in register SMHW is compared with the total number of lines revolved contained in register T 3, and if 30 the content of SMHW is the larger, indicating that the iso-entropicgram has been passed over, SB 2-8 of the flow is entered To this end the true signal at the P 6 output causes the D 55 and D 56 selection circuits to couple the output of the registers SMHW to T 3 to the input of the ALU and causes the ALU to compare the two values If the content of register SMHW is the larger, a true signal is 35 formed at the G output of the ALU This causes the logic P 6 G and P 6 G CLK to become true, thereby causing true signals at the A 254 and A 255 outputs The true signal at the A 254 output enables the content of register T 3 to be applied to the input of register RIL in the REVOLVE 3 MODULE and the true signal at the A 255 output causes the value in register T 3 to be stored into register RIL Thus register 40 RIL now contains the new line number whose largest and next largest occurrence values are to be generated by the REVOLVE 3 MODULE The true signal at the A 255 output also calls the operation of the REVOLVE 3 MODULE.
The logic P 3 CL 1 RM 3 END is now true After the REVOLVE 3 MODULE completes its operation, the RM 3 END output becomes false, causing the CS input 45 of the generalized clock control 700 to become false, enabling the CLK and CK pulses to resume in the SEED 2 MODULE.
If, during SB 2-7, the content of register T 3 is found to be equal to or greater than that of register SMHW, the ALU will form a false signal at the G output causing the signal inverter 1930 to form a true signal at the G output This in turn 50 causes the logic P 6 G and P 6 G CLK to become true which in turn forms true signals at the A 256 and A 257 outputs of the SEED 2 MODULE The true signal at the A 256 output causes the output of register SLINE (which now stores the length of the current seed line) to be stored into register RIL of the REVOLVE 2 MODULE (rather than the REVOLVE 3 MODULE) and calls the operation of the 55 REVOLVE 2 MODULE In this manner the REVOLVE 2 MODULE will form the actual seed line specified by the line number contained in register SLINE Again, the true condition of logic P 6 CLK RM 2 END causes the clock suspension logic 1922 to suspend its operation until completion of operation of the REVOLVE 2 MODULE 60 Continuing with the operation following SB 2-8, the true condition of logic P 6.G causes the P 7 flip flop to be set to a 1 state and the P 6 flip flop to be reset to a 0 state, following the resumption of the CLK pulses following the end of the operation of the REVOLVE 3 MODULE Thus, SB 2-9 of the flow is entered.
During SB 289, a comparison is made between the largest occurrence value for 65 213 1,570,344 213 the seed line stored in register SN and the largest occurrence value provided by the REVOLVE 3 MODULE in register NI To this end, a true signal is formed at the P 7 output causing the D 55 and D 56 selection circuits to couple the SN register in the SEED 2 MODULE and the NI register in the REVOLVE 3 MODULE to the input of the ALU and causes the ALU to compare the two values Additionally, the true 5 signal at the P 7 output causes the DSI selection circuit to couple the output from the NI register of the REVOLVE 3 MODULE to the input of the SN register If the occurrence value in register Nl is the larger, the ALU forms a true signal at the G output, causing the logic P 7 G CLK to become true, thereby causing the SN register to store the occurrence value from register Nl The true condition of logic 10 P 7.G CLK also causes the SLINE register to store the total number of lines revolved from the T 3 register.
The following CLK pulse causes the P 8 flip flop to be set to a 1 state and the P 7 flip flop to be reset to a 0 state Assuming that the occurrence value in register NI is not larger than the largest occurrence value for the seed line contained in register 15 SN, SB 2-11 is entered To this end, the true signal at the P 8 output causes the D 55 and D 56 selection circuits to couple the width value in the SM Hw register in the SEED 2 MODULE and the largest occurrence value in the Nl register in the REVOLVE 3 MODULE to the input of the ALU and also causes the ALU to subtract the content of register NI from the content of the register SMHW The 20 true signal at the P 8 output causes the D 52 selection circuit to couple the difference to the input of register TI and the true condition of the logic P 8 C causes the value to be stored in register Tl Note that this step is comparable to the one indicated during SB 2-2 in that the largest occurrence value now being provided by the REVOLVE 3 MODULE is subtracted from the width of the iso 25 entropicgram and the value is stored in the register Tl The next CLK pulse causes the P 9 flip flop to be set to a 1 state and the P 8 flip flop to be reset to a 0 state.
The true signal at the P 9 output causes the Nl and N 2 registers to be coupled to the input of the ALU and the true signal at the P 9 output causes the ALU to subtract the two, thereby forming the difference of the largest and next largest 30 occurrence values formed by the REVOLVE 3 MODULE The true signal at the P 9 output causes the D 53 selection circuit to couple the difference to the input of the register TO and the true condition of logic P 9 CLK causes the difference to be stored in register TO.
At this point in time then the register Tl contains the difference between the 35 largest occurrence value and the width of the iso-entropicgram, whereas register TO contains the difference between the largest and next largest occurrence values for the next line of the iso-entropicgram as determined by the REVOLVE 3 MODULE.
The true signal at the P 9 output causes the P 4 flip flop to be set to a 1 state and 40 the P 9 flip flop is reset to a 0 state thereby causing SB 2-4 of the flow to be reentered.
Consider now SB 2-13 which follows SB 2-12 It will be recalled that SB 2-12 et seq is entered if the value in T 3 is found to be larger than that in SMHW, indicating that the lower end of the iso-entropicgram has been passed (i e, 45 see path out the right side of SB 287), or that the end of file has been reached by the DECODE I MODULE (see path out of right side of SB 2-3) It will also be recalled that during SB 2-12, the REVOLVE 2 MODULE has been called and has revolved the seed line which is now stored in MEMORY MODULE area 2 via the ENCODE MODULE 50 During SB 2-13, a true signal is formed at the P 10 output which causes the D 55 and D 56 selection circuits to couple the output of the registers SMLI and SLINE to the input of the ALU The true signal at the P 10 output also causes the ALU to add the two values Thus the ALU now contains the line number for the seed line relative to the input line stored into the SMLI register The true signal at 55 the Pl O output causes the D 54 selection circuit to couple the sum to the input of the SMLI register and the true condition of logic P 10 CLK causes the sum to be stored in register SMLI.
The true signal at the Pl O output causes the Pl 1 flip flop to be set to a I state and the Pl O flip flop to be reset to a 0 state at the following CLK pulse thereby 60 causing SB 2-14 to be entered.
During SB 2-14, the sum value stored in register SMLI is compared with the iso-entropicgram width contained in SMHW To this end, the true signal at the Pl 1 output causes the D 55 and D 56 selection circuits to couple the SMHW and SMLI registers to the input of the ALU and cause the ALU to compare the two values If 65 214 1,570,344 214 215 1,570,344 215 the iso-entropicgram width in register SMHW is less than or equal to the sum value contained in register SMLI, SB 2-15 is entered, where the isoentropicgram width value contained in register SMHW is subtracted from the line value contained in register SMLI so as to form the line value modulo of the iso-entroplcgram width.
To this end, the ALU forms a false signal at the G output and the inventer 1930 5 forms a true signal at the G output The true condition of logic Pl I G causes the P 12 flip flop to be set to a 1 state and the P 11 flip flop to be reset to a O state at the following CLK pulse, causing SB 2-15 to be entered.
During SB 2-15, the true signal at the PI 1 output causes the D 55 and D 56 selection circuits to couple the SMLI and SMHW registers to the input of the ALU 10 and the ALU subtracts the two values, forming the difference at the OP output.
The true signal at the P 12 output causes the D 54 selection circuit to couple the OP output to the input of the SMLI register, and the true condition of logic P 12 CLK causes the difference value to be stored into register SMLI Thus, register SMLI stores the number of the seed line 15 Following SB 2-15, the true signal at the P 12 output causes the P 13 flip flop to be set to a 1 state and the P 12 flip flop is reset to a 0 state Note that should the register SMHW have been the larger during SB 7-14, a true signal would be formed at the G output of the ALU and the logic Pl l G would be true, thereby causing P 13 to be set directly following the true condition of flip flop PI 1 This would be 20 equivalent to moving directly from SB 2-14 to SB 2-16.
During SB 2-16, a true signal is formed at the P 13 output and the number of occurrence values in the seed line now stored in register ENOC of the ENCODE MODULE is transferred to the NOC register of the SEED 2 MODULE and the length of the seed line in words contained in register MLN 3 is tranferred to the 25 SLN register To this end, the true signal at the P 13 output causes the logic P 13 CLK to be true, and the values from registers ENOC and MLN 3 are stored into registers NOC and SML, respectively The CNG flip flop is included here as an indicator to be set by the CHANGE 2 MODULE so that the proper signals are gated and clocked to the DECODE 1, II and ENCODE MODULES The SMB flip 30 flop has been included so that during the first two reads from the DECODE I MODULE the MLNI register is inhibited from clocking This is so since these two values will be re-read when RM 2 or RM 3 is initialized.
D Example of Operation Consider now the example of operation depicted along the right side of the iso 35 entropiegram depicted in Table 51 Assume that the EO vector depicted at line 0 ( 0, 2, 3 and 5) has been stored in MEMORY MODULE area I as described above with respect to the other modules Also assume it is desired to locate the seed line An iso-entropicgram width value of 8 is stored into the HW of the IPRF.
The initial true signal at the SM 2 GO output of the DPM INTERFACE 40 MODULE causes the SEED 2 MODULE to enter SB 2-1 where the DECODE I, ENCODE, and DELTA 2 MODULES are initialized and the value 0 is stored into the SLINE and T 3 registers and the SMB flip flop is set to a I state.
The system enable signals are formed at the A 251 and the system clock is formed at the A 252 outputs causing the iso-entropicgram width value to be 45 transferred from HW of the IPRF into the following modules: DECODE I, ENCODE, and DELTA 2 MODULE The other IPRF values are as described above.
SB 2-2 is then entered where the DECODE I MODULE is called, causing the largest occurrence value 5 to be stored in registers SN and TO of the SEED 2 50 MODULE The largest occurrence value stored in DO 1 is subtracted from the isoentropicgram width value of 8 contained in register SMHW and the difference value of 3 is stored into register T 1.
SB 2-3 is entered where the DECODE I MODULE is called for the second time, causing the next to the largest occurrence value of 3 to be provided by the 55 DECODE I MODULE Also during SB 2-3, the next to largest occurrence value of 3 in register DO (DECODE I MODULE) is subtracted from the largest occurrence value 5 in register TO and the difference value of 2 is stored into register TO.
Since the end of file has not been reached, the EO Fl flip flop in the DECODE 60 I MODULE is in a 0 state and SB 2-4 is entered after SB 2-3.
The difference value of 3 contained in register Ti is larger than the difference value of 2 contained in register TO and accordingly SB 2-6 is entered where the 0 216 1,570,344 216 in register T 3 is added to the larger difference value of 3 contained in register TI, and the resultant value of 3 is stored back into register T 3.
SB 2-7 is then entered where the RIL register of the REVOLVE 3 MODULE is loaded with the value 3 contained in register T 3 and the REVOLVE 3 MODULE is called During SB 2-7 the iso-entropicgram width value of 8 in SMHW is 5 compared with the difference value of 3 in T 3 and the latter is found to be smaller; hence SB 2-8 is entered.
During SB 2-8 the REVOLVE 3 MODULE is called, using as the same inputs those inputs described as examples with respect to the REVOLVE 3 MODULE.
The REVOLVE 3 MODULE then determines the largest occurrence value of line 3 10 of the iso-entropicgram (see Table 51) The largest value is the value 7 and is stored in register NI The REVOLVE 3 MODULE then determines the next largest occurrence value of line 3, namely, a 5 and this value is stored into register N 2 of the REVOLVE 3 MODULE Subsequently, SB 2-9 is entered where the largest occurrence value of the seed line (initially the given line), now stored in register 15 SN, is compared with the largest occurrence value of the new line, now stored in register NI of the REVOLVE 3 MODULE Registers SN and NI now contain the values 7 and 5, respectively, and since the value 5 in register SN is less, SB 2-11 is entered where the value for register Ti is computed.
During SB 2-1 1, the largest occurrence value 7 for the new line, in register 20 N l, is subtracted from the iso-entropicgram width value 8 stored in register SMHW and the difference, 1, is stored back into register Tl Additionally, the difference between the largest occurrence value 7, in register Nl, and the next largest occurrence value 5, in register N 2, is determined and the difference, 2, is stored into register TO and subsequently SB 2-4 is reentered 25 During SB 2-4 it is found that the value of 1 in register Ti is less than the value 2 in register TO Accordingly, SB 2-5 is entered where the larger value 2 in register TO is stored into register T 1.
SB 2-6 is entered where the current seed line value of 3, contained in register T 3, is added to the new largest difference value of 2, contained in register Ti, and 30the sum, 5, is stored into register T 3 Thus register T 3 now contains the number of the next line of the iso-entropicgram to be formed by the REVOLVE 3 MODULE, namely, line 5 of the iso-entropicgram depicted in Table 51.
During SB 2-7, the iso-entropicgram width value of 8 contained in register SMHW is found to be larger than the new line number value of 5 contained in 35 register T 3 and accordingly SB 2-8 is entered.
During SB 2-8, the next line number value cf 5 is stored into register RIL of the REVOLVE 3 MODULE and the REVOLVE 3 MODULE is called From the foregoing discussion it will be seen that the REVOLVE 3 MODULE will return values of 2, in register Nl, and 1, in register N 2, as the largest and next largest 40 occurrence values for line number 5.
During SB 2-9, the register SN contains the value 5 which is the largest occurrence value of the given or input line The given line, up to this time, has been considered to be the seed line, since it is shorter than line 3, the only intermediate line generated up to this point During SB 2-9, the value 5 stored in register SN is 45 compared with the value 2, contained in register Nl, and the latter is found to be smaller Accordingly, SB 2-10 is entered where the smaller occurrence value of 2, contained in register NI, is transferred to register SN, and the line number for the newly assumed seed, namely, 5, is transferred from register T 3 to register SLINE.
Following SB 2-10, SB 2-11 is entered where the difference between the iso 50 entropicgram width value of 8 and the largest occurrence value of 2, contained in register Nl, is determined and the resultant value of 6 is stored into register Tl.
Additionally, the difference between the largest and next largest occurrence value in registers Nl and N 2 of the REVOLVE 3 MODULE is determined and stored into register TO Registers Nl and N 2 contain the values 2 and 1, respectively, and 55 accordingly the difference is 1, and register TO now contains a 1.
Following SB 2-1 1, SB 2-4 is reentered where the value of 6 in register Tl is found to be larger than the value of 1 contained in register TO Accordingly, SB 2-6 is entered where the difference value of 6 contained in register TI is added to the current line value of l 51 contained in register T 3, and the resultant sum of 1 1 60 is stored into register T 3.
SB 2-7 is now entered where the value in T 3 is found to be larger than the isoentropicgram width value of 8 in register SMHW Accordingly, SB 2-12 is entered.
During SB 2-12, the current line value of 5 contained in register SLINE is stored into register RIL of the REVOLVE 2 MODULE and the REVOLVE 2 65 MODULE is called, causing it to generate the entire line 5 of the isoentropicgram depicted in Table 51 and the line is stored by the ENCODE MODULE into MEMORY MODULE area 2.
SB 2-13 is then entered where the value of 0 in register SMLI is added to the line value of 5 in register SLINE and the resultant value of 5 is stored into the 5 register SMLI.
During SB 2-14, the current seed line value of 5 stored in register SMLI is found to be smaller than the iso-entropicgram width value 8 in SMHW and accordingly SB 2-16 is entered During SB 2-16, the number of occurrence values in the seed line stored in MEMORY MODULE area 2 is transferred from register 10 ENOC of the ENCODE MODULE to NOC of the SEED 2 MODULE and the length of seed line in words, stored in register MLN 3, is transferred to register SLN of the SEED 2 MODULE The operation of the SEED 2 MODULE exits at this point.
Thus, upon exit, the SEED 2 MODULE has generated line 5 of the iso 15 entropicgram (see Table 51) and the line has been stored in MEMORY MODULE area 2 Register SMLI contains the seed line value of 5, and register NOC of the SEED 2 MODULE contains the word length value of 2.
XXVI OUTPUT 2 MODULE A General Description 20
The OUTPUT 2 MODULE has two functions The first is that is enables the original input line of an iso-entropicgram to be ontained from a given line representing any of the other lines of the same iso-entropicgram To this end, the OUTPUT 2 MODULE is initialized and, in turn, initializes the DECODE I and II MODULES, the ENCODE MODULE and the REVOLVE 2 MODULE The 25 number of lines that the given line must revolve to obtain the input line of the same iso-entropicgram is determined and sent to the REVOLVE 2 MODULE causing it to generate the input line directly.
The second function of the OUTPUT 2 MODULE comprises an alternative arrangement for determining whether an actual occurrence value exists in an input 30 line of an iso-entropicgram, given one of the other lines of the isoentropicgram, also disclosed herein This alternative embodiment is employed in the alternate DPM system of Fig 61 and involves the OUTPUT 2 MODULE This function was performed in the prior described embodiment of the invention in connection with the OUTPUT MODULE and is referred to herein as the DEL function 35 Briefly, this alternative arrangement can be understood by making reference to Table 9-C and 9-F, and considering the principles involving the use of binary l’s and O ‘s In this alternative embodiment a principle involving the inverted delta from Table 6 which is depicted in Table 9-C is also used The given line, which is generally the seed line, of the iso-entropicgram, together with information from the 40 inverted delta from Table 6, depicted in Table 9-C, is used to determine whether an actual occurrence value is present at the input line of the same isoentropicgram Initially the desired column (in the case of binary notation) or actual occurrence value (in the case of absolute coded notation) is given The number of lines of displacement between the given line and the input line of the iso-entropic 45 gram is determined The number of lines of displacement is of course the number of lines by which the given line must be revolved before the input line is obtained.
This difference value is then used as an index into the inverted delta depicted in Table 6.
Specifically, the line (see Table 9-C) corresponding to the difference value is so obtained from the inverted delta and the right hand side is aligned over the column (in the case of binary notation) or the actual occurrence value (in the case of actual occurrence values) whose presence is to be detained The overlaid l’s and O ‘s (in the case of binary notation) or the presence of actual occurrence values (in the case of absolute notation) are AN Ded together, producing for each position a true 55 condition if there is an actual occurrence value present in both the given line and the selected line of the delta If there is an odd number of true conditions, i e, an odd parity, then the corresponding column of the input line (in the case of binary notation) or the corresponding actual occurrence value, is present at the input line of the iso-entropicgram If the number of true conditions is even, i e, the parity is 60 even, then a 0 (in the cae of binary notation) is present, or the actual occurence value is absent (in the case of actual notation) at the input line of the isoentropricgram.
217 1,570,344 217 A better understanding of the foregoing principles of operation can be had with reference to the examples of Table 9-F.
Initially, the given (usually the seed of any event occurrence vector) line is stored in hybrid coded form in MEMORY MODULE area 1 Additionally, the MINI COMPUTOR stores the actual occurrence values to be checked (i e, a 5 reference line) in MEMORY MODULE area 2 Additionally, the MINI COMPUTER stores in the IPRF the iso-entropicgram width (HW), the line # of the seed line, and the lengths of the seed line and the reference line (i e, the number of physical words that comprise the seed) The OUTPUT 2 MODULE determines the number of lines of displacement between the given line and the 10 input line of the iso-entropicgram, namely, the number of lines which must be revolved before the input line of the iso-entropicgram is obtained The number of lines so determined is used as an index into the inverted delta depicted in Table 9-C Specifically, the line of the inverted delta (depicted in Table 9-C) corresponding to the number of lines so determined, is obtained through the 15 DELTA 2 MODULE In this connection, the line of the inverted delta is aligned with its right hand side in the column (or occurrence value) of interest In order to effect the shift, the OUTPUT 2 MODULE determines the difference between the occurrence value of interest and the iso-entropicgram width and this difference is then sent to the DELTA 2 MODULE The representations of the presence and 20 absence of occurrence values from the given and shifted delta lines, as represented by the respective occurrence values, are AN Ded together to form a true representation if an occurrence value is true in both lines and a 0 if an occurrence value is absent from either one or both lines An odd number of true conditions indicates the presence of the occurrence value at the input line of the iso-entropic 25 gram whereas an even number of true conditions indicates the absence of an occurrence value at the input line.
Since the EO vectors have been arranged in a monotonically decreasing sequence and the DELTA 2 MODULE generates its output in a monotonically increasing sequence, an intermediate storage step is necessary This procedure was 30 described in discussing the REVOLVE 2 MODULE above The OUTPUT 2 MODULE computes from the current reference line value the minimum possible occurrence value that can be affected by the inverted “DEL” pattern This minimum value is passed to the DELTA 2 MODULE as the starting column of its sequence 35 A sequence of monotonically decreasing EO values are read from the seed line in DPM MEMORY MODULE area I and placed in temporary storage (i e, AUXILIARY MEMORY II) Next the DELTA 2 MODULE starts to generate a monotonically increasing representing a bit pattern in the delta corresponding to the number of lines to be revolved; the starting value in this sequence being the 40 minimum valued column computed above These shifted DELTA 2 values are AN Ded to the seed line portion in temporary storage at AUXILIARY MEMORY II MODULE The parity of the number of true output AND’S (i e, the same value occurs in both the seed line segment and in the delta line pattern) is monitored by toggle flip flop T If an odd number of true valued AND’s are encountered, the 45 reference line value read by the DECODE 2 MODULE and stored in RI is written directly to MEMORY MODULE area 3 If an even number of true valued ANS’s are encountered, the writing to the MEMORY MODULE area 3 is omitted Seed line values in the seed line segment in temporary storage at AUXILIARY MEMORY II which are greater than the highest shifted value from the DELTA 2 50 MODULE need no longer be considered and accordingly the bottom memory pointer (WB) for AUXILIARY MEMORY II is set to reflect this situation It should be noted here that the above described process whereby the seed line values larger than the largest generated shifted DELTA 2 MODULE value are ignored causes the current seed line segments to process through the AUXILIARY 55 MEMORY II module area 1 When the end of memory is reached, wrap around occurs.
The above stated process repeats for each value to be checked in the reference line After all reference line values have been processed, exit is taken from the module with the values in MEMORY MODULE area 3 representing those values 60 in the reference line which also appeared on the input line of the same iso-entropicgram that contains the seed line It is important to note that the “DEL” function as described above allows the user of this system to make data dependent decisions without regenerating the entire input line of the iso-entropicgram that contains the seed 65 218 1,570,344 218 B Components A list of hardware components used in designing the OUTPUT 2 MODULE is given in Table 57 of this disclosure.
C Detailed Description
Refer now to the schematic and block diagram of Fig 76 and the flow diagram 5 of Figs 74 and 75 and consider the general structure of the OUTPUT 2 MODULE.
The following description will make reference to the general operation as depicted in the flow diagram of Figs 74 and 75 Initially, the MINI COMPUTER stores the following into the IPRF of the DPM INTERFACE MODULE:
1 Iso-entropicgram width into HW 10 2 The line # of the seed into the line # 3 The length of the seed line is stored into LNI.
Additionally, if the DEL function is to be performed by the OUTPUT 2 MODULE, the length of the reference line is stored in IPRF register LN 2, the DELOP flip flop in the status register of the DPM INTERFACE MODULE and 15 hence the DELOP flip flop in the OUTPUT 2 MODULE, are set to a I state, whereas these flip flops are initially set to a 0 state if the regular output operation is to be performed.
In addition the MINI COMPUTER stores the following information into the indicated areas of the MEMORY MODULE: 20 Area I-given (seed) event occurrence (EO) vector Area 2-actual occurrence value to be checked (reference line) (only if the DEL operation is to be performed and flip flop DELOP is 1) Area 3-reserved for the regenerated input line or the actual occurrence values found to be present at the input line 25 The MINI COMPUTER calls the OUTPUT 2 MODULE by forming a true signal at the OM 2 GO output in the case of a regular output, and a true signal at the outputs OM 2 GO causing OB I of the flow to be entered During OB 1 of the flow, the OUTPUT 2 MODULE is initialized thereby storing the iso-entropicgram width (HW) into register OHW and the line number of the given line (line #) is stored into 30 register OLINE of the OUTPUT 2 MODULE Additionally, the OUTPUT 2 MODULE forms a true signal at the A 201 output and the A 202 output, initializing the operation of the DECODE I and II ENCODE, and REVOLVE 2 MODULES.
OB 2 of the flow is then entered where the OUTPUT 2 MODULE computes the number of lines required to revolve the given line to the original input line of 35 the corresponding iso-entropicgram To this end, the line # of the given line contained in register OLINE is substracted from the width value of the isoentropicgram stored in register OHW and the result is stored into register N of the OUTPUT 2 MODULE.
OB 2 is then entered where the state of the DELOP flip flop in the OUTPUT 2 40 MODULE is checked If the DELOP flip flop is in a 0 state, indicating that a regular output operation is to be performed, OB 4 is then entered During OB 4 the number of lines to be revolved is fed from the N register of the OUTPUT 2 MODULE to register RIL of the REVOLVE 2 MODULE The operation of the REVOLVE 2 MODULE is then called, causing the given line of the isoentropic 45 gram stored in MEMORY MODULE area 1 to be revolved back to the input line of its iso-entropicgram The final input line so generated is stored into MEMORY MODULE area 3.
Return to OB 3 or the flow and assume that the DELOP flip flop is in a I state, so indicating that the DEL operation is to be performed OB 5 is entered following 50 OB 3 During OB 5, DECODE I MODULE enable flip flop EFF is set to a I state in the OUTPUT 2 MODULE The number of lines to be revolved value stored in register N is sent to register DELRO of the DELTA 2 MODULE thereby indicating the desired line of the inverted delta which is to be shifted and provided bv the DETA 2 MODULE Additionally, the WP and WB pointer register in the 55 OUTPUT 2 MODULE are reset to 0.
QB 6 of the flow is entered following OB 5 During OB 6 the operation of the DECODE II MODULE is called causing it to provide one of the occurrence values to be checked from the EO vector stored in MEMORY MODULE area 2 (i e a reference line value) It will be recalled the DECODE II MODULE provides the 60 occurrence values from the EO vector in decreasing value order If the DECODE II MODULE has already provided the last or smallest occurrence value from the 219 I 1,570,344 219 EO vector in MEMORY MODULE area 2, the EOF 2 flip-flop will be in a 1 state and the OUTPUT 2 MODULE exits, following OB 6 However, if the DECODE II MODULE has not provided the last occurrence value, OB 7 is entered following OB 6.
OB 7 stores and saves the occurrence value to be checked in the input line into 5 register RI Additionally the minimun occurrence value that can be effected by the shifted line of the delta is computed by subtracting the value in N from the value just read and the result is stored in register R 2 of the OUTPUT 2 MODULE The minimum value stored in register R 2 is then transferred to register DELV of the DELTA 2 MODULE, causing the DELTA 2 MODULE to effect the corres 10 ponding offset or shift in the line of the inverted delta specified by the value now stored in register DELRO of the DELTA 2 MODULE.
OB 8 of the flow is now entered If during OB 8 the DECODE I MODULE enable flip-flop EFF is in a 1 state, OB 10 of the flow is entered where the operation of the DECODE I MODULE is called, causing it to provide one of the occurrence 15 values from the EO vector stored in MEMORY MODULE area 1 Again it will be noted that the DECODE I MODULE provides the occurrence value from the EO vector stored in MEMORY MODULE area 1 in decreasingly value order starting with the largest value If the DECODE I MODULE has not reached the end of the EO vector in MEMORY MODULE area 1, then OBII is entered where the 20 occurrence value from the DECODE I MODULE is stored into register RII of the OUTPUT 2 MODULE and if the EFF flip-flop is in a 1 state, as is the case when OB 10 has been entered, causing a value to be provided by the DECODE I MODULE, then the value stored in register RII is stored into the write area of the AM-II MEMORY at the location specified by the WP pointer, and the address 25 contained in the WP pointer is counted up by 1 Note that the values are read from the EO vector for the given line in decreasing value order and are stored in that order in the AM-II MEMORY.
Following O Bll, OB 12 is entered During OB 12 the OUTPUT 2 MODULE checks to determine if sufficient values have been read from the given line to 30 determine if the actual occurrence value stored in the register RI is present The decision cannot be made if the minimum value stored in register R 2 is less than the occurrence value of the WO vector for the given line stored in register R 11 If this condition exists and hence the decision cannot be made, then OB 10 and OB 11 are reentered where the process depicted is repeated, causing another value from the 35 EO vector of the given line to be read in and stored into register RI This operation is repeated until the occurrence value stored in register RII is less than or equal to the minimum value in register R 2 When the foregoing condition exists during OB 12, the decision can be made and either OB 13 or OB 14 is entered depending on the relative values of the content of registers R 2 and RI If the minimum value in 40 register R 2 is equal to the occurrence value of the EO vector from the given line in register RII, the OB 14 is entered where the EFF flip-flop is set to a 1 state indicating that the DECODE I MODULE is to be called on the nest cycle, causing the next lower occurrence value from the given line to be provided If, on the other hand, the minimum value in register R 2 is greater than the occurrence value from 45 the given line stored in register RII, OB 13 is entered where the EFF flip-flop is set to a 0 state, indicating that the DECODE I MODULE is not to be called.
Returning to OB 10, it will be noted that when the DECODE I MODULE has reached the end of file and the EOFI flip-flop is hence in a 1 state, the operation of OB 11 and OB 12 is shunted and OB 13 is directly entered for all future entries into so OB 10.
Following OB 13 or OB 14, OB 15-OB 24 is entered OB 15 through OB 24 performs the operation of AN Ding an parity checking the indication of occurrence values from the given line and from the shifted line received from the DELTA 2 MODULE The AND operation performed an occurrence value at a time while 55 keeping track of the parity in the flip-flop T The DELTA 2 MODULE outputs the shifted delta line values from lowest to highest value, i e, in inverse order to that in which the occurrence values are provided by the DECODE I and II MODULES.
Advantage is taken of this order of reading since whe OB 14 through OB 24 is completed, the AM-II MEMORY pointers WT, WR are in such a state that the 60 higher values of the given line which are no longer needed are dropped The memory address register WP is such as to cause the wraparound to occur when the highest memory location is reached in the AM-II MEMORY.
Referring specifically to OB 15, here the pointer to the highest value so far recorded in the AM-II MEMORY, as indicated by the WP pointer, is stored into 65 220 1,570,344 220 register WT and, saved Additionally, the parity flip flop T is set to 0 Following O Bi S, OB 16 of the flow is entered where, if the end of the shifted line of the delta has not been reached, i e, DELEND is in a 0 state, then the DELTA 2 MODULE is called, causing it to provide the next shifted occurrence value in the delta line being generated OB 17 is entered where the next shifted occurrence value is 5 transferred from register DELO of the DELTA 2 MODULE to register DO of the OUTPUT 2 MODULE OB 18 is next entered where the WT pointer is decreased by 1 so that it identifies the next address in the AM-II MEMORY for reading.
OB 19 is subsequently entered where the address in the current pointer WT is compared to the last allowable address which is stored in register WB To be 10 explained in more detail in connection with OB 27, the content of pointer WT plus I is stored into pointer WB in order to denote that seed line values at addresses lower than WB are to be ignored Thus during OB 19, if the content of pointer WT is greater than or equal to the minimum value in pointer WB, OB 20 is entered where a shifted occurrence value is read from the AM-I 1 MEMORY and stored into 15 register RII of the OUTPUT 2 MODULE If the content of register WT is smaller, then O 82 is entered following OB 19, causing a maximum value 255 to be stored into register RI Maximum value 255 is the largest allowable postive number that can be stored into register RII in the configuration used here by way of example.
Following OB 21 or OB 20, OB 22 is entered where the actual AND and parity 20 check operation is performed To this end, if during OB 22 the value in register RII is smaller than the shifted delta value in register DO, the operation returns to OB 18 and another seed line segment value is read from the AM-II MEMORY If, during O 822, the content of register RII is found to be greater than the shifted delta value in register DO, then OB 24 is entered where the next higher shifted delta 25 line value is called from the DELTA 2 MODULE, then OB 22 is re-entered following OB 24, causing the comparison during OB 22 to be repeated When, during OB 22, the content of registers RII and DO are found to be equal, OB 23 is entered where the flip flop T is complemented, indicating equality has been detected, thereby indicating that the presence of the same valued occurrence 30 values has been detected in both the shifted delta line and from the given line In other words, the AND of the presence of an occurrence value from both the shifted delta line and from the given line, is true and, thus, the parity is toggled.
Following OB 23, OB 16 is reentered where the next shifted delta value is read from the DELTA 2 MODULE and subseqently during OB 20, the next seed line 35 segment value is read from the AM-II MEMORY.
When, during O 824, the last shifted line value has been provided by the DELTA 2 MODULE and the DELEND flip flop is in a 1 state, OB 25 is next entered During OB 25 a decision is made whether the occurrence value under test is present and thus is to be outputted to MEMORY MODULE area 3 To this end, 40 if the T flip flop is in a 1 state, OB 26 is entered where the refrence line occurrence value under test, stored in register RI, is sent into MEMORY MODULE area 3 In addition the M 3 address register in the OUTPUT 2 MODULE is conted up by I so that it now contains the address of the next location in MEMORY MODULE area 3 for writing If the T flip flop is in a 0 state, indicating that the number of true 45 conditions detected by the AND an parity check operation is even, OB 27 is entered where the occurrence value under test in register RI is ignored, and OB 27 is entered directly During OB 27, the pointer WT is counted up by 1 and the result stored in pointer WB causing all seed line segment values in AM-I 1 that addresses so lower than WB to be ignored on future cycles Following O 827, OB 6 is reentered 50 and the cycle of operation is repeated Finally, when the last occurrence value to be checked is provided from the EO vector in MEMORY MODULE area 3, the EOF 2 flip flop in the DECODE II MODULE is set to a 1 state and the machine exist following OB 6.
Therefore, it should now be apparent that when the DEL function is complete, 55 upon exit, that MEMORY MODULE area 3 will contain those and only those actual occurrence values from the reference line EO vector stored in MEMORY MODULE area 2 which exist at the input line of the iso-entropicgram corresponding to the given line represented by the EO vector stored in MEMORY MODULE area 1 60 With the foregoing general description of the OUTPUT 2 MODULE in more detail, again making reference to the flow chart of Figs 74 and 75 and the schematic and block diagram of Fig 76.
The operation of the OUTPUT 2 MODULE is called by the MINI COMPUTER by applying a true signal at the OMGO output to cause a regular 65 221 1,570,344 221 output operation and by applying the true signal at the OMGO output together with a true signal at the DELOP output of the DPM INTERFACE MODULE to cause the DEL operation to be performed.
The true signal at the OMGO output causes the generalized clock control 700 to start forming clock pulses at the CLK output Initially, all of the flips Pl through 5 Pl 1 are in a 0 state (having been set there by a control signal at the MINIT output of the DPM INTERFACE MODULE) The true signal at the Pl output and the true condition of logic P 1 CLK causes true signals to be formed at the A 201 and the A 202 output, the first signal causing a system enable signal to be sent to the ENCODE, DECODE I and II, and REVOLVE 2 MODULES and the the SM flip 10 flop in the AM-I 1 MEMORY and the latter signal providing a system clock to the same parts of the system.
The true condition of logic PI CIK causes the OHW register to load the isoentropicgram width from register HW in the IPRF and causes the OLINE register to store the line number of the given line from the line # from the IPRF register is The true signal at the Pl output of the Pl flip flop causes the P 2 flip flop to be set to a I state at the following CLK pulse.
OB 2 is now entered The iso-entropicgram width in register OHW and the given line number in register OLINE are subtracted and the result is stored into the N register To this end the true signal formed at the P 2 output causes the D 52 20 and D 53 selection circuits to couple the OHW and OLINE registers to the input of the ALU and causes the ALU to subtract the content of register OLINE from that of register OHW The difference value formed by the ALU is applied to the input of the N register and the true condition of logic P 2 C causes the N register to store the difference value Thus, the N register now contains the number of lines to 25 revolve the seed in order to obtain the original input The true condition at the P 2 output also causes the EFF flip flop to be set at a 1 state Assuming that the regular output is to take place, the DELOP flip flop is now in a 0 state Accordingly, OB 4 is entered During OB 4 the true condition of logic P 2 DELOP and the true condition of logic P 2 DELOP CLK causes the A 203 and A 204 outputs of the OUTPUT 2 30 MODULE to receive true signals, causing the RIL register in the REVOLVE 2 MODULE to receive the number of lines to be revolved value from register N in the OUTPUT 2 MODULE. If during OB 3 the DELOP flip flop is in ax 1 state, indicating that the
DEL function is to be performed, OB 5 is entered rather than OB 4 During OB 5, the true 35 signal at the P 2 output causes the WP, and WT pointers to be reset to 0.
Logic P 2 DELOP and the logic P 2 DELOP CLK now become true causing true signals at the A 205, A 206, and A 207 outputs, causing the DELTA 2 MODULE to receive the number lines to be revolved from the N register of the OUTPUT 2 MODULE and causing the value to be stored into register DELRO 40 OB 6 of the flow is now entered The true signal at the P 2 SELOP CLK output causes a true signal at the A 207 output which in turn calls the operation of the DECODE II MODULE Additionally, in the clock suspension logic 2013 the logic A 207 D 2 MEND becomes true, causing a true signal at the CS input of the generalized clock control 700 thereby causing the generalized clock control to 45 terminate pulses at the CLK and CLK outputs Thus, the OUTPUT 2 MODULE operation is momentarily suspended while the DECODE II MODULE provides an occurrence value from the EO vector designating the occurrence values to be checked, which EO vector is stored in MEMORY MODULE area 2.
After the DECODE II MODULE has completed its operation and provided 50 an occurrence value, the true signal at the D 2 MEND output thereof becomes false, causing the CS input of the clock suspension logic 2013 to become false and the generalized clock control 700 starts providing CLK and CLK pulses.
Assuming that the DECODE II MODULE has not reached the end of the reference line EO vector field in MEMORY MODULE area 2, the EOF 2 flip flop 55 is now in a 0 state, and the logic P 2 DELOP EOF 2 is now true and the following CLK pule causes the P 3 flip flop to be set to a 1 state and the P 2 flip flop is reset to a 0 state, causing OB 7 of the flow to be entered.
During OB 7 of the flow, a true signal is formed at the P 3 output thereby causing register RI to store the reference line occurrence value to be checked from 60 register D 02 of the DECODE II MODULE Additionally, the true signal at the P 3 output causes the D 52 and D 53 selection circuits to couple the RI and N register outputs to the input of the ALU and causes a true signal at the S input of the ALU which in turn causes the ALU to subtract the two values, forming the difference at 222 1,570,344 222 the OP output Additionally, the true signal at P 3 causes the value in the WT register to be clocked into the WB register.
The logic P 3 CLK becomes true and the difference is stored into register R 2.
The true condition of the output P 3 and of the logic P 3 CLK causes true signals at the A 208 and A 209 outputs of the OUTPUT 2 MODULE, thereby applying an 5 enable signal to the DELV register of the DELTA 2 MODULE which in turn causes the difference at the OP output to be stored into the DELV register Thus, the DELTA 2 MODULE now contains the difference value indicating the number of lines to be revolved in DELRO and the beginning occurrence value that will begin the shifted output values in DELV 10 OB 8 is now entered where the state of flip flop EFF is checked Assuming that flip flop EFF is now in a 1 state, OB 10 is entered During OB 10 the true condition of logic P 3 EFF CLK causes a true signal at the A 2010 output of the OUTPUT 2 MODULE, which in turn calls the operation of the DECODE I MODULE.
Additionally, the true condition of logic A 2010 DIMEND causes a true signal at 15 the CS input of the generalized clock control 700 which in turn stops providing CLK and CLK pulses, suspending the operation of the OUTPUT 2 MODULE.
The DECODE I MODULE then provides from MEMORY MODULE area 1 and occurrence value from the seed EO vector of the given line The occurrence value is provided at the D Ol register of the DECODE I MODULE When this 20 occurs the true signal at the DIMEND output of the DECODE I MODULE becomes false, causing a false signal at the CS input of the generalized clock control which in turn commences the CLK and CLK pulses The following CLK pulse causes the P 4 flip flop to be set to a 1 state and the P 3 flip flop is reset to a 0 state there by causing OB 11 to be entered 25 The true signal at the P 4 output causes the DO 1 register from the DECODE I MODULE to be coupled through the DS I selection circuit to the input of register RI Additionally, the true signal at P 4 causes the value in counter WB to be clocked up one The true condition of logic P 4 CLK causes the register RII to store the occurrence value from the EO vector of the given line The true condition of 30 logic P 4 EFF causes the A 0211 output of the OUTPUT 2 MODULE to be true which in turn causes the AM-TI MEMORY to write the occurrence value from the given line stored in register RII into the locatoin of the AM-II MEMORY specified by the WP pointer Additionally, the true condition of logic P 4 EFF CLK causes the WP pointer to be counted up so that it now contains the address of the 35 next location into which a write is to take place in the AM-II MEMORY.
The true signal at the P 4 output of the P 4 flip flop causes the P 5 flip flop to be set to a 1 state and the P 4 flip flop is reset to a 0 state at the following CLK pulse, thereby causing OB 12 to be entered.
During OB 12, the true signal at the P 5 outpout causes the D 52 and D 53, 40 selection circuits to couple the registers R 2 and RII to the input of the ALU The true signal at the P 5 output causes the ALU to compare the two values and provide outputs indicating the result of the comparison It will be recalled that register R 2 contains the difference value indicating the minimum occurrence value that can be effected by shifted delta values Thus, if the value in register R 2 is equal to the 45 occurrence value from the given line in register Rll, a false signal is formed at the G output and hence a true signal is formed at the G output of the inverter 2032 The true signal at the G output causes the logic P 5 G to become true, thereby setting the EEF flip flop to a 1 state, as indicated during OB 14 of the flow If, during OB 12,.
the comparison indicates that the lower boundary value in register R 2 is greater 50 than the occurrence value from the given line stored in register RH, then the ALU forms a true signal at the G output causing the logic P 5 G to become true Thus, during OB 13 the EFF flip flop is thereby set to a 0 state.
Note that OB 15 is entered following either OB 13 or O 814 To this end, whenever the minimum value contained in register R 2 is not less than (i e, equal to 55 or greater than) the occurrence value in register RII, a false signal is formed at the L output of the ALU and a true signal is formed at the L output of the inverter 2034 Thus the logic P 5 L is true, causing the P 6 flip flop to be set to a 1 state at the following CLK pulse, causing OB 15 to be entered Additionally, if during OB 10 of the flow, it is found that the EOFI flip flop is in a 1 state, indicating that the 60 DECODE I MODULE has reached the end of the given line, the logic P 5 L EOF 1 will become true, also causing the P 6 flip flop to be set to a 1 state at the CLK pulse.
During OB 15, a true signal is formed at the P 6 output causing the WT pointer to load the content of the WP pointer Thus, both WT and WP now contain the address of or point to the next location in the AM-I 1 MEMORY to be written 65 223 223 I 1,570 344 The true signal at the P 6 output also resets the T flip flop to 0.
OB 16 is now entered During OB 16 the logic P 6 CLK is true, causing a true signal at the A 2012 output causes the logic A 2012 DMEND to become true, enabling the clock suspension logic 2013 to apply a true signal at the CS input of the generalized clock control 700, thereby suspending pulses at the CLK and CLK 5 outputs The DELTA 2 MODULE then provides the first shifted occurrence value.
After the DELTA 2 MODULE has formed its shifted delta value in its register DELO, a false signal is formed at the DMEND output thereof, causing a false input to the CS input of the generalized clock control 700, causing pulses to again be formed at the CLK and =K outputs 10 Assuming that the DELTA 2 MODULE has not reached the last shifted occurrence value to be formed, the flip flop DELEND thereof is now in a 0 state.
Therefore the logic P 6 DELEND is not true and at the following CLK pulse, flip flop P 7 is set to a I state and flip flop P 6 is reset to a 0 state, causing OB 17 to be entered 15 During OB 17 the true signal at the P 7 output causes the DO 1 register to store the shifted occurrence value from register DELO of the DELTA 2 MODULE A true signal is now being formed at the P 7 output and at the following CLK pulse the P 8 flip flop is set to a 1 state and the P 7 flip flop is reset to a 0 state, causing OB 18 of the flow to be entered 20 During OB 18 a true signal is formed at the P 8 output causing the WT (pointer) to count down the address therein th the next lower address OB 19 is now entered where the content of the WB and WT pointers are compared The WT pointer now contains the last address of the AM-II MEMORY in which reading has occurred.
The WB pointer contains the address of the location beyond which seed line values 25 are to be ignored.
For comparison, the true signal at the P 8 output causes the D 52 and D 53 selection circuits to couple the outputs of registers WB and WT to the input of the ALU and the true signal at the P 8 causes the ALU to compare the values stored therein If the content of the AM-II MEMORY area one pointer WT is now 30 greater than or equal to the content of register WB The content of register WB is not the larger value and accordingly the ALU forms a true signal at the G output.
Under these conditions, OB 20 is entered where the next value in the AMII MEMORY specified by the WT pointer is read and stored in the RH register To this end, the true condition of logic P 8 causes a true signal at the A 2013 output 35 which in turn causes the AM-IT MEMORY to read out the content of the read memory area specified by the address in the read pointer WT The true condition of logic P 8 G causes the D Sl selection circuit to couple the seed line segment value read from the AM-II MEMORY to the input of register RI The true condition of logic P 8 CLK causes the value to be stored into register RII At the following 40 CLK pulse the true signal at P 8 causes the P 9 flip flop to be set to a 1 state and the P 8 flip flop is reset to a 0 state, causing OB 22 to be entered.
Return now to OB 19 and consider the situation where the content of the WT read pointer is smaller than that of the WB pointer Under these conditions the content of the WB pointer is the larger and accordingly a true signal is formed at 45 the G output of the ALU The true signal at the G output causes OB 21 to be entered where the logic P 8 G is true, causing the maximum value 255, represented by the switches 2040 to be coupled through the DS I selection circuit to the input of register RH, and the logic P 8 CLK is now true, causing the maximum value 255 to be stored in the register RI As before, the P 9 flip flop is set to a true state and the 50 P 8 flip flop is subsequently set to a 0 state, causing OB 22 to be entered.
During OB 22, a true signal is formed at the P 9 output where the seed line segment value stored in register RII is compared with the shifted delta line value in register DO To this end the true signal at the P 9 output causes the D 52 and D 53 selection circuits to couple the output of Registers RII and DO to the input of the 55 ALU and causes the ALU to compare the two values If the seed line segment value in register RII is the smaller, a true signal is formed at the I output, causing the logic P 9.L to become true which in turn causes the P 8 flip flop to be set to a 1 state and the P 9 flip flop is reset to a 0 state at the following CLK pulse, thereby causing OB 18 of the flow to be reentered This pass through OB 18 thrugh OB 22 is repeated 60 until the seed line segment value read from the AM-II MEMORY and stored in register RH becomes equal to or less than the shifted delta line value in register DO.
If during OB 22 the seed line segment value in register RII is equal to that of the shifted delta line value in register DO, a true signal is formed at the E output of the ALU, causing the logic P 9 E CLK to become true, which triggers the T flip flop to 65 224 1,570,344 224 225 1,570,344 225 22 its complementary state The true condition of logic P 9 E DELEND causes the P 7 flip flop to be s&t to a 1 state at the following CLK pulse, and OB 16 of the flow is reentered where the DELTA 2 MODULE is again called, causing the next higher shifted delta line value to be read and stored into the DO register In this regard, it will be noted that the logic P 9 L CLK causes true signal at the A 2012 output calls 5 the operation of the DELTA 2 MODULE.
If during O B 22, the seed line segment value stored in register RII is found to be larger than the shifted delta line value in register DO, the logic P 9 L CLK causes a true signal at the A 2012 output which in turn calls the operation of the DELTA 2 MODULE As before, the clock suspension logic 2013 causes the CLK and MK 10 pulses to be suspended until the DELTA 2 MODULE completes its operation and provides the next higher shifted delta value to be stored in the DELO register When this occurs, the clock suspension logic 2013 causes the generalized clock control 700 to again apply CLK and CLK pulses The ALU also forms a true signal at the G output which causes the logic P 9 G DELEND to become true 15 and thereby set the Pl O flip flop to a 1 state at the following CLK pulse The true signal at the Pl O output causes the DOI register to load the next shifted delta value from register DELO of the DELTA 2 MODULE.
Note that if, during OB 24, the DELEND flip flop is in a 1 state, OB 25 is next entered However, if the DELEND flip flop is in a 0 state, OB 22 is next entered 20 Assume that OB 25 has been entered If the T flip flop is now in a 1 state, the logic (P 9 L + P 6) DELEND causes the Pl 1 to be set to a I state, thereby causing OB 26 to be entered The true condition of logic Pl l T causes a true signal at the A 2014 output of the OUTPUT 2 MODULE which in turn causes the MEMORY MODULE to write the reference line occurrence value to be checked, from 25 register RI, into area 3 at the location specified by the address in register M 3 in the OUTPUT 2 MODULE Additionally, the true condition of logic Pl 1 T MK causes the register M 3 to be counted up by 1 address so that it now contains the address of the next available location in area 3 Note that if the T flip flop is in a 0 state, that OB 27 is entered directly, bypassing OB 26 During OB 27 the true signal 30 occurs at the Pl 1 output.
The true condition of the logic P 11 EOF 2 causes the P 3 flip flop to be set to a 1 state and causes the Pl 1 flip flop to be reset to a 0 state at the following CLK pulse, thereby causing OB 6 to be entered In this connection, the true condition of the logic Pl I CLK causes a true condition at the A 207 output of the OUTPUT 2 35 MODULE which in turn calls the operation of the DECODE II MODULE, causing it during OB 6 to provide the next occurrence value to be checked, which value is subsequently stored in register RI during OB 7.
D Example of Operation (under OUTPUT 2 MODULE) Consider now the example of operation of the OUTPUT 2 MODULE 40 depicted in Table 58 The initial information stored in the IPRF is as follows:
Line # 5 lLine number of given linel HW 8 (iso-entropicgram width) LNI 12 (length of given line).
The initial condition in the status register of the DPM INTERFACE MODULE is 45 as follows:
DELOP = O The hybrid coded EO vectors stored in the MEMORY MODULE are as follows:
Area 1 2, 1, 0 (given line value in hybrid coded form) Area 2 n/a 50 Area 3 n/a Under these conditions the given line is actually a seed line and the OUTPUT 2 MODULE is now going to cause the WO vector to be rotated back to the input line of its iso-entropicgram.
To this end, the DELOP flip flop being in a 0 state in the DPM INTERFACE 55 MODULE, causes the DELOP flip flop in the OUTPUT 2 MODULE to be set to a I state OB I is now entered where the DECODE I and II, ENCODE, and REVOLVE 2 MODULES are initialized Additionally, the iso-entropicgram width 225 1,570,344 225 226 1,570,344 226 value and line number value in registers HW and LINE # are transferred from the DPM INTERFACE MODULE to registers OHW and OLINE of the OUTPUT 2 MODULE Additionally, the SWITCH MATRIX 2 for the AM-II MEMORY is initialized During OB 2, the line # 5 contained in register OLINE is subtracted from the iso-entropicgram width value 8 stored in register OHW and the 5 difference, 3, is stored into the N register During OB 3, the DELOP flip flop is in a 0 state and accordingly OB 4 is entered During OB 4 the difference value in register N specifies the number of lines by which the revolve is to be effected in order to generate the input line of the iso-entropic gram Accordingly, the difference value 3 in register N is transferred to register RIL of the OUTPUT 2 MODULE and the 10 operation of the REVOLVE 2 MODULE is called, causing the REVOLVE 2 MODULE to revolve the given line in MEMORY MODULE area I back to the input line of its iso-entropicgram and the result is stored back in MEMORY MODULE area 3 Following OB 4, the operation of the OUTPUT 2 MODULE is exited 15 Consider now an alternative example of operation for the OUTPUT 2 MODULE as depicted in Table 58 By way of example, assume that the IPRF contains-the following initial conditions:
LINE # 5 (line number of the given line) HW 8 (iso-entropicgram width) 20 LN 1 2 (physical length of the seed line in words) LN 2 2 (length of the request line specifying the occurrence values to be checked) In addition, the status register in the DPM INTERFACE MODULE contains the following condition: 25 DELOP I (indicating that the “DEL” operation is to be performed by the OUTPUT 2 MODULE) The MEMORY MODULE contains the following in nybrid coded form:
Area 1 2, 1, 0 (given or seed line) Area 2 6, 2 (request occurrence vector specifying the occurrence values to 30 be checked) Initially, the DELOP flip flop in the OUTPUT 2 MODULE is set to a I state corresponding to the state of the DELOP flip flop in the STATUS register of the DPM INTERFACE MODULE The operation of the OUTPUT 2 MODULE during OB I and OB 2 is identical to that described hereinabove with respect to the 35 first example.
The following is an example of the operation, using symbolic notation:
Alternative Output Module control sequence OB 1-OB 3, OB 5-OB 8, OB 10-OB 13, OB 15-OB 20, OB 22, OB 18, OB 19, OB 21, OB 22, OB 24, OB 22, OB 24, OB 22, OB 24, OB 22, OB 24, 40 OB 25, OB 27 OB 1 perform the initialization OB 2 N( 3) = OHW( 8) OLINE( 5) OB 3, OB 5 DELOP= 1 EFF= 1 DELRO = N = 3 45 WP, WT, WB= O OB 6 call DECODE II returns 6, EOF 2 = O OB 7 RI-D O 2 = 6 R 2 ( 3) = RI( 6) N( 3) DELV = R 2 = 3 50 OB 8, OB 10 EFF= 1 call DECODE I returns 2, EOF 1 = O OB 11 RII = R 1 O = 2 Write RII to AM-II M EM WP = WP + 1 1 OB 12, OB 13 R 2 ( 3)> RII( 2) EFF = 0 55 OB 15 WT=WT= 1 T= 0 OB 16, OB 17 call DELTA 2 returns DELO= 3 DO = DELO = 3 OB 18 WT=WT-I = O OB 19, OB 20 WB =ST= O OB 19, OB 20 WB = ST = O Read Rll = 2 from AM-II MEM at address WT O OB 22, OB 18, RII( 2) < DO( 3) 5 WT = WT 1 = 1 OB 19, OB 21 WB > WT RI = 255 OB 22, OB 24 RI 1 ( 255) > DO( 3) call Delta 2 returns DO = DELO = 4 PB 22, OB 24 RI > DO( 4) 10 call DELTA 2 returns DO = DELO = 5 OB 22, OB 24 RII > DO call DELTA 2 returns DELEND OB 25, OB 27 T= O WB=WT+I= O End of first cycle 15 Note nothing has been written to MEMORY MODULE area 3 indicating that column 6 line 0 has a 0 value.
Second cycle OB 6-OB 9, OB-1 1, OB 12, OB 10, OB 12, OB 2, OB 12, OBIO, OB 13, OB 15, OB 16, OB 17-OB 20, OB 22, OB 24, OB 22, OB 23, OB 18, OB 20, OB 22, OB 24, OB 22, OB 23, OB 18-OB 20, OB 22, OB 24,20 OB 22, OB 23, OB 18, OB 19, OB 21, OB 22, OB 24-OB 27, OB 6 OB 6 call Decode II returns DO 2 = 2, EOF 2 = O OB 7 RI-DO 2 = 2 R 2 = RI( 2) N( 3) =-1 DELV = R 2 =-1 (minus indicated left shift) 25 OB 8, OB 9 OB 11 EFF= O & EOFI = O RII = DOI 2 (no write takes place since EFF = 0) OB 12, OBI O R 2 (-1) < RII( 2) EFF= 1 Call Decode I returns SO 1 = 1, EOFI = O 30 RII = DO 1 = 1 write RII to AM-II MEM WP = WP + 1 = 2 OB 12, OBO 10 R 2 DO( 1) Call DELTA 2 returns DELO = O DO= DELO = O o 50 OB 22, OB 23 RII = DO = O 50 T= I OB 18 WT=WT-1 = 1 OB 19, OB 20 WB( 0) < WT( 1) Read RII(I) from AM-II MEM at address WT OB 22, OB 24 RII( 1) > DO( 0) 55 call DELTA 2 returns DELO= 1 DO= DELO= I OB 22, OB 23, OB 18 RII=D O = 1 T= 0 WT=WT I = O 60 OB 19, OB 20 WB =WT= O Read RII( 2) from AM-II MEM at address WT SB 22, OB 24 RII > DO Call DELTA 2 returns DELO = 2 DO = DELO = 2 65 227 1,570,344 227 OB 22, OB 23, OB 18 RII = DO = 2 T= I WT = WT -l -1 OB 19, ON 21 WB(O) > WT(-l) RI = 255 5 OB 22, OB 24 RII > DO call DELTA 2 returns DELEND OB 25, OB 26 write RI = 2 to memory area 3 M 3 = M 3 + I OB 27 WB=WT+l= 10 OB 6 call Decode 2 returns EOF 2 = 1 EXIT Note that upon return the only value in MEMORY MODULE area 3 is a 2 Thus, of the check occurrence values 6, 2 only 2 was present in the given line.
is XXVII CHANGE 2 MODULE 15 A General Description
The CHANGE 2 MODULE has the function of modifying information contained in EO vectors The module is initially presented with a seed line whose values are arranged in monotonically decreasing order The seed line is the isoentropic compressed version of the input line to be changed Additionally, an input 20 value representing the iso-entropicgram line number of the above seed is input.
Additionally, a set of monotonically decreasing values representing values to be changed in the input line (i e, a change line) whose seed was initially input, is entered these values represent event occurrence values to be changed Hence, if an event occurrence value exists both in the input line of the isoentropicgram 25 represented by the seed and the change line, it will be removed from the input line.
However, if a value exists in the change line but not in the input line of the isoentropicgram represented by the seed, then the change line value is added to the input line The above process is accomplished by revolving the change line so that the change line representation and the seed line are on equivalent lines of their 30 respective iso-entropicgrams When this is the case, the two lines from their respective iso-entropicgrams are merged, forming a single line of a new isoentropicgram which is not necessarily the seed line This new representation contains as one of its lines the original input line of the seed with the appropriate changes made This new representation is then passed to the alternative seed 35 finding program.
A new seed line is obtained by the SEED 2 MODULE and the iso-entropic line number is adjusted to reflect this new seed The CHANGE 2 MODULE exits with the new changed seed in MEMORY MODULE area 3 and its line number reflecting the relative distance of this seed from the changed input line 40 B Components A list of the hardware components for the CHANGE 2 MODULE is given in Table 58 A All components shown therein have been disclosed elsewhere in this system and will not be repeated here Similarly the comparator and the data selectors have also been disclosed elsewhere Table 5 OF lists the input/output requirements 45 for the CHANGE 2 MODULE.
C Detailed Description
For the following discussion of the detailed description of the operation of the
CHANGE 2 MODULE, refer to the flow diagram of Fig 77 B and the component design of Fig 77 A 50 Prior to the calling of the CHANGE 2 MODULE, the seed line of the input EO vector to be changed is placed in DPM MEMORY MODULE area 2 The change line is placed into the MEMORY MODULE area 1 Additionally, information is placed in the DPM INTERFACE MODULE IPRF representing the line number of the seed line, the length of the seed line, and the length of the 55 change line Once the proper information is placed into the DPM the change module can be called.
At Cl the line number of the seed line is read from the IPRF into the CHANGE 2 MODULE Additionally, during Cl the DECODE I, II, ENCODE, and SWITCH MATRIX 2 MODULES are initialized At C 2 the line number of the 60 seed line is transferred to the REVOLVE 2 MODULE which is then initiated The 228 1.570 344 AIR 9 REVOLVE 2 MODULE then proceeds to revolve the change line which is in MEMORY MODULE area 1 to the same iso-entropicgram line number as the seed line The resulting representation is then placed in MEMORY MODULE area 3.
At C 3 the length of this revolved representation of the change line is placed in the MLNI register of the DECODE I MODULE The SWITCH MATRIX 2 is then reset so that the DECODE I MODULE will read from MEMORY MODULE area 3 and DECODE II will read from MEMORY MODULE area 2.
Boxes C 4 through C 14 of the flow diagram perform the merging operation between the seed line and the revolved change line Thus, at C 4 the DECODE I MODULE is initiated and the resulting revolved change line value read is placed in 10 hardware register RI Similarly, at C 5 the DECODE II MODULE is initiated and the resulting value read from the seed line is placed into hardware register RI At C 6 a comparison is made between RI and RII If the value in register RI is less than the value in register RII, block C 7 is entered Recalling that both sequences being read by DECODE I and II are monotonically decreasing and the above definition 15 of the merge operation, it can be seen that the seed line value contained is not to be cnanged and is thus written to MEMORY MODULE area 1 by the ENCODE MODULE After RII has been written, the DECODE II MODULE is again activated to read a next value into R 11 Control then goes to block C 13.
Returning to block C 6 and assuming that the value in RI is greater than or 20 equal to the value in register RII, control is passed to block C 9 for further testing.
An additional test is made on RI and RI This time if RI is equal in value to RII, according to the merging rules defined above, the seed line value is not written out.
Accordingly, at C 10 the DECODE II MODULE is called and the results of the read are placed in RIIControl then goes to C 12 25 Returning to C 9, if RI is greater than RII, this indicates that the value in RI must be written to MEMORY MODULE area 1 via the ENCODE MODULE.
Control goes to C 12 from both C 10 and Cl 1 Note that in either case the DECODE I MODULE has to be activated Thus, at C 12 the DECODE I MODULE is called and the resulting revolved seed line value read is placed into register RI 30 Control from C 8 and C 12 comes to C 13 Here a check is made to see whether both modules have finished reading, i e, both EOFI and EOF 2 are set to one If not, control loops back to box C 6 and the merging process continued If both EOFI and EOF 2 are set, control comes to C 14 where the ELAST flip flop in the ENCODE MODULE is set and the ENCODE MODULE is activated so that the 35 final value is written out to MEMORY MODULE area 1.
At this point the change line has been revolved down to seed line and the two have been merged The resultant merged line is now in MEMORY MODULE area 1 C 15 activates a call on the SEED 2 MODULE This module has been described in detail hereinabove It locates a new seed for the now changed input line and 40 places the results in MEMORY MODULE area 3 Control returns to the CHANGE 2 MODULE and exit is taken.
Having completed a detailed description of the flow diagram, a detailed description of the component design can now be given The actual hardware component design is given in Fig 77 B along with all the input/output signals which 45 are used to operate the module. The CHANGE 2 MODULE is initiated at system start-up time when the MINI
COMPUTER asserts its RESET condition to all of its peripherals This RESET condition is received by the DPM INTERFACE MODULE and passed to the CHANGE 2 MODULE as the MINIT signal MINIT enters the CLOCK control 50 circuit, as described previously in this disclosure, causing the MR (Module Reset) pulse to go true and be applied to the asynchronous reset input of the pulse generator circuit Pl through P 6 This causes each of the flip flops Pl through P 6 to be set to the zero state.
To activate the CHANGE 2 MODULE, the CMGO signal is applied to the I 55 input of the clock control circuit causing the clock to be enabled and causing the output of the clock to be applied to the MC line of the clock control circuit, thus causing the clock to be applied to the clock input of each of the flip flops Pl through P 6 Since all the flip flops are reset, the input to the Pl flip flop is true and thus on the first CLK pulse from the clock control circuit the Pl output of the Pl 60 flip flop is set to the true or one state The true signal at Pl causes the A 2 CI to become true thus sending the system enable pulse to the DECODE I, DECODE II, ENCODE, and SWITCH MATRIX 2 MODULES On the complementary clock (CLK) signal the circuit P 1 CLK is asserted true causing the system clock A 2 C 2 to be asserted to the system modules mentioned above Additionally, the Pl CLK 65 229 1,570,344 229 signal causes the line number of the seed contained in MEMORY MODULE area 2 to be clocked into hardware register CLINE Since the Pl flip flop is true, the next CLK pulse causes the Pl flip flop to be set to the 0 state and the P 2 flip flop to be set to the 1 state.
During the P 2 pulse the contents of the CLINE register are enabled to the RIL 5 register in the REVOLVE 2 MODULE During the CLK portion of the pulse, P 2.CLK is asserted This causes A 2 C 4 to be asserted which clocks the value CLINE into RIL of the REVOLVE 2 MODULE The RM 2 GO signal is also asserted activating the REVOLVE 2 MODULE Additionally the circuit P 2 CLK RM 2 END is true causing a true signal to be applied to the clock suspension (CS) input of the 10 clock control circuit thereby causing cessation of the clock The CHANGE 2 MODULE remains suspended until the REVOLVE 2 MODULE completes at which time the RM 2 END pulse is asserted This, in turn, causes the clock suspension logic to be reset thus activating the clock On the next CLK pulse the flip flop P 2 is set to the 0 state 15 The C 2 box in the flow diagram has just been completed at this point causing the change line to be revolved down to the same iso-entropic line number as the seed line.
The true output at P 3 causes a true signal at A 2 C 5 This causes the DECODE I, DECODE II, and the ENCODE MODULES to be initialized Additionally, 20 A 2 C 5 enables the MLN 3 output from the ENCODE MODULE to be gated through AND gate 220 and OR gate 226 of the DECODE I MODULE to the counter MLNI Flip flops 513 and 531 of the SWITCH MATRIX 2 are also set by the A 2 C 5 line During the CLK portion of the pulse, P 3 CLK becomes true thus asserting A 2 C 6 The true pulse at A 2 C 6 causes the contents of MLN 3 to be loaded 25 into MLNI of the DECODE I MODULE and the DECODE I MODULE is activated The P 3 CLK pulse also causes A 2 C 8 to be asserted causing the DECODE II MODULE to be activated DIMEND and D 2 MEND are both asserted by the respective DECODE modules This causes the clock in the CHANGE 2 MODULE to be suspended When both DECODE modules have 30 completed, the next CLK pulse causes the P 3 flip flop to be reset to 0 and the P 4 flip flop to be set to 1 Pulse P 3 has executed the functions shown in boxes C 3, C 4 and C 5.
Boxes C 6 through C 14 are implemented during pulse P 4 During P 4 the values read by DECODE I and DECODE II are clocked into registers RI and RII, 35 respectively Additionally during P 4 the comparator circuit is enabled causing the values in RI and RII to be compared If the value in RI is greater than RII, the contents of RI are gated through data selector DS 1 to the data selector ED 56 of the ENCODE MODULE However, if the contents of RI are smaller than RII, then the contents of RII are gated through data selector DSI to the date selector ED 56 40 of the ENCODE MODULE In either case the signal P 4 E causes the signal A 2 C 9 to be true thereby enabling the output of DS I through to the EI register of the ENCODE MODULE On the CLK portion of the pulse the circuit P 4 CLK becomes true From C 12 it is obvious that the DECODE I MODULE is activated whenever RI is not less than RII and from C 8 and C 10 it is obvious that the 45 DECODE II MODULE is activated whenever RI is not greater than RII.
Accordingly, if RI is greater than or equal to RII, the L output of the comparator is 0 Thus, its complement is 1 and P 4 1 CLK is true thereby asserting A 2 C 7 and activating the DECODE I MODULE Similarly, if RI is less than or equal to RII, the G output of the comparator is 0 Thus its complement is true thereby asserting 50 A 2 C 8 and activating the DECODE II MODULE Additionallv if either RI is greater than RII or RI is less than RII, then the E output of the comparator is 0.
Thus the complement of the E output (E) is 1 This activates the circuit P 4 E CLK thereby asserting signal A 2 C 10, causing the value gated through DSI to be loaded into the El register of the ENCODE MODULE and activating that module While 55 any of the above mentioned modules are active, the clock suspension circuits are true and the CHANGE 2 MODULE clock is disabled When all the above modules complete, the CHANGE 2 MODULE clock is again enabled and, depending upon the DECODE module outputs, either P 5 is reentered or P 4 reset and P 5 is activated Considering C 13 of the flow diagram, if EOF 1 and 60 EOF 2 are not both asserted, this indicates that the merging operation is not complete and that another series of compares is necessary.
Thus if EOFL EOF 2 is true the P 4 flip flop is reactivated and the comparison is repeated If both DECODE modules have completed, t’ EOFI EOF 2 is true thereby causing P 4 to be reset on the next pulse and P 5 set t 65 230 1.570,344 230 Duringipulse P 5 the ELAST flip flop in the ENCODE MODULE is set via pulse A Cl During P 5 CLK, A 2 C 10 is asserted causing activation of the ENCODE MODULE This forces the writing to MEMORY MODULE area 1 of the last value in the ENCODE MODULE Additionally, the circuit P 5 CL EMEND is true causing the CHANGE 2 MODULE clock to be disabled 5 The module remains dormant until EMEND is asserted by the ENCORE MODULE causing the clock suspension logic to be 0, thus enabling the CHANGE 2 MODULE clock On the next CLK pulse the P 5 flip flop is reset and the P 6 flip flop is set to a 1 During the CLK portion of the pulse, P 6 CLK becomes true causing A 2 C 12 to be asserted This, in turn, activates the SEED 2 MODULE 10 Again the clock in the CHANGE 2 MODULE is suspended by the P 6.CMK SM 2 END The SEED 2 MODULE proceeds to find the new seed and store it in MEMORY MODULE area 3 Upon completion, P 6 CLK SM 2 END is asserted at the modulate terminate (MT) port of the clock control circuit This causes the module to be reset and the function complete signal to be asserted The 15 function complete signal returns to the calling module as signal CM 2 END at which time all activity ceases in the CHANGE 2 MODULE while the new seed is located in MEMORY MODULE area 3.
D Example of Operation Since the majority of the data manipulation during the change process takes 20 place, this example will depict the change process by showing the interrelationship of the MEMORY MODULE memory areas at various stages Refer to Fig 77 C during the remainder of this discussion.
Initially, the change line, i e, the occurrence values to be changed in the input line represented by the seed, is placed into MEMORY MODULE area 1 The seed 25 line representing the input line under consideration is placed in MEMORY MODULE area 2 The length of the two lines just mentioned is placed in the IPRF of the DPM INTERFACE MODULE along with the iso-entropicgram line number of the seed.
The REVOLVE 2 MODULE is then activated by the CHANGE 2 MODULE 30 It proceeds to revolve the change line down to the same line of the isoentropicgram as the seed line The results are stored in MEMORY MODULE area 3.
Now that the seed and the requested changes are on equivalent lines of their iso-entropicgrams, they can be merged together The CHANGE 2 MODULE performs that merge operation by reading the information in MEMORY 35 MODULE areas 2 and 3, merging the two, and writing the results into MEMORY MODULE area 1.
Once the merging operation is complete, the result is a new line in the isoentropicgram representing the input line merged with the change line Therefore, the SEED 2 MODULE has to be called to locate the new seed for this changed 40 input line It does so and in the process stores the new seed in MEMORY MODULE area 3 At this point the change operation is complete and exit is taken from the CHANGE 2 MODULE.
XXVIII MEMORY 2 MODULE The MEMORY 2 MODULE disclosed here and depicted in Fig 77 D is, for 45 the most part a duplicate of the first MEMORY MODULE disclosed The module is included here for the sake of clarity in disclosing this alternative implementation Since the MEMORY 2 MODULE is so similar to the MEMORY MODULE, no general disclosure will be given here A detailed description of the operation of the MEMORY 2 MODULE can be obtained by referring to Section 50 XVIII MEMORY MODULE The MEMORY 2 MODULE operates as disclosed in the above mentioned section with the following additional capability The OUTPUT 2 MODULE has the capability of writing to MEMORY MODULE area 3 To do this the data signal M 3 is added as the seventh input to data selector D 53.
Another data signal from register RI in OUTPUT 2 MODULE is added as the fifth 55 signal to data selector D 54 The final signal added to the MEMORY 2 MODULE is the control signal A 2014 from the OUTPUT 2 MODULE.
The write procedure from OUTPUT 2 MODULE into MEMORY 2 MODULE area 3 is as follows The address is gated through D 53 to the address decoder of memory area 3 The address is gated through D 53 when the 60 OUTPUT 2 MODULE asserts signal A 2014 At the same time the RI register from OUTPUT 2 MODULE is gated through D 54 to the MIR port of memory area 3.
The OUTPUT 2 signal is also added to the write enable circuit The circuit 231 1,570,344 231 responds by asserting WE which, in turn, enables the write enable port on memory area 3 thus writing RI into the memory Througout the description of this alternative disclosure, MEMORY 2 MODULE has been referred to as MEMORY
MODULE.
XXIX SWITCH MATRIX 2 5 The SWITCH MATRIX 2 of Fig 77 E has 9 flip flops designated S 1 l-S 13, 521-523, and 531-533 The flip flops are set to allow the DECODE I, DECODE II, and ENCODE MODULES to read and write in the proper MEMORY MODULE areas The flip flops are labeled as follows: Sij where i = 1 designates DECODE I; i = 2 designates DECODE II, i = 3 designates ENCODE, and where 10 j = 1 identifies MEMORY MODULE area 1; j = 2 identifies MEMORY MODULE area 2; j = 3 identifies MEMORY MODULE area 3 With reference to the SWITCH MATRIX 2 of Fig 77 E, and the descriptions of the DECODE I,
DECODE II, and ENCODE MODULES, it will be recalled that the DECODE I and II MODULES always read from memory, whereas the ENCODE MODULE 15 always writes in memory Thus, when flip flop 511 is in a 1 state, it designates that the DECODE I MODULE is to read from MEMORY MODULE area 1 If flip flop 521 is in a 1 state, it designates that the DECODE II MODULE is to read from MEMORY MODULE area i, and if the 531 flip flop is in the I state it designates that the ENCODE MODULE is to write to MEMORY MODULE area 1; In 20 addition to the flip flops the SWITCH MATRIX 2 has input/output signals for controlling the operation of the module along the right hand side of Fig 77 E, along with the modules from which the signals originate.
It will be noted that the SWITCH MATRIX 2 MODULE disclosed herein is much simpler in design than the originally disclosed SWITCH MATRIX This is so 25 since the method of finding a seed as disclosed in SEED FINDING 2 MODULE does not require that a copy of the current “best seed” be saved As a result the seed line number is computed and then generated directly into MEMORY MODULE area 3.
The flip flops are all of type SN 7474 having the characteristics disclosed above 30 Consider now generally the operation of the SWITCH MATRIX 2 As mentioned above, the SWITCH MATRIX 2 is used for controlling the operation of the MEMORY MODULE Normally, the MEMORY MODULE will be used in the manipulation of seeds A seed must be read, acted upon, and the possibly new line of the iso-entropicgram which is represented by the seed must be written out 35 During normal operation of the DPM SYSTEM the method of reading and writing in the memory area is through the DECODE I and II MODULES and the ENCODE MODULE However, there are times when information will be written directly in a memory area without recourse to the ENCODE MODULE The proper routing of all these read/write signals is handled by the SWITCH MATRIX 40 2.
Turning now more specifically to the SWITCH MATRIX 2, initially the flip flops 5118513, 521-523, and 531-533 are set to 0 by the MINIT pulse from the DPM INTERFACE MODULE which resets the entire DPM SYSTEM The flip flops are then set by the calling modules (SEED 2, OUTPUT 2, CHANGE 2, PIPE, 45 and BRIGHTNESS) It will be noted that the SEED 2, PIPE, BRIGHTNESS, and OUTPUT 2 MODULES simply set the SI 1, 522, and 533 flip flops Thus DECODE I will read from MEMORY MODULE area 1, DECODE II will read, if necessary, from MEMORY MODULE area 2, and ENCODE will write to MEMORY So MODULE area 3 The CHANGE 2 MODULE initially sets these flip flops as do 50 the other modules However, A 2 C 5 resets Sli and 533 while setting 513 and 531.
Recalling the description of the CHANGE 2 MODULE, this sets the SWITCH
MATRIX 2 so that the merging phase of the CHANGE 2 MODULE can read from MEMORY MODULE areas 2 and 3 and write into MEMORY MODULE area 1 Since this is done, note also that the A 251 pulse from the SEED 2 MODULE has to 55 reset 513 and 531 This is so since the SEED 2 MODULE can be called from the CHANGE 2 MODULE.
XXX AUXILIARY MEMORY MODULE II Fig 77 F shows the AUXILIARY MEMORY MODULE II On the right are shown the input/output control signals used for controlling the AUXILIARY 60 MEMORY MODULE II and the information input/output lines Double lines are used to designate multiple signal data lines.
The AUXILIARY MEMORY MODULE II (AM-II MODULE) includes 232 1,570,344 232 233 1,570,344 233 two random access memories Al, A 2 The memory areas Al and A 2 are TTL RAM type SN 7489, disclosed at page 220 of the above referenced book Each memory has 256 memory locations, each of which contains 8 binary coded bits The aforementioned type of memory is only used herein by way of example and, within the scope of the present invention, may be of different sizes and types, depending on 5 the particular application In most applications, it may be desirable to replace the TTL RAM memories with one or more disc files to give greater storage capacity.
Associated with each memory is an address decoder which decodes the binary signals into unique addresses.
Also with each of the memories is a Memory Information Register (MIR) 10 Each MIR is connected to the output of the data selector D 55 from which it receives 8 binary bits of information for storage in one of the memory locations of the corresponding RAM memory Each MIR forms part of the RAM memory disclosed in the above TTL book Also included in each of the memories is a memory data register (MDR) which forms the information output for the corres 15 ponding RAM memory Eight binary coded bits are applied as output at each of the MDR circuits when information is being read out of the corresponding memory.
Writing takes’place in one of the memories Al or A 2 by applying an information word to the corresponding MIR and an address word to the corresponding address decoder After the signals have stabilized, a true write enable 20 signal is applied at the WRITE ENABLE input to the memory causing it to write the information word at the MIR input to the address specified by the address word applied to the address decoder.
Reading takes place in a memory merely by applying the address of the desired location to the address decoder for the memory thereby causing the word at the 25 corresponding address to read out and applied at the MDR output of the memory.
Selection circuits DSI through D 56 are data selectors as disclosed in the ENCODE MODULE Connected to each data selector is a double line to designate information lines and single lines to indicate control signals Each double line is numbered and has a correspondingly numbered signal line A true signal at the 30 control line causes the signals applied at the corresponding information lines to be coupled through to the output of the data selector.
The WRITE ENABLE circuit is the same as that described for the MEMORY MODULES It has logic circuit A 3 R 9 + A 2 RII + A 2011 + P 17 + B 8 + PBWE 35 applied to the MEMGO input line of the WRITE ENABLE circuit The MINIT signal is also applied to the WRITE ENABLE circuit The WE output from the WRITE ENABLE circuit is then applied to the input AND gates of the memories Al and A 2.
The modules which communicate with the AM-II MODULE and whether 40 information is read out from the MEMORY MODULE or/and written into AM-Il, is summarized as follows:
REVOLVE MODULE 2 -read and write REVOLVE MODULE 3 -read and write OUTPUT MODULE 2 -read and write 45 PIPE MODULE -read and write BRIGHTNESS MODULE -read and write INTERFACE MODULE -read and write Gating circuits are depicted by logical equations using the outputs of other modules, flip flops, etcas to designate terms in the equations so The sequence of operation of AM-II during a WRITE operation in one of the memories will now be described with reference to the timing diagram of Fig 2 A’ WRITE operation is initiated by the REVOLVE 2, REVOLVE 3, OUTPUT 2, PIPE, BRIGHTNESS, or INTERFACE MODULES The calling signal causes a true signal at the MEMGO input of the WRITE ENABLE circuit The WRITE 55 ENABLE circuit operates as disclosed in the MEMORY MODULE Finally the WRITE ENABLE circuit forms a true signal at the WE output The signal WE is applied to the AND gates at the WRITE ENABLE ports of the memory modules The second input of these AND gates controls the particular one of the memories into which information is to be written from data selector D 55 The control flip flop SM will be ex 60 plained Initially, control signals from the three modules serviced will set the SM flip flop to a 1 state This allows for reading from area Al and writing to area A 2 To switch 234 1 5703444 areas, a signal is applied to the clock input of SM causing it to toggle to the next state, i.e the SM output will be reset to 0 and the SM output will be reset to 1 This, in turn, allows for reading from memory area A 23 and writing to memory area Al.
In summary then, it should now be understood that the outputs of D 54 from
REVOLVE MODULE 2, D 54 or REVOLVE MODULE 3, RII from OUTPUT 5 MODULE 2, D 52 of PIPE MODULE, D 54 of BRIGHTNESS, and D 53 of the INTERFACE MODULE, are coupled to the inputs of data selector D 55 A true signal from the A 2 Rll, A 3 R 9, A 2011, P 17, B 8, PBWE outputs from REVOLVE 2, REVOLVE 3, OUTPUT 2, PIPE, BRIGHTNESS, and INTERFACE MODULES, respectively cause D 55 to couple outputs from the corresponding modules through 10 to the MIR input of memory areas Al, A 2 The DSI, D 52 selection circuits couple the addresses of the inputs to the corresponding address decoders.
The D 56 selection circuit couples the information being read out of areas Al, A 2 to the inputs of the REVOLVE 2, REVOLVE 3, OUTPUT 2, PIPE, and BRIGHTNESS MODULES After sufficient time for the signals to be applied at 15 the output of D 56 and stabilized to the input of the modules receiving the signals, the M 2 multivibrator of the WRITE ENABLE circuit automatically resets to the 0 state, causing a true signal at the M 2 output, which in turn causes the WRITE ENABLE circuit to reset itself and terminate the WE signal applied to the memories 20 XXXI COMPUTER, DATA BASE, AND SOFTWARE ORGANIZATION A MINI COMPUTER A software package is provided for handling of the piping and brightness functions The software disclosed herein is for use in the DPM system of Fig 1 and is employed on the PDP-1 1/45 computer manufactured by the Digital Equipment 25 Corporation which is disclosed by way of example for the MINI COMPUTER.
The disclosure of the software package is in terms of a computer program and subroutine listings in assembler language for the PDP-1 1/45 and flow charts each of which will be discussed in more detail hereinafter.
Appendix B contains an index of the program listings together with the actual 30 listings The actual assembler provided with the PDP-1 1/45 can be used for assembling the listings into machine code The meaning of the terms used in the listings of Appendix B together with the corresponding operation within the PDP-1 1/45 can be understood with reference to the following manuals, incorporated by reference, and published by the Digital Equipment Corporation: 35 Processor handbook PDP-1 1/45, published in 1971, Batch- 11/DOS-11 Assembler (MACRO-11), pub Isihed in 1971, and Peripherals and Interfacing Handbook, published in 1971.
The operator console has a typewriter which forms electrical coded signals in ASCII code representing the characters entered on the keyboard The typewriter is 40 of type LA 30 (DECWRITER) manufactured by Digital Equipment Corporation.
The operator console also includes a printer for printing out and displaying on paper, characters represented by signals coded in ASCII code The printer is part of the LA 30 (DECWRITER).
B General Description of Data Base Structure 45
The building of the layered data base is described in detail in the section HARDWARE/SOFTWARE ORGANISATION FOR BUILDING LAYERED DATA BASE For purposes of illustration, a simple two layer structure is assumed and disclosed.
so Briefly, it is assumed that the two layer textual data base has a word layer 0 and 50 a sentence layer 1 As discussed hereinabove, the word layer is for letters and other symbols Fig 78 shows a generalized representation of the data structure for the layers As indicated, LXPTR (where X denotes the layer number) is the base address of a layer header that includes a base address pointer LXET to a layer event pointer table (LXET) The layer header contains four words of information 55 The first is the address LXET of the base of the table LXET The second word is an iso-entropicgram width value (HW) which identifies the width of the isoentropicgram in event-times or clock occurrence values for all associated seeds The third word is a value NE specifying the number of events (seeds) associated with the corresponding LEPT The fourth value TIKX is the current highest clock or event 60 time value associated with this layer.
The table LXET contains a series of sequentially addressable memory locations, one corresponding to each event (seed) associated with the LXET The 234 1.570-344 ALAA first memory location of this table is at address LXET An entry is received as the base address of the table 1 for a pointer to a null seed This allows a common pointer to all those events which are unknown to the layer Each memory location of the LXET contains a base address of a different seed heater Each seed header is associated with a memory area containing the seed line for the corresponding seed 5 Each seed header has four words The first word is called pointer to seed and is a base address pointer to the first memory location of a memory area contained in the seed line of the corresponding seed The second word in the seed header is the iso-entropicgram line number for the corresponding seed line The third word is the value identifying the physical length (in 8 bit bytes) The fourth word is the number 10 of event-times (actual occurrence values) contained in line 0 of the seed line.
Each seed header and corresponding seed line represents one event occurrence vector in the corresponding layer The seed line is stored in a series of sequentially addressable memory locations starting with the pointer to the seed i 5 address in the corresponding seed header 15 Figs 79 A and 79 B show data structure for layers 0 and 1, respectively, of the data base.
C General Description of Software
The general functions which must be performed by a data base system are:
1 Initialize the data structures; 20 2 Enter the date; 3 Manipulate the data; The first two functions comprise what shall be called the layer building aspect of the data base system A detailed description of the layer building function is given in section XXXIII HARDWARE/SOFTWARE ORGANIZATION FOR 25 BUILDING A LAYERED DATA BASE The third function is known as the retrieval aspect of the data base system A detailed description of said retrieval aspect is disclosed in Section XXXII INQUIRY AND RETRIEVAL HARDWARE/SOFTWARE ORGANIZATION.
What follows is a general description of the data base system being disclosed 30 here The programs and subroutines required for operating the data base system are listed in the Index under Section XXXII INQUIRY AND RETRIEVAL HARDWARE/SOFTWARE ORGANIZATION and Section XXXIII HARDWARE/SOFTWARE ORGANIZATION FOR BUILDING A LAYERED DATA BASE 35 Fig 79 C depicts the generalized operation of the disclosed data base which is shown in Fig 121 and which is described in detail in Section XXXIII Fig 79 C depicts the hierarchical arrangements of the programs and subroutines which comprise the data base system.
The manner in which the data base system is activated is to have the assembled 40 code, which describes the system, loaded into main memory of the MINI COMPUTER Program execution is initiated by directing the MINI COMPUTER to execute the first instruction in the system.
1 Data base Initialization It is obvious that before any meaningful manipulation of the data base can be 45 performed that the system data structures must be initialized Initialization is performed by the LAYER INITIALIZATION program Layer initialization is depicted in block DB 6 0 of Fig 121 and expanded in Fig 122 Layer initialization is described in detail in Section XXXIII.
so Data structure initialization begins by initializing the I/O conversion tables so CVRTBL and CVTBL 2 of Fig 117 These tables are used to convert the characters input from some input device into internal event numbers Event numbers bind the event occurrence vectors to original input characters.
Secondly, the main data structures depicted in Fig 78 are initialized Memory areas are set aside for layer headers, layer event pointer tables, seed headers, and 55 seeds Pointers and beginning value numbers are inserted wherever they are needed When initialization is complete, the main data structures are as shown in Fig 120.
2 Layer Building The next function to be performed after initialization is the entering of the 60 235 1,570,344 235 236 1,570,344 236 data base information In entering information into the data base system, layers are constructed The control would be given to the level one program in Fig 79 C LAYER BUILDING The flow for this program is given in Figs 122-131 The program is described in detail in Section XXXIII HARDWARE/SOFTWARE ORGANIZATION FOR BUILDING LAYERED DATA BASE 5 Information is entered into the data base in layer one entries, i e, sentences.
Thus an input entry would consist of a sentence delimiter followed by a series of Words each beginning and ending with a blank character Finally, a sentence delimiter would complete the entry, e g, #THIS IS A TYPICAL INPUT ENTRY# 10 The LAYER BUILDING program processes each input entry and enters it into the data base The method for doing this is as follows; 1 A sequence of events between blanks is obtained (i e, a word). 2 A check is made as to whether this sequence is already in the data base
on the lowest layer If it is, it already points to an event on the next higher 15 layer If the entry does not exist on the lower layer, it is added to this layer and an event number on the next higher layer is created.
3 Steps 1 and 2 are repeated as long as there is another word in the input request to be processed.
4 When the ending sentence delimiter is recognized, the sequence of words 20 (entries on layer 0, events on layer 1) is added to layer 1 Since the system disclosed is a two layer system, no redundancy is squeezed from layer 1.
The control sequences on Fig 77 G for performing steps 1 through 4 are as follows:
The LAYER BUILDING program calls the level 2 PROCESS ENTRY 25 program The PROCESS ENTRY program starts to process the request by taking the events in the first word converting them from ASCII input code to internal code representing layer 0 event numbers The event numbers are used to stack on ESTAK the corresponding LOET entries The process continues until a trailing blank is recognized 30 Since a blank has just been recognized and hence a layer 0 entry is now being dealt with, control goes to the level 3 program PROCESS A LAYER 0 ENTRY.
This program will process the word which is now represented on the top of ESTAK.
PLOE is entered with the top of ESTAK containing pointers to the seeds of the events which comprise the word being processed PLOE passes the contact of 35 ESTAK to the level 4 program PIPE The PIPE program performs piping on the events on ESTAK If the sequence of events on ESTAK are in the data base exactly, the number of the entry which caused the exact match is returned to PLOE.
However, if the sequence did not match exactly, then this sequence must be added as an entry to level 0 Accordingly, the level 4 program ADD N EVENTS is called 40 This program will take the top of ESTAK elements which correspond to the word being processed and add the entry to the data base as a level 0 entry This addition is performed by calling the hardware CHANGE MODULE This procedure adds the next appropriate event occurrence time value to the event occurrence vectors of the events in question This process creates new seeds for the events in question 45 The new seed has to be placed in storage by the level 5 program, PUT NEW SEED IN STORAGE program.
The PUT NEW SEED IN STORAGE program first calls the level 6 program SEARCH FREE SPACE The SEARCH FREE SPACE program searches the storage area available for seeds until a slot is found which can accommodate the so new seed The address of this slot is passed back to PUT NEW SEED IN STORAGE The program then transfers the new seed from a temporary area into the slot The old seed must now be released since its values are no longer required.
This is done by calling the level 6 program RELEASE SPACE RELEASE SPACE returns the area occupied by the old seed into an available space pool 55 Finally a check is made as to whether the seed storage area is too fragmented.
If it is, control goes to the level 6 program, PERFORM GARBAGE COLLECTION This program rearranges core so that all the seeds are located in a contiguous area of core To do this some seeds must be physically moved from one area in storage to another When this is done the seed headers for these seeds must 60 be updated to reflect this change This is done by the level 7 program ADJUST SEED HEADERS.
When the above completes, the PUT NEW SEED IN STORAGE program has also completed its task Hence, control goes back to level 4 ADD N EVENTS.
ADD N EVENTS RETURNS TO LEVEL 3 PLOE with the entry number of the entry just added PLOE takes this entry number or the one obtained if an exact match was found and converts it to a level I event number The current entry is 5 cleared from ESTAK since it is no longer needed The level 1 event number just computed is used to push a LIET pointer onto ESTAK This value on ESTAK represents the collapsing of the current word being processed into a single value representing a layer 1 event number Control returns to PROCESS ENTRY.
The above process repeats as long as there is another word to be processed 10 When the ending sentence delimiter is recognized, control goes directly from the PROCESS ENTRY program to the level 4 program ADD N EVENTS In this case the layer 1 events on ESTAK representing the words of the input entry are entered into layer I as a new entry Note that PIPE was not called since redundancy is not squeezed from layer 1 15 ADD N EVENTS operates as described hereinabove New seeds are created and stored GARBAGE COLLECTION is performed if necessary Control finally returns to PROCESS ENTRY which passes it back to the LAYER BUILDING program The above process repeats for each input entry to be added to the system.
Once the data base has been input, the system can be used to manipulate the 20 information it contains This is done by control passing from the DATA BASE program to the level I FORMATER program The FORMATER program in turn passes control to one of the following level 2 programs: COMMAND or REQUEST.
* The level two program COMMAND is entered if a change in control 25 parameters is desired The control parameters are mainly four:
1 Pipe width (PW) 2 Pipe cutoff (PCO) 3 Brightness cutoff (BVCO) 4 Length switch (LNGSW) 30 These parameters are used to control the quality of response They are used in determining the closeness of match criterion by which possible output responses are discriminated.
The other level two program in the data manipulation area is the REQUEST program This program will accept requests from an input terminal and output as 35 responses those entries of the data base which pass the closeness-of-fit criterion imposed by the control parameters.
The first task of the REQUEST program is to pre-process the input request to assure an input entry format which is the same as that described in the LAYER BUILDING program description This being done, control goes to the level 3 40 program PARSER.
The PARSER starts to process the input request The initial delimiter in the request determines whether the response will be from level O or level 1.
First, assume a level 0 response This assures an input request as follows:
< blank > < letter > < letter >< letter > < blank > 45 The PARSER strips off the input code and converts it to layer 0 event numbers The event numbers are used to stack LOET pointers on ESTAK of the layer 0 events which comprise the word being processed When the trailing blank is recognized control goes to the level 4 program PIPE.
PIPE performs hardware piping on the word and returns to PARSER with the 50 candidates for response prepared for the BRIGHT module The level 4 program BRIGHT is called.
B RIGHT performs the hardware brightness function on the candidates selected by PIPE Those which pass this final test are placed on an order list determined by their closeness-of-fit values Control returns to PARSER which, in 55 turn, passes control to the REQUEST program.
The REQUEST program passes the list obtained by the BRIGHT program to the level three program (PROCOUT) PROCOUT converts the entries on the ordered list into printed responses It does this by first calling the program SETUP.
SETUP computes the beginning and ending boundaries of the responses 60 GENERATE is then called which searches through all the event-occurrence 237 1,570,344 237 238 1,570,34423 vectors in this layer until all the events are found which lie between the beginning and ending boundaries established in SETUP Control goes back to PROCOUT which converts the event numbers to output code and prints the response on the output device PROCOUT continues calling SETUP and GENERATE until the list prepared by BRIGHT is exhausted or until the system requests that no more 5 responses be output In either case control returns to the REQUEST program.
A second kind of request can be a layer 1 request In this case the operation is as follows:
The REQUEST program pre-processes the input request and control goes to the PARSER The PARSER processes each word as described hereinabove 10 However when the list is returned from BRIGHT, only the best (i e, the top) layer 0 entry (layer 1 event) is stacked on ESTAK In this way the system is building a series of layer I events on ESTAK which represent a sequence of words which are as close as possible to the input request Once this sequence is generated, PARSER again calls PIPE and BRIGHT The difference here is that level 1 events are being is used BRIGHT still returns a list of best possible responses to PARSER and control finally returns to REQUEST.
At this point the REQUEST program contains an ordered list of layer 1 entries that are possible responses to the input request The next step is to output and print out this responseTo do this, PROCOUT is called 20 PROCOUT, in turn, calls SETUP and GENERATE as described hereinabove.
The difference here is that upon completion of GENERATE a list has been generated which represents the layer 0 words which must be generated in order to output a response These words are then generated by calling SETUP and GENERATE a second time The letters contained in the words are generated 25 Control goes back to PROCOUT and the response is printed on the output device.
The above sequence continues until the list is exhausted or until the system requests termination Control returns to REQUEST AND THE PROCESS REPEATS.
Having constructed the data base, various types of requests and retrievals can 30 be made with ease The following section deals with this subject.
XXXII INQUIRY AND RETRIEVAL HARDWARE/SOFTWARE ORGANIZATION A General Description of Inquiry and Retrieval Software
The primary supervisory program for inquiry and retrieval is the FORMATER 35 program whose operation is initiated from the data base program when a requestor indicates that he wishes to do retrieval on the typewriter This occurs, as will be explained, when the operator types an R on the typewriter during initial steps in the operation The FORMATER program responds and in turn calls into operation others of the programs and subroutines which in turn call into operation others 40 The general overall operation of the software system under control of the FORMATER program is depicted in Fig 102 A for a layer 0 request and Fig 102 B for a layer 1 request Each of the new modules is presented with a flow diagram of operation and a computer program which will execute the flow For ease of presentation and understanding the following standards have been adhered to in 45 the flow diagrams.
1 A concise portion of the program is represented in the flow by a narrative description surrounded by a single lined box.
2 A broad portion of the code indicating a function to be performed but which is not to be treated as a subroutine in the code is presented as a 50 narrative surrounded by a box whose vertical ends are double lined This function will then be expanded in a later flow diagram; however the code will be presented in line.
3 A function to be called is a subroutine which has the same description as ( 2) above; however there is an “X” between the vertical lines (see Fig 80) 55 In this case both the flow for the box and the computer code will be expanded at a later time.
The FORMATER program accepts and processes entries presented by a requestor at the typewriter of the operator console The entries can be either a request’to the layered data base or can be a command which has to be executed 60 Commands are of two types One type of command is an “END” command which denotes an end to the particular request and causes an exit from the 238 1,570,344 238 239 1,570,344 239 FORMATER piogram The second type of command is a “CHANGE” command which allows the operator to change one of the globals that are used in the piping and brightness computations Globals are the a used in the Equation 11 for the length value L, LNGSW which is a flag which states whether or not the length of the request is to be used in making a response, the piping and brightness cutoff 5 values PCO and BVCO, and the pipe width value PW.
Consider now the general operation of the FORMATER program for a data base request and assume that a requestor is making a layer 0 request The general operation of the FORMATER program is depicted for a layer 0 request in Fig.
102 A and should be referenced in the following discussion As described above, the 10 requestor enters a request at the keyboard of the typewriter with the following format:
where represents letters of a word and b represents a typewriter blank and word delimiter The FORMATER program first causes a carriage return line feed on the 15 printer and causes an asterisk () to be printed out by the printer The requestor then types the letters of the request word surrounded by the word delimiters} 6 The typewriter presents ASCII coded electrical signals to the MINI COMPUTER The FORMATER program responds to the ending delimiter b and calls the operation of the REQUEST subroutine 20 The REQUEST subroutine places the first word delimiterso into the parse string (PSTRING) shown at 2211 It then converts the ASCII coded letters of the request word using a table CVRTBL into corresponding layre 0 event number signals el, e 2, etc, and stores these event numbers into PSTRING The ending word delimiter 6 is then stored in PSTRING The REQUEST subroutine then 25 passes a pointer to the PSTRING over to the PARSER program In this regard the MINI COMPUTER hardware register R 4 receives an address pointer to PSTRING A blank E is used herein to refer to an ASCII coded character, and the script e is used to refer to a layer event number.
The PARSER program causes an interrogation function in the data base The 30 interrogation function is performed by piping and brightness functions using the content of PSTRING and forms a list known as PNBOUT shown at 2213.
PNBOUT contains a series of two value pairs the first of which is an entry number, i.e, El, E 2, et seq, and the second of which is a brightness value B Vl, BV 2, et seq, corresponding to the same numbered entry number The entry numbers identify 35 the number of the entries in layer 0 and the brightness values identify the brightness value for the corresponding entry as determined by the piping and brightness functions The entries in PNBOUT at 2213 only include those whose brightness values are above the brightness cutoff value BVCO entered as a global by the requestor 40 Having formed PNBOUT at 2213 it is now necessary to generate the outputs for the entries contained therein To this end the PROCOUT subroutine is called which takes each layer 0 entry, i e, El, E 2, et seq from PNBOUT and moves it into a Table Gl shown at 2215 Table G 1 contains a series of three word entries the first of which contains one of the entry numbers from PNBOUT and the second and 45 third are initially set to 0 The PROCOUT subroutine then calls the SETUP subroutine which goes through and, for each entry in Table G 1, determines the ending delimiter for the corresponding entry, i e, EDI, ED 2, et seq a length value for each entry, i e, Li, L 2, et seq, and an accumulated length value for each entry, i e, ALI, AL 2, et seq 50 The length value for each entry is the difference between the beginning and ending delimiters, less 1 The accumulated length value, as will be discussed in more detail, is used to select the beginning of each entry in an output string.
Having generated Table G 1 as depicted at 2217 in Fig 102 A, each entry in Table Gl is now output The entries are output to the operator console and printed, 55 one entry at a time To this end, the PROCOUT subroutine is again called and takes off one entry of Table Gl beginning with the top one The entry is moved into a Table G 2 as depicted at 2219 The GENERATE subroutine is then called and takes the ending delimiter for the entry in Table G 2 and generates a reference line which includes all of the event-times which lie between the beginning and ending 60 delimiters for the entry in Table G 2 Having generated all event-times in the reference line the GENERATE subroutine then goes through all event occurrence vectors (each represented by a seed header and seed line) of the data base layer 0 240 1,570,344 240 and forms a series of layer 0 event numbers (e #) and occurrence value (OC) pairs representing the corresponding events in the stored data base A layer 0 event number (e #) and occurrence value (OC) pair is formed for each event-time value in the reference line which is the same as any one of the event occurrence vectors making up the data base The event number (e #) identifies the event occurrence 5 vector in which the actual occurrence value is located This series of pairs is stored in a main memory area called OLIST depicted at 2221 The GENERATE subroutine also causes OLIST to be sorted so that the pairs are arranged with the occurrence values in descending value order thereby representing the order of the events for output 10 The PROCOUT subroutine is then called causing ASCII coded signals to be sent to the operator console for printing This is accomplished by taking each entry number E, in order, using a table called CVTBL 2, converting each to ASCII code and sending the result to the printer of the operator console for printing out and is display 15 Consider now the general operation for a layer 1 request Fig 102 B is a pictorial flow diagram for the operation of the FORMATER program during a layer 1 request Similar to a layer 0 request, the operator types in the request, using the typewriter at the operator console The FORMATER first causes a carriage return and line feed on the printer and causes an asterisk () to be printed to alert 20 the user that the system is ready to accept requests The user then responds by typing the request The requestor will type in a request of the following formal:
b 1 Y 6;S; # where represent letters of a word, # represents a sentence delimiter, and 25 H 15 represents a word delimiter.
The typewriter presents ASCII electrically coded characters The ASCII characters representing letters are converted to their corresponding layer 0 event numbers and placed in the PSTRING as at 2231 in between the beginning and ending sentence and word delimiters (in ASCII code) similar to that described with 30 respect to the layer 0 request of Fig 102 A.
The PARSER subroutine is then called which causes the piping and brightness functions to be applied to the content of the PSTRING and return the PNBOUT list as at 2233 PNBOUT contains the layer 1 entry numbers and corresponding brightness values with only brightness values greater than the brightness cutoff 35 value (BVCO) Thus PNBOUT contains a series of layer 1 entry numbers, i e, El, E 2, E 3, et seq, followed by the corresponding brightness values BVI, BV 2, BV 3, et seq.
The PROCOUT subroutine takes the entry numbers from PNBOUT and sets up a table G 1 as depicted at 2235 Similar to that described for Fig 102 A, the table 40 Gl consists of a series of sets of three word entries, the first of which is the layer 1 entry number, i e, El, E 2, E 3, and the second two of which are initially set to 0.
The SETUP subroutine is then called which fills out the 0 values in the Gl table for each entry number to that depicted at 2237 in Fig 102 B Specifically, for each entry number the SETUP subroutine fills in the corresponding ending 45 delimiter EDI, ED 2, ED 3, et seq, the corresponding accumulated length AL, A 12, AL 3, et seq, and the length of the corresponding entry LI, L 2, L 3 et seq.
The PROCOUT subroutine is again called ‘which takes the values in Gl corresponding to the one entry (beginning with the first) and moves them into Table G 2 as depicted at 2239 50 The GENERATE subroutine is then called causing a reference line to be formed with all of the event-times between the beginning and end delimiters of the layer 1 entry stored in Table G 2 The GENERATE subroutine then goes through each entry on layer 1 and forms in OLIST (see 2241) a series of event number and occurrence value pairs similar to that described at 2221 of Fig 102 A An event 55 number and an occurrence value pair is formed for each actual occurrence value in layer 1 which is the same as an event-time value in the reference line The event number identifies the layer 1 event number in which the actual occurrence value is located AT this point OLIST is as depicted at 2241 with a series of two value pairs, the first of which is a layer I event number (layer 0 entry number) and the second of 60 which is a corresponding occurrence value.
It should be noted that the event numbers in OLIST are event numbers on layer 1 and therefore identify words as oppose to letters Also these event numbers on layer 1 are entry numbers on layer 0 It should also be understood that it is necessary to locate the corresponding letters or events in layer 0 of the data base in order to generate the letters of the word for output by the printer Therefore, the PROCOUT subroutine is again called and takes all the layer 1 event numbers (hereinafter called layer 0 entry numbers) from OLIST at 2241 and arranges them 5 in Table G 2 as shown at 2242 Table G 2 similar to that described with reference to Fig 102 A contains a series of sets of three worded entries, the first one of which is the layer 0 entry number from OLIST and the second two of which are initially set to 0.
The SETUP subroutine is then called, filling in the corresponding ending 10 delimiters, i e, EDI, ED 2, et seq, the corresponding accumulated length values, i.e, ALI, AL 2, et seq, and corresponding length of entry values, i e, LI, L 2, et seq.
The GENERATE subroutine is again called at 2244 and generates a segment of a reference line for each layer 1 entry number in Table G 2 To this end, for each 15 layer 0 entry number in Table G 2, the GENERATE subroutine sets up the list of event-time values that lie between the corresponding beginning and ending delimiters The event-time values are then sorted into descending value order The GENERATE subroutine then proceeds through layer 0 of the data base, setting up a layer 0 event number and an occurrence value pair for each event-time value in 20 the reference line for which there is found an event number and corresponding occurrence value in layer 0 of the data base These event number and occurrence value pairs are placed into OLIST Subsequently OLIST is sorted so that the event number and occurrence value pairs are ordered in descending value order by occurrence value 25 The PROCOUT subroutine is then called to start generating the ASCII coded characters for the printer of the operator console To this end the layer 0 event numbers of OLIST are stripped off, one by one, starting with the event at the beginning of the list and each is used as an index into Table CVRTBL 2 To this end each event number is added to the base address of Table CVRTBL 2 to get an 30 address which address is used to read the corresponding ASCII coded character from Table CVRTBL 2 The ASCII coded character is then transferred to the printer for printing and display.
A decision is made during PROCOUT at 2246 as to whether to print the “next best” entry if one exists Note this allow the user to selectively print out possible 35 responses to the request based on the brightness value of the entries.
This continues until the sentence corresponding to the layer I entry stripped off from Table G 1 at 2238 has been completely printed Upon completion the system returns over to 2238 where the PROCOUT subroutine is called and another layer I entry is stripped off from Table Gl and the process proceeding from there 40 on is repeated.
Consider now more specifically the general operation of the PARSER program and those programs called by the PARSER program The PARSER program is called, as discussed above, by the FORMATER program The PARSER program causes the MINI COMPUTER to perform a number of 45 retrieval functions and calls the operation of the PIPE and BRIGHT programs.
Briefly, as depicted at A in Table 60, the PARSER program scans the letter events of the request after having been converted to base relative address by the FORMATER Program and utilizing the layer header for the desired layer (see Figs 77, 78 A and 78 B), obtains the seed header pointers from the LOET table and 50 stacks (i e, on a last-in-first-out basis) the LOET pointers in the order scanned into a reserved area of main memory in the MINI COMPUTER referred to as ESTAK.
In addition, the PARSER program stores a value representing the number of LOET pointers contained in ESTAK into software register RLNO for a layer 0 request or RLNI for layer 1 request in main memory of the MINI COMPUTER 55 The relevant data produced by calls on the PIPE and BRIGHT programs are depicted at B through E of Table 60.
It should be noted that the purpose of a request as applied to the PIPE and B RIGHT programs is to determine the “best” response in the data base contained in main memory for the word or sentence request When a sentence request is 60 made, then the “best response” is determined based on the actual words in the request sentence The “best” response from the word layer 0 will provide actual sentence layer 1 events to be used in determining the sentence layer 1 response.
These and other aspects of the PARSER, PIPE and BRIGHT software will be more fully described in connection with these programs 65 1,570,344 241 241 Figs 88 A, 88 B through 93 are sketches illustrating the sequence of operation and primary storage areas used during operation of the PARSER, PIPE and BRIGHT programs Consider in general the overall operation Fig 88 is a general diagram indicating how PARSER program sets up a stack area in memory referred to as ESTAK and performs a layer 0 request The PARSER program stores in 5 ESTAK a layer event pointer LXET for each layer 0 event in the request and the LXET’S are stored in the order presented by the request Each LXET is the base address of a seed header for the corresponding event in the request This configuration is generally depicted in Fig 88 A by the lines between ESTAK and an example of layer 0 of the data base 10 The final output area for the PIPE and BRIGHT program is a main memory area referred to as PNBOUT (see Fig 88 A) whose base address is designated by the address in the first location of a two word area identified by the symbol PNBPTR.
The base (or first) address of the area PNBPTR is known as address PNBPTR The second location of PNBPTR contains a value identifying the number of entries in 15 the area PNBOUT As indicated, each entry in PNBOUT contains an entry number, i e, ENTRY 4, ENTRY 2, identifying the number of the corresponding entries on layer 0 In this connection it will be recalled that an entry on layer 0 corresponds to an event on layer 1 PNBOUT contains in the memory locations immediately following each entry number the brightness value BV for the corres 20 ponding entry To be explained in more detail, the BRIGHT program arranges the entry numbers and corresponding brightness values in descending order by brightness value.
Fig 88 is a general figure depicting the base address LXET (Fig 78) in ESTAK which points to the beginning of the corresponding seed headers The first location 25 of each seed header in turn contains the base address of the beginning of the corresponding main memory area containing the corresponding seed lipe.
Referring to Fig 89, the main memory of the MINI COMPUTER contains the delmiter seed line and the event seed line in separate memory areas The PIPE program during P Il through PI 22 transfers the delimiter seed line to MEMORY 30 MODULE area 1 and the event seed line to MEMORY MODULE area 2 The PIPE program causes the PIPE MODULE to process the delimiter seed line and event seed line from MEMORY MODULE areas 1 and 2 and the results are stored in the P/B MEMORY With reference to Fig 89 it will be seen that the P/B MEMORY contains a series of intermediate two value pairs (vi, vii) The first is an 35 event-time (or occurrence) representing a center pipe value vi and the second is anumber of hits value vii.
When the operation of the PIPE MODULE completes and the LAST flip flop in the STATUS register of the INTERFACE MODULE has been set, the PIPE MODULE modifies the two value pairs contained in the P/B MEMORY and 40 causes them to be transferred to MEMORY MODULE area 3.
Fig 90 depicts the general operation of the PIPE program from P 122 to the end of the PIPE program The PIPE program causes the two value pairs vi and vii to be read out from MEMORY MODULE area 3 and the number of hits value, vii, for each of the two value pairs is compared against the pipe cutoff 45 value PCO Those event-time values vi whose number of hits values meet the pipe cutoff criteria, i e, are equal to or greater than the PCO value, are then transferred to P/B MEMORY area 1 If the PIPE program is processing on layer 0 and a response is required from layer 1, the center pipe values are transferred to the area PNBOUT for processing by the BRIGHT program 50 Fig 91 shows an example of a single pass for processing a layer 1 request involving three words As generally indicated, ESTAK contains the address pointers from LXET to the seed headers which in turn identify the beginning location of the corresponding seed lines in main memory It is illustrated that entries 2 and 4 in layer 0 pass the pipe cutoff value test Under these conditions the 55 BRIGHT program generates a two value pair for each of entries 2 and 4 and the results are stored in PNBOUT The two value pairs are a value E identifying the number of the corresponding layer 0 entry and a brightness value BV As indicated above, the BRIGHT program causes the entries to be ordered in decreasing value order by brightness value To be explained in more detail in connection with the 60 PARSER program, the two value pair with the largest or best brightness value is transferred to the top of ESTAK as indicated at e 4 1 (indicating event 4, layer 1).
Since an entry on layer 0 corresponds to an event on layer 1, e 4 1 is a pointer to event 4 on layer 1.
Fig 92 depicts the same example as in Fig 91 after the second pass through 65 242 1.570344 IA’I the PARSER program, assuming that an exact hit was found on entry 3 Under these conditions the PIPE program will transfer directly to PNB OUT the two value pair consisting of a value identifying the entry number 3 on layer 0 or event 3 on layer 1 followed by a forced value indicating a 100 % brightness value The PARSER program will leave in the top of ESTAK the LIET address (e 31) for 5 event 3 on layer I and an LIET address (e 4 1) for event 4 on layer 1 Note that events 3 and 4 of layer I are for event seeds 3 and 4 Fig 93 contains the example of Fig 91 following pass 3 As indicated at the end of pass 3, the BRIGHT program leaves in PNBOUT the values indicated at the right side of Fig 93.
The foregoing modules require five subroutines to call the OUTPUT and 10 DECODE I MODULES, cause information to be transferred between the MINI COMPUTER main memory and the MEMORY MODULE and to order the results of the BRIGHT program in the right order in outpout area PNBOUT in main memory.
Consider now an actual example of the operation of the PARSER, PIPE and 15 BRIGHT programs and their related subroutines Fig 79 C shows an actual example of the address pointer information for the layer 0 header, the layer 0 event pointer table (LOEPT) as well as the corresponding seed headers and the corresponding seed lines Fig 79 D shows the corresponding information for layer 1 Thus by way of example the layer 0 header contains four ( 4) words the first of which 20 contains address 100 which is an address pointer to the layer 0 event pointer table (LOEPT), the second word of which is the value 32 representing the width (number of possible occurrence values or event-times) in layer 0, the third word of which is the value 10 representing the number of the events in layer 0, and the fourth word of which is the value 30 which represents the highest event-time (clock tick) for 25 layer 0 The layer 0 event pointer table LOEPT has an address pointer for each of the 10 events in layer 0 and each such address pointer points to the corresponding event seed header To be explained in more detail, while constructing the data base as each new event is encountered in a data base layer it is assigned an event number Event numbers are assigned consecutive numbers in the order 30 encountered The event number is used to compute the offset into the LOET Thus, for example, the letter “I” has an event number value of 3 which when added to the base address 100 of the LOET gives address 103 for the event “I” Location 103 in turn contains an address pointer to base address 212 which in turn is the base address for the seed header for event “I” 35 Looking at the seed header for the beginning delimiter 6, the first word is the beginning address of the delimiter seed line, the second word is a value 0 identifying the line number of the iso-entropicgram for the corresponding seed line, the third word is a value 8 identifying the length in words of the delimiter seed line,.
and the fourth word is a value 8 identifying the number of actual occurrence values 40 in line 0 of the seed line (which in this case is the same as the content of the preceding location since it is assumed for the example that all seed lines are at line 0) For ease of explanation it is assumed that the non delimiter seed lines as well as the delimiter seed line are at line 0 of their corresponding iso-entropicgram, which need not be the 45 case.
Layers 0 and 1 of the data base, the example about to be explained, are depicted in Table 60 B It is assumed by way of example that layer 0 contains word entries 1 through 7 which are as follows: THIS IS A TEST, WHICH IS THE BEST, THIS IS BEST The words are grouped according to sentences which they so represent Table 60 B depicts the data base structure in binary form using a I to indicate the presence of actual occurrence values Thus, by way of example, the T event number 1 in layer 0 contains the actual occurrence values 1, 11, 14, 22, and 29 which are the same as those occurrence values depicted for the seed line T in Fig.
79 C It should further be noted that the entries numbers 1, 2, 3, 4, 5, 6, and 7 on 55 layer 0 are the same event numbers on layer 1 of the data base.
The following general description of operation will be made with reference to the PARSER, PIPE and BRIGHT flow diagrams of Figs 80, 82 and 94 in order to provide the reader with a better understanding of the operation.
In the following example it is assumed that the requester has presented the 60 word layer 0 request K, BETTER i 6 as depicted in Table 60 C Refer now to the PARSER program flow of Fig 80 and consider the general sequence of operation for the example Upon entry into the PARSER program flow of Fig 80 it is assumed that the FORMATER program (to be described) has set the state of the machine as generally depicted, has stored values representing the request; 6 65 243 1,570,344 243 BETTER} 6 into main memory, and has set the input string pointer, R 4, to point to the beginning delimiter b of the request which has been stored in main memory and has set the main memory areas ESTAK and PNB OUT to null or 0, all as depicted in Table 60 C It is also assumed that the requestor has entered into the system a pipe width (PW) of 1, a pipe cutoff value (PCO) and 50 % and a brightness cutoff value 5 (BVCO) of 0 50.
During PAI of the PARSER program flow the beginning delimiter 6 is stripped from the request during PA 2 and it is detected that this is a beginning delimiter} 6 thereby indicating a word request Control then goes to PA 4 of the flow where the software length switch LNGSW is set to 1 to indicate that the actual 10 word BETTER is desired and not some other word which contains that request word In addition the ESCAPE flag is set to I in order to cause the PARSER program to terminate its operation after processing data base layer 0.
If the initial character has been a sentence delimiter # this would have indicated a sentence request in process and therefore control would have gone to 15 PA 3 following PA 2 where the length of the request in software register RLNI would have initialized to 0 and a word delimiter 1 S, which always follows the sentence delimiter, would have been bypassed Continuing with the example, JOINI, JOIN 2 and PA 5 of the flow are entered following PA 4 During PA 5 the layer 0 request length in software register RLNO is initialized to 0 so that it can be 20 used to count the length of the request word in characters Operation then passes through JOIN 3 to PA 6 where the first non delimiter character “B” is obtained.
During PA 7 the current character “B” is checked to see whether it is a sentence delimiter # Since it is not, PA 8 is next entered where the same character is checked to see whether it is a word delimiter b Since it is not, PA 9 of the flow is 25 entered where the layer 0 event number 9 for “B” (See Table 60 B) is added to the base address 100 from the layer 0 header ‘for access to the LOET (see Fig 79 C).
Address 109 of the LOET contains the base address 236 of the seed header for event “B” Accordingly, during PA 9 the LOET pointer 236 is stored in main memory area ESTAK During PA 10 the layer 0 request length RLNO is increased by 1 to the 30 value 1 indicating that one non delimiter value of the request has now been stored in ESTAK.
The EXIT flag is used to indicate that the LOET pointers for all events in the request have been stored into ESTAK The 1 state of EXIT indicates this has occurred, whereas the 0 state indicates that it has not At this point the EXIT flag is 35 0 and accordingly operation loops back to JOIN 3 of the PARSER program and the operation from there on is repeated where the LOET address pointer 224 for the event “E” is stored into the next sequential location in ESTAK This same operation is repeated for the request events TTER, building up the LOET pointers depicted for ESTAK in Table 60 D 40 Finally during PA 6 the ending delimiterb’is obtained and hence during the subsequent entry to PA 8 is detected, causing PA 11 of the flow to be entered.
During PA II the EXIT flag is set to 1 and subsequently detected during PA 13, causing PA 14 of the PARSER program flow to be entered.
At this point in the operation the main memory locations and pointers in the 45 system are as generally depicted in Table 60 D Thus ESTAK contains the LOET pointers for the data base events BETTER, software register RLNO contains the value 6 identifying the number of LOET pointers in ESTAK and the PNBOUT is still null Further, the input string pointer R 4 is pointing at the ending delimiter}o 6 of the request 50 During PA 14 of the PARSER program flow, the PIPE program is called To be explained in more detail hereinafter, the PIPE program performs the piping function and forms results which are passed to the BRIGHT program After the operation of the PIPE program has completed, the main memory and P/B MEMORY areas contain the information depicted at Table 60 E 55 The BRSW switch is set by the PIPE program if inexact retrieval is to be performed (i e, if BRIGHT is to be scheduled) For the example being described, BRSW switch is now 1, indicating that the BRIGHT program is to be called to perform the brightness function Accordingly PA 17 of the flow is entered where the BRIGHT program is called To be explained in more detail, the BRIGHT program 60 calls the operation of the hardware BRIGHTNESS MODULE and generates a list of two value pairs in PNBOUT of the main memory The first of each pair is an entry number (E) and the second is a brightness value (BV) corresponding to the entry number Also to be explained in more detail, the two value pairs are ordered in the order of brightness value with the best or highest brightness value being given 65 244 1,570,344 244 first In the example being described, PNBOUT only contains a single entry since only one entry in layer 0 has met the brightness cutoff (BVCO) criterion The address of area PNBOUT is contained in the first of a two word area called PNBPTR The second of the two word area is referred to as PNBCNT and contains a value identifying the number of entries stored in PNBOUT during the BRIGHT 5 program operation.
If the BRIGHT program is not to be called, BRSW will be 0 during PA 15 this will occur when an exact hit has been found on layer 0 in a request string pertaining to layer 1 BRIGHT need not be called if an exact hit is found on layer 0 and the response is to be made from layer 1 This is so since only the “best” hit on layer 1 is 10 taken as an event on layer 1 and it is known that one can do no better than an exact hit Whe BRSW is 0 during PA 15, PA 16 is entered where the top of stack pointer for ESTAK, R 3, is adjusted to point to the top of stack entry prior to the last entry processed If B RIGHT is not called, the entries must be removed from ESTAK In the particular example, the pointer R 3 will be adjusted past the pointer to the seed 15 header for the first event in the request “BETTER”.
Continuing with the example, consider the operation during PA 18 During PA 18 the ESCAPE flag is found to be 1 and accordingly PA 23 is entered where the context of the machine is returned to that existing when the PARSER program was called and the operation of the PARSER program is exited leaving the main memory 20 area in the condition depicted in Table 60 F ESCAPE is set in PA 4 if this is a word request It is set in PA 12 if this is a sentence request.
If during PA 18 the ESCAPE flag has not been set to 1 and is therefore 0, it would indicate that entries in data base layer 0 were found that passed the brightness cutoff (BVCO) criterion but that a sentence layer 1 request had been 25 made by the requestor If this occurs an LIET address pointer for the “best” event seed header is placed in ESTAK and the request length software register for layer I (RLNI) is incremented during PA 19 through PA 22 Control then returns to JOIN 2 where the operation repeats.
If the response is to be from layer I the system checks word-by-word for the 30 “best” events on layer 1 These events are the result of PIPE/BRIGHT on layer 0.
Once all of the words in the request have been processed, there are a series of “best” words on layer 1 These are used to locate the best sentence request.
With the general operation of the PARSER program in mind, consider the operation of the PIPE program making reference to the PIPE program 35 flow of Fig 82 The purpose of the PIPE program is to examine the poper layer in the data base to find candidates for a response to a request out of the data base If an exact hit is found on layer 0, i e, the request matches exactly an entry on layer 0, but a layer I request has been made, there is no need for the BRIGHT program to be called The “best” response has already been 40 found With these general comments in mind, consider in more detail the operation of the PIPE program.
The configuration of the main memory prior to calling of the PIPE program is depicted in Table 60 D for the example under discussion The PIPE program begins during Pl 1 by saving the context of the registers in the MINI COMPUTER At P 12 45 a check is made of the status of the layer 1 switch Ll SW which will be set at PA 12 of the PARSER program if an ending sentence delimiter has been detected, thereby indicating a layer I request is being processed In the example under consideration a layer 0 request is being processed and accordingly LlSW is 0 and therefore control goes from PI 2 to P 13 of the PIPE program flow During P 13 and 50 PI 4 of the flow, the address pointer 200 to the seed header for the layer 0 delimiter is obtained and stored into register RO; the iso-entropicgram width value 32 of data base layer 0 is obtained and stored in storage area HW of main memory and the request length software register RLN is set to 6 which is the request length of layer 0 (RLN 0) 55 It should be noted at this juncture that the operation at PI 5 and P 16 is similar to that during P 13 and PI 4 except that the corresponding information is stored for layer.
At PI 7 the OUTPUT subroutine is called causing the seed line of the delimiter to be revolved back to its input line 0 and the resultant line 0 is stored into one of 60 the three areas of the MEMORY MODULE In the example given, the delimiter seed line is already at its input line 0 and accordingly the hybrid coded value representing the occurrence values 30, 25, 21, 15, 10, 8, 5, 0 are stored into one of the MEMORY MODULE areas The area in which the line 0 of the delimiter is stored is identified by register OAR in the OUTPUT MODULE During P 18 the 65 245 1,570,344 245 246 1,570,344 246 delimiter line 0 is transferred from the MEMORY MODULE into main memory area DAREA During P 19 the FIRST bit in the STATUS register of the DPM INTERFACE MODULE is set to 0 which will subsequently cause the hardware PIPE MODULE to initialize itself upon first call During P 110 the MINI COMPUTER register R 4 is set so that it points to the end of ESTAK which 5 contains the LOET pointer address 236 for the event “B” Register R 4 will act as a pointer during processing of ESTAK moving from LOET 236 (“B”) to LOET 240 (“R”).
The top of stack pointer R 3 will remain unchanged The condition of ESTAK and the R 4 pointers is depicted at Table 60 G.
JOIN 2 and Pl 11 are entered where the OUTPUT subroutine is again called 10 this time causing the non delimiter seed line for the event identified by the pointer R 4 (see Table 60 G) to be revolved back to its line 0 and stored into one of the three MEMORY MODULE areas Since each of the seed lines in the example is already at line 0, the line is unchanged In the example, R 4 is now pointing to the LOET pointer 236 for event “B” and accordingly the MEMORY MODULE now contains 15 the event occurrence vector for 26 in hybrid code.
During PI 12 a check is made to see if line 0 of the event now being processed (current event) is in MEMORY MODULE area 1 and if so, Pl 13 1 is entered To be explained in more detail the MEMORY MODULE area will be identified by the value in main memory area WOAR If line 0 for the current event is not in 20 MEMORY MODULE area 1, control goes to P 113 where line 0 of the current event seed is transferred to main memory area WAREA and then to MEMORY MODULE area 1 If this is the last event to be processed, the LAST bit is set in the DPM INTERFACE STATUS register ( 13 2).
Continuing with the example, during PI 14 line 0 of the delimiter is transferred 25 to MEMORY MODULE area 2 so that it can be-read and decoded by the DECODE II MODULE as described above This is one of-the steps in initializing the hardware PIPE MODULE.
During PI 15 the IPRF of the DPM INTERFACE MODULE is initialized by storing the physical 1 of the current event “B” into LNI; by storing the physical 30 length 8 of the delimiter} into LN 2; by storing the value 1 representing the pipe width into PW: and by storing the length of the request 6 into LNRQ.
During P 116 the operation of the PIPE MODULE is called When the operation is complete, the condition is detected during P 117 and P 118 is entered.
For the example being discussed, the content of the MEMORY MODULE areas 35 and the P/B MEMORY, upon completion for the event “B”, is as detected in Table H Thus MEMORY MODULE area I contains the biased occurrence value 26 and ara 2 contains the occurrence value of the delimiter for layer 0, whereas the P/B MEMORY area 2 contains in sequence a biased occurrence value 26, a number of hits value 1 (for biased occurrence value 26), and an end of field marker 40
1 During Pl 18 the ESTAK pointer R 4 is adjusted so that it points to the next tolast LOET as depicted in Table 601 The “E” event on layer 0 of the data base is about to be processed.
During P 121 a check is made to determine if there are more entries in ESTAK to be processed, by comparing the top of ESTAK pointer R 3 with the pointer R 4 If 45 they are equal, no more entries are to be processed and P 122 is subsequently entered In the example they are unequal, as more entries are to be processed, and accordingly the false exit is taken back to JOIN 2 and PI 1 1 of the flow The loop from PII 1 through P 121 is repeated for the event “E” in layer 0 of the data base.
Upon completion, the content of the main memory and P/B MEMORY area 1 are so depicted in Table 60 I Thus the P/B MEMORY area 1 contains biased occurrence values 26, 23 and 11 each followed by its corresponding hit count Additionally the ESTAK pointer R 4 is adjusted to the LOET pointer 224 for the event “T” and since this is not the last event, operation loops back to JOIN 2 and PII 1 through P 121 This looping operation is repeated until each event in ESTAK has been 55 processed When during P 113 1 the last event in ESTAK is detected, P 113 2 is entered where the LAST flip flop in the STATUS register is set to 1 Subsequently during PI 21 no nore entries are detected and P 122 is entered At this point the main memory and the MEMORY MODULE area 3 are as depicted in Table 60 J.
As indicated in Table 60 J there are seven entries in layer 0 MEMORY MODULE 60 area 3 will contain a center pipe value for each entry which contains a hit along with an indication of the number of hits at the corresponding center pipe For those entries in layer 0 which do not contain a hit, the center pipe value is replaced by so indicating Thus, with reference to Table 60 J, center pipe hit values were found at center pipe 26 for entry 7, center pipe 21 for entry 6, center pipe 12 for entry 4, 65 whereas the remaining entries do not contain hits for the request word “BETTER”.
Additionally the ESTAK pointer R 4 now points to the address which is one above that of the first LOEPT pointer in ESTAK If the number of hits value following the center pipe value is 1, it indicates that the request has been found exactly in layer 0 of the data base This condition is not found in the example 5 During the remainder of operation of the PIPE program a discrimination function will be applied to the information developed by the PIPE MODULE To this end the possible responses which pass the piping cutoff value PCO will be formed and sent to the BRIGHTNESS MODULE.
During P 122 et seq of the PIPE program, if a number of hits value (NH) is 10 found which is negative, indicating that an exact match is found between the request and an entry in the data base, and a layer 1 request has been made, it is unnecessary to perform brightness since an exact match has been found Consider this and other operations during the PIPE program operation that follows.
At P 122 the PNBPTR register is set so that the PNBOUT list is null or zero, 15 and the MINI COMPUTER registers A 2 AD and M 3 AD, which are address pointers to the P/B MEMORY and MEMORY MODULE area 3 in the DPM system, are initialized to 0 In addition the value 8 representing the number of occurrence values in line 0 of the delimiter seed line is stored into register NOC and decremented by I so that it can be used as a pointer to the entries on layer 0 20 and hence to events on the next higher layer 1 Thus NOC now contains a pointer to the 7th entry in layer 0 and hence the 7th event on layer 1 which is for the word “BEST” Further, the BRCNT pointer is initialized to 0 so that it can be used to count the number of entries which subsequently need to be processed by the BRIGHT program 25 Subsequently, JOIN 5 and P 123 are entered and the first center pipe value 26, the number of hits value 4 are read from MEMORY MODULE area 3 and stored into software registers OV and NH During P 124 it was found that the center pipe value 24 is greater than 0 and therefore control goes to P 125 During P 125 the number of hits value is found to be greater than 0 and accordingly P 129 is entered 30 During P 129 the number of hits value 4 is compared with the pipe cutoff value of 3 and is found to be greater Therefore P 130 is entered where the center pipe value 26 is stored into P/B MEMORY area 1 This occurs because the number of hits value 4 is greater than the pipe cutoff value 3, indicating that the word “BEST” in the data base is a possible candidate for a response to the request and therefore must be 35 processed by the BRIGHT program.
Backing up to P 125 momentarily, if the number of hits value NH is negative (less than 0), indicating an exact hit, P 126 is entered where the ESCAPE flag is checked If ESCAPE is 1, indicating that a response is expected from the layer currently being processed, all responses, exact and inexact, which are above the 40 brightness cutoff value BVCO and are now being processed, are to be returned to the requestor Thus P 128 is entered where the center pipe value (OV) is written to the P/B MEMORY and the BRCNT software register is incremented by I to keep track of the number of values stored into the P/B MEMORY If the ESCAPE flag is 0, thereby indicating the response is expected from the next higher layer 1, it is 45 unnecessary to call the BRIGHT program because the corresponding part of the request has been found exactly If the response is from the next layer, all that is required from this layer is the “best” hit An exact hit is the “best” hit.
Thus during P 128 and P 130, center pipe values are writtefi into the P/B MEMORY which, as will be described, are passed to the BRIGHT program for 50 processing Subsequently, JOIN 9 and P 131 of the flow are entered During PI 31 the entry counter NOC is decremented from 7 to 6 to cause the next lower numbered entry “THE” on layer 0 to be processed During PI 32 the state of the entry counter NOC is checked and since it is not 0, the operation loops back to JOIN 5 et seq, causing the entry “THE” to be processed in the manner discussed 55 above to this end the next two values are read from MEMORY MODULE area 3.
Thus the center pipe value 21 and the number of hits value 2 are read (see Table J) At PI 24 the center pipe value 21 is greater than 0 and therefore P 125 is entered During P 129 the number of hits value 2 is less than the pipe cutoff value 3 and therefore control goes directly to JOIN 6, JOIN 8 and JOIN 9 to PI 31, 60 bypassing P 130 This action is taken since the word “THE” in the data base does not pass the piping cutoff value 3 and therefore the corresponding center pipe value 21 is not sent to the BRIGHT program for processing During P 131 the entry counter NOC is decremented by 1 to 5, corresponding to the entry 5 on layer 0.
With reference to Table 60 J it will be seen that entry 5 contains a center pipe 65 247 1,570,344 247 1 and a number of hits value 0, indicating that the current entry word “WHICH” now being processed has no letters in common with the request Therefore during P 124 the negative center pipe value is noted and JOIN 9 is entered by passing P 125 through PI 30 Therefore the PIPE program does not cause anything to be stored in the P/B MEMORY corresponding to entry 5.
The PIPE program continues in the loop of JOIN 2 through PI 32 until every entry in the layer being processed has been checked Upon completion the entry pointer NOC will be counted down to 0 for the example under consideration When this occurs the main memory and the P/B MEMORY will be as depicted in Table 60 K Thus the P/B MEMORY will contain the center pipe values 26 and 12 and end 10 of field marker 1 The center pipe 26 and 12 corresponding to the data base words “BEST” and “TEST” will be the only ones to be processed by the BRIGHT program.
Consider now the general operation of the BRIGHT program for the example.
The BRIGHT program calls the operation of the BRIGHTNESS MODULE The is B RIGHTNESS MODULE computes the brightness value for each entry which has been passed to it by the PIPE program Those entries whose brightness values are higher than the brightness cutoff value (BVCO) are placed in an ordered list in main memory called PNBOUT along with the corresponding brightness value (BV) and then are returned to the requester The main memory and P/B MEMORY area 20 configurations of interest prior to the call on the B RIGHT program are depicted in Table 60 K.
Consider now the operation of the BRIGHT program as depicted by the flowdiagram of Fig 94 During B Rl the context of the PARSER program is saved so that the PARSER program can be reentered following the BRIGHT program 25 During BR 2, loop registers are initialized so that each event in the data base corresponding to the request will be processed To this end the content of the software register RLN which contains the value 6, representing the number of entries 6 in the request, is stored into register LNRQ in the IPRF of the DPM INTERFACE MODULE JOIN 1 and BR 3 of the flow are entered where the software OUTPUT 30 subroutine is called The OUTPUT subroutine forms line 0 of the non delimiter event seed identified by the ESTAK pointer R 4 (less 1) Initially the ESTAK pointer R 4 identifies the LOEPT pointer 240 and hence when decreased by I identifies LOEPT pointer 224 corresponding to the event “B” Line 0 formed during BR 3 will be referred to as the current seed 35 Line 0 of the current seed then is formed by the OUTPUT subroutine in a MEMORY MODULE area Thus, the MEMORY MODULE area will contain the occurrence value 26 corresponding to the event “B” on layer 0.
BR 4 is entered where a check is made to make sure that the line 0 of the current seed has been stored into MEMORY MODULE area I and if it is not, B R 5 40 is entered where it is transferred to area 1.
During BR 6 the length of line 0 of the current seed for event “B” which is 1 is moved into LNI of the IPRF in the DPM INTERFACE MODULE Additionally, the value 8 representing the length of the word delimiter is moved to LN 2 of the IPRF Control then goes to BR 7 where the line 0 of the word delimiter is moved to 45 MEMORY MODULE area 2 from DAREA in main memory During BR 8 the hardware BRIGHTNESS MODULE is called for “B” entry 7 After the BRIGHTNESS MODULE completes its operation the P/B MEMORY area 2 contains the values indicated in Table 60 L.
AT BR 9 a check is made to determine if the operation is completed If not, 50 control returns to BR 3.
To this end during BR 9 the state of the ESTAK pointer R 4 is compared with the tot of stack pointer R 3 and since all information in ESTAK has not yet been processed, they are unequal, causing control to return to JOIN 1 Similar to the description above for the event “B”, the event “E” is processed during the repeat 55 loop through JOIN 1 through BR 9 Thus the line 0 representation of the seed line for event “E” is generated and stored in MEMORY MODULE area 1 during BR 4 and BR 5 and the length values 3 and 8 are moved into the IPRF during BR 6 Line 0 of the delimiter is moved into MEMORY MODULE area 2 during BR 7 During BR 8 the BRIGHTNESS MODULE is again called causing the results depicted in 60 Table 60 M to be formed in the P/B MEMORY area 1 Since all entries in ESTAK have not been processed and R 4 is not yet equal to the top of stack register R 3, control again returns to JOIN 1 This operation continues with the loop being repeated until all entries in ESTAK have been processed When all entries in ESTAK have been processed and the ESTAK pointer R 4 is equal to the top of 65 248 1,570,344 248 249 1,570,344 249 stack pointer R 3 BRI 2 et seq is entered The contents of the P/B MEMORY area 3 are then as depicted in Table 60 N Thus the P/B MEMORY area l will contain delimiters 25 and 10 corresponding to the beginning delimiters for entries “BEST” and “TEST” in layer O of the data base Following each beginning delimiter will be, in order, the number of hits for the corresponding entry (N), the 8 ( 8min) value and 5 do value for the corresponding entry The results of the hardware BRIGHTNESS MODULE now contained in the P/B MEMORY area l depicted in Table 60 N are now used to compute a brightness value BV and to order the results of the brightness process.
The number of the entry corresponding to the first four brightness values in 10 the P/B MEMORY area 1 is now determined To this end during BRI 3 the event counter NOC is set to 7 indicating that the BRIGHT program is processing entry 7 on layer O corresponding to the entry “BEST” At BRI 4 the DECODE I MODULE is called causing it to load the ending delimiter occurrence value 30 into software register TD 2 During B R 15 the first four brightness values are read from 15 P/B MEMORY area I and are stored into software registers in the MINI COMPUTER These registers and the values now contained therein are as follows:
Dl = 25 N = 5 S = 5 20 DO = 28 During B R 16 the beginning delimiter occurrence value (next in order) is read from line O of the delimiter seed and stored into software register TD 1 At this juncture software register TD 2 contains 30 and software register TD I contains 25 and the length of the corresponding entry, entry 7, is now computed by taking the 25 diference therebetween The result, a value 4, is stored into the software register LS.
During B R 17 the delimiter in register TD 1 is compared to the beginning delimiter 25 stored in register Dl from the P/B MEMORY area 1 and found equal because they are for the same entry Since they are equal, control goes to BRI 9 30 where the computer converts the values now stored in the software registers into floating point notation During BR 17 through BR 22 the scatter value S depicted in equations 8 and 9 (see p 371) is computed as follows:
At BR 20, VI is computed:
Vl =(RLN-N)RLN+D O 35 =( 6-5) 6 + 28 = 34 BR 21:
V 2 =DO-S = 28-4 40 = 24 BR 22:
Vl = V 2/VI = 24/34 = 0 706 45 Thus, following BR 22 the scatter value S is as depicted at Vl above.
250 1,570,344 250 During BR 323 the state of the LNGSW switch is checked The length of the request is to be taken into effect and since the LNGSW is 1, therefore the length factor L shown at equation 11 must be taken into account Accordingly BR 25 is entered where the DEL value corresponding to DELTA in equation 11 is found to be 2 With reference to equation 11 it will be seen that if the DELTA value is 5 smaller than the length of request value LNRQ, the upper equation in equation 11 is to be used to determine the length factor L Accordingly, BR 27 is entered where the following computations take place:
L = (a (DEL/RLN))3 = I ( 0 63 ( 2/6))3 10 = 1 ( 2079)3 = 991 Control then goes through JOIN 6 and JOIN 27 to BR 29 where the final brightness value BV is determined as follows:
BV =LVl 15 = 706 991 =.699 The brightness cutoff value BVCO was set to 0 50 by the requestor During BR 30 the brightness value BV computed during BR 29 is compared against the brightness value cutoff value BVCO and since the former is larger, the entry now 20 being processed passes the brightness cutoff value Therefore, BR 31 is entered where the value 7 corresponding to the current entry (NOC = 7) is stored into main memory area PNBOUT followed by the brightness value 0 699 During BR 32, BRCNT which identifies the number of entries in the P/B MEMORY area 1, is reduced from 1 to 0 Since BRCNT is 0 and not less than 0, control returns through 25 2.1 to JOIN 4 and the loop back through BR 32 where the next four brightness values for beginning delimiter 10 are processed from P/B MEMORY area 1 in the manner described above The brightness value BV for the entry corresponding to the begining delimiter 10 in Table 60 N is 4620 Hence during B 230 it is found that this value is less than the brightness value cutoff value BVCO and 30 therefore BR 3 l is skipped, BR 32 and BR 33 being entered directly Thus an entry value corresponding to beginning delimiter 10 (see Table 60 M) is not stored into PNBOUT because its brightness value does not pass the brightness cutoff value originally set by the requestor When BR 33 is subsequently entered it is found that it has now been reduced to less than 0 and 35 therefore B R 34 is entered and the operation of the BRIGHT program is exited At this point the contents of main memory are as depicted at Table 600.
B FORMATER PROGRAM Appendix B -9 is a program listing for the FORMATER program Fig 102 C is a flow diagram for the FORMATER program the blocks of the flow diagram are 40 identified by the symbols Fl to F 9 The relationship between the flow diagram of Fig 102 C and Appendix B -9 is indicated in Appendix B -9 where, on the left hand side, the symbols Fl to F 9 are shown alongside the corresponding listing.
Consider now the operation of the FORMATER program, with reference to the FORMATER program flow diagram of Fig 102 C The Data Base program 45 causes the FORMATER program to be called First, Fl of the FORMATER program flow is entered where the context is saved similar to that described hereinabove and the software flag ENDFLG is cleared or reset to 0 Operation then passes through JOIN 10 to F 2.
During F 2 the FORMATER program calls the operation of the PRINTR 50 subroutine which outputs to the printer a carriage return character, a line feed character, and an asterisk The carriage return causes the carriage to reset to the beginning of a line and the line feed causes the roller to set the paper to a new line.
The asterisk is displayed by the printer telling the requestor that the system is ready to accept the rest of the request (the blank is used simply to separate the asterisks 55 251 1,570,344 251 from the requestor’s request) CRLFA indicates to the PRINTR routine that it is a string of length four (blank) F 3 is now entered and the requestor types the first request character at the operator console During F 3 the FORMATER program calls the operation of the 5 GETC subroutine which in turn reads the character typed by the requestor at the typewriter.
During F 4 a comparison is made to see whether the character just obtained from the typewriter is a sentence delimiter (#) If the comparison is false, i e, the character is not a sentence delimiter, F 5 is entered where the same character 10 is compared to see if it is a word delimiter If the comparison in F 5 is false and therefore the character is not a word delimiter, F 6 is entered This sequence of steps through F 4 and F 5 indicates then that the character is not a sentence delimiter (#) nor a blank (b) and therefore the request character identifies a command To this end, F 6 is entered 15 During F 6 the FORMATER program calls the operation of the COMMAND subroutine The COMMAND subroutine determines whether a meaningful command is being presented or whether there is an error Following F 6, F 8 is entered.
Return now to F 4 and assume that the comparison was true, indicating a 20 sentence delimiter (v#) has been typed by the requestor Under these conditions, JOIN 20 and F 7 are entered.
During F 7 the REQUEST subroutine is called This occurs because, if the first character is a sentence delimiter (#), then the following characters which are to be typed by the requestor are the request characters Note that if during F 5 the 25 comparison is true, and hence a word delimiter b is detected, JOIN 20 and F 7 are sequentially entered where again the characters entered on the typewriter following the word (A) delimiter are processed Following F 7, JOIN 30 and F 8 are entered.
During F 8 a check is made to see whether the ENDFLG flag has not been set, 30 i.e, is 0, indicating that the requestor has not reached the end of his request If ENDFLG is not set, it indicates that the user does not wish to end this session and therefore JOIN 10 and F 2 are reentered and the operation continues as described above.
When the requestor reaches the end of his request he types an “END” 35 command The END command causes the COMMAND subroutine (see F 6) to set ENDFLG to a 1 state When this occurs and the 1 state of the ENDFLG is detected during F 8, F 9 is entered where the context of the program is restored and the FORMATER program is exited.
C PARSER PROGRAM 40 To be explained in more detail the REQUEST program forms coded signals in a main memory area PSTRING The coded signals represent the request entered by the requestor on the typewriter and are in the form depicted in Table 60 The delimiters 6 and # are in ASCII code The letters in between delimiters have been converted to layer 0 event numbers depicted in Table 60 B PSTRING is processed 45 by the PARSER program moving from the beginning delimiter to the end delimiter in PSTRING The register R 4 always contains the address of the layer 0 event in PSTRING which is to be processed by the PARSER.
The PARSER program converts the information in PSTRING to ESTAK.
ESTAK is an area in main memory and the PARSER program stores a layer event 50 pointer (LXET) (see Figs 77, 78 A and 78 B) in ESTAK for each of the non delimiter characters in PSTRING and also stores a value representing the number of LXE Ts in ESTAK into software register RLNO The PIPE and BRIGHT programs are then called by the PARSER program causing PNBOUT to be formed PNBOUT is depicted at 2211 for the layer 0 request of Fig 102 A and 2233 for the layer I request 55 of Fig 102 B and contains a series of two value pairs, the first of which is an event number (E) and the second of which is a corresponding brightness value (BV) Only those two value pairs with a brightness value exceeding the brightness cutoff value (BVCO) are stored in PNBOUT.
Table 59 is a list of the hardware and software flags and registers and main memory areas used for the PARSER program.
Appendix B I is a program listing of the PARSER program Figs 80 and 81 form a flow diagram of the PARSER program The symbols P Al through PA 22 identify the boxes used in the flow diagram The correspondence between the 5 program listings and flow diagram is illustrated to the left in the program listings where the symbols for blocks of the PARSER program flow are shown.
Consider now the organization of the PARSER program with reference to the flow diagram of Figs 80 and 81 Initially, the PARSER program is called by the REQUEST subroutine (see R 27, Fig 106) causing PAI’ of the flow to be entered 10 During PA l’ the MOV instructions store the content of the hardware registers RO, RI, R 2, R 3 and R 4 of the MINI COMPUTER into reserved memory locations for future recall to these registers after the PARSER program operation completes.
This is referred to at PA 1 ‘ as SAVE CONTEXT This enables the machine to return to the same place in the REQUEST subroutine from which the PARSER program 15 was called In addition, the software flags Ll SW, ESCAPE, BRSW, are all reset to 0 as designated by the CLR instructions Additionally, the MOV # ESTAK, R 3 instruction causes the beginning address of ESTAK to be moved into hardware register R 3.
During PAI, the MOV instruction causes the beginning delimiter of the 20 request in PSTRING pointed to by the hardware register R 4, to be placed in hardware register R 2 and the address in register R 4 is incremented one address to the address for the next request character in PSTRING.
During PA 2, determination is made of whether the first request character in register R 2 is a word delimiter 6 If so, PA 4 of the flow is entered If it is not a word 25 delimiter 6, it must be a sentence delimiter #, and accordingly PA 3 is entered To this end, the CMP instruction causes the request character in register R 2 to be compared with the 15 value in software register WDEL and the instruction BEQ causes a branch on equal to PFI of the PARSER program listing, which causes PA 4 of the flow to be entered 30 If a word delimiter, 6, is detected this means a word, layer 0, request is being made If a sentence delimiter, #, is detected, this means a sentence, layer 1, request is being made.
Assume a sentence delimiter # is detected during PA 2 and therefore PA 3 is entered This will occur when a sentence, layer 1, request is made During PA 3 the 35 register RLNI is reset to 0, responsive to the CLR instruction Further, the word delimiter 6, which always follows the sentence delimiter #, is bypassed using the dummy instruction TST which in effect causes the request address counter to be counted up by 1, thereby skipping the word delimiter h Thus, the register R 4 now contains the address of the first non delimiter character of the request in 40 PSTRING The branch instruction BR causes a branch to JOIN 1 of the PARSER program thereby causing JOIN 1, JOIN 2 and PA 5 of the flow to be entered.
Returning to PA 2, assume a word delimiter b is detected and therefore PA 4 is entered following PA 2 This will occur when a layer 0 or word request is made.
Under these conditions the software length switch LNGSW is set to 1, to assure 45 that the BRIGHT program will take the length of the request into effect when determining a brightness value Specifically, setting the LNGSW switch to 1 will prohibit the BRIGHT program for retrieving words from the data base which contain the requested word as a part of a larger word For example, “funda ME Ntal” contains the word “MEN” exactly and hence the brightness value 50 for this word would be less than for the word “MEN” alone To this end the first increment instruction INC causes the LNGSW flag to be set to 1 In addition, the second INC instruction causes the ESCAPE flag to be set to 1 to assure that an exit will be taken from the PARSER flow after one word has been retrieved from the request, as there is only one word in a word layer 0 request 55 Note that JOIN 1 occurs immediately following PA 4 During PA 5, the CLR instruction causes the RLNO register to be reset to 0 thereby initializing it to its initial state The CLR exit causes the loop flag to be reset to 0, i e, closed.
Following PA 5, JOIN 3 and PA 6 of the flow are sequentially entered.
During PA 6 the MOV instruction causes the next layer 0 event number of the 60 request in PSTRING specified by register R 4 to be stored into hardware register R 2 and the address in register R 4 is incremented to the address of the next layer 0 event number PSTRING PA 7 is next entered.
During PA 7, a check is made to determine whether a sentence delimiter # is now contained in register R 2 To this end the CMP instruction compares the value 65 252 1,570,344 252 in register R 2 with the sentence delimiter contained in software register SDEL and the “branch on not equal” instruction BNE causes a branch to PF 2 of the PARSER program and hence PA 8 of the flow, if a not equal condition is detected Otherwise PA 12 of the flow is entered.
During PA 8, since during PA 7 a sentence delimiter # was not found, the value 5 in register R 2 is either a word delimiter 6, or one of the non delimiter layer 0 event numbers of the request PA 8 determines which is stored in register R 2 To this end, the CMP instruction compares the value in register R 2 with the word delimiter stored in software register WDEL and the BNE instruction causes a branch to PF 3 of the PARSER program if a “not equal” condition is detected, whereas P All of 10 the flow is entered if an equal condition is detected.
PA 9 of the flow is entered if the current value in hardware register R 2 is not a sentence delimiter # or a word delimiter} 6 (see PA 7 and PA 8) Hence, during PA 9 the value in register R 2 represents a non delimiter character of the request The layer 0 event number in R 2 is a base relative address pointer for the layer 0 event 15 pointer table LOET (See Fig 78) Hence the base relative address pointer in register R 2 is added to the base address LOET to form an address in the layer 0 event pointer table LOET which contains the address pointer to the corresponding seed header The address of the seed header is then placed in the first memory location of ESTAK whose address is specified by the hardware register R 3 The value stored 20 in ESTAK is later used by the PIPE and BRIGHT programs To this end, during PA 9 the move instruction MOV LOET (R 2),-(R 3) causes the MINI COMPUTER to subtract 1 from the ESTAK address in register R 3 and then causes the value of the character in register R 2 to be added to the base address LOET to form an address in the layer 0 event pointer table LOET from which the address of the 25 corresponding seed header is obtained and stored in the memory location specified by the address in hardware register R 3 Thus the first location in ESTAK now contains the address pointer for the base of the event seed header, which event corresponds to the first non delimiter character of the request.
During PA 10 the increment instruction INC causes the software register 30 RLNO to be incremented by 1 to reflect the fact that one value is now stored in ESTAK.
JOIN 4, JOIN 5 and PA 13 of the flow are now sequentially entered.
Return now to PA 8 and assume that the value in R 2 is a word delimiterb This will be an ending delimiter PA 1 l of the flow is now entered During PA 1 l the INC 35 instruction causes the EXIT flag to be set to I and the JMP instruction causes a jump to JOIN 4 of the PARSER program EXIT being set to a I state indicates that the PARSER program is about to call on the PIPE and BRIGHT programs to process the content of ESTAK.
Return now to PA 7 and assume that the value in R 2 is a sentence delimiter # 40 indicating the end of a sentence layer 1 request Under these conditions PA 12 is entered where the EXIT flag is set to 1 to indicate that all non layer 0 event numbers in PSTRING have been converted to seed header address pointers and have been stored in ESTAK The ESCAPE software flag is also set to 1 to indicate that all of the events on layer 0 have been processed through PA 14-PA 19 If the 45 sentence delimiter is found, this means that all the words in the request have been processed through layer 0 Additionally the layer 1 decision switch L I SW is set to a 1 state which will subsequently cause the proper parameters to be moved into work registers when the PIPE program is called.
so Following PA 12, JOIN 5 and PA 13 of the flow are sequentially entered 50 During PA 13, the software flag EXIT is checked to determine whether it has been set to I or is at 0 To this end, the test instruction TST checks the EXIT flag and a branch on non equal instruction BNE causes a branch to PA 14 of the PARSER program if the EXIT flag is 1, whereas the JMP instruction causes ajump back to JOIN 3 if the EXIT FLAG is 0 Thus, PA 14 of the flow is entered if the 55 EXIT flag is 1, indicating that a complete request on layer 0 has been found and JOIN 3 is entered if the EXIT flag is 0, indicating that there are still more events in this request.
During PA 14, the PIPE program is called by the PARSER program causing it to perform its piping function on the events specified by the seed header address 60 pointers contained in ESTAK To this end the JSR R 5, PIPE instruction calls the PIPE program subroutine The operation of the PIPE program and the related PIPE hardware operation is discussed subsequently.
Following PA 14, PA 15 is entered where the BRSW software switch is checked to determine if it is in a 1 state, indicating that the BRIGHTNESS MODULE is 65 1,570,344 253 253 254 1,570,344 254 now to be called, or whether it is in a 0 state, indicating that the brightness operation is to be skipped Note that BRSW is reset to 0 by the PIPE program during P 127 to indicate if a call on BRIGHT is not necessary To this end, the test instruction TST checks the BRSW to see if it is 1, and if not, the instruction BEQ PA 16 causes PAI 6 of the flow to be entered, whereas, if the BRSW switch is 1, 5 PA 17 of the flow is entered.
RLN is a work register which is filled in the PIPE program (P 14, P 16) It contains the length of the current entry whether it be for layer 0 or layer I PA 16 of the flow is entered when the BRSW switch is 0 and the “best hit” is already in the software list PNBOUT The events for the current entry are “popped” from the 10 stack, ESTAK This operation is effected by the ADD RLN, R 3 instruction which causes the number of events in this entry to be added to R 3 which effectively erases them from ESTAK.
Following PA 16, JOIN 6 and PA 18 of the flow are sequentially entered.
Return now and assume that PA 17 of the flow is entered During PA 17 15 the JSR R 5, BRIGHT instruction calls the BRIGHT program The branch instruction BR causes JOIN 6 of the PARSER program to be entered following the end of the BRIGHT program.
The BRIGHT program forms the information in PNBOUT depicted at 2213 of Fig 102 A for a word layer 0 request and depicted at 2233 of Fig 102 B for a 20 sentence layer I request Therefore when PA 18 is entered and ESCAPE is 1, PNBOUT contains a series of two value pairs the first of which is an event number (E) and the second is a brightness value (BV) Only those events whose brightness values exceed the brightness cutoff value (BVCO) appear in PNBOUT.
During PA 18 a test is made on the ESCAPE flag To this end, the test 25 instruction TST checks to determine whether the ESCAPE flag is a I or a 0 If the ESCAPE flag is a 1, the result of the test is true and PA 23 of the flow is entered.
The ESCAPE flag will be set to a I in PA 12 when an ending sentence delimiter has previously been detected in PA 12, or when a layer 0 request has been made (in PA 4) When this occurs the brightness value has been computed for the layer of the 30 request Thus if a layer 0 request, the brightness value will be on layer 0 and if a layer I request, the brightness value will be on layer 1.
PA 23 causes the context of the MINI COMPUTER to be restored to the REQUEST program and causes a set up of the output parameters To this end the MOV instruction, associated with registers RO through R 4, causes the content of 35 these registers, which was saved during P Al’, to be restored to the same registers.
The MOV # PNBTR,R O instruction causes the beginning address of the two word memory area PNBTR to be stored into register RO Subsequently the PARSER program exits.
Return to PA 18 and assume that the branch on not equal instruction BNE 40 detected that the ESCAPE flag is 0 and hence the test TST detected a false condition Under these conditions PA 19-PA 22 of the flow is entered PA 19 checks PNBCNT to see if it contains a non 0 value and hence whether an entry was computed above the brightness cutoff value (BVCO) If none was found, control goes to PA 20 where an event number for the null seed is stored in R 2 This is done 45 since an entry was not found which corresponds closely to anything in the data base However to maintain the relative positions of the events in the request a null seed event number is entered into the request If, however, a “best” entry has been found the event number is moved from PNBTR to R 2 at PA 21 At PA 22 such event number (layer 0 entry number or layer 1 event number) is used to locate the corres 50 ponding layer I event header address from LI ET which is stacked on ESTAK The length of the layer 1 request (RLNI) is incremented and control returns to JOIN 3.
D PIPE PROGRAM At the time the PIPE program is called, ESTAK in main memory contains a layer event pointer (LXET, see Fig 77) for each non delimiter character in the 55 entry Each LXET pointer is a base address to the corresponding seed header The LXET pointers are arranged in the same order as the request was presented In addition the software register RLNO or RLNI contains a value identifying the number of LXET pointers contained in ESTAK.
It will be recalled that the PIPE program is called at PA 14 (see Fig 81) of the 60 PARSER program Briefly, the PIPE program forms a two value pair in MEMORY MODULE area 3 for each entry in the layer of the data base at which the request is made With reference to final output for the hardware PIPE MODULE in Table 11 and Table 60 J it will be seen that the two value pairs are (I) vi-a center pipe value 255 or a minus if there are no hits in the entry, and ( 2) vii-the number of hits in the pipe or a minus if the request has been found to be present exactly.
When the requestor composes his request he not only types in the beginning and ending delimiters along with the non delimiter characters as depicted in Table 60, but in addition enters commands which set the pipe width value (PW), pipe 5 cutoff value (PCO), and the brightness cutoff value (BVCO) used by the PIPE and BRIGHTNESS MODULES as described above The pipe width (PW) is the one used by the PIPE MODULE in determining the number of hits within each pipe.
The pipe cutoff value (PCO) is used by the PIPE program to determine those centerpipes and hence entries which have hit counts meeting the criteria specified by the 10 pipe cutoff value (PCO) In other words the PIPE program selects those data base entries which have hit counts which are equal to or greater than the pipe cutott value (PCO) selected by the requester The center pipe values which have hit count values equal to or exceeding the pipe cutoff value (PCO) are stored in the P/B MEMORY for future processing by the BRIGHT program 15 The assembly language listing of the PIPE program is set forth in Appendix B-2 To aid in the understanding of the overall operation of the PIPE program, Table 61 includes a list of the hardware and software flags, registers and memory areas used for the PIPE program.
Consider now the details of the PIPE program flow as set forth in Figs 8284 20 Figs 82-84 contain a flow diagram for the PIPE program using symbols Pl IP 135 to identify the various flow blocks Labels for the PIPE flow diagram are shown at the left hand side of the PIPE program listing to show the relationship therebetween.
The PIPE program is called during PA 14 of the PARSER program flow (see 25 Fig 81) During PII of the PIPE program flow, the MOV instruction causes the context of the RO to R 4 registers to be saved so that they can be restored when the PIPE program exits back to the PARSER program.
During P 12, the state of the LI SW software flag is checked If the L I SW flag is in a 0 state it indicates that the request on layer 0 is being processed and accord 30 ingly P 13 and P 14 are entred, whereas if the LISW flag is in a l state it indicates that a layer l request is in process, and P 15 and PI 6 are entered LISW is set during the PARSER program PA 12 when the ending sentence delimiter is sensed.
The general purpose of P 13 through P 16 is to load the hardware and software registes RO, LPTR HW and RLN with the values corresponding to the layer which 35 will be processed during the rest of the operation of the PIPE program To this end, if a layer 0 request is being processed and the LISW flip flop is in a 0 state, PI 3 is entered where the instruction MOV @ LOPTR,R O causes the address located at the base of the layer 0 event table (address of base of delimiter seed header) to be stored in register RO and the instruction MOV LOPTR, LPTR 40 causes the address LOET at LOPTR to be stored in software register LPTR During P 114 the two MOV instructions cause the iso-entropicgram width value (HW) contained in register HWO to be stored into register HW and cause the value in RLN O representing the number of LOET pointers, now contained in ESTAK, to be stored into software register RLN The operation during P 15 and P 16 when a layer 1 45 request is processed causes the corresponding parameters for layer 1 to be loaded into registers RO, LPTR, HW, and RLN.
Following PI 4 or PI 6, JOINI is entered and a subsequent operation takes place using the initial parameters just loaded during P 13 and PI 4, or P 15 and P 16.
During P 17, the PIPE program calls the operation of the OUTPUT program 50 causing it to output the delimiter for the layer designated by the content of registers RO, LPTR, HW and RLN The OUTPUT program revolves the delimiter from its seed line to line 0 of its iso-entropicgram To this end the first MOV instruction causes the address DOAR (beginning of a memory area called DOAR) to be loaded into register RI Referring to Fig 86 the first word of memory area DOAR will store a 55 number value identifying the MEMORY MODULE area which contains the outputted delimiter The second word of DOAR will store a value identifying the physical length of the delimiter seed line in words Note that register RO now contains the address of the base of the seed header for the delimiter An area called DAREA or DOAR will receive line 0 of the revolved delimiter of the seed line 60 The instruction JSR R 5,OUTPUT calls the operation of the output program causing the seed line of the delimiter to be revolved back to the input or line O of its iso-entropicgram To be explained in more detail, the OUTPUT program calls the operation of the OUTPUT MODULE and when its operation is complete its register OAR contains the number of the MEMORY MODULE area containing 65 1,570,344 255 the delimiter and its register OLN contains the physical length of the delitniter The content of registers OAR and OLN are transferred by the OUTPUT program into software registers DOAR and DOLN.
The instruction MOV 6 (R 0),DNOC causes the content of the fourth location in the delimiter seed header to be stored into software register DNOC With 5 reference to Fig 77 the fourth location contains the number of occurrences (or l’s) in the delimiter line 0 The number of occurrences is saved in DNOC for future use in the PIPE program.
During P 18, line 0 of the delimiter is moved into DAREA (see Fig 86) To this end, the first MOV instruction causes the address of the beginning of area DAREA 10 to be stored into register R O and the jump to subroutine instruction JSR R 5,DPMMEM calls the operation of the DPMMEM program causing the content of the MEMORY MODULE area specified by DOAR (which contains line 0 of the delimiter) to be stored into DAREA of the main memory.
Briefly, when DPMMEM is called the following values exist in registers RO, 15 RI.
RO-contain address of area to which transfer is to be made.
Rl-contain the address of a two word area containing i the memory area containing line 0 of seed, ii the number of words (physical) to be transferred 20 The JSR routine transfers control to the DPMMEM routine which accomplishes the actual physical transfer.
During P 19, the FIRST bit in the STATUS register of the DPM INTERFACE MODULE is set and this is accomplished by storing the literal FIRST which is the octal number 10008 (see Appendix B-21 CONSTANTS DEFINED BY 25 FORMATER PROGRAM), into the STATUS register, responsive to the first MOV instruction of P 19 As a result the FIRST bit in the STATUS register is set to I and all of the rest of the bits in the STATUS register are set to 0 The MOV # l,BRSW instruction causes the BRSW software flag to be set to 1 thereby indicating that the BRIGHT program is to be called after the PIPE program has 30 completed To be explained in more detail hereinafter, the B RSW flag maybe reset to 0 thereby preventing the call on the BRIGHT program depending on future conditions encountered during the PIPE program.
N PIP 10 is a housekeeping operation during which the pointer register R 4 is set to the address of the first LXET address pointer in ESTAK which is to be processed 35 ESTAK is formed on a last-in-first-out basis and therefore the register R 3 contains the address of the last LXET pointer stored into ESTAK The instruction MOV R 3, R 4 causes the top of stack pointer address to be copied from register R 3 to register R 4 so that register R 4 now contains the address of the last LXET pointer stored in ESTAK Due to the action during P 13 and P 14 or P 15 and P 16, software register 40 RLN now contains the number of LXET pointers in ESTAK Accordingly, the instruction ADD RLN, R 4 causes the number of LXET pointers contained in register RLN to be added to the end of stack pointer in register R 4, adjusting the value of the pointer in R 4 so that it now contains an address which is one higher than the address containing the first LXET pointer stored in ESTAK 45 Referring to Fig 87 the main memory area WOAR is the base address of an area in main memory known as WOAR Address WOAR will receive a value identifying the MEMORY MODULE area where line 0 of an event seed is stored.
The second address of WOAR will store the value identifying the physical length of the seed in words (computer) and WAREA is an area where line 0 of the event seed 50 is to be stored WOAR is set by the OUTPUT program.
The first LXET pointer in ESTAK is the pointer to the event seed header for the first non delimiter character of the request presented by the requestor The.
purpose of Pl 11 is to revolve the event seed for the first LXET pointer, on ESTAK back to line 0 of its iso-entropicgram which is referred to as outputting the current 55 event To this end the first MOV instruction depicted during P 111 causes the address in register R 4 to be counted down 1 so that it now contains an address pointer to the first LXET pointer in ESTAK and the result is transferred to register RO The second MOV instruction depicted during PII 1 causes the address of WOAR (see Fig 87) to be loaded into register RI Similar to that described with 60 reference to P 17, the jump to subroutine instruction JSR depicted during PI 11 causes the OUTPUT subroutine to be called to revolve the event seed line identified by the LXET pointer in register RO back to its line 0 Thus at the end of Pl I l, one of the MEMORY MODULE areas contains the line 0 of the event seed corresponding to the first LXET pointer in ESTAK 65 1,570,344 256 256 PI 12 and Pl 13 assure that line 0 corresponding to the first event seed is in MEMORY MODULE area 1 as is required for the operation of the PIPE MODULE To this end, during PI 12 a check is made to see if the resultant line 0 of the event seed is contained in MEMORY MODULE area 1 Specifically, the compare instruction CMP compares the literal I with the number of the 5 MEMORY MODULE area contained in WOAR (see Fig 87) If the value in WOAR is 1, the result of the comparison is true and the branch on equal instruction BEQ causes a branch to JOIN 3 of the flow If, on the other hand, the result of the comparison is not true, and hence is false, PI 13 of the flow is entered.
During P 113, line 0 of the event seed line is transferred from whatever MEMORY 10 MODULE area in which it is contained, to MEMORY MODULE area 1 To this end the first MOV instruction of PI 13 causes the address pointer to WAREA to be transferred to register RO and the jump to subroutine instruction JSR causes line 0 of the event seed to be transferred to WAREA of main memory The second MOV instruction causes the literal value 1 to be stored into main memory location 15 WOAR the address of which is contained in register Rl The final jump to subroutine instruction JSR causes line 0 of the event seed contained in main memory to be transferred back to MEMORY MODULE area 1.
Pl 13 1 and 13 2 of the flow are used to determine if the last entry of the request contained in ESTAK is about to the processed and if so, the LAST flip flop in the 20 STATUS register of the DPM INTERFACE MODULE is set to 1 during PI 13 2.
To this end, during PI 13 1, the compare instruction CMP causes the current stack pointer in R 4 (which is being decremented during PI 10) to be compared with the top of stack pointer in R 3 and if the comparison is equal or true, the last event in ESTAK is about to be processed and P 113 2 is entered During P 113 2 the literal 25 LAST is stored into the STATUS register which in effect causes the LAST bit thereof to be set to 1 and all other bits to remain at 0 Following PI 13 2, PI 14 is entered The purpose of setting the LAST bit in the STATUS register is to cause the hardware PIPE MODULE to complete its operation on the next call If the result of the comparison during P 113 1 is not equal or false, then P 114 is entered 30 directly.
During P 114, line 0 of the delimiter, which was stored in main memory area DAREA during P 118, is transferred to MEMORY MODULE area 2 as is required for the operation of the MEMORY MODULE To this end, the first two MOV instructions during PI 14 cause the addresses of areas DAREA and DOAR to be 35 transferred to registers RO and Rl, respectively The third MOV instruction causes the literal value 2 to be stored in the memory location DOAR (see Fig 86) specified by the address in register Rl The jump to subroutine instruction JSR causes the MINI COMPUTER and MEMORY MODULE to move line 0 of the delimiter from DAREA to MEMORY MODULE area 2 40 During PI 15 the following values are moved from main memory into the indicated registers in IPRF of the DPM INTERFACE MODULE:
WOLN (physical length of the seed of current event) to LNI of the IPRF; DOLN (physical length of the seed of the delimiter) to LN 2 of IPRF; PW (pipe width) to PW of IPRF; 45 RLN (length of request) to LNRQ of IPRF.
It will be recalled in connection with the discussion of the DPM INTERFACE MODULE that the register AI determines which one of the IPRF registers into which information is to be transferred from the DATAO register It will also be recalled that the value 6 in register AI selects register LN I Accordingly, the MOV 50 #6, AI instruction causes the constant value 6 to be stored into register AI and the following MOV WOLN, DATAO instruction causes the content of WOLN to be stored into LN 1 of the IPRF It will also be recalled that the AI register increments itself after each instruction that references it This will cause words sequentially stored in the DATAO register to be stored in the L 1, L 2, PW and LNRQ registers 55 of the IPRF in the order presented in the DATAO register Each subsequent MOV instruction causes the value in register AI to be incremented so that it selects the next register in IPRF.
Accordingly, the following MOV instructions during P 115 cause the contents of DOLN, PW and RLN to be stored into the LN 2, PW and LNRQ registers of the 60 IPRF.
During PI 16, piping is performed by calling the operation of the PIPE MODULE in the manner discussed hereinabove The MINI COMPUTER causes 257 1,570,344 257 258 1,570,344 258 the operation of the PIPE MODULE to be called by storing the appropriate instructions into the STATUS register of the IPRF To this end, the ADD DPM + P 1 PGO, STATUS instruction causes the literals DPM and PIPGO (see Appendix B-21 CONSTANTS DEFINED BY FORMATER PROGRAM) to be added together resulting in the octal value 204 and the result is stored in the 5 STATUS register This causes the PIPE MODULE to be called, using line 0 of the delimiter stored in MEMORY MODULE area 2, line 0 of the event seed contained in MEMORY MODULE area 1, and the other necessary inputs depicted under the PIPE MODULE in Table 11 1 Finally the PIPE MODULE forms in MEMORY MODULE area 3 a series of two value pairs of the type noted under final output in 10 Table 11 One set of two value pairs is formed for each event in the layer being processed.
During the operation of the PIPE MODULE the program causes the MINI COMPUTER to continue checking to see whether the PIPE MODULE function is complete This is accomplished by the instruction BIT, BDONE, STATUS which 15 causes the flag BDONE in main memory to be compared against the STATUS register for equality When equality is detected, i e, the PIPE MODULE has completed its operation and has set the DONE flip flop in the STATUS register, PI 18 of the flow is entered.
During Pl 18 the MOV instruction causes the STATUS register to be reset to O 20 P 119 and P 120 do not occur in the PIPE program flow.
During PI 21 a test is made to see if there are any more entries left in ESTAK to be processed Assume that only the first event or LXET pointer in ESTAK has been processed Accordingly, if there is more than one LXET pointer in ESTAK, the test during PI 21 will fail and the PIPE program will branch back to JOIN 2 of 25 the flow where the operation during PI 11 through P 121 will repeat for the next LXET pointer in ESTAK.
The test during PI 21 is performed responsive to the compare instruction CMP which causes the current stack pointer R 4 to be compared with the top of stack pointer R 3 If the result of the comparison is true, P 122 of the flow is then entered 30 If the result of the comparison is false, then the JMP instruction is executed, causing JOIN 2 of the flow to be reentered.
JOIN 5 et seq of the flow is the analysis phase of the PIPE process At this point in time MEMORY MODULE area 3 contains a two value pair for each entry in the layer of the data base being processed (see Fig 60 J) One of the two values is 35 a center pipe value OV and the other is a hit value (No of hits) (NH) During the following analysis phase of the operation, the two value pairs are checked to see if the hit value of each pair passes (is equal to or greater than) the pipe cutoff value PCO The first of the two values, namely the center pipe value, is stored in the P/B MEMORY area I if its hit value passes the pipe cutoff value 40 The DPM INTERFACE MODULE will be reading and writing from different MEMORY MODULE and P/B MEMORY locations at different times Therefore it is necessary to keep pointers of these memory locations A pointer M 3 AD points to the addresses in MEMORY MODULE area 3 from which reading is to take place, whereas a pointer A 2 AD points to the addresses in the P/B MEMORY into 45 which writing is to occur The center pipe value and hit value for each entry are transferred out of the MEMORY MODULE area 3 from the locations specified by the pointer M 3 AD and only those center pipe values whose hit value passes the pipe cutoff value PCO are written back into the P/B MEMORY location specified by the address in A 2 AD It should also be noted that PNBOUT is the area in main 50 memory which contains the output list following the end of the BRIGHT program.
With reference to Fig 88 A, PNBPTR is a base address pointer to a two word area whose second location is PNBCNT The first word in PNBPTR is a base address pointer to the area PNBOUT and the second word stores the number of entries in PNBOUT Consider now the actual operation during PI 22 in which the 55 various address registers are initialized The MOV #PNBOUT,R 4 instruction causes the address of the area PNBOUT to be transferred from PNBPTR to register R 4 The move instruction MOV@LPTR,R 2 causes the content of the memory location specified by the address in LPTR to be moved to register R 2.
LPTR is a software register that contains the base address of the LXET layer 60 pointer table Accordingly, the pointer to the seed header for the corresponding delimiter is moved to register R 2 The move instruction MOV 6 (R 2),NOC causes the number of occurrences in the delimiter line to be moved from the third word of the delimiter seed header to register NOC NOC is a software counter that identifies the entry number of the layer being processed The DEC instruction 65 258 1.570,344 258 causes the pointer in NOC to be counted down by 1 so that it now effectively identifies the last (right most) entry in the layer The clear instruction CLR causes the A 2 AD,M 3 AD and BRCNT registers to be reset to 0 To be explained in more detail, the BRCNT register keeps track of the number of entries written to the P/B MEMORY for future processing by the BRIGHT program 5 During P 123, one of the two value pairs vi, vii is read from the MEMORY MODULE area 3 and stored into software registers OV and NH respectively in readiness for the subsequent test to determine if the corresponding hit value passes the pipe cutoff value To this end the MOV #30,STATUS instruction causes the ml, m 2 bits of the STATUS register in the DPM INTERFACE MODULE to be set 10 to 1,1 causing a read from the MEMORY MODULE area 3 The MOV M 3 AD,Al instruction causes the Al register in the DPM INTERFACE MODULE to be loaded with the address contained in the software register M 3 AD In this connection it will be noted that M 3 AD will contain a 0 value if P 123 directly follows P 122, whereas a non 0 value if P 123 is entered following P 132 The first value vi of 15 the two value pair is read out of the MEMORY MODULE area 3 and stored into the DATAI register in the DPM INTERFACE MODULE The instruction MOV DATAIOV causes the value vi to be transferred from the DATAI register to the software register OV and causes the address in register Al to be incremented by 1.
The MEMORY MODULE provides the next value vii of the pair, and this is stored 20 into the DATAI register The instruction MOV DATAI,NH causes the value vii to be transferred from the DATAI register to the software register NH in main memory and causes the address in register Al to be incremented by I so that it now contains the address of the vii value for the next two value pair in MEMORY MODULE area 3 The ADD #2,M 3 AD instruction causes the address in register 25 M 3 AD to be incremented by 2 so that it now contains the address of the vi for the next entry in MEMORY MODULE area 3.
During P 124, the value vi contained in register OV is checked for a negative value If negative (see Table 11 under Final Output of Pipe Module), it indicates that the entry is not worth looking at or passing to the BRIGHTNESS MODULE 30 because there are no hits in the data base for this center pipe value Under this condition, JOIN 9 of the flow is next entered, skipping the intermediate boxes P 125 through P 130 of the flow If, on the other hand, the value vi in OV is not negative, PI 25 is next entered.
During P 125 the value vii contained in software register NH is tested to 35 determine if it is a negative value If it is a negative value it indicates that there is an exact hit for the entry in question and P 126, P 127 and P 128 of the flow are entered.
If the value vii is not negative, P 129 and P 130 are entered.
Consider now the condition where during P 125, it has been detected that the number of hits value in NH is negative During P 126 the ESCAPE 40 flag is checked to see if it is 1 or 0 The ESCAPE flag is a 1 if the system is presently processing the data base layer for which the request was made Assume that the machine is processing at the layer of the request and therefore the ESCAPE flag is 1 An exact hit has been found and therefore P 128 is entered The value vi in OV is a center pipe value and is transferred to the P/B MEMORY where 45 it is saved and the B RCNT counter, which tallies the number of writes made to P/B MEMORY area 1, is incremented by I and A 2 AD is incremented by I so it points to the next write address in P/B MEMORY.
To this end during PI 28, the instruction MOV 10 + PBM,STATUS causes the octal constant 10 to be added to the octal value PBM and the resultant value is 50 stored in the STATUS register thereby causing a write to the P/B MEMORY The subsequent two MOV instructions cause the address in register A 2 AD to be transferred to register AI of the DPM INTERFACE MODULE and the center pipe value to be transferred from the software register OV to the DATAO register of the DPM INTERFACE MODULE The DPM INTERFACE MODULE in 55 conjunction with the P/B MEMORY then causes the center pipe value in OV to be stored into the address in the P/B MEMORY specified by the register AI The INC instructions cause the instructions in software registers A 2 AD and BRCNT to be incremented by 1.
Return now to P 126 and assume that during the test on the ESCAPE flag it was 60 found to be 0 and therefore that layer 0 is being processed whereas the request is for layer 1 of the data base PI 27 is then entered.
P 125, PI 26 and PI 27 are entered when an exact hit has been detected Under these conditions it is unnecessary to perform the brightness function on the corresponding entry To this end, during PI 27 and CLR BRSW instruction causes 65 259 1,570,344 259 the software flag BRSW to be reset to 0, indicating that it is unnecessary to call the BRIGHT program At this point the address in register R 4 contains the address of a location in PNBOUT The instruction MOV NOC,-(R 4) causes the number of the entry now being processed to be transferred from register NOC to the main memory location specified by the address, less one, in register R 4 Fl is a constant 5 whose value is 1 0 The instruction MOVF FI,-(R 4) is a floating point move instruction which causes the value at Fl to be stored into the next sequential location in PNBOUT indicating a 100 % brightness factor This is required since an exact hit has been detected at P 125.
The instruction MOV #l,BRCNT causes BRCNT to be loaded with the value 10 1 This indicates one hit has been found and that is all that is necessary.
The instruction INC PNBCNT causes the register PNBCNT to be incremented by 1 to indicate one additional entry has been stored in PNBOUT.
Additionally the instruction CLR NOC causes the content of the software register NOC to be cleared to 0 to assure that there will be a loop exit at PI 33 15 Thus it will now be seen that if the value vii in NH is negative (an exact hit) and the data base layer corresponding to the layer of the request is being processed (ESCAPE = 1), the PIPE program will pass through P 125 and PI 26 to P 128 where the center pipe value is written from OV into the P/B MEMORY and the BRCNT software register is incremented by 1 to indicate a value has been written into the 20 P/B MEMORY If the value vii in NH is negative (exact hit) and the data base layer 0 is being processed, whereas a layer I request has been made (ESCAPE = 0) , then PI 27 is entered where the number of the event now being processed as designated by NOC and a 100 % brightness value are stored in sequential memory locations of the main memory area PNBOUT 25 Consider now the operation assuming that during PI 25 it was found that the value vii was not negative Under these conditions PI 29 will be entered following P 125 During PI 29 the value vi, which is the number of hits value, contained in software register NH is compared with the pipe cutoff value in software register PCO If the number of hits in register NH is equal to or greater than the pipe cutoff 30 value, P 130 -is entered where the corresponding center pipe is transferred from software register OV to the P/B MEMORY in the manner discussed with respect to P 128 and the BRCNT register is incremented by 1 to indicate another value has been written into the P/B MEMORY area 1, all as discussed hereinabove with respect to P 128 35 If during P 129 it was found that the number of hits in register NH is not equal to or greater than the pipe cutoff value, then P 130 is skipped and PI 31 is entered directly.
Software register NOC, an entry pointer for layer 0, is also an index pointer to events on the layer 1 During P 131 the software register NOC is decremented to 1 40 so that it contains the value of the next lower value entry number on data base layer 0.
During P 132, a test is made to determine whether register NOC has been reduced to a negative value, indicating that all events on layer 1 have been processed If the register NOC is not negative, indicating that all of the events on 45 layer 1 have not been processed, then JOIN 5 and the sequence of operations thereafter are repeated for the next entry on layer 0 and hence event on layer 1 and its corresponding two value pair vi, vii in MEMORY MODULE area 3 If during P 132 the test indicates that register NOC has been reduced to a negative value, indicating that all entries on layer 0 have been processed, PI 33 et seq are entered 50 During P 133 the value in software register BRCNT is checked to see whether the number of writes to P/B MEMORY area I value is O If it is O it indicates that no values have been stored in the P/B MEMORY and therefore none is to be passed to the BRIGHTNESS MODULE and accordingly PI 34 is entered where the BRSW software flag is reset to 0 to prevent the BRIGHT program from being called 55 Additionally, the address pointer PNBCNT to the PNBOUT memory area is reset to 0 and P 135 is next entered.
If during PI 33 it is found that the pointer BRCNT is not 0, then there are values in the P/B MEMORY area I which are to be passed to the BRIGHTNESS MODULE PI 35 is entered directly During P 135 the context of the hardware 60 registers RO through R 4 are restored and the operation of the PIPE program is exited and returned to the PARSER program.
A layer I request is handled in much the same fashion as a layer 0 request, one difference being at P 127 Other than that the difference in operation is transparent.
The way in which PIPE determines whether it is dealing with a layer 1 request as 65 260 260 1,570,344 opposed to a layer 0 request is by testing the layer 1 switch If L I SW is set, then the PIPE program initializes itself to point to the layer I descriptions, otherwise PIPE assumes it is dealing with a layer 0 request and so initializes itself.
Consider the operation during interrogation (pipe and brightness) andgeneration in a layer 1 request Briefly, the pipe and brightness functions are 5 performed on the data base for each word of the request The purpose is to locate those word entries in layer 0 of the data base which either exactly or most closely match the words of the request After piping and brightness has been performed for a particular word of the request, PNBOUT contains a series of layer 0 entry numbers and brightness values ordered in decreasing order of brightness value and 10 indicates the word entries in layer 0 and the degree of match between such word entry and the corresponding request word Subsequently, the LEPT corresponding to the best word entry (best brightness cutoff value) in PNBOUT, is stored in ESTAK After piping and brightness have been performed for all words of the sentence request thereon, ESTAK will contain an LEPT corresponding to the best 15 word entry on layer 0 for each word of the request The LEP Ts are in the same order as the corresponding request words.
* Piping and brightness are then performed on data base layer 1 During this process those event vectors which correspond to the LEP Ts in ESTAK are selected and interrogated using the piping and brightness processes Afterwards, PNBOUT 20 will contain a series of layer 1 entry numbers and brightness values ordered in decreasing order of brightness The best layer 1 entry number (best brightness cutoff value) in PNBOUT is then selected for the generation in the process of output.
The bias operation is discussed in connection with the PIPE and 25 BRIGHTNESS MODULES and is also% used during the piping and brightness operations on layer 1 In this connection, ESTAK contains the best LEPT for each word entry of the request and the LEP Ts are ordered in the same order in which the corresponding word entries occur in the request Similar to the piping and brightness on layer 0, a bias signal is formed for each entry of the request and hence 30 for each LEPT in ESTAK As the layer 1 vector signal corresponding to each LEPT is read out for processing, the event-times in such vector signal are added to the corresponding bias value to form biased event-time values As a result, piping and brightness operates on layer I in a much similar manner to that on layer 0 using the bias signals 35 E BRIGHT PROGRAM The BRIGHTNESS MODULE operates on the event seeds which the PIPE program has just processed Although the PIPE MODULE itself could determine those results of piping which pass the pipe cutoff value and then provide those values which pass to the BRIGHTNESS MODULE, the software performs this 40 function as described above The BRIGHT program determines those results found by the PIPE program to pass the pipe cutoff value and therefore to have been stored into the P/B MEMORY As explained above in connection with Table 11 under BRIGHTNESS MODULE final outputs, the BRIGHTNESS MODULE forms in the P/B MEMORY a set of four values for each entry in the data base 45 which has been passed by the pipe module, each of which in turn is used by the BRIGHT program software to determine a brightness value BV Consider now the actual operation of the BRIGHT program with reference to Fig 94 The status of the system is the same as it is at the end of the PIPE program (Table 60 E) Which layer is being processed should be transparent to the BRIGHT program 50 It should be kept in mind during the following discussion that only the PARSER program adds things into the top of ESTAK, whereas only the PIPE and BRIGHTNESS MODULES remove information therefrom.
BR 3-BR 9 Set up and perform the hardware BRIGHTNESS function.
BR 12-BR 23 Analyze the results of hardware BRIGHTNESS and save all 55 entries which surpass the brightness cutoff value (BVCO).
The following discussion will be given with reference to the BRIGHT program flow diagram of Figs 94, 95 and 96 which use BR 1-BR 34 to identify the various flow boxes The correspondence between the actual program listings and the blocks of the flow is shown by the BRIGHT program block symbols shown along 60 the left in the code.
The PARSER program calls the operation of the BRIGHT program during PA 17 (see Fig 81) When called, the BRIGHT program enters BRI of the flow 1.570344 261 2 M 1 where the context of RO, RI, R 2, R 3 and R 4 registers are saved for future reentry into the PARSER program.
During BR 2 the BRIGHT program flow initializes the loop registers, and the request length (number of non delimiter characters) contained in software register RLN is moved into LNRQ of the IPRF To this end, the instruction CLR resets the 5 register PNBCNT to 0 so that is can be used in counting the number of entries made into PNBOUT during the BRIGHT program operation The next MOV instruction sets the top of stack pointer from hardware register R 3 to R 4 The next ADD instruction causes the length of the request stored in software register RLN to be added to register R 4 so that R 4 now points at one address above the 10 beginning of ESTAK where the first LEPT of the request is stored The last three MOV instructions cause the FIRST flip flop and the AI register in the DPM INTERFACE MODULE to be set to 1 and 9, respectively A value 9 in register AI selects the register LNRQ of the IPRF in the DPM INTERFACE MODULE and the request length is transferred from software register RLN to LNRQ of the IPRF 15 During BR 3, the address in the stack pointer register R 4 is decreased by 1 so that it now points at the first LXET in ESTAK and the resulting stack address is stored in register RO, responsive to the first MOV instruction and at the second MOV instruction the content of WOAR (see Fig 87) is transferred to hardware register RI The memory location WOAR stores the number of the MEMORY 20 MODULE area where line 0 of an event seed (non delimiter seed) is stored The JSR instruction causes the OUTPUT subroutine to be called where the seed line specified by the address LXET in register RO is revolved back to its input line 0 and stored in one of the MEMORY MODULE areas Line 0 formed during BR 3 is referred to as the current seed line 0 25 During B R 4 a check is made to see if the current seed line 0 has been stored in MEMORY MODULE area 1 If it has, the value 1 will have been stored in software memory location WOAR and the CMP instruction will detect equality, causing JBR 6 to be entered If some other MEMORY MODULE area number has been stored in WOAR, the result of the comparison is false, and BR 5 will be entered 30 where, as explained with reference to the PIPE program, line 0 of the current seed will be moved to MEMORY MODULE area 1 Thus, when BR 6 is entered, the current seed line 0 will always be in MEMORY MODULE area 1.
During BR 6, line 0 of the delimiter seed is already contained in DAREA and the physical length of the delimiter is contained in memory location DOLN (see 35 Fig 86) As explained with reference to the PIPE MODULE, the first three MOV instructions during BR 6 cause a value representing MEMORY MODULE area 2 to be stored in memory location DOAR (see Fig 86), the address of location DOAR is moved to hardware register Rl, and the address of the beginning of memory area DAREA is moved to register RO The JSR instruction causes a jump 40 to the MEMDPM subroutine where the delimiter seed line 0 is moved to MEMORY MODULE area 2, under control of the content of DOAR, Rl and RO.
During BR 7 the physical length of line 0 of the current seed is contained in WOLN (see Fig 87) and the physical length of the delimiter seed is contained in register DOLN and are moved into registers LNI and LN 2 of the IPRF in the DPM 45 INTERFACE MODULE.
BR 7 1 and BR 7 2 are provided to determine whether the seed for the last LXET stored in ESTAK is about to be processed To this end, the content of top of ESTAK register R 3 is compared with register R 4 and if equal, i e, a true comparison is detected, BR 7 2 is entered where the LAST flip flop in the STATUS 50 register of the DPM INTERFACE MODULE is set to 1 and BR 8 is entered If the result of the comparison is not equal, indicating that the top of ESTAK register R 3 is not equal to R 4, BR 8 is entered directly.
During B R 8 the BRIGHT program calls the operation of the BRIGHTNESS MODULE, causing the performance of brightness and causing the clearing of the 55 STATUS register in the DPM INTERFACE MODULE With reference to Fig 89 and Table 11 under final output for PIPE MODULE, it will be seen that the P/B MEMORY now contains the two value pairs depicted in Fig 89 and Table 11 under PIPE MODULE final output In operation, during BR 8 the ADD instruction causes the constants DPM and BRGO to be added and the result stored in the 60 STATUS register of the DPM INTERFACE MODULE This causes the flip flops DPM and B RGO to be set, calling the operation of the hardware BRIGHTNESS MODULE, causing it to perform brightness, using the delimiter seed line 0 now stored in MEMORY MODULE area 2, using the current event seed line 0 (from the data base) now stored in MEMORY MODULE area 1, and the two value pairs 65 1,570,344 262 262 vi, vii stored in P/B MEMORY The BRIGHT program then performs the brightness operation and generates the four value results depicted in Table 11 under final output for BRIGHTNESS MODULE which in turn are stored in the P/B MEMORY In addition, during BR 8 the instruction BIT, BDONE,STATUS, causes the BDONE bit in the STATUS register to be monitored When the 5 operation of the BRIGHTNESS MODULE is complete, the BDONE flip flop is set to a I state indicating that the BRIGHTNESS MODULE has completed its operation The BEQ -l instruction is a loop back instruction that causes a loop back to the BIT instruction until the BDONE bit is set After the BDONE flip flop has been set, the MOV #0,STATUS instruction causes the STATUS register to be 10 reset to 0.
During BR 9 the CMP instruction causes the content of registers R 4 and R 3 to be compared and when equal, BRI 2 is entered If they are not equal it indicates that the current LXET pointer register R 4 has not yet been decremented to the top of stack address contained in register R 3 As a result there are more LXET pointers 15 in ESTAK to be processed and BR 3 is reentered following BR 9 The loop through BR 3-BR 9 continues until each LXET pointer in ESTAK and hence each of the corresponding event seeds has been processed, resulting in the sets of four values depicted under final output for BRIGHTNESS MODULE in Table 11.
When all LXET pointers in ESTAK have been processed and R 4 is equal to 20 R 3, B R 12 is entered With BRI 2 the BRIGHT program starts the computation of the brightness value BV This computation requires that the DECODE I MODULE provide the actual occurrence values from the delimiter line 0 contained in MEMORY MODULE area I (see Fig 89) To this end the MOV #1,DOAR instruction transfers to DOAR (see Fig 86) a value designating 25 MEMORY MODULE area 1 The MOV # DOAR,RI instruction causes the address of area DOAR to be transferred to register RI The MOV # DAREA,RO instruction causes the address of area DAREA to be transferred to register RO The JSR instruction causes a jump to the MEMDPM subroutine which actually transfers the delimiter seed line 0 from main memory via the DPM INTERFACE 30 MODULE to MEMORY MODULE area 1.
The following three MOV instructions cause the DPM INTERFACE register Al to be set to a 6, to select register LNI and causing the physical length of seed in DOLN (see Fig 86) to be transferred to register LNI The instruction MOV D l INIT,STATUS causes the D I INIT flip flop in the STATUS register to be set to a 35 I to thereby initialize the hardware DECODE I MODULE The instruction CLR AICNT causes the address pointer to the MEMORY MODULE area 3 to be set to 0, thereby allowing the memory locations of this area to be read, commencing with address 0, when the results of the BRIGHTNESS MODULE are processed.
During B R 13 the number of entries in the delimiter line 0 (DNOC) is moved 40 by the move instruction to the software register NOC and is reduced by one by the DEC instruction NOC now specifies the required number of calls to the DECODE I MODULE.
During BR 14 the operation of the DECODE I MODULE is called causing it to load a delimiter occurrence value into the software register TDI To this end the 45 instruction JSR R 5,DECODE I causes the DECODE I subroutine to be called and the resultant delimiter occurrence value is loaded into RO The subsequent MOV RO,TDI instruction causes the result from the DECODE I subroutine, namely, the beginning delimiter occurrence value, to be moved from register RO to TDI.
During BRI 5 the following operations take place which have generally been 50 discussed above with reference to the previous programs:
1 A value identifying the MEMORY MODULE area 3 from which the results of the BRIGHT MODULE operation are to be read is transferred to m l, m 2 of the STATUS register.
2 The address pointer to the current MEMORY MODULE area 3 address 55 contained in AICNT is transferred to address register AI and is subsequently incremented to point to registers N, S, and DO.
3 A set of four values generated by the BRIGHTNESS MODULE and now stored in the MEMORY MODULE area 3 are transferred to registers DI, N, S, and DO 60 4 The software address pointer AICNT is incremented by 4 so that it now points at the beginning of the next set of four values in MEMORY MODULE area 3 which are to be read during a subsequent entry to BR 15.
With reference to Table 11 under BRIGHTNESS MODULE final output, it will be seen that registers DI, N, S, and DO now contain, respectively, the beginning 65 1,570,344 263 263 delimiter of the corresponding entry, the number of hits N, Dmin, and d O.
It is now necessary to go through the delimiter occurrence vector in MEMORY MODULE area 1 and locate the delimiters defining the entry corresponding to the beginning delimiter in register DI The length of that entry will then be determined and stored into register LS To this end the MOV TD 2,TDI 5 instruction causes the beginning delimiter (if any) previously stored in TDI to be transferred from register TDI to TD 2 The JSR instruction causes a jump to the DECODE I subroutine which in turn calls the operation of the DECODE I MODULE, causing it to provide the next beginning delimiter into register RO The MOV ROTDI instruction causes the next beginning delimiter to be moved to 10 register TDI The following SUB instruction causes the current and previous delimiters in registers TDI and TD 2, respectively, to be subtracted and the result is stored in register TD 2 The instruction MOV TD 2,LS causes the difference to be stored in register LS and the following DEC LS instruction causes the difference in LS to be decremented by 1 to form the actual length of the entry 15 During BR 17 the current delimiter in register TDI and the beginning delimiter from the BRIGHTNESS MODULE contained in register DI are compared to determine if the DECODE I MODULE has reached (and hence the BRIGHT program is processing) the entry corresponding to the delimiter in register DI.
Recall the hardware BRIGHTNESS MODULE has only outputted the set of four 20 values (in registers DI, N, S and DO) for those entries that are of interest, as designated by the two value pairs from the PIPE MODULE.
The loop through BR 16, BRI 7 and BR 18 is to enable the DECODE I MODULE to spin down through the delimiter occurrence vector until the delimiter is found which is equal to the beginning delimiter in register DI which was 25 stored during BR 15 To this end, when the comparison indicates that the delimiter from the delimiter occurrence vector in register TDI is larger than the beginning delimiter from the BRIGHTNESS MODULE in register DI, B R 18 is entered where the NOC counter is decreased by 1 so that it contains a value identifying the next current entry whose beginning delimiter will be obtained from the delimiter 30 occurrence vector 1 When BRI 6 is reentered the next lower valued delimiter is provided from the delimiter occurrence vector by the DECODE I MODULE This operation continues until a delimiter is provided by the DECODE I MODULE which is equal to or matches the beginning delimiter in register DI in which case BRI 9 is entered 35 At this time the value in NOC identifies the number of the entry for the beginning delimiter in TDI.
During BR 19 the three floating point instructions LDCIF are executed The MINI COMPUTER disclosed herein includes a floating point module Registers ACO-AC 4 are hardware registers in the floating point package 40 The floating point instruction LDCIF ACO,RLN causes the length of request in register RLN to be converted to floating point form and transferred to hardware register ACO Similarly, the following two LDCIF instructions cause the floating point form of the request length in register RLN to be stored in register ACI and causes the number of hits value in register N to be converted to floating point 45 notation and stored in software register AC 2.
During BR 20 the value shown in the denominator of equations 8 and 9 in Section XVI, BRIGHTNESS MODULE, is determined To this end, the number of hits (N) in register AC 2 is subtracted from the length of the request (RLN) in register ACO and the difference is placed in register ACO The floating point 50 instruction MULF causes the length of request contained in register ACI to be multiplied times the difference value in register ACO and the result is stored into register ACO Thus the value NM = (LNRQ N) LNRQ has now been formed in ACO The floating point instruction LDCIF AC 2,DO causes the d O value (equation 8) to be transferred from hardware register DO to software register AC 2 and the 55 following instruction ADDF ACO,AC 2 to be added together and the result stored into register ACO Thus, register ACO now contains the value shown in the denominator of equation 8.
During BR 21 the term shown in the numerator of equation 8 is formed To this end, the floating point instruction LDCIF AC 3,S causes the dmin value formed by 60 the BRIGHTNESS MODULE to be converted to floating point form and stored in register AC 3 The next instruction SUBF AC 2,AC 3 causes the dmin value in register AC 3 to be substracted from the do value in register AC 2 and the difference is stored into register AC 2 Thus, register AC 2 now contains the value representing the numerator in equation 8 65 264 264 1,570,344 During Bl R 22 the value in register ACO representing the denominator is divided into the value in register AC 2 representing the numerator of equation 8 and the result is stored into register AC 2 Thus, register AC 2 now contains the actual scatter value S depicted in equation 8 in the BRIGHTNESS MODULE for the entry specified by register NOC whose beginning delimiter is stored in TDI 5 During BR 23 the length switch LNGSW is checked The length switch LNGSW may be set to 1 during the PARSE program to indicate whether length is to be taken into account in determining the brightness value BV (see equation 12 under section XVI BRIGHTNESS MODULE) Thus the two instructions depicted adjacent BR 23 cause the LNGSW switch to be checked for 1 and if 1, BR 25 10 through BR 28 are entered where the length factor L (see equation 12) is determined If the LNGSW switch is 0, then B R 24 is entered where the instruction BFX 7: LDCIF ACI,#l is executed causing a value representing a I to be stored into register ACI so that during the subsequent BR 29, a 1 is multiplied times the scatter value S in software register AC 2 15 When the L value for equation 8 stored in register ACI is the value 1, the resulting BV value formed during BR 27 is the same as scatter value S (see equation 8) stored in register AC 2.
Assume that the LNGSW switch is in a 1 state and BR 25 is entered During B R 25 the absolute value of the difference is taken between the actual length of the 20 request (RLN) in register ACI and the length of the data base entry -(LS) stored in register ACO and the result is saved into register ACO This value then represents the absolute value of the difference LNRQ-N which is the A value in equation 11 section XVI BRIGHTNESS MODULE The A value formed in register ACO is then divided by the LNRQ value transferred from register RLN to AC I, and the result is 25 cubed, thereby forming the value depicted in equation 11 To this end, the floating point instruction LDCIF ACO,LS causes the length of the data base entry contained in register LS to be converted to floating point form and stored in register ACO The instruction SUBF causes the 30 length of response (N) contained in register ACI to be subtracted from the length of the request (LNRQ) contained in register ACO and the result is stored into register ACO Thus, register ACO now contains the A (DEL value in program listing) depicted in equation 11 The instruction ABSF ACO causes the absolute value of the A value in register ACO to be converted to absolute form thereby converting to 35 positive form any negative values in ACO The instruction MOVF ACO,AC 4 causes the A value to be moved from register ACO to register AC 4 The instruction DIVF AG 0,AC 1 causes the length of request value stored in register ACI from RLN to be divided into the A value in register ACO and the result stored into register ACO The instruction MOVF ACO,AC 3 causes the result in register ACO to be copied into 40 register AC 3 and the following two MULF instructions cause the value to be cubed and the result stored in register ACO Thus, at the end of BR 25, the register ACO contains the value ( 3 depicted in equation 11 in terms of the program listing 45 3 (DEIJ\ During B R 26 the A value in register AC 4 is compared with the LNRQ value of equation 11 (RLN in program listing) contained in register ACI If the former is equal to or less than the latter, BR 27 is entered where the value depicted at the top of equation 11 is computed If the latter is larger, then B R 28 is entered so Consider now BR 27 where A (DEL) is equal to or less than LNRQ (see upper equation 11) The LDF ACI,ALPHA instruction causes the ca value, namely, 63, to be converted to floating point form and stored into register AC 1 The following two 1,570,344 265 265 MULF instructions cause the alpha value 63 to be cubed and the result is stored in ACI The instruction MULF AC 0,ACI causes the cubed alpha value in register ACI to be multiplied times the value contained in register ACO and the result is stored into register ACO The 5 instruction LDCIF ACI,#1 causes the constant value I to be converted to floating point notation and stored into register ACI The instruction SUBF ACI,ACO causes the value 3 V NR Q to be substracted from the value 1 in register ACI and the result is stored into 10 register ACI Following BR 27, BR 29 of the flow is entered.
Consider now the operation during BR 28 where the lower equation 11 is used (D > LNRQ) The instruction LDCIF ACI, #1 causes a 1 to be stored into register ACI The instruction DIVF ACI,ACO causes the I in register ACI to be divided by the value 15 in register ACO and the result is stored back into register ACI By this means the value L depicted for the lower equation 11 has been computed and stored into register ACI Thus, at JOIN 7, register ACI contains the value for the upper equation 11 if BR 27 was entered, whereas register A Ci contains the value L for the 20 lower equation 11 if BR 28 is entered.
During B R 29 the final brightness value BV is computed The equation for the value BV is depicted in equation 12 for section XVI of the BRIGHTNESS MODULE To this end, the length factor (L) is now contained in register ACI and the scatter value is contained in register AC 2 (S) Accordingly, the instruction 25 MULF ACI,AC 2 causes the two values to be multiplied together and the result stored into register A Cd The register AC 1 now contains the final brightness value BV.
During BR 30 a comparison is made between the brightness value BV and the brightness cutoff value BVCO If the brightness value is less than and hence below 30 the brightness cutoff value BVCO, BR 32 is directly entered without storing anything in the BRIGHT program output area PNBOUT If, on the other hand, during B R 30 it is found that the brightness value BV is equal to or greater than the brightness cutoff value BVCO, BR 31 is entered where the corresponding entry number in software register NOC and the brightness value are transferred, in 35 sequence, to the output area PNBOUT To this end the instruction JSR R 5,INSERT causes the INSERT subroutine to be entered which inserts the entry value (E) and brightness value (BV) contained in NOC and ACI into sequentially addressable locations of the area PNBOUT, as generally depicted by Fig 91.
Consider now the operation during BR 32 The software register BRCNT was 40 set by the PIPE program to identify the number of entries passed by the PIPE program to the BRIGHT program for processing Thus BRCNT will contain a value identifying the number of four value entries stored in MEMORY MODULE area 3 by the BRIGHTNESS MODULE Each time one of the four value entries in MEMORY MODULE area 3 is processed, the register BRCNT is decremented by 45 1 at BR 32 To this end the instruction DEC BRCNT decrements the value in register B RCNT.
During BR 33 a test is made to determine whether the value in register BRCNT has been decremented to 0 If it is greater than or equal to 0, then the BRIGHT program jumps back to JOIN 4 where BR 1 5 et seq is repeated for the next four 50 value entry in MEMORY MODULE area 3 Finally, when during BR 33, BRCNT is found to contain a negative value, BR 34 is entered where the context of register RO-R 4 are reset to return to the PARSER program Also the instruction ADD RLNR 3 causes the length of the request value stored in register RLN to be added to the content of the top of stack register R 3 which effectively pops or removes the 55 1,570,344 266 266 o 7 1,7,4 267 number of events from ESTAK which has just been processed Following B R 34 the operation of the BRIGHT program is exited.
F OUTPUT SUBROUTINE The OUTPUT subroutine is called by the PIPE program during P 17 and Pl 11 and by BRIGHT program during BR 3 and in turn calls the operation of the 5 hardware OUTPUT MODULE Generally, the OUTPUT subroutine requires, as input parameters:
1) an address pointer to the seed header which in turn contains the address of a seed line in MAIN MEMORY, which is to be revolved back to the O line of its isoentropicgram; 10 2) a pointer to a main memory area referred to as area DOAR for a delimiter or a pointer to area WOAR for an event The contents of DOAR and WOAR are depicted in Figs 86 and 87.
Appendix B-A contains the program listing for the OUTPUT subroutine Fig.
97 is a flow diagram illustrating the sequence of operation of the OUTPUT 15 subroutine and should be referred to in the following discussion.
During 01 of the OUTPUT subroutine operation the context of hardware register RO through R 4 of the MINI COMPUTER is saved for a return to the calling program.
During 02 the seed line (i e, delimiter seed line or event seed line) is 20 transferred to MEMORY MODULE area 1 When the OUTPUT subroutine is entered, hardware register RO contains the beginning address of a seed header and RI contains the beginning address of DOAR or WOAR depending on whether a delimiter seed line or non delimiter seed line is to be output Accordingly, during 02, the MOV 2 (R 0),R 2 instruction moves the third word in the seed header 25 (namely the number of occurrences in the corresponding seed line) to register R 2.
The instruction MOV #1 OSTATUS causes the ml, m 2 flip flops in the STATUS register of the DPM INTERFACE MODULE to be set to states 0,1 respectively, which designates that a write to MEMORY MODULE area 1 is about to take place The instruction MOV #O,AI sets the address register AI in the DPM 30 INTERFACE MODULE to 0, pointing to the first address in the MEMORY MODULE area 1, in which a write is to take place The instruction MOV (RO)+ ,R 3 moves the first word in the seed header (namely, the base address pointer to the seed line) to hardware register R 3 and counts up the address in register RO by 1.
The instruction MOV (R 3)+,DATAO, DEC R 2 and BNE -2 cause the DPM 35 INTERFACE MODULE to transfer the seed line via register DATAO toMEMORY MODULE area 1 into the locations specified by the addresses as in register AI.
The register R 2 contains the length of the seed in words The instruction DEC R 2 causes the value in register R 2 to be counted down by 1 each time a word has 40 been transferred from the seed to the main memory The instruction BNE -2 causes the MINI COMPUTER to branch back to the MOV instruction As explained above, the address register AI is incremented by 1 each time a word is transferred so that it contains the address of the next location in main memory into which a word is to be stored This is repeated until the length of the seed in register 45 R 2 has been counted down to O thereby indicating that all words have been transferred from the seed line in main memory to MEMORY MODULE area 1.
When register R 2 has been counted down to 0, 03 of the flow is entered.
During 03, the IPRF registers are initialized as follows:
TL HW 50 BL O IR O HW HW iso-entropicgram width LINE# seed line number LNI physical length of the seed 55 LN 2 O To this end the instruction MOV #O,STATUS causes the STATUS register to be reset to O and the instruction MOV #O,AI causes the address register AI to be reset to O thereby causing the MEMORY MODULE to be addressing the IPRF starting with register TL The following seven MOV instructions cause the 60 information indicated above to be transferred to the indicated registers in the IPRF in sequence.
I 1,570,344 267 267 268 1,570,344 268 During 04 of the flow the hardware OUTPUT MODULE is called To this end, the instruction MOV DPM + OMGO,STATUS causes the DPM flip flop to be set to 1 and the fi, f 2, f 3 flip flops to be set to a state selecting the DC 2 decoder outline line OMGO This in turn causes the hardware OUTPUT MODULE operation to be called as discussed in detail hereinabove The instruction BIT 5 BDONE,STATUS causes the MINI COMPUTER to monitor the BDONE flip flop in the STATUS register until it has been set to a 1, indicating that the output operation is complete, at which time 05 of the flow is entered The instruction BEO -I causes the MINI COMPUTER to branch back to the BIT instruction until BDONE is found to be 0 10 During 05 of the flow, the output parameters from registers OAR and OLN of the OUTPUT MODULE are transferred to the main memory of the MINI COMPUTER It will be recalled that the registers OAR and OLN, respectively, identify the MEMORY MODULE area containing the seed and the length of the seed line in words which seed line is now contained in the MEMORY MODULE 15 Thus the CLR STATUS instruction clears the STATUS register to 0 and the MOV #6,AI instruction causes the address register AI to be set to 6, thereby causing the MEMORY MODULE area number in register OAR of the OUTPUT MODULE to be coupled through the DATAI gate to I/O bus 1210 to the MINI COMPUTER.
The instruction MOV DATAI,(Rl)+ causes the value applied to the I/O bus 1210 to 20 be stored into the first of the two word memory area (of DOAR or WOAR) specified by register Rl and the content of register Rl is incremented by 1 The instruction MOV DATAI,(RI)+ causes the address in register AI to be incremented by 1 so that the length of the seed in register OLN of the OUTPUT MODULE is coupled through the DATAI gate to the I/O bus 1210 and the length 25 of seed line value is stored into the second word of the two word area specified by register Rl The address in register Rl is then incremented.
During 06 the content of registers RO through R 4 is then restored for reentry to the program which called the OUTPUT subroutine.
G MEMDPM SUBROUTINE 30 The MEMDPM subroutine transfers a seed line from the main memory of the MINI COMPUTER to a specified MEMORY MODULE The program listing for the MEMDPM subroutine is shown in the appendix and Fig 98 is a flow diagram illustrating the sequence of operation using flow boxes MDI-MD 7 Upon entering the MEMDPM subroutine the input parameters provided are as follows: 35 1 Register RO contains an address pointer to the main memory save area (DAREA for a delimiter seed or WAREA for an event seed) from which a transfer is to be made.
2 Register RI contains an address pointer to a two word save area (DOAR for a delimiter seed or WOAR for an event seed) 40 Figs 86 and 87 depict these relationships The PIPE (PI 8 Pl 13, Pl 14) B RIGHT (BR 5, BR 6, BR 12) programs call the MEMDPM subroutine When called, M Dl is entered where the context of the MINI COMPUTER registers RO through R 4 is saved for a return to the calling program.
During MD 2 the MEMORY MODULE area number and the physical length 45 of the seed are obtained from either the DOAR or WOAR two word save areas To this end the instruction MOV RO,R 2 causes the address pointer to the main memory save area (DAREA or WAREA, Figs 86,87) to be transferred from register RO to register R 2 The instruction MOV(Rl)+,R 3 causes the content of the so location in DOAR or WOAR specified by register Rl (namely, the MEMORY So MODULE area) to be transferred to register R 3 and the address pointer in register Rl is incremented by 1 so that it now points at the second of the two word store area (DOAR or WOAR) The instruction MOV(RI)+,R 4 causes the content of the location specified by RI (namely, the physical length of seed from DOLN or WOLN) to be transferred to register R 4 The bits specifying the MEMORY 55 MODULE area into which a transfer is to be made are stored at the least significant two bits of register R 3, whereas, with reference to Fig 53, it will be seen that the MEMORY MODULE area bits ml, m 2 are displaced three bits from the right hand end of the STATUS register The following three left shift instructions ROL cause the content of the register R 3 to be shifted three places to the left for 60 alignment with the STATUS register.
During MD 3 the STATUS register and the address register AI in the DPM INTERFACE MODULE are initialized To this end the MOV R 3,STATUS instruction causes the shifted word in register R 3 to be stored into the STATUS register thereby setting the mnl, m 2 bits to a state which selects the proper MEMORY M Ob ULE area Additionally the instruction MOV #0,AI causes a 0 to be stored into register AI thereby selecting address 0 of the MEMORY MODULE area specified by the STATUS register.
During MD 4 a word is transferred from the main memory of the MINI 5 COMPUTER to the MEMORY MODULE The word is stored at the MEMORY MODULE area specified by bits ml, m 2 in the STATUS register and at the location specified by the address register AI, both in the DPM INTERFACE MODULE The instruction MOV (R 2)+,DATAO causes the move to take place from the memory location of the seed area specified by register R 2 and the content 10 of register R 2 is increased by 1 for the next read.
During MD 5 the value representing the physical length of the seed contained in register R 4 is decremented by 1, reflecting the fact that one word has been transferred to the MEMORY MODULE During MD 6, the instruction BNE -2 causes a transfer back to JOIN 1 if the content of register R 4 has not been 15 decremented to 0 When the physical length in register R 4 has been decremented to 0, MD 7 is entered following MD 6 where the context of registers RO through R 4 is restored for reentry to the calling program.
H DPMMEM SUBROUTINE The DPMMEM subroutine is the complement of the MEMDPM subroutine 20 Specifically, the DPMMEM subroutine sets up and transfers data from a specified MEMORY MODULE area to a specified main memory area The initial parameters for the DPMMEM subroutine are as follows:
1 Register RO contains a base address pointer to the main memory save area (DAREA or WAREA) to which a transfer is to be made 25 2 Register Rl contains a base address pointer to the two word area (DOAR or WOAR) containing in the first word the number of the MEMORY MODULE area from which the transfer is to be made, and in the second word, the physical length of the field to be transferred in words.
The Appendix B contains the program listing for the DPMMEM subroutine 30 Fig 99 depicts the sequence of operation for the DPMMEM subroutine and identifies the flow blocks with the symbols DM l-DM 7 It will be noted that the sequence of operation is basically the same as for the MEMDPM subroutine depicted in Fig 98 except that during DM 4 the instruction MOV DATAI,(R 2) + causes a word to be moved from the specified MEMORY MODULE to the main 35 memory area specified by the address in register R 2 rather than the reverse.
Accordingly, the description will not be repeated.
I DECODE I SUBROUTINE The DECODE I subroutine calls the hardware DECODE I MODULE The operation of the DECODE I subroutine assumes that the hardware module has 40 been initialized prior to the first call The output from the DECODE I MODULE includes seven bits from register D Ol and positionally located at the most significant end is the 8th bit which is always 0, the output of the end of file flip flop EOFI Due to its simplicity the boxes of the flow are not labeled As long as the end of file flip flop EOFI is not set to 0, at least one more decoded occurrence value is 45 to be provided by the DECODE I MODULE However, as soon as nothing remains to be provided by the DECODE I MODULE, the EOFI flip flop is set to a 1 state.
The resulting 8 bit value is passed through the DPM INTERFACE MODULE to the MINI COMPUTER which interprets it as the end of the decoded data.
Consider now the operation of the DECODE I subroutine Fig 100 depicts the 50 flow diagram of operation for the DECODE I MODULE Appendix B contains the program listing for the DECODE I subroutine.
Initially the contest of registers RI through R 4 is saved for return to the calling module after exit from the DECODE I subroutine Next the DECODE I MODULE is called and the absolute coded occurrence value provided by the 55 DECODE I MODULE is saved in register RO To this end, the instruction MOV DPM+DIGO,STATUS causes the DPM flip flop in the STATUS register to be set to a I state and the f 1, f 2, f 3 flip flops in the STATUS register to be set which in turn causes the DC 2 decoder to form a true signal at the DIGO output which in turn calls the operation of the DECODE I MODULE 60 When the operation of the DECODE I MODULE is complete the BDONE flip flop in the STATUS register is set to a 1 state The instruction BIT BDONE,STATUS causes the BDONE flip flop to be monitored for a 1 state The 1,570,344 269 269 instruction BEQ -I causes the MINI COMPUTER to branch back to the previous MOV instruction and repeat the call on the DECODE I MODULE until the BDONE flip flop is in a I state When the BDONE flip flop is in a I state, the instruction CLR STATUS is executed causing the STATUS register to be cleared to 0 The instruction MOV #8,AI causes the value 8 to be stored into the address 5 register AI which in turn causes the output of register D 01 in the DECODE I MODULE to be coupled through to the I/O bus 1210 The subsequent instruction MOV DATAIRO causes the actual occurrence value formed by the DECODE I MODULE in register DOI to be stored into the register RO.
Finally, the DECODE I subroutine causes the context of registers Rl through 10 R 4 to be restored and the operation of the DECODE I subroutine exits.
J INSERT SUBROUTINE The INSERT subroutine is called by the programs at the points indicated as follows The INSERT subroutine inserts a two value pair, which consists of an entry number (E) and a brightness value (BV), in sequential memory locations into the 15 ordered list in the main memory area PNBOUT, see 2213 of Fig 102 A, and 223 of Fig 102 B In general the operation involves inserting the two value pair into the ordered list PNBOUT and shifting the remainder of the list down one position.
When the INSERT subroutine is called the following values have been set up:
1 The software register NOC contains an entry number (E) 20 2 The floating software register ACI contains a brightness value (BV) which is to be stored into the output area PNBOUT immediately following the entry number (E).
Additionally, PNBPTR is the base address of a two word area PNBPTR containing the beginning address of PNBOUT and a value which identifies the 25 number of entries now stored in the output area PNBOUT PNCNT is the address of the second word of PNBPTR which contains the number of entries The addresses PNBPTR and PNBCNT are generated by the assembler when assembling the program listing.
Appendix B contains the program listing for the INSERT subroutine and Fig 30 101 contains the flow diagrams thereof whose flow boxes are identified by the symbols INI-IN 8.
Upon call of the INSERT subroutine, INI is entered During INI the context of registers RO through R 4 is saved for a subsequent return to the calling program.
During IN 2 the base address pointers PNBPTR and PNBCNT are obtained 35 and stored into registers R 3 and R 4, respectively The instruction MOV NOC,R 2 causes the current entry number (E) contained in software register NOC to be stored into register R 2 With registers R 2, R 3 and R 4 loaded, IN 3 through IN 7 of the INSERT subroutine flow are ready to be carried out where the current entry number in register R 2 and the brightness value BV in floating register ACI are 40 stored in PNBOUT It should be noted that the two value pairs are stored as they are stored in PNBOUT so that the brightness values are in decreasing value order.
R 3 points to the current (entry BV) pair to be processed The floating point instruction LDF ACO,2 (R 3) causes the old brightness value in the address specified by R 3 plus two addresses to be read out from PNBOUT and stored into floating 45 point register ACO.
During IN 4 the current brightness value stored in floating register ACI is compared with the old brightness value in register ACO using the floating point instruction CMPF If the current brightness value (BV) in floating register ACI is so less than or equal to that of the old brightness value (BV) in register ACO, IN 6 is 50 entered directly where PNBOUT is left unaltered If the current brightness value (BV) in register ACI is greater than the old brightness value in register ACO, then the current one must be stored into the list in PNBOUT along with its entry number above the old brightness value (BV) in register ACO (and the corresponding old entry number) and the list PNBOUT appropriately shifted To this end, IN 5 is 55 entered.
During IN 5 the MOV (R 3),Rl causes the old entry number (E) to be read from PNBOUT and stored into register RI The MOV R 2,(R 3)+ instruction causes the current entry number to be stored into the address specified by register R 3 and register R 3 is incremented Thus the new entry number in register R 2 (from NOC) 60 has replaced the old entry number now contained in register Rl The instruction MOV Rl,R 2 causes the old entry number in register Rl to be transferred to register R 2 and thereby become the current one The floating point instruction LDF AC 2,ACO causes the old brightness value in floating register ACO to be transferred 270 1,570,344 270 2711573421 to floating register AC 2 where it is temporarily saved as the current brightness value The floating instruction MOVF ACI,(R 3)+ causes the current brightness value (BV) in floating register ACI to be stored into the incremented address specified by register R 3 at the memory location following the current entry number Also the address in register R 3 is incremented by the appropriate amount 5 so that it now points to the next old entry number in PNBOUT The floating instruction LDF ACIAC 2 then causes the old brightness value temporarily stored in register AC 2 to be transferred to the floating register ACI.
Following IN 5, IN 6 of the flow is entered where the value representing the number of entries in PNBOUT is decremented by 1 to reflect that one entry 10 number and associated brightness value in PNBOUT have been processed by the INSERT subroutine.
During IN 7 the number of entries value in register R 4 is checked and if greater than 0, indicating that there are more entry numbers and associated brightness values in PNBOUT to be processed, JOINI of the flow is reentered where the 15 current entry number and brightness values stored in registers R 2 and AC Il respectively, are processed In this manner the entry numbers and brightness values are arranged in PNBOUT in decreasing value order by brightness value.
When the number of entries value in register R 4 has been decremented to 0, IN 7 1 is entered At this point registers R 2 and ACI contain the remaining entry 20 number and brightness value which is to be stored into PNBOUT To this end, the MOV and MOVF instructions cause these values to be stored into PNBOUT under control of address register R 3 and the INC instruction causes the number of entries value at the location specified by PNBCNT to be incremented to reflect that one additional entry number and associated brightness value has been added to 25 PNBOUT During IN 8 the context of registers RO through R 4 is restored to allow a return to the calling program.
K COMMAND SUBROUTINE Appendix B-10 shows the program listing for the COMMAND subroutine.
Fig 103 is a flow diagram illustrating the sequence of operation during execution of 30 the COMMAND subroutine Fig 103 uses the symbols Cl through C 42 to identify the various blocks in the flow diagram Along the left hand side of Appendix B-10 the symbols Cl-C 42 are used to tie in the program listings to the blocks shown in Fig 103.
Briefly, the COMMAND subroutine is provided for handling a number of 35 housekeeping functions in connection with two commands which may be used by the requestor in presenting his request to the system As noted above, these two commands are the “END” command and the “CHANGE” command The items that can be changed by the CHANGE command are software globals and have been described above as a (alpha) used in computing length value L of Equation 11, 40 brightness cutoff value BVCO, the length switch (LNGSW) which determines whether the length of the request is to be taken into account in determining a response, pipe width PW, and pipe cutoff value PCO.
The primary functions handled by the COMMAND subroutine are as follows:
After the requestor has typed in the letter E, for the END command, the 45 COMMAND subroutine causes the printer to type out the two additional letters ND so that the complete command word END is displayed; after the requestor types the letter C, for the CHANGE command, the COMMAND subroutine causes the printer to print out the additional letters HANGE so that the complete command word CHANGE is displayed: after the complete command word 50 CHANGE has been displayed and after the requestor types the letter A, for the word ALPHA (a), the COMMAND subroutine causes the printer to print out the additional letters LPHA, displaying the complete word ALPHA; after the complete command word CHANGE has been displayed and after the letter B, for BVCO, has been typed, the COMMAND subroutine causes the printer to print out 55 the additional letters VCO, displaying the complete word BVCO; after the complete word CHANGE has been displayed and the requestor has typed the letter L, for LNGSW, the COMMAND subroutine causes the printer to type out the letters NGSW, displaying the complete word LNGSW; after the complete word CHANGE has been displayed and if the requestor has typed the letters PC, the 60 COMMAND subroutine causes the printer to type out the additional letter O so that the complete word PCO is displayed; after ALPHA or BVCO or LNGSW or PW (typed out in full by the requestor) or PCO has been typed by the requestor, the COMMAND subroutine automatically causes the printer to type out the message I 1,570,344 271 271 “TO”; subsequently, after the message “TO” has been printed out and the requestor has subsequently entered either an integer value (i e, a percentage representing BVCO, LNGSW, PCO, PW, or a floating point value representing a (alpha) and the COMMAND subroutine stores them in the proper program global.
These and other functions and operations of the COMMAND subroutine will be 5 more fully explained in the following discussion.
Consider now the sequence of operation of the COMMAND subroutine, making reference to the flow diagram of Fig 103 It will be recalled with reference to the FORMATER program flow diagram of Fig 102 C that when a requestor types an E or a C, that this indicates that either the END command or CHANGE 10 command is being entered by the requestor It will also be recalled that such E or C is detected by the FORMATER program during F 6 and calls the operation of the COMMAND subroutine.
Initially, during Cl of the COMMAND subroutine the context of the MINI COMPUTER is saved 15 During C 2 the switch ERRSW is cleared or reset to 0 so that it can be set to I later on in the event that an error is detected during the operation of the COMMAND subroutine.
During C 3 et seq the COMMAND subroutine determines whether or not an E, corresponding to an END command, or a C, corresponding to a CHANGE 20 command, has been entered To this end, during C 3 the COMMAND subroutine reads the character typed on the typewriter and compares it with a stored representation of the character E If the comparison results in an inequality or a false result, C 4 of the COMMAND subroutine flow is entered.
During C 4, the same character is compared with a stored representation of the 25 character C and if the comparison results in an inequality, C 5 is entered where the ERRSW switch is set to 1, indicating that a prohibitive condition exists, i e, something other than an E or a C has been typed by the requestor following a beginning delimiter, since there are only two commands, namely, an END command and a CHANGE command Following C 5, JOIN 7 and C 30 are entered 30 the operation of which is discussed in more detail hereinafter.
Return now to C 4 of the flow and assume that the character typed by the requestor is a C The comparison during C 4 is equal or true and C 6 is entered.
During C 6 the PRINTR subroutine is called causing the letters HANGE to be automatically typed out by the printer so that the requestor sees the word 35 CHANGE.
The COMMAND subroutine then waits until the requestor enters a character on the typewriter corresponding to the information that is to be changed The item to be changed is stored in the software as a global During C 7 the GETC subroutine is called causing the next character entered by the requestor to be read During C 8 40 the FLTSW and BVFLG software flags are cleared to O so that they can be set later on during the operation of the software The FLTSW is a float switch which indicates if a floating point number is being read The BVFLG is a software flag which, when a 1, indicates that a value for brightness cutoff has been entered on the typewriter and is being read 45 During C 9 a check is made to see whether the character read from the typewriter during C 7 is an A This is accomplished as discussed above by comparing A with a pre-stored value representing A If the comparison results in an equality, indicating an A, C 10 is entered where the PRINTR subroutine is called, causing the printer to type the additional letters LPHA, thereby displaying the 50 complete word ALPHA Thus far the printer has displayed the partial phrase “CHANGE ALPHA”.
ALPHA is a floating point number; accordingly, during Cl 1 the float switch FLTSW is set to 1 Subsequently, during C 12 a software pointer is set to the storage location of the word ALPHA which has been reserved at the end of the 55 FORMATER program Following C 12, CJOIN 6, CJOIN 7 and C 30 are entered.
Returning back to C 9, assume that the comparison resulted in an inequality and hence C 13 is entered During C 13 the character is compared against a stored representation of the character B If the comparison results in an equality, C 14 is entered where the PRINTR subroutine is called and causes the printer to print out 60 the letters VCO following the letter B, resulting in the displayed word BVCO Thus at this point the words displayed by the printer are “CHANGE BYCO”.
During C 15 the BVFLG is set to 1, indicating that the requestor is about to enter a brightness cutoff value (BVCO) Subsequently, during C 34, C 35 and C 37 the brightness cutoff value BVCO is read in and stored at a location BVCO 65 1,570,344 272 272 reserved by the FORMATER program During C 16 a pointer is set to the memory location for the word BVCO Following C 16, CJOIN 5, CJOIN 6, CJOIN 7 and C 30 are entered.
Return now to C 13 and assume that the comparison resulted in an inequality thereby indicating that the character just read is not a B C 17 is then entered where 5 the character is compared against the stored designation for the letter L If the comparison results in an equality, C 18 is entered where the PRINTR subroutine is called causing the printer to type out the letters NGSW following the letter L, resulting in the displayed word LNGSW At this point the operator console is displaying the words “CHANGE LNGSW” 10 C 19 is then entered where a pointer is set to the memory location containing the word LNGSW which has been stored at the end of the FORMATER program.
Space for all global variables has been reserved at assembly time at the end of the FORMATER program Following C 19, CJOIN 4, CJOIN 5, CJOIN 6, CJOIN 7 and C 30 are entered 15 Return now to C 17 and assume that the comparison resulted in an inequality, indicating that the character is not the letter L C 20 is now entered where the character is compared against the stored designation of the letter P If an inequality is detected, the character is not a P and C 21 is entered where the ERRSW switch is set to 1 The ERRSW switch is set to indicate an error since the only permissible 20 globals are A-ALPHA, B-BVCO, L-LNGSW, P-PW, or P-PCO and if an equality is not detected by C 21 it indicates that some other character has been entered and hence the character entered is an error.
Following C 21, CJOIN 3, CJOIN 4, CJOIN 5, CJOIN 6, CJOIN 7, and C 30 are entered 25 Return now to C 20 and assume that the comparison resulted in an equality, indicating that the character is indeed a P It should be noted that the P might designate either a PW or a PCO global Accordingly, C 22 is entered where the GETC subroutine is called to await and read the next character entered by the requestor During C 23 the next character entered and read is compared against the 30 stored designation of the letter C If an equality is detected, C 24 is entered where the PRINTR subroutine is called causing the printer to type out the letter 0, following the letters PC C 25 is then entered, where a pointer is set to the memory location containing the word PCO which has been stored at the end of the FORMATER program The flag BVFLG is set so that the number entered as PCO 35 will be converted to floating point Thus at this point the operator console displays the words “CHANGE PCO”.
Following C 25, CJOIN 2 through CJOIN 7 and C 30 are entered.
Return now to C 23 and assume that the comparison resulted in an inequality, indicating that the character is not the letter C This means that the character just 40 read should be a W which is the next letter for PW Accordingly, C 26 is entered where a comparison is made between a stored designation for the letter W and the character which was just entered and read If an equality is detected, C 27 is entered where a pointer is set to the memory location for the word PW At this point the printer displays the words CHANGE PW 45 Return now to C 26 and assume that the comparison resulted in an inequality.
This means that the character typed following the letter P is something other than either a C or a W and is therefore in error C 28 is then entered where the ERRSW switch is set to 1 Following either C 27 or C 38,CJOIN 1 through CJOIN 7 and C 30 so are entered 50 Drop down to C 30 of the flow During C 30 the ERRSW switch is checked to see if it is a 1 or a 0 If it is a I, a true condition exists indicating that there is an error and C 31 is entered During C 31 the PRINTR subroutine is called causing theprinter to type out the message “ERROR IN FORMAT” Following C 31,CJOIN 14 and CJOIN 1 I and C 42 are entered 55 Return now to C 30 and assume that the ERRSW switch is in a 0 state and hence a false condition exists, indicating that the error switch has not been set and that no error exists C 32 is then entered where the PRINTR subroutine is called causing the printer to type out the word TO following the message now displayed on the printer At this point the printer has displayed the words “CHANGE” 60 followed by any one of the words “ALPHA” or “BVCO” or “LNGSW” or “PCO” or “PW” followed by the word “TO” The COMMAND subroutine must now read the new value to be entered on the typewriter by the requestor.
During C 33 the FLTSW switch is checked to see whether it is a 1 or a 0 If it is a 0 a false condition exists and C 34 is entered where the GET INTEGER 65 1,570,344 273 2731 subroutine is called causing an integer value to be read from the typewriter and converted from ASCII code to binary code During C 35 the BVFLG flag is checked to see if it is a 1, indicating that a BVCO value is being dealt with If the BVFLG flag is 0, a false condition exists indicating that a BVCO value is not being dealt with, and C 36 is entered where the integer which was just read is stored at the 5 appropriate location by the software MOV command Following C 36,CJOIN 8, 9, and 11 and C 42 are entered.
Return now to C 35 and assume that the BVFLG flag is a 1, indicating a true condition and therefore that the entry by the requestor is a BVCO value C 37 is then entered where the BVCO value is floated and divided by 100 to convert it from 10 a percentage value to decimal value between 0 and 1 This operation is effected by the software commands Following C 37,CJOIN 8 through 11 and C 42 are entered.
Return now to C 33 and assume that the FLTSW flag is a 1 and accordingly a true condition exists indicating that the floating point number ALPHA (a) has been entered on the typewriter by the requestor C 38 is entered where the GET 15 FLOATING POINT subroutine causes the number entered by the requestor to be converted to floating point notation It should be noted that the number will be a decimal number between 0 and 1 as are all ALPHA (a) values During C 39 the ALPHA (a) value, in floating point notation, is stored at location ALPHA and CJOIN 9 through CJOINI 1 and C 42 are entered 20 Return now to C 3 and assume that the comparison with the character indicated that an E had actually been entered by the requestor on the typewriter and accordingly the result of the comparison was true, causing C 40 to be entered.
During C 40 the PRINTR subroutine causes the letters ND to-be typed out by the printer causing the word END to be displayed thereby indicating that an END 25 command has been entered by the requestor on the typewriter During C 41 the ENDFL flag is set to 1, indicating that an END command has been entered and JOIN 11 is subsequently entered.
During C 42 the context of the MINI COMPUTER is restored to that which existed when the COMMAND subroutine was called by the FORMATER 30 program Subsequently the operation of the COMMAND subroutine is exited.
L GET INTEGER SUBROUTINE Fig 104 shows a flow diagram of the GET INTEGER subroutine Fig 104 shows blocks C 340 through C 348 depicting the sequence of operation of the GET INTEGER subroutine Towards the end of Appendix B-10, the symbols C 340 35 through C 348 are used to indicate the corresponding program listings for the GET INTEGER subroutine.
Consider now the GET INTEGER subroutine with reference to Fig 104 The GET INTEGER subroutine is called during box C 34 of the COMMAND subroutine depicted in Fig 103 The GET INTEGER subroutine converts an 40 ASCII coded number string into integer form With reference to Fig 104 during C 340 the GET INTEGER subroutine reads a character from the typewriter.
During C 341 the character is checked against code representing a blank If the character is a blank, nothing has been entered by the requester and C 340 is reentered This loop is continued until a nonblank character is detected during 45 C 341 When a nonblank character is detected during C 341, a false condition exists causing C 342 to be entered where the MINI COMPUTER register R 2 is cleared ready to receive the result of the conversion of the ASCII coded number string.
During C 343 the character read from the typewriter is compared with code representing zero and if the character is less than or equal to zero, C 344 is entered 50 During C 344 the character is compared with code representing the decimal number nine and if the character is greater than or equal to nine, C 345 is entered.
This sequence during C 343 and C 344 is used to assure that the ASCII coded number character lies between zero and nine If this condition exists, C 345 will be reached; otherwise, the GET INTEGER subroutine depicted in Fig 104 is exited 55 back to C 35 of the COMMAND subroutine (see Fig 103) leaving a character in register R 2.
During C 345 et seq, the character is converted to its binary equivalent by subtracting the value representing an ASCII coded zero from the character The ASCII coded zero is represented by the decimal number ASCII code is depicted at 60 page B 2-1 of the book entitled Programming Languages, published by Digital Equipment Corp, in 1972.
After the binary equivalent of the number is obtained, C 346 is entered where the previous value which is stored in software register R 2 is multiplied by 10 1,570,344 274 274 thereby shifting the value to the left one decimal position and then the current number is added to the resultant partial result.
During C 347 the results of C 346 are added to the result of the subtraction in C 345 and the result is stored back into software register R 2 During C 348 the next ASCII character from the typewriter is read, the C 343 through C 348 are repeated 5 in the manner discussed above This loop is repeated as long as numbers are entered on the typewriter As soon as a non-numeric quantity is entered, an exit will be taken from either C 343 or C 344 back to C 35 of the COMMAND subroutine with the result of the computation in the register R 2.
Summarizing, the GET INTEGER subroutine receives ASCII coded 10 characters from the typewriter, converts the character to straight binary code by subtracting the binary code for an ASCII zero from each character to form a modified ASCII value, multiplying the modified ASCII value by 10 and adding the modified ASCII value to a previous result, if any, to form a new result The process is described at p 281, Vol II of the book Seminumerical Algorithms by Knuth, 15 published 1960 by Addison-Wisley Publishing Co.
M GET FLOATING POINT SUBROUTINE Fig 102 shows the GET FLOATING POINT subroutine flow diagram Blocks C 380 through C 388 are used for depicting the sequence of operation of the GET FLOATING POINT subroutine 20 Appendix B-10 has the symbol C 381 depicted along the left hand side of the program listing towards the end of the COMMAND subroutine listing and identifies that portion of the COMMAND subroutine which forms the GET FLOATING POINT subroutine.
The GET FLOATING POINT subroutine is called during block C 38 of the 25 COMMAND subroutine (see Fig 103) The GET FLOATING POINT subroutine converts an ASCII coded number string (representing a decimal number between 0 and 1) into a floating point number When called, the GET FLOATING POINT subroutine first enters block C 380 where a character is read from the typewriter of the printer The character is compared against code representing a period in C 381 30 If the character is not a period, C 380 is reentered C 380 and C 381 are repeated until a period is detected indicating the beginning of the decimal number representing ALPHA (a) When an equality is detected during C 381, C 382 is entered.
During C 382 floating point register ACO is loaded with a value 0 and software register ACI is loaded with a value representing 1 C 383 and C 384 of the GET 35 FLOATING POINT subroutine are similar to C 343 and C 344 of the GET INTEGER subroutine in that they are provided to make sure that the ASCII character just read from the typewriter is a number and that it lies between 0 and 9.
If true, i e, the character lies between 0 and 9, C 385 of the flow will be entered.
During C 385 the binary equivalent of the character is computed by subtracting 40 the ASCII code representing a 0 from the character.
During C 386 the result obtained during C 385 is converted to floating point and then multiplied by the value 1 contained in floating point register ACI During C 387, any partial result contained in register ACO (first time through C 387, register ACO contains a 0) is added to the result of the multiplication during C 386 and the 45 result is stored into ACO Also during C 387, ACI is multiplied by the value 1 contained in software register TENTH and the result is stored back into register AC I As a result of these steps the next number processed by the GET FLOATING POINT subroutine will be, effectively, divided by 100.
During C 388 the next character is read in and C 383 et seq is repeated This 50 loop is repeated until the last character is read and an exit is taken from either C 383 or C 384 because the comparison indicates that the character just read is less than zero or greater than nine When an exit is taken from C 383 or C 384, the floating point number is contained in register ACO and block C 38 of the COMMAND subroutine flow (Fig 103) is reentered 55 N REQUEST SUBROUTINE The REQUEST subroutine is called at F 7 of the FORMATER program (Fig.
102 C) F 7 of the FORMATER program is entered and hence the REQUEST subroutine is called only if the first character received from the typewriter is either a sentence delimiter # or a word delimiter-b As a result, F 7 is only entered if the 60 FORMATER program is dealing with a request on a data base as opposed to a command.
Briefly, the REQUEST subroutine reads the characters from the typewriter 275 1,570,344 275 276 1,570,344 276 and converts each character, following the delimiter, from ASCII code to absolute coded values representing the corresponding event numbers on layer 0, and stores the resultant absolute coded values into the PSTRING table in between the beginning and end delimiters (see 2211, Fig 102 A) In addition, the REQUEST subroutine calls the operation of the PARSER subroutine which performs the 5 parsing operation, applies the piping and brightness function to the results, and stores in the output area PNBOUT (see 2213, Fig 102 A) those entries which are above the brightness cutoff value The entries in PNBOUT are then converted one at a time into strings of numbers and words and are then printed out on the printer of the operator console 10 Consider now the details of the REQUEST subroutine Appendix B-1 1 is a listing of the REQUEST subroutine Fig 106 is a flow diagram for the REQUEST subroutine with boxes identified by the symbols Rl through R 29 The relation between the program listing in Appendix B-11 and the flow diagram of Fig 106 is indicated by the symbols Rl-R 29 shown along the left hand side of the program 15 listing of Appendix B-1 1.
Consider now the sequence of operation with reference to Fig 106 As discussed above, the FORMATER program calls the operation of the REQUEST subroutine during F 7 (see Fig 102 C) After being called the REQUEST subroutine enters Rl of the flow During RI the context of the MINI COMPUTER is saved 20 Subsequently, R 2 is entered where pointers are set up to the beginning of the parse string (PSTRING) where the values are going to be stored during operation of the REQUEST subroutine Also during R 2 the EXIT flag is reset to 0 so that it can be appropriately set to 1 to cause the REQUEST subroutine to enter R 26 through R 29 which are the ending steps for the REQUEST subroutine 25 Fig 117 depicts Table CVRTBL for layer 0 depicting the ASCII numbers and the corresponding layer event numbers used in the system As indicated, all of the event numbers are located in Table CVRTBL The coded value representing the ASCII character provided by the typewriter has the eighth bit set This bit is stripped from the character by subtracting octal value 200 from the character 30 converting the character to a true ASCII character.
Continuing with the flow diagram of Fig 106, during R 3 the first character obtained from the operator during F 3 in the FORMATER program is checked to see whether it is a sentence delimiter If the first character is not a sentence delimiter, then the requestor has presented a layer 0 request and R 4 et seq are 35 entered If the first character is a sentence delimiter, then the requestor has presented a layer 1 request and Rl 1 et seq are entered.
Assume that a sentence delimiter is not detected, hence a false condition exists and therefore a layer 0 request is presented by the requestor at the printer R 4 is then entered Since the first character is not a sentence delimiter, it must be a word 40 delimiter Therefore during R 4 the word delimiter-b is moved into the PSTRING and R 5 is entered.
During R 5 the next character in sequence of the request is read from the keyboard During R 6 this character is compared with a coded value representing a word delimiter (WDEL) and if the character is not a word delimiter, R 7 is entered 45 where the character (in ASCII) is added to the base address of Table CVRTBL to find the address of the corresponding memory location which contains the corresponding layer 0 event number In this manner the ASCII character is converted to its layer 0 event number In addition, during R 7 the layer 0 event number is stored at the next available location in the parse string (PSTRING) 50 Following R 7, RIO is entered where the EXIT flag is checked to see if it is a 1.
If it is not, a false condition exists and JOIN I and R 5 are reentered where the next character is read from the keyboard Following R 5, R 6 is again entered where the new character is compared against the stored word delimiter representation WDEL and if the character is not a word delimiter, R 7 and RIO are again entered 55 as discussed above The loop through JOIN 1 through RIO is repeated until a word delimiter-b is read When this occurs, the comparison during R 6 is true and R 8 and R 9 are entered.
During R 8 the stored word delimiter representation WDEL-15 is stored into the parse string PSTRING as and R 9 is entered where the EXIT flag is set to 1 60 Following R 9, JOIN 2 and RIO are entered During RIO the EXIT flag will then be found to be a i and therefore true, causing JOIN 8 and R 26 through R 29 is entered.
During R 26 the pointer R 4 is reset back to the beginning of the parse string PSTRING During R 27 the PARSER subroutine is called where all of the entries in the parse string which have a brightness value above that of the brightness cutoff 65 value BVCO are stored in the output area PNBOUT During R 28 the PROCOUT subroutine is called which converts the entries in the area PNBOUT into strings of characters and words and prints out the words on the printer of the operator console This continues until the list PNBOUT is exhausted or the requester decides he has had enough and terminates the printout by so indicating his desire in 5 response to the message “WANT ANOTHER ENTRY” In either case, R 29 is next entered During R 29 the original context which was saved during RI is restored and the operation of the REQUEST subroutine is exited.
Return now to R 3 of the REQUEST subroutine flow and assume that the first character is a sentence delimiter, indicating a layer I request by the requester A 10 true condition will occur and RI 1 et seq will be entered.
A word delimiterb always follows a sentence delimiter Therefore, during Rl 1 the sentence delimiter # detected during R 3 and the next character in the request string, a word delimiter, are moved into sequential locations of the parse string PSTRING 15 During R 12 the next character in the request is read from the keyboard The character may either be a word delimiter-b or a character representing a letter.
Thus, R 13 is entered where the character is compared with the stored representation of a word delimiter and if the comparison is true, i e, the character is a word delimiter, then R 14 is entered where the next character of the request is 20 read from the keyboard If the comparison is false, i e, the character is not a word delimiter, then JOIN 3 is entered directly, skipping R 14 R 13 and R 14 then take care of the situation where the requester fails to enter a word delimiter following a sentence delimiter During Rl 1 and #bf are entered into PSTRING for PARSE.
However, the requester may have entered one of the following: 25 1 #b 2; In either case by the time JOIN 4 is reached, PSTRING contains a #b and RO contains the first letter of the request.
JOIN 3, JOIN 4 and R 15 are sequentially entered During R 15 the character 30 just read from the request is compared against the stored representation of a word delimiter and if the character is not a word delimiter, a false condition exists and R 16 is entered where the same character is compared against a stored representation of a sentence delimiter If a sentence delimiter is not detected during R 16, a false condition exists and this indicates that the character presently 35 being processed is a character of the request rather than a delimiter and R 17 is entered R 17 is similar to R 7 in that the character, in ASCII code, is converted to the corresponding event number and is stored in the next sequentially available location in the parse string PSTRING It should be noted that the character represents a letter no matter whether this is a word layer 0 or a sentence layer 1 40 request.
Following R 17, JOIN 5, JOIN 7 and R 25 are sequentially entered During R 25 the EXIT flag is checked to see if it is a 1 If it is, then R 26 through R 29 are entered.
To be explained in more detail, if the EXIT flag is a 0, then a false condition exists during R 25 and JOIN 4 and R 15 et seq are reentered 45 Return now to R 15 and assume that the comparison reveals that the character just read from the request is a word delimiter and a true condition exists R 20 is subsequently entered where the word delimiter is moved into the next sequential location of the parse string PSTRING During R 21 the next character of the request is read from the keyboard During R 22 a check is made to see whether the 50 character just read is a sentence delimiter If the character is not a sentence delimiter, then JOIN 6, JOIN 7 and R 25 are entered If the EXIT flag is a 0 the condition during R 25 is false and JOIN 4 and R 15 are then reentered This occurs when the REQUEST subroutine has just processed one word and since this is a sentence or layer I request, there may be another word in the request 55 Return now to R 22 and assume that a sentence delimiter is detected, causing a true condition Under these conditions R 23 of the flow is entered where the sentence delimiter is moved into the parse string PSTRING Subsequently during R 24 the EXIT flag is set to a I indicating that the REQUEST subroutine has now detected the END character of a sentence layer I request Subsequently, JOIN 6, 60 JOIN 7 and R 25 are entered This time during R 25 the EXIT flag is in a 1 state, causing a true condition and therefore R 26 through R 29 are entered.
1,570,344 277 277 Return now to RI 5 Assume that the comparison is false and therefore the character just obtained from the keyboard is not a word delimiter R 16 is then entered Assume that during R 16 the comparison is true, indicating that the character is a sentence delimiter This condition will occur if the requestor has finished a request and, instead of placing a word delimiter at the end of the last 5 word, he has placed only a sentence delimiter Under these conditions, R 18 is entered where a word delimiter and a sentence delimiter are moved into the parse string PSTRING Following R 18, R 19 is entered where the EXIT flag is set to 1, indicating the end of the sentence layer 1 request Following R 19, JOIN 5, JOIN 7, R 25, JOIN 8, and R 26 through R 29 will then be entered 10 In summary, during R 26 through R 29, the PARSER subroutine is called which returns the results which are in the software area PNBOUT The output area PNBOUT will contain a list of the entries in layer 1 if a sentence layer I request has been made, or a list of entries in layer 0 if a word layer 0 request has been made.
The word or sentence entries in PNBOUT are possible responses to the request It 15 should also be noted that the possible responses to the request left in the area PNBOUT by the PARSER subroutine are ordered from highest brightness value to lowest brightness value.
During R 28 the PROCOUT subroutine is called which ultimately causes the printer of the operator console to type out the results stored in PNB OUT After the 20 PROCOUT subroutine is complete, R 29 is entered where the context of the MINI COMPUTER is restored and the REQUEST subroutine exits back to the FORMATER program where the next entry is requested.
0 PROCOUT (PROCESS OUTPUT) SUBROUTINE The PROCOUT subroutine is called during R 28 of the REQUEST subroutine 25 (see Fig 106) The PROCOUT subroutine takes the entries that have been placed in PNBOUT by the PARSER program and generates the response, which causes a response on the printer of the operator console.
The printer displays letters; therefore, a sequence of ASCII coded signals representing letters must be sent to the printer Therefore, if a layer 0 request has 30 been made by the requester, the PROCOUT subroutine takes the entries in PNBOUT which represent words and signals are sent to the printer so as to print out words, a letter at a time If a layer 1 request has been made, the entries in PNBOUT are sentences, and the PROCOUT subroutine takes the entries in PNBOUT and generates signals representing a series of letters again for printing a 35 letter at a time.
Since the data is arranged in layers it is necessary to utilize a number of tables in order to regenerate the data from the layers These and other aspects of the PROCOUT subroutine will become evident in the following discussion.
Referring now to Figs 102 A and 102 B, when the PROCOUT subroutine is 40 called by the REQUEST subroutine, the PARSER subroutine has completed the area PNBOUT PNBOUT contains the possible responses to the request in the form of entry value (E) and brightness value (BV) pairs ordered from highest brightness value to lowest brightness value.
PROCOUT then causes the rest of the steps depicted in Figs 102 A and 102 B 45 following PNBOUT to take place More specifically, the PROCOUT subroutine responds to a layer 0 request and outputs one entry, i e, one word, at a time, serially by letters, until either the number of entries in PNBOUT is exhausted or until the requestor indicates that he does not want any further responses, by typing an “N” in response to the question: “WANT ANOTHER ENTRY?” The 50 PROCOUT subroutine responds to a layer 1 request and outputs one entry at a time, i e, one sentence at a time, serially by letters, until PNBOUT is exhausted or until the requestor again indicates that he does not want further responses.
Table GI is a series of entries each containing three words, the first word containing the entry number (E), the second word containing the ending delimiter 55 (ED) for the corresponding entry, and the third word containing two bytes The first of the two bytes contains an accumulated length value (AL) which identifies the smallest occurrence value (event time) at the beginning of the corresponding entry, and the second byte containing the length or number of occurrence values (L) in the corresponding entry Table G 2 has a similar construction to that of Table 60 Cl.
A better understanding of the construction of Tables Gl and G 2 can be understood with reference to Fig 108 for Table G 2 Fig 108 is a sketch giving an example and illustrating the correspondence between the G 2 table and the OLIST 1,570,344 278 278 list OLIST is an area in MAIN MEMORY in which information is stored just prior to output by the PROCOUT subroutine OLIST contains a series of two value pairs, the first value of the pair representing an event number on layer 0 and the second of which represents an occurrence value (event time) The two value pairs are arranged in descending value by occurrence value from left to right as seen in 5 Fig 108 Because of the sequence with which data is entered into the data base it is necessary to return the information from the data base in descending order b occurrence value.
Returning to the purpose of the table G 2 the accumulated length value (AL) is a pointer to the two value pairs in OLIST Specifically, each accumulated length 10 value identifies the two value pair containing the smallest occurrence value within the corresponding entry or word For example, entry I contains an accumulated length value 4 identifying the fourth two value pair from the left end of OLIST in Fig 108 The entry length identifies the number of two value pairs contained in OLIST for the corresponding entry Thus, it will be seen that entry 4 of OLIST is contains four two value pairs.
With the foregoing in mind consider now the details of the PROCOUT subroutine Appendix B-12 contains a program listing for the PROCOUT (PROCESS OUTPUT) subroutine Fig 107 contains a flow diagram illustrating the sequence of operation of the PROCOUT subroutine Fig 107 identifies the various 20 boxes of the flow diagram by the symbols POI through P 018 Correspondence between the program listing of Appendix B-12 and the flow diagram of Fig 107 is shown along the left hand side of Appendix B-12 where the labels POI-PO 18 of Fig 107 are shown.
Refer now to the sequence of operation with reference to Fig 107 During 25 P 01, the context of the MINI COMPUTER is saved in the manner described above so that it can return to the REQUEST subroutine During P 02, the PROCOUT subroutine determines whether anything is contained in MAIN MEMORY area PNBOUT If PNBOUT contains all O ‘s, and therefore is empty, P 03 is entered where the PRINTR subroutine is called causing the printer of the 30 operator console to type out the message “NO HITS FOUNDS” Following P 03, the JOIN and P 018 are entered During P 018 the context of the MINI COMPUTER is restored to that existing when the PROCOUT subroutine was called.
Return now to P 02 and assume that PNBOUT does not contain O ‘s and 35 therefore there is something to be output by the PROCOUT subroutine.
Speaking generally the first step is to take the entry numbers in PNBOUT and move them over to Table GI and at the same time zero out the second and third words for each entry as indicated at 2202 in Fig 102 A.
During P 05 the SETUP subroutine is called by the PROCOUT subroutine 40 The SETUP subroutine goes through the data base delimiter line for the layer corresponding to the request, computes the length of each entry and determines the length accumulated from the beginning of OLIST to the first event of each entrv The SETUP subroutine also fills in the last two words for each entry in Table GI, utilizing the values determined for each entry 45 Following P 05 the JOIN and P 06 are sequentially entered During P 06 one of the three word entries is moved from Table GI to Table G 2 The PROCOUT subroutine marks the fact that Table G 2 is only of length 1 by moving the value I to register R 3, and P 07 is entered.
During P 07 the PROCOUT subroutine calls the GENERATE subroutine so which forms OLIST in the manner described with reference to the FORMATER program.
During P 08 the LISW software switch is checked The LISW switch, if 0, indicates a layer 0 request, and if 1, indicates a layer 1 request If the LISW switch is a 0 a false condition exists and the JOIN and P 012 are entered directly 55 If the L l SW switch is a 1, and hence a true condition exists, P 09 is entered to process a layer 1 request Reference should now be made to Fig 102 B which depicts the sequence of operation for a layer I request The OLIST generatedduring P 07 for a layer 1 request is depicted at 2241 The OLIST contains event numbers for layer I identifying entries or words in layer 0 During P 09 the 60 PROCOUT subroutine takes the layer 1 event numbers from OLIST and from this generates a new Table G 2 depicted at 2242 The new Table G 2 will contain each of the entry numbers in layer 0 corresponding to the event selected from OLIST for processing In addition the PROCOUT subroutine zeros out the second and third words for each of the 3 word entries 65 279 I 1,570,344 279 280 1,570,344 280 PO 10 is then entered where the SETUP subroutine is called Similar to P 05, the SETUP subroutine goes through each event in the new Table G 2, determines the ending delimiter (ED) for each event, determines the accumulated length (AL) to the smallest occurrence value for each entry, determines the length (L) of each entry, and places this information in association with each entry number in Table 5 G 2 as depicted at 2243.
P Ol l is now entered where the GENERATE subroutine is again called The GENERATE subroutine now goes through all of the entries in Table G 2 and generates OLIST as depicted at 2245 which contains a series of layer 0 event number and occurrence value pairs, all as described with reference to the 10 FORMATER program The resultant OLIST is depicted at 2245 The relation between Table G 2 at 2243 and OLIST at 2245 is similar to that depicted in Fig 108.
Following P 01 1 the JOIN and PO 12 are entered where the PRNTC (Print a character) is called repeatedly and the sentence is typed out by the printer at the operator console Briefly, the PROCOUT subroutine goes through the OLIST 15 depicted at 2245 It gets the character and calls subroutine PRNTC which sends the printer an ASCII coded character for each event in OLIST, 2245 To this end and with reference to Fig 108 the first entry is 4, the accumulated length is 4, and its entry length is 4 Therefore the accumulated length value of 4 is added to the base address of OLIST and then the four events or characters in the entry are converted 20 to ASCII code and printed out in descending value order of event, moving from right to left.
After having printed out the entire entry P 013 is entered.
PNBCNT is initially set with the number of entries in the last PNBOUT.
During P 013 the value in PNBCNT is decreased by 1 to reflect that one of the 25 entries in PNBOUT has been processed When PNBCNT reaches 0, all of the entries in PNBOUT have been processed and PO 14 is entered where the EXIT flag is set to 1 and PO 17 is entered.
If PNBCNT is not 0, then P 015 is entered following P 013, causing the PRINTR subroutine to be called which prints out the message “PRINT 30 ANOTHER ENTRY” This is a signal to the requestor to either enter a Y for yes or a N for no further requests If the requester enters a Y for yes, the two JOI Ns and PO 17 are sequentially entered If the requester strikes an N for no, PO 16 is entered where the EXIT flag is set and the two JOI Ns and P 017 are entered.
During PO 17, the EXIT flag is checked and if 0, i e, false, then the JOIN and 35 P 06 are entered where the next layer 1 entry in Table Gl at 2237 is moved into Table G 2 as depicted at 2239 If the EXIT flag is 1, indicating a true condition, then PO 18 is entered where the context of the MINI COMPUTER is restored to that existing when PROCOUT was entered and the PROCOUT subroutine is exited.
P SETUP SUBROUTINE 40 The SETUP subroutine is called by the PROCOUT subroutine during P 05 and PO 10 (see Fig 107) The SETUP subroutine takes the Tables Gl or G 2 in the form depicted at 2215 of Fig 102 A and 2235 and 2242 of Fig 102 B and fills in the ending delimiter (ED), the accumulated length (AL), and the entry length (L) (see 2217, Fig 102 A and 2237, 2243 of Fig 102 B) 45 The program listing for the SETUP subroutine is depicted in Appendix B-13.
Fig 109 is a flow diagram for the SETUP subroutine showing boxes S I through S 17 to depict the sequence of operation The correspondence between the listing of Appendix B-13 and the flow diagram of Fig 109 is shown along the left hand side of Appendix B-13 using the symbols Sl through 517 50 Consider now the sequence of operation with reference to the flow diagram of Fig 109 During SI the context of the MINI COMPUTER is saved so that it may return to the PROCOUT subroutine upon completion of the SETUP subroutine.
The beginning and ending delimiters for the entries in the Tables is determined from the delimiter for the layer being processed Accordingly, it is necessary to 55 generate the line 0 representation from the seed representing the delimiter.
To this end, 52 of the SETUP subroutine flow is entered where the OUTPUT subroutine is called, causing line 0 of the delimiter to be formed.
MEMORY MODULE area 1 is the area from which the DECODE I MODULE converts information from hybrid code to absolute coded occurrence 60 values Therefore it is necessary that the line 0 representation of the delimiter be stored in MEMORY MODULE area 1 To this end, 53 of the flow is provided to determine whether software register DOAR identifies MEMORY MODULE area 1 If it does, then the flow proceeds through the JOIN to 55 directly, bypassing 54.
1,570,344 280 280 If DOAR contains a value identifying some other MEMORY MODULE area, then the condition during 53 is false, and 54 is entered.
During 54 the line 0 representation of the delimiter is transferred into MEMORY MODULE area 1 Following 54 the JOIN and 55 are entered.
During 55 the DECODE I MODULE is initialized To this end the length of 5 the delimiter stored in MEMORY MODULE area 1 is transferred from software register DOLN through the DATAO of the DPM INTERFACE MODULE to register LNI of the IPRF In addition, DINIT of the STATUS register is set to 1 and the DCODEI subroutine is called causing the DECODE I MODULE to provide the first occurrence value from the delimiter in MEMORY MODULE 10 area 1 and the value is stored in software register TDI.
Previously during the PROCOUT program the length of the Table G I or G 2 is stored into hardware register R 3 of the MINI COMPUTER During 56 of the SETUP subroutine the length of the table is transferred from register R 3 to software register WOLN where it is saved and a software register SUM is cleared 15 or set to 0 To be explained in more detail, the software register SUM is used to keep the accumulated length value which is stored into the GITBL and G 2 TBL.
During 58 through 512 the table Gl or G 2 is scanned for those entries which have not been processed as yet and therefore do not have an ending delimiter (ED), an accumulated length value (AL) and an entry length value (L) During the 20 scanning process the missing values are filled into the table, one at a time moving from the largest entry value to the smallest entry value.
To this end, 58 is now entered where the first entry in the table is checked to see whether it has been processed It will have been processed if the missing values have been filled in and this is determined by determining whether the ending 25 delimiter value is present in the table If the ending delimiter value is present in the entry of the table being checked, then a YES condition exists and the JOIN and S 11 are entered from 58 If, on the other hand, the ending delimiter value is missing and therefore the entry has not been processed, 59 is entered.
Register Rl is cleared to 0 during 57 and is used to store the maximum entry 30 value that has not yet been processed.
During 59 the entry number being scanned in the table is compared with the maximum entry number being saved in register Rl If the entry number from the table is greater, then a true condition exists and 510 is entered from 59 If the entry value from the table is not larger, a false condition exists and the SETUP 35 subroutine goes through the two JOI Ns to S 1 During 510 the table address of the new maximum entry number is saved from register R 2 in register R 4.
During S I register R 2 is set so it points to the next entry in the table Also the value representing the number of elements processed contained in register R 3 is decremented by one during 512 If the decremented number of elements value is 40 not equal to 0, then the SETUP subroutine returns through the JOIN to 58 where the next entry value in the table is checked to see whether it is the maximum entry value The loop through 58 through 512 is repeated until all of the elements in the table have been checked for maximum When the number of elements value in register R 3 has been decremented to 0, then 513 is entered following 512 45 During 513 the table address containing the maximum entry is contained in register R 4; the maximum entry value is contained in register Rl The SETUP subroutine now computes the number of reads necessary to reach the beginning and ending delimiters of the entry Since every entry in the layer has an ending delimiter, the number of reads is equal to the number of occurrences in the so delimiter line Thus, for example, if there are four entries, as depicted for entry 4 in Fig 108, there are five occurrences in the delimiter line One delimiter identifies the beginning of the data base and the remaining four delimiters mark the beginning of the four entries in entry 4 Therefore the number of reads necessary is obtained by taking the difference between the entry number and the number of 55 occurrences in line 0 and the result is stored into software register DNOC during 513.
During 514 the DCODEI subroutine and hence the DECODE I MODULE are repeatedly called, causing the DECODE I MODULE to provide the actual occurrence values from the delimiter contained in MEMORY MODULE area 1 60 and the number of elements value in register R 3 is decremented for each call until the content of register R 3 is 0 On each read the delimiter provided by the DECODE I MODULE is stored into software register TDI.
During 515 the ending delimiter is moved from register TD 2 into the second word of the table corresponding to the entry being processed This is actually done 65 281 1,570,344 281 282 1,570,344 282 during 515 where the MOV TDI, TD 2 instruction saves the previous beginning delimiter which becomes the current ending delimiter.
The length of the entry is then stored into the third word of the table corresponding to the entry being processed Also during 515 the difference is taken between the content of software registers TD 1 and TD 2 and decrementing this by 5 one, resulting in the length of the entry being processed The accumulated length from the beginning of the entry being processed is determined by adding the computed length to the content of the SUM software register The resultant content of the SUM register is-then the accumulated length value and is moved into the third word of the table corresponding to the entry being processed Thus during 10 515 the ending delimites the accumulated length value, and the entry length value are added to one of the entries in the table Gl or G 2 (see Fig 108).
516 is now entered where the length of the table (stored in software register WOLN during 56) is checked to see whether it is 0 If it is not 0, indicating that there are more elements in the table to be processed, a YES condition exists and 15 the SETUP subroutine goes back through the JOIN to 57 where the loop through 57 through 516 is repeated The loop through 57 through 516 is repeated for each of the remaining entries in the table thereby filling out the table When 516 is entered and WOLN has been decremented to 0, a NO condition exists and 517 is entered where the context of the MINI COMPUTER is restored back to that 20 existing when the PROCOUT program called the SETUP subroutine and the operation of the SETUP subroutine is exited.
Q GENERATE SUBROUTINE The PROCOUT subroutine calls the GENERATE subroutine during P 07 and PO 11 (see Fig 107) The GENERATE subroutine forms OLIST depicted at 2221 of 25 Fig 102 A and 2241 and 2245 of Fig 102 B using table G 2 The program listing for the GENERATE subroutine is shown in Appendix B-14 A flow diagram of the GENERATE subroutine is shown in Fig 110 Boxes Gl through G 22 depict the sequence of operation of the GENERATE subroutine The correspondence between the program listing and the flow diagram is depicted along the left hand 30 side of Appendix B-14 using the symbols GI through G 22 of Fig 110.
Consider now the sequence of operation during the GENERATE subroutine operation After being called, Gl of the flow is entered where the context of the MINI COMPUTER is saved so that it will return to the same state of the PROCOUT subroutine where entry to the GENERATE subroutine was made 35 During G 2, preparation is made to form a reference line in the MAIN MEMORY area known as WAREA The reference line in area WAREA is formed by taking the ending delimiter for a particular entry in table Gl or G 2 minus 1 and sequentially decreasing the value, forming as many decreased values as designated by the entry length for the corresponding entry in the table GI or G 2 The series of 40 decreased occurrence values are stored in WAREA These occurrence values are the occurrence values in the data base for the entry being processed Thus, for example, for entry 4 of Fig 108 the beginning delimiter 41 is decremented to form decremented possible occurrence value 40 and is subsequently decremented three additional times, forming the actual occurrence values 40, 39, 38 and 37 These 45 actual occurrence values are stored into WAREA This same process is repeated for each of the other entries in Table Gl or G 2 At this point the possible occurrence values are not in decreasing value order For example, using Fig 108 by way of example, possible occurrence values 40 through 37 would be followed by possible occurrence values 10 through 6 which would be followed by possible 50 occurrence values 24 through 21 which would be followed by possible occurrence values 17 through 15.
Therefore, G 4 of the flow is entered where the SORT subroutine is called and the possible occurrence values are sorted into a continuous string of occurrence values in descending order value 55 During G 5 the reference line is moved to DPM MEMORY MODULE area 2.
During G 6 software registers ENUMB and ESCAPE are cleared The address of OLIST is placed in register 2 (R 2) and the length of the reference line is moved to R 3 R 4 is set to point to LOET/L l ET depending upon whether this is a layer 0 or a layer 1 request The TST instruction steps R 4 past the pointer to the delimiter seed 60 header.
G 7 is next entered where the address of the seed header (LXET, i e, LOET for layer 0 or LIET for layer 1) is transferred to register RO and the address of the beginning of memory area WOAR is stored into register Rl.
282 1,570,344 282 At this point all occurrence values for the entries contained in Table G I or G 2 are contained in WAREA It is now necessary to find out which events have those occurrence values in the data base This is done using each of the events in the layer More specifically, this is accomplished by going down through the corresponding data base layer to find out if there is an actual occurrence value for 5 each event in the data base (at its line 0 or input line) corresponding to each possible occurrence value in WAREA The DEL function is utilized for accomplishing this task.
To this end, G 7 of the flow is entered where the seed header address stored in R 4 during G 6 is incremented and stored into register R O 10 During G 7 the number of the MEMORY MODULE area containing the event seed is stored into register RI During G 8 the current event # is obtained in the left byte of ENUMB During G 9 the OUTPUT subroutine is called causing it to perform the DEL function wherein the actual occurrence value present for each event identified by the reference line is determined The OUTPUT subroutine 15 returns a two word value, the first word being the number of the MEMORY MODULE area containing the output seed and this is stored into WOAR and the length of the result which is stored into WOLN.
G 10 is then entered where the length of the result stored in WOLN is checked.
If 0, no actual occurrence values exist in the data base in the reference line for this 20 event, causing JOIN 5 of the flow to be entered directly If the length of the result is other than 0, such actual occurrence values do exist, and G 11 of the flow is entered.
During Gl 1 a check is made to see whether the results are stored in MEMORY MODULE area I (this is true when register RI contains the value 1).
Again it is necessary to have the results in MEMORY MODULE area 1 in order 25 for the DECODE I MODULE to convert the hybrid coded form of the result to absolute coded form If the result is not in MEMORY MODULE area 1, a NO condition exists and G 12 of the flow is entered where the results are transferred to MEMORY MODULE area 1 and JOIN 2 and G 13 are sequentially entered If the results are already in MEMORY MODULE area 1, then a YES condition exists 30 and JOIN 2 and G 13 of the flow are sequentially entered.
During G 13 the DECODE I MODULE is initialized by moving the length of the result from the address designated by register Rl to LNI of the IPRF in the DPM INTERFACE MODULE and by setting DIINIT of the STATUS REGISTER to a I state 35 During G 14 through G 19, the results of the DEL operation are stored in association with the corresponding event number into OLIST, forming a series of two value pairs as depicted in Fig 108 During G 14 the DECODE I subroutine is called causing one absolute coded actual occurrence value to be provided from the hybrid coded result in MEMORY MODULE area 1 During G 15, EOFI in the 40 DECODE I MODULE is checked to see whether it is 1, or true, thereby indicating that the end of the result field has been reached, or whether it is 0, or false, thereby indicating that the end has not been reached.
Assume that the end of the file for the results has not been reached by the DECODE I MODULE and therefore G 16 is entered During G 16 the entry 45 number is stored on the left side of and in association with the actual occurrence value obtained during G 14 To this end, during G 17 the pair of values is stored in OLIST in the address specified by register R 2.
During G 18 the content of R 3, the total number of two value pairs to be stored in OLIST (originally stored in R 3 during G 6 (MOV WOLN,R 3), is decremented by 50 1 to indicate that one event has now been stored into OLIST Additionally a check is made to see whether the content of register R 3 is equal to or less than 0 If the content of register R 3 is equal to or less than 0, then G 19 is entered where the ESCAPE flag is set to 1 and the flow passes through the two JOINS back to G 14 If, on the other hand, the content of register R 3 has not been decreased to 0, and is 55 therefore greater than 0, G 19 is bypassed so that G 14 is entered directly The loop through G 14 through G 18 is repeated until during G 15, EOFI is 1 and therefore the end of file is detected at which time JOIN 5 and G 22 are entered.
During G 20 the ESCAPE flag is checked and if it has not been set to 1, a false condition exists, causing JOIN 1 and G 7 of the flow to be reentered This causes the 60 next event seed in the same layer to be obtained and processed as described above.
This operation is repeated until, during G 18, the content of R 3 has been reduced to 0, indicating that all entries in OLIST have been processed, in which case G 19 will be entered where the ESCAPE flag is set The following pass through G 20 will cause G 21 to be entered where OLIST is again sorted so that the two value pairs 65 1.570,344 283 283 are sorted in descending value order by event occurrence value OLIST will then contain a series of two value pairs (or bytes) the left one of which contains the event number and the right one of which contains the corresponding event occurrence value.
Tables GI or G 2 in conjunction with OLIST are then used to cause OLIST to 5 be printed out in the manner described hereinabove.
During G 22, context is restored and control returns to PROCOUT.
R SORT SUBROUTINE The SORT subroutine is called during G 4 and G 21 of the GENERATE la subroutine (see Fig 110) The purpose of a SORT subroutine is to sort the content 10 of OLIST so that the event occurrence values are ordered in descending value order It will be recalled with reference to Fig 108 that OLIST contains a series of word entries and each word entry contains a value pair (byte), the first of which is an event number and the second of which is an actual occurrence value from the corresponding layer of the data base 15 The program listing for the SORT subroutine is shown in Appendix B-15.
Fig 112 shows a flow diagram of the SORT subroutine Boxes SRTI-SRT 12 are shown in Fig 112 to identify the various steps in the SORT subroutine operation.
The correspondence between the SORT subroutine program listing and the SORT subroutine flow diagram is shown along the left hand side of Appendix B15 20 where the symbols corresponding to the boxes of Fig 112 are shown.
The sort is a bubble type of sort in that the content of OLIST is scanned, a value pair at a time, and when an event occurrence value is found in a value pair which is larger than that of a preceding one, that value pair is moved up in OLIST to the appropriate relative position 25 Referring now to the SORT subroutine flow diagram of Fig 112, during SRTI the context of the MINI COMPUTER is saved so that a return can be made to the GENERATE subroutine at the place where it was exited.
The GENERATE subroutine initially sets the register RO to the number of value pairs contained in OLIST which are to be sorted During the sort process the 30 SORT subroutine will be comparing a current occurrence value from OLIST with the next occurrence value in OLIST and therefore it is necessary to have a pointer corresponding to the next value in OLIST which is being compared To this end, during SRT 2 the length value in RO is decremented by 1.
The MINI COMPUTER register RI contains the beginning address of OLIST 35 (having been set there by the GENERATE subroutine During SRT 3, the beginning address of OLIST is moved from register RI to R 2 where it is saved.
Following SRT 3 the JOIN SRTJ 1 and SRT 4 of the flow are entered During SRT 4 the instruction CMPB(Rl),2 (R 1) (see Appendix B-15) causes the current and next occurrence value to be obtained from OLIST and compared If the 40 current occurrence value is greater than or equal to the next occurrence value, then the current occurrence value is in the correct position in OLIST and SRTJ 4 and SRT 1 O are entered If, however, the current occurrence value is smaller than the next occurrence value, then the next occurrence value is to be bubbled up or moved up toward the beginning of OLIST to its appropriate position Accordingly, 45 SRT 5 is entered where the address of the current occurrence value is moved from register RI to register R 3 where it is saved Subsequently, SRTJ 2 and SRT 6 are entered During SRT 6 the CMPB(R 3),2 (R 3) instruction causes the current and next occurrence values to be read from OLIST and compared It will be noted that when coming from SRT 4 and SRT 5 that the same two values will be compared 50 during SRT 6 If the current occurrence value is smaller, then SRT 7 is entered where an exchange takes place Specifically, the value pair including the current occurrence value and the value pair including the next occurrence value are interchanged in OLIST, subsequent to which SRTJ 3 and SRT 8 of the flow are sequentially entered If during SRT 6 the current occurrence value is equal to or 55 greater than the next occurrence value, then SRTJ 3 and SRT 8 are entered directly, bypassing the exchange operation of SRT 7.
During SRT 8 the pointer to the two value pair containing the current occurrence value in register R 3 is decremented by 1 and then SRT 9 is entered where the beginning of the OLIST pointer R 2 is compared with the decremented 60 value in R 3 to see if the sort has reached the top of OLIST If the current pointer in R 3 is equal to or greater than the beginning of OLIST pointer in register R 2, then SRTJ 2 and SRT 6 are reentered where the loop through SRTJ 2, SRT 6 through SRT 9 is repeated This loop is repeated until it is found that the current pointer in 284 284 1,570,344 1,570,344 register R 3 is greater than the beginning of OLIST pointer in register R 3 is greater than the beginning of OLIST pointer in register R 2 at which time SRTJ 4 and SRTIO are sequentially entered.
During SRTIO the current occurrence value pointed to by register RI is incremented by I to point to the next t in OLIST During SRTI I the length value in 5 register RO is decremented by I and if the result is greater than 0, SRTJ I and SRT 4 are entered where the loop through SRTJ 1, SRT 4 through SRTI I is repeated until the length value in register RO has been decremented to 0, indicating that every two value pair in OLIST has been processed When this occurs, SRT 12 is entered where the context of the MINI COMPUTER is restored to that existing in the 10 GENERATE subroutine at the time the SORT subroutine was called.
S PRINTR (PRINTER) Subroutine The PRINTR subroutine is called by any routine that requires an output to the printer The program listing for the PRINTR subroutine is depicted in appendix B-16 The flow diagram for depicting the sequence of operation is shown in Fig 15 113 The symbols PRNTRI through PRNTR 6 are used to identify the boxes in the flow diagram of Fig 113 Correspondence between the flow diagram and program listing is shown along the left hand side of the program listing of Appendix B-16 using the symbols for the PRINTR subroutine flow diagram of Fig 113.
Refer now to Fig 113 and the listing of Appendix B-16 As mentioned, the 20 PRINTR subroutine is called during P 012 of the PROCOUT subroutine The PRINTR subroutine expects a parameter which is the address of the message to be printed This parameter is stored immediately following the PRINTR call instruction JSR R 5 PRINTR The address of the parameter is contained in register R 5 25 The parameter immediately following the above mentioned instruction is the address of a message The message has two parts The first part of the message is one word in length, providing the length of the message in numbers of characters and the second part of the message are those ASCII characters to be printed out.
Initially, the context of the MINI COMPUTER is saved during PRNTRI, so that a 30 return can be made to the PROCOUT subroutine.
During PRNTR 2 the instruction MOV(R 5),+Rl causes the parameter (address of message) to be obtained and stored in register R 1 The instruction MOV(RI)+,R 2 causes the first word of the message, namely, the length of the message, to be read and stored in register R 2 35 turing PRNTR 4 a character of the message is printed out utilizing the MOVB(Rl)+,RO and JSR R 5, PRNTC instructions.
During PRNTR 5 the length of the message in register R 2 is decremented by 1 and, if the decremented length value is not 0, the JOIN PRNTJ I and PRNTR 4 are reentered The loop around PRNTJI, PRNTR 4 and PRNTR 5 is repeated until the 40 length value in register R 2 is decremented to 0 and, thus, all characters in the message have been output When this occurs the content of register R 2 will be 0, causing PRNTR 6 to be entered where the context of the MINI COMPUTER is restored to that existing in the PROCOUT subroutine at the time the PRINTR subroutine is called 45 The PRINTR subroutine is utilized by any module having a message to be output In all cases here the message was known at assembly time and is contained at the end of the program The PROCOUT procedure goes through OLIST and obtains a character to be output Since it is a single character, P 012 calls the PRNTC (print a character) subroutine directly 50 T PRNTC (PRINT A CHARACTER) Subroutine The PRNTC subroutine is called during PRNTR 4 of the PRINTR subroutine (Fig 113) and P 012 of PROCOUT subroutine and causes a character to be typed by the printer The printer in the operator console has a STATUS register 55identified by the symbol TPS (Teleprinter Status) and another register known as the TPB (Teleprinter Buffer).
Appendix B-17 contains the program listing for the PRNTC subroutine.
Since the subroutine is relatively simple, a flow chart is not shown and therefore reference should be made to Appendix B-17 for the following discussion 60 Initially the MINI COMPUTER determines whether the printer is ready to receive a character for printing To this end the instruction TSTB TPS causes the TPS register to be checked to see if it is ready to receive a character The printer monitors its status asynchronously When a character is placed in the TPB, the 285 1.570 344 ?RS 1 printer performs the mechanical task of printing the character When it completes this task it sets the DONE bit in TPS.
The instruction BPL -4 causes a branch back to the preceding instruction if the printer is not ready The tight loop between the first two instructions is maintained until the DONE bit in TPS is set When this occurs, the instruction 5 MOVB ROTPB is executed wherein a character is moved from the MINI COMPUTER register RO to the TPB register in the printer, causing the character to be printed The next instruction causes the PRNTC subroutine to be exited.
U GETC (GET A CHARACTER) Subroutine Appendix B-18 shows the program listing for the GETC (Get a Character) 10 subroutine Since the subroutine is quite simple, a flow diagram is not shown.
* Briefly, the GETC subroutine is called by the REQUEST subroutine, the FORMATER subroutine, GET INTEGER, GET FLOATING subroutines (see Fig 106) GETC is called whenever the program wants to obtain information from the keyboard The GETC subroutine obtains a character in ASCII code from the 15 typewriter of the operator console and causes the character to be printed by the printer for observation by the requester and sends an ASCII coded value, representing the character, to the MINI COMPUTER.
With reference to Appendix B-18, the operation is as follows: The typewriter or keyboard of the operator console has a register known as TKS (Teletype 20 Keyboard Status) and a register known as TKB (Teletype Keyboard Buffer) The instruction INC TKS readies the keyboard to receive a character from the requester by unlocking the keyboard so the requester can enter a character The instructions TSTB TKS and BPL 4 form a loop which causes the GETC subroutine to wait until the requester has entered a character on the keyboard of 25 the typewriter Once a character has been entered the system drops through to the loop formed by instructions TSTB TKS and BPL -4 where the system againwaits until the printer is ready to receive a character The waiting is done via the TSTB TBS and BPL 04 instruction loop When the printer is ready, the instruction MOVB TKB, TPB is executed which moves the character just entered on the 30 typewriter keyboard from register TKB to the printer register TPB where it is printed out and displayed for the requester The following instruction MOVB TKP, RO causes the same character to be transferred from register TKP in the typewriter keyboard to register RO in the MINI COMPUTER The instruction BICB #200, RO clears off an extraneous bit which is always set in RO but not used by the MINI 35 COMPUTER The last instruction causes the content of the MINI COMPUTER to be restored to the place in the REQUEST subroutine where it was left.
XXXIII HARDWARE/SOFTWARE ORGANIZATION FOR BUILDING LAYERED DATA BASE A Layered Data Base Structure 40 Typically the problem of storing and retrieving data has been made complex by the opposite demands of technology and economics Systems are typically structured with anticipated knowledge as to the structure of the retrieval request.
Any major deviation from this defined strategy usually results in chaos or at best ambiguity The solution to this problem is usually met with a costly and laborious 45 task of restructuring the data base to meet current demands.
By way of contrast with prior solutions, a data base structure according to the present invention has the following advantages: 1) less required physical space; 2) faster retrieval times; 3) unanticipated retrieval is handled with the same ease as anticipated retrievals; 4) ease of restructuring and updating; 5) ease of specifying 50 new retrieval criteria; and 6) ease of specifying and carrying out a process.
In order to provide a better understanding of the invention as it applies to the layered data base structure, consider a general overview as to how the present and prior art data base structures are derived.
As a working definition it may be stated: information retrieval deals with the 55 structuring and storing of large amounts of data which are in some way related so that any or all of this data can be retrieved at any time it is needed, with accuracy and speed.
Consider now the current data base structures and the data base structure according to the present invention in light of the aforegoing definition Regardless 60 of their physical characteristics, presently known data bases can be thought of as systems which conceptually transform input data into a linear event-time domain.
As each basic unit (e g, character, letter, number, or other symbol), called an 286 1,570,344 286 event, is entered into the system it is conceptually assigned a linear positional value which corresponds to the next state of some clock or sequentially ordering mechanism This concept of the prior art data base system is depicted in Fig 114.
With a data base conceived in this fashion, the problem of retrieving information can be related to the problem of answering the following question: Where in this linear sequence do the events of the request occur? If the ordering mechanism for the events in the data base is considered to be a clock, and the positional values are considered as clock times, the question becomes: At what clock time in the sequence do the events of the request occur? The question can be answered by linearly searching the data base until the response to the request is found With 10 large data bases this approach violates the preceding definition that information is to be retrieved with speed.
One way to achieve speed is to skip down through the current data base and search those areas where a response seems likely This has been done by adding inverted index files for various key words to the data base The key word files 15 enable the data base to be searched much more quickly than in a linear search The disadvantage of this approach is that the request must contain a system of key words This means that the data base organizer has to know in advance what the requests on the data base will be and from this knowledge he must derive the words to be used as key words and from this create key word files 20 There are other disadvantages If requests to the data base change (i e, are unanticipated), then the total system has to be recreated so that new key word files can be made This process is costly and time consuming.
The layered data structure according to the present invention extends the concept of an inverted index (key word) file The right hand side of Fig 115 25 illustrates an example of a data base in accordance with the present invention in which each horizontal line represents a different event, whereas the order of occurrence of the events in each line are identified by the value of the numbers in each line The numbers correspond to the clock (or ordering mechanism) at the bottom Thus, in contrast to the ordering of data depicted in Fig 114, a data 30 structure according to the present invention is organized into a collection of inverted index files as depicted in Fig 115 Each file then need only contain positional or time information.
Advantages of this type of system are as follows: 1) only those events (e g, letters or words) which are stated in the request need to be searched; as a result, a 35 relatively small portion of the data base needs to be searched for any one request, resulting in reduced search time; 2) the clock positional values of the events (also called event occurrence values) can be compared with each other until a sequence which is exactly like the request is found, or if desired, until a sequence is found which is “almost” like the input request This feature allows retrieval by context 40 According to the present invention a response to a request must be regenerated before it can be output The regeneration process involves finding those events whose clock values are sequentially ordered over some range.
However, any disadvantage of this requirement is far outweighed by the increase in speed, the ability to handle unanticipated requests, and the ability to respond from 45 context (e g, inexact response).
Consider now the example depicted in Tables 2 A and 2 B Assume that the sentence “THIS IS A TEST” is to be entered into the data base As depicted in Table 2 A, a clock is initiated so that the event time values generated thereby correspond to the input events as they are entered into the data base Table 2 B 50 depicts each event in the example of Table 2 A in an inverted index file Each inverted index file is called an event time sequence.
Thus, Table 2 B depicts a data structure in accordance with the present invention which completely inverts the input This provides the invention with speed of retrieval, allows unanticipated requests, and allows inexact responses to a 55 request.
As a result, the preceding question: “At what clock time in the sequence do the events of the request occur?” can now be answered by asking the question: “At what clock times did the event occur?” for each event in the request and from this, derive a response The basic data structure depicted in Table 2 B is referred to 60 herein as a layer.
A further way in which the present invention speeds up a search is to store only new information If information being entered into the data is already contained ill the data base there is no need to store it again Therefore, according to the present invention, a hierarchical structuring of layers is employed which will permit 65 287 I 1.570,344 287 redundancy to be squeezed out from the input data In this way the information is compressed, less physical storage is used, and less search time is required to retrieve data Such an arrangement is depicted by way of example in Tables 60 B and 60 C described hereinabove.
From the foregoing description of a layer, a layer can be viewed as a collection 5 of event time sequences The clock sequence for each event contains only the clock values, indicating when the corresponding event has occurred.
(Note by way of example, Table 2 A) Another way of viewing the layer is as a two dimensional matrix whose rows (lines) are the primative events associated with the layer and each column of which 10 is associated with a clock (or, as described hereinabove, an event occurrence value) Whenever an event occurs, a binary 1 is shown in association with the proper row and column (see Table 2 A).
A layer can then be considered as a “map”, giving the sequence of events as they were entered into the data base These sequences are broken into groups 15 called “entries” so that by monitoring the input stream of data, it is possible to determine when redundant data are entered To this end, a “group separator”, called a “delimiter”, is introduced into the data stream as a special character.
Delimiters may be natural, e g, spaces between words in a contextual data base.
They may also be artifical, for example, separating source statements in a computer 20 program Delimiters break the layer into “groups” or “entries” which consist of a sequence of events between delimiters.
When a second layer is introduced it has “events” which are “entries” in the first layer and whose clock values change (or tick) only when a delimiter is recognized for the first layer Consider the first layer as layer 0 and the second layer 25 as layer 1 The input stream of data is monitored and a current sequence of events between delimiters on layer 0 is obtained Layer 0 is checked to see if the current sequence of events has already been entered into the data base If it has, it has a corresponding line containing an event number in layer 1 Therefore, the next sequential clock time for layer I is added to the event time sequence for the current 30 sequence of events If the current sequence of events does not exist in layer 0, it is added as an entry (i e, clock value in one or more event lines) into layer 0 and the entry is then added as a new line and event number in layer 1.
As a result it will be seen that only unique entries are entered on layer 0 and these correspond to events on layer 1 Thus a redundant sequence of events on 35 layer 0 is added as a simple clock value on layer 1 The sequence has squeezed into a single clock value that which normally would require a sequence of clock values This process can also be reversed Thus each event in layer 1 is completely described by a sequence of events on layer 0.
Also, the concept of the invention can be extended to include delimiters to 40 squeeze out redundancy on layer 1 Thus, layers 0 and I identify letters and sentences A layer 2 could be added to identify paragraphs or chapters, etc The process is recursive and need only stop when there is no more redundancy that can be squeezed out from the system The result of this process provides a hierarchical ordering of layers bound together by delimiters which attach the entries of a lower 45 layer to events on the next higher layer These delimiters then can be considered as the glue which holds the layers together Delimiters may be implicit in that the Nth entry of a layer may implicitly point to the Nth event on the next higher layer It should also be noted that no pointer storage is needed Additionally, delimiters may be explicit in that there may be a table which relates each entry on a layer with 50 events on other layers The structure of this table can vary from a simple pointer table to a layer itself.
It should further be noted that the primitive events which make up the lowest layer are not limited to a literal string but could also be a process to be perfomed.
These basic processes can be layered in the same manner as that described above 55 Very complex manipulative processes can be described easily and with no change to the basic structure on the data base Therefore, a request might trigger a contextual response or trigger a process for perform some task.
With the foregoing general description of layered data base structure in mind, consider the definition of layers in more detail This will be done using the above 60 mentioned event-time relationship.
Each line or event in a layer consists of an event-time sequence in that it is an ordered set of values which are homogeneous and represent a clock A layer is a fully formed collection of all of such event-time sequences which is ( 1) isosynchronous, i e, each row is a binary sequence and the occurrence of any event 65 288 1,570,344 288 is a clock time for all entries, and ( 2) open ended, i e, it can be expanded.
Ordering is contained in the concept of layering Consider the example of two layers A and B. 1 Layer A is immediately superior to layer B if an event on layer A is elaborated by a uniquely defined sequence on layer B 5 2 Any occurrence of an event “a” on layer A implies the same more detailed sequence b M,, bj 2, -, bik on a layer B Note also that layer B is inferior to layer A.
3 Layer A is totally superior tb layer B if all the events on layer A are elaborated on layer B. 4 Layer A is partially superior to layer B if only a subset of the events on layer 10 A can be elaborated on layer B, e g, events “a 1,,2 an E A” could be elaborated by layer B while “a-+ 1, an+ 2 an+m E A” are elaborated by layer C.
Layers can be nested so that layer A is totally superior to layer B, which in turn is totally superior to layer C, i e, layer A requires that layer B be defined.
Layer B requires that layer C be defined 15 6 There are primitive layers which have event tokens which are primitive to the total system, e g, in text system literals (letters, numbers, punctuation) are picked off the lowest layer Primitive events can be (i) bit strings, which are the events, (ii) actions to be performed (processes).
7 An event can be primitive at different levels in this system: (i) it can be 20 primitive to the interpreter that is elaborating the events on this layer, i e, primitive within the concept of their interpreters; (ii) the event can be totally primitive, i e, no interpreter in the total system can elaborate on it further.
8 Delimiters are connected with the various interpreters and are the “glue” that binds one layer to another This binding can be implicit, e g, entry “n” on an 25 inferior layer relates to event “n” on the superior layer The binding can also be explicit, e g, a table which relates entry “i” on the inferior layer to event “j” on the superior layer Delimiters also aid in defining the scope of an interpreter in which events are primitive to this layer.
Consider now a specific example of the layered data base according to the 30 present invention In the data base the four major data base structures which need to be considered are as follows: First the layered data base itself which is depicted in Fig 116; Second the structure of certain conversion tables known as CVRTBL and CVTBL 2 which are depicted in Fig 117; Third, ESTAK, the event stack, which is depicted in Fig 118; Fourth, the available space and free space and their 35 management associated with the main memory storage area.
Consider now the details of the layered data base structure as depicted in Fig.
116 the layered data base structure of Fig 116 is similar to that depicted in Figs 78 and 79 but it is more complete as noted hereinafter In the example, the layered data base has two layers, layer O and layer 1 Each layer has a layer header pointed 40 to by a pointer which, in the case of layer 0, is LOPTR, and in the case of layer 1, LI PTR Each layer header contains four words of description as follows: the first.
word LOET layer 0, L 1 ET -layer 1) points to the address of the corresponding layer event pointer table; the second word contains the iso-entropicgram width (HWO layer 0, HWI layer 1) of the corresponding layer; the third word 45 contains the number of events (NEO layer 0, NEI layer 1) associated with the corresponding layer; and the fourth word contains the current tick value of the clock (TIKO layer 0, TIKI layer 1) associated with the corresponding layer.
By way of example, layer O has 128 events corresponding to the 128 different possible ASCII coded characters Additional events could be introduced by 50 expanding the number of bits in the characters Layer I contains 256 events, by way of example Referring to the event pointer tables, the layer O event pointer table contains a pointer for events I through 128, plus a delimiter plus a null seed, on layer 0, and the layer 1 event pointer table contains a pointer for events 1 through 256 on layer 1, plus a delimiter plus a null seed for layer 0, LOET is an address 55 pointer to the address containing the pointer for the layer O delimiter, whereas the immediately preceding address contains an address pointer to null seed For layer 1, LI ET is an address pointer to the address containing the pointer for the layer 1 delimiter whereas the immediately preceding address contains an address pointer to the null seed To be explained in more detail, it is possible for a request to be 60 made to the data base using a request event that the layered data base does not contain When a request is made for an event not contained in the data base, the request is simply directed to the pointer at LOET minus I for the null seed.
Similarly, when requesting information from the data base there are times when no 289 I 1.570,344 289 layer 0 entry passes the closeness of fit criteria When this is the case the null seed is substituted for the requested word.
The address pointers for event 0 in the layer 0 and layer 1 event pointer tables, respectively, point to the seed headers for the layer 0 and layer 1 delimiters For purposes of explanation, the layer 1 event pointer table contains pointers for 256 events This is the maximum number of events possible for the 8 bit wide data structure assumed for the DPM SYSTEM shown by way of example herein.
A IK storage area is reserved in main memory for seed headers As a new event is assigned to either layer 0 or layer 1, formation of a new seed header is initiated for the new event To this end a pointer word identified by the symbol 10 NXTSH (next seed header) points to the beginning of the new four word area which is available for a seed header After the next four words are utilized for a seed header, the pointer NXTSH is advanced forward by four words so that it points at the next available four words for a seed header The seed headers, once they are created, are not destroyed in the program described herein However, 15 such a feature may be desirable and may be incorporated into the program within the scope of the invention herein.
The main memory area for storage of the seed lines generally depicted along the right hand side of Fig 116 will now be described The seed lines are stored in a storage area for seeds in main memory This can easily be extended to DISK space 20 using conventional disk management and transfer techniques The seed lines are so stored in the order the need arises for storage of each As a result the seed lines for layer 0 and layer 1 are intermixed in the seed line storage area Each event seed line or delimiter seed line is pointed to by a corresponding event seed header or delimiter in the manner described hereinabove with respect to Figs 78 and 79 The 25 structure of the seed headers is depicted in and described above with reference to Figs 78 and 79.
As new seed lines are created and old seed lines are eliminated, storage is not modified immediately by moving the old seed lines out and compressing storage.
Instead, there is a linked list of free space areas available in a storage area called 30 “free space” Each free space area has an address pointer to the next free space area As a new seed is to be entered into the data base a check is made through the linked list of free space areas to see if the new seed line can be entered in any one of the free space areas The last free space area has a pointer to a memory area known as “available space” (the amount of main memory core left for needs) The free 35 space and the free space pointer list will be described in more detail in connection with the description of the data storage structure However, “free space” as used herein refers to the main memory area which has been vacated by seed lines which are no longer used, and “available space” refers to the area in which no seed line has yet been stored 40 Consider now the structure and content of the tables CVRTBL and CVTBL 2 depicted in Fig 117 Table CVRTBL is used for converting ASCII coded characters to event numbers on layer 0 Table CVTBL 2 is used for converting layer 0 event numbers back to ASCII coded characters CVRTBL contains layer 0 event numbers and the ASCII coded characters are used as an address index into table 45 CVRTB, As described hereinabove with respect to the FORMATER program, when an input character is received from the operator console, the binary equivalent of the octal number 200 is subtracted from the character to form an ASCII coded character To convert an ASCII coded character to a layer 0 event number, the ASCII coded character is added to the base address CVRTBL and the content 50 of the resultant address is the corresponding layer 0 event number Table CVTB 1 L 2 contains ASCII characters and the layer 0 event numbers form an index into table CVTBL 2 To convert a layer 0 event number to the corresponding ASCII character, the layer 0 event number is added to the base address CVTBL 2 and the content of the resultant address is the corresponding ASCII character 55 Consider now the way in which tables CVRTBL and CVTBL 2 are formed.
With reference to Fig 116 it will be recalled that the address LOET minus one is the address of the pointer for event -I which in turn points to a null seed header.
Initially the entire content of CVRTBL is initialized by storing the event number -I in each of its storage locations Additionally, table CVTBL 2 is initialized so 60 that each of its locations contains an ASCII coded value representing the symbol The symbol is used herein as an invalid character A software event counter formed by NEO in the layer 0 header IS used to count the new events (in ASCII code) as they are received and entered into the data base.
The event counter forms the event numbers on layer 0 65 290 1,570,344 Can 291 1,570,344 291 When entering information into the data base it is first determined whether the received ASCII character is a new character and therefore has not been entered into the data base If it is a new character, the ASCII coded value is added to the location in table CVTB L 2 whose address is determined by adding NEO to the base address CVTBL 2 New characters are determined as follows: a received ASCII 5 character is added to base address CVRTBL of the table CVRTBL and the content of the resultant address in CVTRBL is checked for a negative number If negative, it indicates that the current ASCII character has not yet been added into the data base and the event number indicated by the event counter is stored into the addressed location of CVRTBL As the event number is added to a particular 10 storage location of CVRTBL, the corresponding ASCII coded character is added to the storage locations of CVTBL 2 whose address is CVTL 2 plus the event number (i e, NEO) and a corresponding new seed header is made up for the particular event If the received ASCII character was previously entered in the Table CVRTBL, the content of the address location in CVRTBL is positive (since 15 all layer 0 event numbers are positive) and the aforegoing table storage process is skipped.
When outputting a layer 0 event number, the corresponding ASCII coded representation can be obtained simply by adding the event number to the base address, CVTBL 2, of table CVTBL 2 to form the address of the corresponding 20 location from which the corresponding ASCII coded character can be read.
Consider now the structure of ESTAK as depicted in Fig 118 The manipulation of ESTAK has been considered in connection with the FORMATER and related programs ESTAK is a stack into which all of the event numbers of a request are pushed as they are received into the system The number of events 25 pushed into ESTAK are counted by the software registers RI-NO and RLN I Thus, once a complete word (i e, a series of tokens or letters between two delimiters,,6) has been entered into the system, the total number of layer 0 event numbers pushed into ESTAK will be reflected by RLNO With reference to Fig 118, Example a, TOS is the top of stack pointer for ESTAK, whereas RLNO represents the number of 30 layer 0 event numbers in ESTAK, and RLNI represents the number of layer 1 event numbers in ESTAK and both are initially set to 0 Example b assumes that four layer 0 event numbers have been stored into ESTAK at which time RLNO will contain the value 4.
Once the ending delimiter ( 6) is encountered, a complete entry is contained in 35 ESTAK The event numbers making up the entry in ESTAK are then processed using the PIPE program (discussed above) to determine whether the entry (i e, the sequence of tokens or event numbers) has been encountered and hence stored into the data base If the sequence has been encountered before, an event number on layer 1 is returned which represents the sequence of event numbers in question If 40 the particular sequence of event numbers in question If the particular seqeunce of event numbers has not been encountered before, then the sequence of event numbers on layer 0 are entered into layer 0 and they are assigned the nextsequential entry number on layer I which in turn is stored at the top of ESTAK.
This is depicted at Example c in Fig 118 where event 11 is depicted, the first ” 1 ” 45 representing layer 1 and the second “I” depicting event number 1 on layer 1 The corresponding sequence of event numbers on layer 0 are removed from ESTAK by reducing the value represented by RILNO by the number of layer 0 event numbers and increasing the count in RLNI by 1 In this way a series of events such as letters making up words may be entered as a sentence into the data base structure 50 When the ending delimiter # for a sentence is encountered, register RLNI will represent the number of layer I entries in ESTAK then added to layer I of the data base To be explained in more detail, the entries are added to the data base using the CHANGE subroutine.
Consider now the structures and general principles of maintaining available 55 space Fig 119 A depicts the available space or storage area for seed lines When a seed line is computed, it is placed in available space and the first word in the seed header (corresponding to the seed line) is adjusted so that it becomes a pointer to the beginning address of the seed line It will be recalled with reference to Figs 78 and 79 that the third word in the seed header contains the length of seed (in words) 60 During the course of changing seed lines a new seed line may be computed which is less than or greater than the old seed line in length Hence the storage space for the old seed line will not be exactly the same as that required for the changed seed line To provide for this possibility a linked list called the “freespace pointer list” is provided whose beginning is identified by a software pointer FSP This list 65 contains an ordered set of pointers for free space Each area of free space consists of two header words and a free section The first of the two word headers is a pointer to the next link in the list (as depicted by arrows in Fig 119 B), and the second is the length of the corresponding free space section As space is created from available space for a new seed line, the length of the space required for the 5 new seed line is incremented by two words for the two header words This is quite important as it saves processing time when trying to determine if a new seed line can be added in a particular free space section.
Refer now to Fig 119 C and consider the general procedure for adding a seed line entry to the free space list Assume that originally, link A points to link B which 10 in turn points to the next link in the list Also assume that a new section C is to be added to the linked list The free space section C which is to be added has a beginning address which is greater than the address of section A but less than that of section B In order to keep this in the ordered list it is only necessary to juggle pointers so that the address of link C is placed in link A and the old link that was in 15 A is placed in link C The dashed lines indicate the condition prior to the addition to section C whereas the heavy lines indicate the changed condition.
Refer now to Fig 119 D and consider the general operation when data is added to a free space area Example a of Fig 119 D depicts the condition before the seed line in inserted As depicted, link A points to link B which in turn points to link C 20 Assume for purposes of explanation that a portion of section B is to be taken for a new seed line It is assumed that the sections containing links A, B and C contain length values 4, 8 and 5, respectively Also assume that the new seed line requires a length of five words which will leave in free space three words plus the two word header Thus when the new seed line of five words is placed into the section 25 containing link B, link B does not disappear from free space but in effect is shifted to the right as depicted at B. “Free space”, as discussed above, is the linked list of free areas which have been vacated by seed lines “Available space” is the area in main memory where no seed lines have yet been stored 30 A function described herein as “GARBAGE COLLECTION” will now be discussed Once the free space gets above a certain length in words it is necessary’ to compress the storage area so that all of the free space is returned to available space The following discusses this operation.
Fig 119 E at a depicts an example of the main memory storage area prior to 35 garbage collection Note that free space includes linked free space sections of 5, 4, and 7 words in length and available space separated by seed line storage sections of A 2, A 3 and A 4 The free space sections can be considered as a linear list from left to right starting at pointer FSP A pointer Pl is depicted pointing to the link in the first free space section and a pointer P 2 pointing to the beginning of the seed line 40 section A 2 The general operation is to shift the entire seed line storage area to the left until the free space sections are eliminated and placed into available space The first step is to shift the free space storage between Pl and P 2 to the left In this process all seed line sections whose starting address is greater than pointer Pl will have new starting addresses which are shifted to the left by an amount equal to the 45 length of the first free space section In this first step, pointer Pl is moved from its current position to the right by an amount equal to the length of A 2 and pointer P 2 is moved from the seed section A 2 to the beginning of the next seed line section A 3 as depicted in b of Fig 119 E While the seed headers have been adjusted, not all of So them point to meaningful data since only a portion of the data base has been shifted 50 to the left.
This process repeats for the next free space section of length 4 The result is depicted at c of Fig 119 E where the seed line section A 3 is moved to the left adjacent seed line A 2 and freed sections of lengths 5 and 4 are added together as depicted at “freed section” This process is repeated until all free space is 55 eliminated and returned to available space and the free space pointer FSP has been set to the beginning of available space The seed headers are adjusted for the new location of the corresponding seed line sections and therefore point to the new starting addresses for their corresponding seed lines The result is as depicted at d in Fig 119 E 60 B Data Base Program, Level 1 The DATA BASE program level I performs the major functions of the DATA BASE program which are: initialization, layer building which builds the data base described above, and request on the data base, which has been discussed in more 292 I 1,570,344 292 detail in connection with the FORMATER program Initialization prepares the data base to receive input by priming tables and headers.
Its functions are:
1 Initialize CVRTBL with a negative number which will correspond to the NULL seed 5 2 Initialize CVTBL 2 to all “‘” representing invalid characters; 3 Initialize layer 0 header and place first entry in delimiter seed; 4 Initialize layer I header and place first entry in delimiter seed; Initialize NULL seed; 6 Initialize seed header pointer (NXTSH) and free space pointer (FSP); 10 7 Initialize the globals: LNGSW, ESCAPE, PW, BVCO, ESTAK.
The DATA BASE program sequences the entire data base operation from initialization through layer building for subsequent use in handling of requests.
The program code for carrying out the DATA BASE program operation is set forth in Appendix B-22 Fig 121 is a DATA BASE program flow diagram and 15 depicts the overall sequence of operation thereof Symbols DB 1 0 through DB 12 0 are used The correspondence between the program code and the flow diagram is shown in Appendix B-22 where the symbols corresponding to the blocks of the flow diagram are shown for the corresponding code.
Consider now the operation of the DATA BASE program making reference to 20 Fig 121 The DATA BASE program is loaded and executed by the user He does this by instructing the system to bring the DATA BASE program into core of main memory and execute it.
During DB 1 0 of the flow diagram the context of the registers in the MINI COMPUTER are stored for a return to the operating system During DB 2 0 the 25 ENDFLAG switch is reset to 0 for subsequent use during DB 9 0, DB 11 0 of the DATA BASE program to indicate the end of the DATA BASE program and for proper control during DB 11 0 of the DATA BASE program flow, JOIN 1 and DB 3 0 of the flow are entered During DB 3 0 the instruction JSR R 5,PRINTR is executed causing the PRINTR subroutine (discussed above) to be 30 called which causes an ASCII coded character to be sent to the printer, representing a A The + signals the user that the system is ready to process a command.
Control then goes to DB 4 0 of the flow where a command character is read from the keyboard The user has the option of entering an “I” representing 35 initialization, an “A” indicating data is to be appended to the data base, or an “R” indicating a request is to be made to the data base, or an “E” to indicate an end of session Any other entry by the user at the typewriter of the operator console is considered an error.
The character is obtained from the typewriter utilizing the GETC sub 40 routine discussed in connection with the FORMATER program and related subprograms.
DB 5 0 of the flow is next entered where the character just read during DB 4 0 is checked to determine the type of character For this purpose a series of comparison statements are employed 45
First a comparison is made for the character I (INITIALIZATION) To this end the CMPB RO,I instruction is executed causing the character just read and stored in register RO to be compared against the stored representation of the character I If the comparison results in equality, the instruction BEQ + 2 causes the DATA BASE program level 1 to enter DR 6 0 of the flow and thereby enter the 50 initialization block of the DATA BASE program.
If the comparison results in an inequality, the instruction JMP TBLM causes the program to jump to TLBM of the program where the instruction CMPB RO, A, BEQ + 2 tests to check if the character is an A and hence the layer building block (DB 7 0) portion of the program is to be executed If an inequality results the 55 instruction JMP TREQ causes a jump to TREQ.
Here the character is checked for an R by the instruction CMPB R 0,R and if it is control goes to DR 38 0 where a subsequent request presented by the requestor is processed Note that the character R represents a request and calls the operation of the FORMATER program discussed above If not an R, the instruction BNE 60 TEND causes a jump to TEND.
Here the character is-checked for an E on the instruction CMPB RO,E and if it is control goes to DB 9 0 of the flow where the instruction JSR R 5, PRINTR is 293 I 1,570,344 293 executed, calling the operation of the PRINTR subroutine which in turn causes the message “ND” to be output following the character “E” on the printer and the ENDFLAG is set to 1 which will cause DB 12 0 to be entered following DB 11 0 of the flow.
If during DB 4 0 a lack of comparison is detected, (i e, the character is one 5 other than I, A, R or E), DR 10 0 of the flow is entered where the PRINTR subroutine is called causing the message ERROR MESSAGE to be printed out by the printer.
Following DB 6 0, DB 7 0, DB 8 0, DR 9 0 or DRB 10 0 of the flow, JOIN 2 and DB 11 0 of the flow are entered where the ENDFLAG is checked If it has been set 10 to 1, which occurs when the user has entered an E during DB 4 0 of the flow, the instruction TST ENDFLAG detects this condition and will cause a jump to DB 12 0 of the flow where the context of the MINI COMPUTER is restored and the operation of the flow is exited If during DB 11 0 the TST instruction determines that the ENDFLAG has not been set to 1, JOIN 1 and DB 3 0 of the flow will be 15 reentered where another +,B is output to the requestor allowing him to enter another command character which will be read during DB 4 0 of the DATA BASE program, level 0 flow.
C Layer initialization Program, Level 2 Consider now the program which is called into operation during DB 6 0 of the 20 DATA BASE program flow diagram of Fig 121 The LAYER INITIALIZATION program is called into operation and initializes the data base to accept input data.
The LAYER INITIALIZATION program is a level 2 program and the code is depicted under the heading LAYER INITIALIZATION BLOCK of Table B-22.
The LAYER INITIALIZATION flow is shown in Fig 122 The blocks of the flow 25 are identified by the symbols DB 6 O through DB 6 12 The correspondence between The LAYER INITIALIZATION program code and the blocks of the flow diagram is depicted in Appendix B-22 using the symbols of the flow.
As described above, if during DB 5 0 of the DATA BASE program (Fig 121) a command character of I is detected, DB 6 0 is entered where the LAYER 30 INITIALIZATION program is called into operation During DB 6 1 of the LAYER INITIALIZATION flow of Fig 122, the instructions JSR P 5,PRINTR and WORD INITMSG are executed, which cause the message INITIALIZE to be output and printed by the printer for observation by the user Subsequently, DB 6 2 of the flow is entered where each of the entry locations in Table CVRTBL is set to -1 to 35 identify empty locations (see Fig 120) This is accomplished by the instruction MOV #2,Rl which causes a 2 to be placed in register Rl and the instruction NEG Rl which causes Rl to be negated and thus contains a value of -2.
A word of explanation as to what a -2 is stored rather than a -1.
Logically it is desired to address the location which is one word (-1) before address 40 CVRTBL However, since the PDP-1 1 is a byte addressable machine and since one word contains two bytes, the location is addressed which is two bytes(-2) before CVRTRL Thus the entries in CVRTBL are initialized to -2 The flow charts show -I since that is logically what is happening.
During DB 6 3, an ASCII character representing a is stored in each of the 45 storage locations in Table CVTBL 2 The is used to denote a presently undefined character in CVTBL 2 (see Fig 120).
NXTSH is a pointer which points to the beginning of the available storage in main memory area reserved for seed headers (see Fig 116) During DRB 6 4 of the LAYER INITIALIZATION flow of Fig 122, the software pointer NXTSH is 50 initialized or set to an initial value represented by the beginning address SEEDHDR.
Referring to Figs 78 and 116 it will be recalled that the layer 0 header is four words in length and contains the indicated items of information During DB 6 5 of the flow the four words of the layer 0 header are initialized as follows: MOV 55 LOPTR,R 1 moves the base address of the layer 0 header into register Rl: MOV #LOET, (RI)+ moves the address of the layer 0 event table into the first word of the layer 0 header whose address is identified by register Rl and then increments the address; the two instructions MOV #1,(Rl)+ cause the next two words of the layer 0 header representing the iso-entropicgram width (HWO) and layer 0 event number 60 (NEO) to be set to 1; CLR (Rl)+ sets the layer 0 event-time count TIKO to an initial value of 0.
During DB 6 6 a seed header and a seed line are generated for the layer 0 delimiter The instructions operate as follows: MOV NXTSH, LOET moves the 294 I 1,570,344 294 address pointer to the next available seed header to the first word in the layer 0 event table (LOET) and MOV NXTSH,RI saves the same address in register RI:
ADD #10,NXTSH adds 10, = 8,0 to the address in NXTSH to bypass 4 words (each 2 bytes long) which are required for a seed header; AS is an address pointer to the available space for seed line storage and MOV #AS,(RI)+ moves the address to the 5 first word of the delimiter seed header The address in RI is then incremented to the next word (for the line number of seed) in the seed header; CLR (RI)+ sets the line number of the delimiter seed line to 0 and increments the address in RI to the next word (length of seed) in the delimiter seed header; MOV A, (RI)+ moves a I into the length of seed word of the delimiter seed header and increments the 10 address in RI to the address of the fourth word (no of occurrences in line); MOV 1,(R 1) moves a I into the number of occurrences in line word of the delimiter seed header, CLR AS sets the first event-time occurrence value in the delimiter 0 seed line to 0.
During DB 6 7 of the flow the four words of the layer 1 header are initialized 15 similar to that described for the layer 0 header at DB 6 5 At DB 6 8 the seed header and seed line for the layer I delimiter are generated in a similar manner to that described hereinabove with respect to DB 6 5 for the layer 0 header.
During DB 6 9 a null seed header for nonexistent events is formed To this end an address pointer to the null seed header is stored into the location for the -I 20 entry pointer in the layer 0 event pointer table and the -1 entry pointer in the layer 1 event pointer table and a null seed header is formed.
MOVNXTSH,RI stores the next available seed header address in Rl; ADD #10,NXTSH updates the pointer to the next available seed header; MOV RL LOET-2 puts seed header address in proper LOET word; 25 MOV RI Ll ET-2 puts seed header address in proper LIET word; CLR (Rl)+ CLR (Rl)+ creates the null seed header by setting all entries to 0.
CLR (RI)+ CLR (RI)+ j 30 During DB 6 10 the free space software pointer FSP is initialized so that it points to the beginning of the available space used for storing seed lines using the instruction MOV #AS + 4,FSP In addition, the first word of available space is set to 0 using the instruction CLR j FSP Thus the FSP will subsequently be used as the head of a linked list which will arise when storing seed lines into the available space storage 35 area As new seed lines are added and old ones are removed, the free space pointer FSP is used to form a chain, keeping track of all unused space within the storage area.
During DB 6 11 certain globals are initialized which are subsequently used when the PIPE PROGRAM is called To this end a literal value of I is stored into 40 the software register LNGSW and the software registers ESCAPE and PW are reset to 0 In addition the instruction LDCIF causes a value representing the brightness cutoff value of 10000 to be stored into floating software register ACO and the instruction STF AC 0,BVCO causes the value to be transferred from floating register ACO to software register BVC O 45 During DB 6 12, ESTAK is initialized by storing the address of the beginning of ESTAK into register R 3 R 3 is subsequently used as the top of stack pointer for ESTAK Subsequently, the operation of the LAYER INITIALIZATION flow is exited.
D LAYER BUILDING PROGRAM, LEVEL 2 50 The LAYER BUILDING program is a level 2 program which operates during DB 7 0 of the DATA BASE program flow of Fig 121 The LAYER BUILDING program creates layers as they are needed, augments old entries in a layer, and manipulates storage as old seeds are replaced by new ones.
The programming system disclosed herein is designed to create a two layer 55 system, i e layer 0 and layer 1 It will be understood that the building of additional layers is contemplated within the scope of the invention herein.
The program code for the LAYER BUILDING program is depicted at DB 7 0 et seq of the listing of Appendix B-22 Fig 123 shows the LAYER BUILDING I 1,570,344 295 295 program, level 2, flow diagram The flow diagram contains blocks identified by the symbols DB 7 0 through DB 7 11 to identify the various flow blocks The correspondence between the program code and the flow diagram is shown in Appendix B-22, using the symbols for the flow diagram.
The LAYER BUILDING program operation is called when, during DB 5 O of 5 the DATA BASE program (see Fig 121) an “A” command leter is detected.
During DB 7 1 of the LAYER BUILDING program flow the instructions JSR R 5.PRINTR and WORD APPMSG cause the message APPEND to be typed out on the printer of the operator console to indicate to the user that he may now enter new data or modify old entries in a layer of the data base 10 During DB 7 2 of the flow the EXIT flag LBXIT for the LAYER BUILDING program is cleared or reset to 0 During DB 7 3 and DB 7 4 the following actions take place The instructions JSR R 5,PRINTR and WORD BGNMSG cause the PRINTR subroutine to provide the characters #6 to the printer, causing the symbols X 6 to be printed followed by a blank The two instructions MOV 15 LI ET,-(R 3) and MOV LOET,-(R 3) cause the two consecutive locations in ESTAK beginning with the address originally in R 3 to be filled with seed header addresses representing the beginning delimiters “#6 ” for layer 0 and layer 1 The instructions MOV #l,RLNI and MOV #l,RLN O set the software registers RLNI and RLNO to 1, representing one event on layers 1 and 0, respectively 20 Since the program is about to append information to the data base, it is assumed that it is starting with a new sentence A sentence always begins with the delimiter symbols # and 6 During DB 7 5 the next character is read from the typewriter of the operator console using the GETC subroutine and is stored in register RO The operator has the option of entering a blank ( 6) or not, on the 25 typewriter During DB 7 6 the character from the typewriter is checked to see if it is a blank ( 6) and if it is, DB 7 7 is entered where the next character is read from the typewriter and stored in register RO If the character read during DB 7 5 is not a blank, DB 7 8 is entered where DB 7 7 is skipped.
During DB 7 8 the instruction CMPB RO,CR is used to determine whether the 30 last character from the typewriter (now stored in register RO in ASCII code) is a carriage return character If it is a carriage return character, it signals, the end of the LAYER BUILDING operation and accordingly, DB 7 10 is entered where the exit flag LBXIT is set to 1 and JOIN LBMJ 3 and DB 7 11 are sequentially entered.
If the character is found not to be a carriage return character during DB 7 8, DB 7 9 35 is entered where the entry being provided by the user is processed in its entirety.
To be explained in more detail in connection with the PROCESS ENTRY program, characters are read from the typewriter of the operator console until another sentence delimiter # is reached and processed in the manner to be described Following either DB 7 9 or DB 7 10, DB 7 11 is entered where the 40 LAYER BUILDING program exit flag LBXIT is checked to see whether it is a 0, and if it is, the JOIN LBMJI is reentered where the loop through DB 7 3 through DB 7 11 is repeated for another sentence In this manner one or more sentences may be added to the layered data base If the exit flag is found to be 1, then the operation of the LAYER BUILDING program is exited 45 E Process Entry Program, Level 3.
The PROCESS ENTRY program is entered during DB 7 9 of the LAYER BUILDING program, level 2, and is therefore a level 3 program The PROCESS ENTRY program processes the entry made by the user up to DB 7 9 of the LAYER BUILDING program At this point in the operation there are two seed header so addresses stacked on ESTAK, representing the sentence delimiter # and the word delimiter i 6 RLN O RLNI are both 1 The PROCESS ENTRY program will then accept the events making up a sentence from the typewriter of the operator console and place them in the data base.
The program code for the PROCESS ENTRY program is depicted at 55 DB 7 9 0 et seq of Appendix B-22 Fig 124 shows a flow diagram for the PROCESS ENTRY program The blocks of the PROCESS ENTRY program are identified by the symbols DB 7 9 0 through DB 7 9 24 and the corresponding symbols are used to identify the corresponding code in Appendix B-22.
During the operation of the PROCESS ENTRY program the ASCII characters 60 are read from the typewriter using the GETC subroutine and, as long as the characters are not delimiters, the PROCESS ENTRY program checks to see whether the particular characters have been processed before If the character has been processed before, the corresponding location in CVRTBL contains an event 296 1,570,344 296 number (i e, is non negative) If the character was processed before, the corresponding event number is obtained from CVRTBL and is stacked on ESTAK.
If the character is a new one which has not been entered in the data base heretofore, appropriate adjustments are made in the two conversions tables CVRTBL and CVTBL 2 to create an event number for the new character on layer O 5 and the event number is stacked on ESTAK This operation is continued until a layer 0 or word delimiter)6 is encountered When the delimiter,6 is encountered, RLNO identifies the layer 0 events in the entry which was just made by the user and these layer 0 events are then processed and are thereby added to layer 0, if they are not already on layer 0 The foregoing operation is accomplished by the PROCESS 10 LAYER 0 subroutine which will be described in more detail in connection with Fig.
125.
When a sentence delimiter # is encountered, a determination is made that the last level 0 entry has been processed and then the events are added on layer I of the data base The number of events in the layer I entry are identified by the value in 15 RLNI It is not necessary to determine if the entry has already been made in layer I since only a two layer system is being considered herein and therefore redundancy is not being squeezed out from layer 1.
With the foregoing general description, consider in more detail the actual sequence of operation for the PROCESS ENTRY program as depicted in the flow 20 diagram of Fig 124 and the corresponding code During DB 7 9 1 the exit flag PEXIT for the PROCESS ENTRY program is reset and cleared to 0 and the PIPSW switch is set to 1 The PIPSW subsequently causes the PIPE program to be called to determine if the entry being processed has been stored in the layered data base unless it is reset to 0 25 Note that the first entry into DB 7 9 2 and DB 7 9 3 follows either DB 7 6 or DB 7 7 of the LAYER BUILDING program flow (Fig 123) and therefore will never be a word delimiterl or a sentence delimiter # However, during DB 7 9 2 the instruction CMPB RO,B LANK checks to see whether the current ASCII character being processed is a delimiter b which indicates an end of word If the character is 30 not an ending word delimiter 6, the instruction BNE CLB causes DB 7 9 3 of the flow to be entered where the character is similarly checked to see whether it is a sentence delimiter # If it is not a sentence delimiter #, DB 7 9 4 of the flow is entered where the layer one switch LISW is reset to 0, indicating a layer 0 entry and in order to cause the proper decision to be made at DB 7 9 15 35 The software register PC is set during DB 7 9 22 so that it normally contains the previous event character entered into the data base However, initially software register PC contains a 0 During DB 7 9 5 of the flow a check is made to determine whether the previous character in register PC is a word delimiter t which would mean that the PROCESS ENTRY program is just starting to process a new word If a 40 word delimiier 6 is detected during DB 7 9 5, DB 7 9 6 of the flow is entered Note that DB 7 9 6 is normally always entered for the first non delimiter input character.
DB 7 9 8 will normally be entered directly after DB 7 9 5 for subsequent input characters.
During DB 7 9 6 a layer 0 event signal representing the seed header address for 45 the word delimiter,6 is stored in ESTAK at the address specified by the address in top of stack register R 3, less 1 To this end the instruction MOV LOET,(R 3) causes the address in top of stack register R 3 to first be decremented by 1 and then causes the corresponding location in ESTAK to be filled with the seed header so address representing the beginning word delimiter A 5 Also the instruction INC 50 RLNO increments the value in RLNO which represents the number of events in the entry on layer 0, now in ESTAK.
During DB 7 9 7, the PIPSW switch is set to 1 which subsequently causes thePIPE program to be called JOIN PEJ 2 and DB 7 9 8 of the flow are than sequentially entered During DB 7 9 8, a determination is made whether the present 55 ASCII character being processed is a new one It is not a new character if the corresoonding location in CVRTBL does not contain a negative number.
Referring to DB 7 9 8 of the code in Appendix B-22, register RO now contains the ASCII character Referring to the code at DB 7 9 8, the instruction MOV CVRTBL(R 0),Rl causes the base address CVRTBL of Table CVRTBL to be 60 added to the ASCII coded value in register RO to derive the corresponding address in Table CVRTBL The content of the corresponding location in CVRTBL is read out and stored in register RI If the value in Rl (from CVRTBL) is a negative number, the character contained in RO is a new character and the instruction BMI + 3 causes the operation of the program to branch forward three instructions to 65 297 I 1,570,344 297 DBI 7 9 10 of the flow If on the other hand the value in register RI is not negative, it now contains a previously formed layer 0 event number representing the ASCII coded character now in register RO Thus the character in RO is not a new character and DB 7 9 9 of the flow is entered.
During DB 7 9 9 of the flow the instruction MOV RI,R 2 causes the layer 0 5 event number to be moved from register RI to register R 2 Subsequently, PEJ 3 and DB 7 9 13 of the flow are sequentially entered.
Return now to DB 7 9 8 and assume that a new ASCII coded character is detected (i e, a negative number was obtained from CVRTBL and detected in register Rl) causing DB 7 9 10 of the flow to be entered 10 During DB 7 9 10 since a new ASCII coded character is detected, the system computes the next layer 0 event number in order and inserts the new layer 0 event number into the location in Table CVRTBL which corresponds to the new ASCII character and the new ASCII coded character is stored at the location in CVTBL 2 which corresponds to the new event number Software counter NEO provides a 15 count of the new layer 0 events (ASCII characters) encountered To this end the instruction INC NEO counts up the number of events value contained in register NEO The subsequent instruction MOV NEO,R 2 causes the new layer 0 event number in register NEO to be stored into register R 2 where it is saved The subsequent instruction MOVB R 2,CVRTBL(R 0) causes the new layer 0 event 20 number in register R 2 to be stored into the location in CVRTBL which is specified by the base address CVRTBL plus the value of the new ASCII character contained in register RO The subsequent instruction MOVB RO,CVTBL 2 (R 2) causes the new ASCII coded character contained in register RO to be stored into the location of Table CVTBL 2 specified by the base address CVTBL 2 plus the 25 value of the new layer 0 event number saved in register R 2.
During DB 7 9 11, a seed header for the new event entered in Tables CVRTBL and CVTBL 2 is created and the address of the new seed header is stored in LOET.
To this end, referring to the code, the instruction MOV NXTSH,RI causes the base address for the next seed header to be moved from software register NXTSH into 30 register RI The instruction ADD #10,NXTSH causes the address in NXTSH to be incremented to the beginning of the mext available seed header storage The instruction MOV R 1,LOET(R 2) causes the base address of the new seed header to be moved from register Rl into the location of the layer 0 event pointer table (LOET) specified by the base address LOET plus the value of the layer 0 event 35 number saved in register R 2 In this manner the layer 0 event pointer table is updated so that it contains at the location relative to its base, corresponding to the new event number, an address pointer to the base of the corresponding seed header In addition the next four instructions CLR (Rl)+ clear out the four words from the seed header storage area thereby creating a null seed header 40 During DB 7 9 12 of the flow the PIPSW switch is reset to 0 This is done because it is now known that the layer 0 entry being processed has not previously -been stored in the data base and therefore piping to determine if it is present is unnecessary.
During DB 7 9 13 and DB 7 9 14 of the flow, the layer 0 seed header address 45 corresponding to the event number saved in R 2 is stacked on ESTAK and the number of events for the entry specified by software register RLNO is incremented by 1 To this end the MOV LOET(R 2),-(R 3) instruction causes the seed header address to be stored at the ESTAK location specified by the address in register R 3, minus 1, and the INC RLNO instruction increments the number of events in RLNO 50 by 1 Subsequently, PEJ 6 and DB 7 9 22 of the flow are entered.
During DB 7 9 22, the present new character in RO is saved in software register PC as the previous character under control of the instruction MOVB RO,PC.
During DB 7 9 23, the PROCESS ENTRY exit flag PEXIT is tested to determine whether it has been set to 1, indicating that the entire layer 0 entry (now 55 being input) has been processed If the exit flag PEXIT is a 0, i e, has not been set to 1, DB 7 9 24 of the flow is entered where the instruction JSR R 5,GETC calls the operation of the GETC subroutine which causes the next input character to be obtained from the typewriter and subsequently DB 7 9 2 et seq of the flow are reentered 60 Return now to DB 7 9 3 of the flow and assume that a sentence delimiter # is detected indicating the end of a sentence DB 7 9 15 of the flow is entered where the Ll SW switch is checked to see whether it is a 1 L I SW will be 1 if DB 7 9 21 had previously been entered (see Fig 125, PLE 1) and hence all events of the layer 0 298 298 1,570,344 entry (now being input) have been processed If the LISW flag is a 0, indicating that all entries connected with layer 0 have not been processed, the entries provided so far on layer 0 are processed by entering DB 7 9 16 of the flow.
During DB 7 9 16 the instruction JSR R 5 PLOE causes the PROCESS LAYER 0 program (PLOE) to be called which in turn processes the layer 0 entry The 5 operation of the PROCESS LAYER 0 program will be discussed in more detail subsequently in connection with Fig 125.
Following DB 7 9 16 or following DB 7 9 15, if the LISW switch is a 1, DB 7 9 17 of the flow is entered During DB 7 9 17 the seed header for the ending sentence delimiter # for layer I is stacked on ESTAK and the length of the layer 1 10 entry specified by the value in register RLNI is incremented by 1 To this end, referring to the code, the instruction MOV LIET,-(R 3) causes the location in ESTAK specified by the address, minus 1, in register R 3 to have the value corresponding to the seed header address for the layer 1 delimiter event 4 X, and the instruction INC RLNI increments by I the number of events in the entry on layer 1 15 specified by register RLN I.
During DB 7 9 18, the ADD N EVENTS program is called and the events associated with the current layer 0 entries whose layer I seed headers are now in ESTAK are added to layer I of the data base The number of such events is specified by the value in register RLNI 20 The instruction JSR R 5,ADDNE causes the ADD N EVENTS (ADDNE) subroutine to be called which in turn takes the events from the top of ESTA, and adds them to the stored data base on the appropriate layer.
During DB 7 9 19 the L I SW switch is reset to 0 and the events that are on top of ESTAK, the total number of which is specified by the value in RLNI, are removed 25 from ESTAK To this end the instruction ADD RLNI, R 3 causes the top of stack printer P 3 to be incremented by the value in RI Nl which in effect causes the entries to be removed from ESTAK In addition the CLR RLNI instruction clears RLNI, setting it to 0.
During DB 7 9 20 the exit flag PEXIT for the PROCESS ENTRY program is 30 reset to 0 indicating that the current entry has been processed and therefore operation of the PROCESS ENTRY program can be exited JOIN PEJ 6 and DB 7 9 22 of the flow are then entered.
During DB 7 9 22, as discussed above, the current ASCII character contained in register RO is stored into the software register PC for use as the previous 35 character for subsequent operations when DB 7 9 2 of the flow is reentered.
When the exit flag PEXIT is set to 1 during DB 7 9 20, then during DB 7 9 23 operation of the PROCESS ENTRY flow is exited.
Return to DB 7 9 2 and assume that the word delimitert character is detected.
This indicates that the last event in a word entry has been reached DB 7 9 21 of the 40 flow is then entered where the PROCESS A LAYER 0 ENTRY is called to enter the entry in the stored data base To this end the instruction JSR R 5, PLOE causes the PROCESS LAYER 0 ENTRY subroutine to be called During the PROCESS LAYER 0 ENTRY subroutine, if the entry whose layer 0 event numbers are now contained in ESTAK is already stored in layer 0 of the data base, the layer 0 entry 45 (layer 1 event) number will be obtained and the seed header for said event stored on ESTAK in place of the layer 0 values on ESTAK without storing the entry in layer 0 Otherwise the entry in ESTAK will be headed to layer 0 and the layer I seed header for the layer 0 entry will be stored in ESTAK.
F Process a Layer O Entry Subroutine 50 Briefly, the PROCESS LAYER 0 ENTRY subroutine takes the top RLNO layer 0 seed headers off ESTAK and, using the PIPING, determines whether this entry is already represented in the stored layer 0 data base If it does already exist, the layer 0 entry number (layer I event number) is returned and its seed header address stored on ESTAK without storing the entry in layer 0 If it does not already 55 exits, signals representing the top RLNO layer 0 events on ESTAK are added to lki er 0 of the stored data babe using the ADD N EVENTS subroutine and the layer 0 entry number (layer I event number) is returned The top RLNO layer 0 events are also popped from ESTAK and the seed header address of the derived layer I event number is stacked on ESTAK and RLNI is incremented to indicate I layer 1 60 event has been added to ESTAK and LISW is set to 1 in case the next layer I event number is an end of sentence character (#).
The ADD N EVENTS subroutine simply takes the top RLNO or RLNI events in ESTAK depending upon whether LISW is set, and adds them to the appropriate 299 1,570,344 299 layer using the CHANGE MODULE The storage is updated as was described earlier and as will be seen in detail in connection with the ADD N EVENTS subroutine.
The program code for the PROCESS A LAYER 0 ENTRY subroutine is depicted in Appendix B-22 Fig 125 is a flow diagram for the PROCESS A 5 LAYER 0 ENTRY subroutine The various boxes in the flow are designated by the symbols PLEI through PLE 12 The correspondence between the code and Appendix B-22 and the various blocks of the flow is identified in the code using the symbols of Fig 125.
Upon entry to the PROCESS A LAYER 0 ENTRY subroutine (PLOE) the top 10 n entries on ESTAK are then N seed header addresses for the events in layer 0 (E E) comprising the current entry (WORD) to be processed PLOE tests and either discovers that the entry is already stored in layer 0 of the stored data base and stacks the layer I seed header address of the event number corresponding to this entry on ESTAK, or PLOE adds the n layer 0 events to layer 0 of the stored 15 data base as the next entry Then PLOE stacks the layer 1 seed header address of the event number on ESTAK.
The PLOE subroutine is called during either DB 7 9 16 or DB 7 9 21 of the PROCESS ENTRY flow of Fig 124 During PLEI the context of register Rl is saved During PLE 2 a value representing the seed header address of the ending 20 delimiter is stored on the top of ESTAK This occurs under the control of the instruction MOV LOET,-(R 3) which causes the centent of the address which is one less than specified by R 3 to be filled with the first entry in table LOET.
Additionally the instruction INC RLNO increments the number of layer 0 events in ESTAK specified by RLNO, by 1 25 During PLE 3 a check is made to see whether the software PIPE switch PIPSW has been set to i requireing a call of the PIPE program If the PIPE switch has not been set and therefore is 0, PLE 4 of the flow is entered.
It will be recalled that the PIPE switch will be 0 (not set to 1) if a new input character is contained in the current word entry (i e, a character which has not 30 been previously input) During PLE 4, signals representing the top RLNO events on ESTAK are added to layer 0 of the data base, utilizing the ADD N EVENTS subroutine of Fig 126 Subsequently, PLEJ 2 and PLE 9 of the flow are entered.
Return to PLE 3 and assume that the PIPE switch is set to 1 indicating that the PIPE program is to be called to determine whether this word or entry already exists 35 in layer 0 If the PIPE switch is set to 1, PLE 5 is entered where piping is performed to see if the word entry is in layer 0 During PLE 6 a check is made to determine if an exact hit was found during the preceding piping operation To this end the instruction TST PNBCNT checks for a 0 in PNBCNT indicating an exact hit and the instruction BNE + 3, if an exact hit is found, skips the next two instructions 40 causing PLE 8 to be entered If an exact hit is not found, PLE 7 of the flow is entered where the ADD N EVENTS subroutine is called, causing signals representing the top RLNO layer 0 events on ESTAK to be stored in layer 0 of the data base The events added into layer 0 of the data base form the next entry.
Return now to PLE 6 and assume an exact hit was found during the piping 45 operation An exact hit is found during the piping operation if all of the events on layer 0 making up the entry in ESTAK were found exactly in the stored data base.
An exact match has to be found both as to position and sequence of events Under these conditions, PLE 8 of the flow is entered where the layer 0 entry number is obtained and used as the event number for layer I To this end the instruction MOV 50 PNBOUT,Rl causes the entry number, which is left in the top of PNBOUT by the PIPE program, to be transferred from PNBOUT to register Ri Following PLE 8, PLEJ 1, PLEJ 2, and PLE 9 of the flow are sequentially entered During PLE 9 the events making up the top layer 0 entry on ESTAK which were either added on layer 0 during PLE 7 or were found to already, exist in the data base, are removed from 55 ESTAK At this point, register RLNO specifies the number of such events and accordingly during PLE 9 the instruction ADD RLNO,R 3 adds the value in RLNO to the top of stack pointer R 3 which bypasses or in effect pops off these events from ESTAK In addition the instruction CLR RLNO clears the number of events value in register RLNO to 0 60 PLE 10 of the flow is then entered where the layer 1 event number contained in register Rl is used to store the associated seed header address on ESTAK To this end the instruction MOV LIET(RI),-(R 3) causes the layer I seed header associated with the event number to be stored into ESTAK at one address below that existing in register R 3 Additionally the instruction INC RLNI causes the 65 300 I 1,570,344 300 3011573430 value in register RLNI identifying the number of events on layer I to be incremented by 1.
During PLEI I the instruction INC LISW sets the layer I switch LISW to I to indicate a possible end of a layer I entry or sentence condition If the next character received is a #, then control will go from DB 7 9 15 to PEJ 4 The purpose 5 of LISW is to provide a means of distinguishing the following end-ofsentence conditions:
#6 A <# (no blank (b) before final) and #A /6# (blank before final #)10 In the first case before the words in the sentence (i e, process layer 1) can be processed, it is necessary to finish processing the final word This is detected at DB 7 9 15 if LISW = O Thus DB 7 9 16 is entered when the final word is processed and then the sentence is processed: DB 7 9 17 DB 7 9 20.
During PLE 12 the context of register Rl is restored to that existing when the 15 PLOE subroutine was entered Subsequently the operation is exited.
G Add N events Subroutine, Level I Appendix B-22 shows the code for the ADD N EVENTS subroutine Fig 126 is a flow diagram illustrating the sequence of operation of the ADD N EVENTS subroutine, level I program The symbols ANEO through ANEIS are used to 20 identify the flow blocks These same symbols are used in the code to show the relation between code and flow.
The ADD N EVENTS (ADDNE) subroutine is the subroutine which adds into either layer I or layer O of the data base the signals which represent the events making up the top entry on ESTAK The N, representing the number of events 25 which are to be added, is specified by RLNO for a layer O entry and RLNI for a layer I entry Referring to ANEO of the flow, the symbol X is used to identify either a 1 or a O for layer I or layer 0 Thus ADDNE stores information on either layer O or layer 1 of the data base.
The ADDNE subroutine is called for adding events on layer O during PLE 4 30 and PLE 7 of the PLOE subroutine (Fig 125) and is called for adding events onto layer I during DB 7 9 18 of the PROCESS ENTRY program (Fig 124).
Upon entry into the ADDNE subroutine the relevant storage structure is as follows: if LISW = 0, ESTAK contains at the top layer O seed header addresses, RLNO = N = number of such layer O events; if LISW = 1, ESTAK contains at the 35 top layer I seed header addresses, RLNI = N = number of such layer I events.
During ANEI of the flow the context of RO, R 2 and R 4 are saved for return to the originating program During ANE 2 to LISW switch is tested to determine whether it is a I, identifying that events are to be added on layer 1, or a 0, designating that events are to be added on layer 0 40 If the LISW switch is a 0, designating layer 0, ANE 3 of the flow is entered where the program obtains the address of the layer O header and obtains the isoentropicgram width value HWO, and the number of events value RLNO The number of entries value is decreased by 1 To this end the instruction MOV LOPTR,LPTR moves the layer O event pointer (LOPTR) for layer O to register 45 LPTR The instruction MOV HWO,HW moves the iso-entropicgram width value HWO from HWO to software register HW The instruction DEC RLN causes the number of layer O events value (on ESTAK) to be transferred from register RLNO to RLN and to be decreased by 1 The value in RLNO is decremented by 1 in RLN to remove from the count the beginning delimiter/6 stored in ESTAK 50 Returning to ANE 2, should the LISW switch be a 1, indicating a layer I addition is to be made, ANE 4 of the flow is entered where the layer I header pointer (LIPTR), the iso-entropicgram width value (HWI), and the number of layer I entries (in ESTAK), are transferred to LPTR,HW and RLN and the value in RLN is decremented by 1 in the same manner described for the corresponding 55 layer O parameters for ANE 3.
Following ANE 4, ANEJ 1, ANEJ 2, and ANE 5 of the flow are entered During ANE 5 the next event-time is computed To this end the instructions and operation are as follows:
1,570,344 301 301 MOV @ LPTR,LXET moves the address of the proper layer event pointer table into LXET; MOV LPTR,R 2 moves the address of the base of the proper layer header into R 2; INC 6 (R 2) increments either the event-time TIKO or TIK 1 5 by one.
During ANE 6, the instruction CMP 2 (R 2),6 (R 2) causes the isoentropicgram width value (HWO or HWI) to be compared with the new event-time (TIKO or TIK I) stored in words I and 4 of the layer header for the layer being processed (see Fig 120) If the new iso-entropicgram width value (HWO or HWI) is the larger, 10 ANE 7 of the flow is entered where the iso-entropicgram width value is doubled in the corresponding layer header If during ANE 6 the iso-entropicgram width value (HW O or HW 1) is found to be the larger, then ANE 8 is entered directly, bypassing ANE 7.
is During ANE 8 a change vector is computed The change vector is the event 15 time value TIKO or TIKI for the corresponding layer presently being processed and is to be stored into the MEMORY MODULE area 1 To this end the instructions depicted in Appendix B-22 for ANE 8 and their operation are as follows:
MOV #1, CNGDPM stores at a I in CNGDPM selecting MEMORY 20 MODULE area 1; MOV #l CNGLNG stores a value of I in CNGLNG for the length of the change seed line; MOV 6 (R 2),CNGVEC moves TIKO or TIKI from the corresponding layer header into CNGVEC; 25 MOV #CNGVEC,RO stores the address of CNGVEC into RO for the call on the MEMDPM routine; MOV #CNGDPM,Rl calls the MEMDPM routine which JSR R 5,MEMDPM moves the one value in the change vector from CNGVEC to MEMORY MODULE area 1 30 Thus, following ANES the change vector for the current event time (i e, occurrence value) is stored into MEMORY MODULE area 1.
During ANE 9 the seed line for the event now being dealt with is stored into MEMORY MODULE area 2 During ANE 10 the program moves the following six values from the indicated registers to the indicated registers of the IPRF: 35 1 HW-TL 2 0-BL 3 O IR 4 The line number of the seed line is moved from the second word of the seed header ( 2 lR 4 l) into LINE # of the IPRF; 40 The length of change vector is moved from CNGDPM+ 2 to LNI of the IPRF:
6 The length of the seed is moved from SEEDPM+ 2 into LN 2 of the IPRF.
During ANEI 1 the CHANGE program is called causing the change vector in 45 MEMORY MODULE area 1 to appropriately modify the seed whose seed line is contained in MEMORY MODULE area 2, thereby adding the event-time count (TIK O or TIKI) to the seed line During ANE 12 the new seed line is transferred to the main memory area called WAREA.
During ANE 13 the PUT NEW SEED IN STORAGE program (Fig 127) is 50 called causing the new seed to be placed into storage.
During ANE 14 the seed header for the changed seed line which has just been put into storage is adjusted with the new values Specifically, the line number of the seed, the length of seed, and the number of occurrences in line 0 of the seed line are updated To this end, during ANE 12 the new line number was stored in CNGLIN 55 and the length of the new seed line was stored in CNGLNG Additionally at this point the register RI contains the base address of the seed header for the new seed line Accordingly, the instruction MOV CNGLIN,2 (R 4) causes the line number for the new seed line to be stored into the second location of the corresponding seed header and the instruction MOV CNGLNG,4 (R 4) causes the new length of seed 60 line value to be stored into the third word of the corresponding seed header The 302 1,570,344 302 instruction INC O(R 4) causes the number of l’s or occurrences in line O of the seed line to be stored into the fourth word of the corresponding seed header Thus the event currently being processed has been updated so that the corresponding seed header and seed line reflect the new seed.
During ANE 15 the number of events value stored in RLN is decreased by 1 5 using the instruction DEC RLN The instruction BEQ + 2 causes ANE 16 of the flow to be entered if RLN has been reduced to 0, indicating that there are no more entries to be processed If RLN has not been reduced to 0, the instruction JMP ANEJ 2 causes the subroutine program to jump back to join ANEJ 2 of the flow lo where the operation of the loop through ANE 5 through ANE 15 is repeated for the 10 next event in ESTAK The loop through ANE 5 through ANE 15 is repeated until RLN has been reduced to 0, indicating that all events in ESTAK have been entered into the data base.
Assume that all events have been processed and ANE 16 is entered During ANE 16 the LISW switch is checked to see whether it is a I, indicating a layer 1 15 entry is being made If the L 1 SW switch is a 0, indicating a layer O entry, ANJ 4 and ANE 18 of the flow are entered directly If the LISW switch is a 1, indicating an entry on layer I, then ANE 17 of the flow is entered where the LI PTR pointer to the layer 1 header is moved into register R 4 The instruction INC 4 (R 4) causes the value representing the number of events in NEI, the third word of the layer 1 20 header, to be incremented by I to reflect the fact that another event has been entered into layer I of the data base Also the following instructions and operations take place:
MOV 4 (R 4),Rl causes NEI to be transferred from the layer 1 header to RI; 25 MOV NXTSH,LIET(R 1) moves the address of the next seed header into the corresponding position in the layer I event pointer table thereby creating a seed header storage area; MOV NXTSH,R 2 saves such address in R 2; 30 ADD # 10,NXTSH updates the seed header pointer to the next available one; CLR (R 2)+’ CLR (R 2)+ creates a null seed by zeroing out all four words from the newly created seed header 35 CLR (R 2)+ storage area CLR (R 2) During ANE 18 the context of the machine is returned to that existing when the subroutine was called and operation of the subroutine exits.
H Put New Seed in Storage Program, Level 2 40 Appendix B-22 contains the program listing for the PUT NEW SEED IN STORAGE program, a level 2 program Fig 127 is a flow diagram for the PUT NEW SEED IN STORAGE program The flow diagram of Fig 127 has its blocks identified by the symbols ANE 13 0 through ANE 13 11 the correspondence between the program code of Appendix B-22 and the flow diagram of Fig 127 is 45 shown in the program code using the symbols of the flow diagram.
The PUT NEW SEED IN STORAGE program is called during ANE 13 of the ADD N EVENTS subroutine (Fig 126) This program places the new seed line into the seed line storage area (see Fig 116).
During ANE 13 1 the context of registers R 2, R 3 and R 4 in the MINI 50 COMPUTER are saved During ANE 13 2, 2 is added to the length of the new seed value which value is now contained in CNGLNG in order to take into account the two words required for the length address (see Fig 116) The modified length of new seed value is then placed into software register NSLN To this end the instruction MOV CNGLNG,NSLN, stores the length of the new seed line into 55 NSLN The instruction ADD #2,NSLN adds the value 2 to the new seed line value in NSLN In addition during ANE 13 2 the value representing the length of the old seed line is obtained from its temporary storage area in SEEDPM+ 2 and stored into software register OSLN To this end the instruction MOV SEEDPM+ 2,05 LN is executed 60 Prior to the entering of the PUT NEW SEED IN STORAGE block the length of the old seed moved from the seed header to the location SEEDPM+ 2 The two 1,570,344 303 303 words at SEEDPM and SEEDPM+ 2 were used by the MEMDPM subroutine while transferring the old seed to the DPM MEMORY MODULE When control reaches ANE 13 2 the length of the old seed is still contained unchanged in SEEDPM+ 2.
ANE 13 3 is now entered where the old length value is compared against the 5 new length value in registers OSLN and NSLN, respectively If the old length value in OSLN is the smaller, ANE 13 4 is entered for a search through free space using the SEARCH FREE SPACE program (Fig 128).
The SEARCH FREE SPACE program returns a pointer in RI to the storage area where the new seed line can be added 10 During ANE 13 5 the new seed line is inserted into “free space” To this end the instruction MOV CNGLNG,RO causes the length of the new seed line to be stored into register RO The instruction MOV #WAREA,R 2 causes the beginning address of WAREA which contains the new seed line to be stored into register R 2.
Register RI following the SEARCH FREE SPACE operation of ANE 13 4 contains 15 the address of the beginning of the space that will contain the new seed It can be either free space or available space The instruction MOV (R 2)+,(Rl)+ causes a word to be moved from the address in WAREA specified by register R 2 to the free space area specified by the address in register R 1 and the addresses in the registers R 2 and Rl are subsequently incremented by 1 The instruction DEC RO causes the 20 length of the new seed line value contained in register RO to be decremented by 1.
The instruction BNE -2 causes the instructions MOV (R 2)+,(Rl)+ and DEC RO tobe repeated until the length of the new seed line value in register RO has been decremented to 0, thereby indicating that each of the words in the seed line has been transferred to the free space area pointed at by register Rl After the value in 25 RO has been decremented to 0, ANE 13 6 is entered where the RELEASE SPACE subroutine (Fig 129) is executed which returns the old seed line space to the “free space” list PNSJ 1 and ANE 13 9 are then entered.
Returning to ANE 13 3, should the length of the old seed line in OSLN be equal to or greater than that of the new seed line in NSLN, ANE 13 7 and ANE 13 8 of the 30 flow are entered where the new seed line is inserted into the storage area that was occupied by the old seed line To this end the address, located at the address specified by R 4, is the address of the beginning of the storage area which contained the old seed line, and is stored into register Rl The instruction MOV CNGLNG,R O causes the length of the new seed line to be stored into register RO 35 WAREA contains the new seed line The instruction MOV #WAREA,R 2 causes the beginning address of WAREA to be stored into register R 2 The instruction MOV (R 2)+,(RI)+ causes a word to be transferred from the memory location in WAREA specified by register R 2 to the location in the old seed line storage area specified by register Rl and the address in these two registers is then incremented The 40 instruction DEC RO decrements the length of new seed line value in register RO by 1 to reflect that one word has been transferred from WAREA to the storage area for the old seed line The instruction BNE -2 causes the program to branch back to the MOV (R 2)+,(RI)+ instruction This loop is repeated until each of the words of the new seed line has been transferred from WAREA to the old seed line storage 45 area.
When the length of new seed line value in RO has been reduced to 0, all words have been transferred from WAREA to the storage area for the old seed line and ANE 13 8 of the flow is entered.
During ANE 13 8, the remainder of the storage space occupied by the old seed 50 is released To this end the instruction MOV OSLN,R O moves the length of the old seed line to register RO The instruction SUB CNGLNG,RO causes the length of the new seed contained in CNGLNG to be subtracted from the old seed length in RO.
The difference is the amounf of space to release The instruction JSR R 5, RLSP causes the RELEASE SPACE subroutine program (Fig 120 to be called 55 Subsequently, PNSJ 1 and ANE 13 9 of the flow are entered During ANE 13 9 a check is made to determine if there are more than 1000 words of unused free space and if so, ANE 13 10 is entered.
Referring to the program code for ANE 13 9, the software register UNSP contains a value representing the unused free space The instruction CMP 60 #1750,UNSP causes the number of words in free space to be compared with the octal value 1750, i e, 1750, = 1000,o If a true comparison results, then the instruction BLOS -2 causes the GARBAGE COLLECTION program to be called into operation If equality is not detected, then the instruction JMP PNSJ 2 causes ANE 13 11 of the flow to be entered 65 1,570,344 304 304 During ANE 13 11 the context of the saved registers is restored.
1 Search Free Space Program, Level 3 Appendix B-22 contains the program code for the SEARCH FREE SPACE program Fig 128 shows a flow diagram of the SEARCH FREE SPACE program.
The flow diagram contains blocks identified by the symbols ANE 13 4 1 through 5 ANE 13 4 14 The correspondence between the code and the flow is depicted in the code using the symbols in the flow.
This routine searches the free space list for a section which can contain the new seed line If such a section is found, the free space list is adjusted and a pointer is returned which points to the section If no such section is found, a pointer is 10 returned x hich points to available space At ANE 13 4 1, the context of registers R 2 and R 3 are saved At ANE 13 4 2, register RI is initialized to 0, register R 3 points to the address of the free space variable pointer, and register R 2 points to the first address in free space At ANE 13 4 3, NSLN (the new seed length) is compared with the length of the current section in free space If the new seed length is less than or 15 equal to this section, control goes to ANE 13 4 4 The pointers are adjusted so that the previous link in the list of free space points around the space which will be used to store the new seed line At ANE 13 4 5 the current link is adjusted to reflect its new status At this point a section has been found that will contain the new seed.
However, there will be space left over and this space must be added to the free space 20 list of 119 D(a and b).
At ANE 13 4 6 the unused space variable (UNSP) is diminished by the amount equivalent to the length of the new seed line Control then goes to ANE 13 4 13.
Returning to ANE 13 4 3, if the new seed line length is greater than the current section of free space, ANE 13 4 7 is entered where R 3 is updated, i e, the current 25 pointer becomes the previous one R 2 points to the next free space available At ANE 13 4 9 a check is made to see whether there is another link in the free space list or if the end of the list has been reached If the end of the list has not been reached, control goes down to ANE 13 4 13 If the end of the list has been reached, RI is adjusted to point at the beginning of the available space and the previous linked list 30 is adjusted to point beyond the amount of space needed to store the new seed This is done at ANE 13 4 10 and ANE 13 4 11 At ANE 13 4 12 the new beginning of available space is lagged with a 0 link Control comes down to ANE 13 4 13 where register I is checked If it is equal to 0, control goes back to ANE 13 4 3 and another section on the linked list is checked Otherwise, registers R 2 and R 3 are restored 35 and control exits from this block with Rl pointing to the storage area which will contain the new seed line.
J Release Space Subroutine Flow, Level 3 The program code for the RELEASE SPACE subroutine is contained in Appendix B-22 Fig 129 contains a flow diagram for the RELEASE SPACE 40 subroutine The various blocks of the flow are depicted by the symbols RSI through RSII The correspondence between the program code and the flow is depicted in the code using the symbols identifying the blocks of the flow.
The RELEASE SPACE subroutine is called during ANE 13 6 and ANE 13 8 of the PUT NEW SEED IN STORAGE program (Fig 127) This subroutine has as 45 input parameters a pointer to the storage area section to be released and the length of the section The routine simply skips down through the linked list of free space and inserts the new link in the proper place The additional free space is reflected in the unused space variable, UNSP Initially during RSI the context of registers R 2 and R 3 are saved Control then goes to R 52 where R 2 is pointed to the 50 beginning of free space, Rl contains the address of the area to be freed, RO contains the length of the area and R 3 points to the beginning address of free space R 3 is a pointer to the previous link and R 2 is a pointer to the current link At R 53, RI is compared with R 2 The address of the area to be freed is compared with the current address If the address of the area to be free is less than the current 55 address, it indicates that the released space is to be inserted into the list at this position At R 54, the new link and its length are inserted into the free space list of Fig 119 c.
At R 55 the old link is adjusted and at R 56, R 2 is cleared to assure an exit.
Control goes to R 59 60 Returning to R 53, if RI, the address of the area to be freed, is greater than R 2, the current address in the link, then R 57 is entered where R 3 is copied from R 2 In other words, the current pointer becomes the previous pointer and R 2 is updated to 305 I 1,570,344 305 point to the next link in the chain Control comes down to R 59 and R 2 is checked.
It it is not 0, control comes back up to R 53 If R 2 is 0, unused space is incremented by the length of the section just inserted, which is reflected in RO Registers R 3 and R 2 are restored and exit is taken from the RELEASE SPACE subroutine.
K Garbage Collection Program, Level 3 Appendix B-22 contains the programcode for the GARBAGE 5 COLLECTION program Fig 130 is a flow diagram of the GARBAGE COLLECTION program Symbols ANE 13 10 1 through ANE 13 10 10 are used to identify the various blocks of the flow and are used in the program code to identify the corresponding code 10 The GARBAGE COLLECTION program is entered during ANE 13 10 of the PUT NEW SEED IN STORAGE program (Fig 127) The GARBAGE COLLECTION program goes through the linked list of free space and returns that space to available space which is located at the end of the seed lines.
In other words, where there is a gap in the storage area, that gap will be closed 15 and the pointer in the seed headers will be updated accordingly This operation was summarized in the foregoing discussion of data structures Therefore, at ANE 13 10 1 the context of registers R 2, R 3 and R 4 is saved At ANE 13 10 2, R 2 points to the first free space area, and R 3 points to the first available address to be used for compression R 3 points to the beginning of the space to be compressed 20 R 4 points to the first data address beyond this free area At ANE 13 10 3 the ADJUST SEED HEADER program is called and the seed headers for layer 0 are adjusted At ANE 13 10 4 the seed headers for layer 1 are adjusted And at ANE 13 10 5, the data are moved up to eliminate the free area At ANE 13 10 6, the data pointer (R 4) is adjusted to point to the data beyond this next free 25 area At ANE 13 10 7, the next pointer is obtained At ANE 13 10 8 a check is made to see whether the linked list of free space has been completely gone through.
If not, control returns to ANE 13 10 3 If so, the free space pointer is reset to point to the first available free word in storage An ANE 13 10 10 R 2, R 3 and R 4 are restored and the block is exited 30 L Adjust seed header subroutine The ADJUST SEED HEADER subroutine program code is contained in Appendix B-22 The flow diagram for the ADJUST SEED HEADER subroutine is depicted in Fig 131 The blocks of the flow are identified by the symbols ASHI through ASH 8 and these symbols are used to identify the corresponding code 35 The ADJUST SEED HEADER subroutine flow is called during ANE 13 10 3 and ANE 13 10 4 of the GARBAGE COLLECTION program, Fig 130.
Briefly, this program adjusts the seed headers for layers 0 and 1 The subroutine searches through the events associated with the corresponding layer.
All those events whose seeds are at addresses which are greater than the address 40 of the free space section being compressed are reduced by an amount which is equal to the length of the free space section Visualizing available space as a linear list, this would be equivalent to a left shift.
At ASH 1, context is saved At ASH 2, RI points to the appropriate layer event table and RO points to the number of events in this layer, whether it be layer 0 or 45 layer 1 At ASH 3, register 3 points to the address of the current seed header At ASH 4, R 4 points to the address of the seed At ASH 5, the address of the seed, R 4, is compared with the current free space address which was passed into the program as a parameter in R 2 If R 4 is greater than R 2, i e, the seed lies beyond this free space, the seed header is adjusted by subtracting the length of the current free 50 space section from the seed header seed address This merely reflects that somewhere the seed is going to be moved to the left by an amount equal to the length of the free space area being compressed At ASH 7, 1 is subtracted from the number of entries In other words, the system is going to go through this loop looking at every entry in the layer event table If it is not 0, ASH 3 is entered If it is 55 0, context is restored and the subroutine is exited.
Although tables and memory linkages are shown by way of example, it should be understood that these may be replaced by the layering mechanism disclosed herein.
Reference is made to our copending patent application nos 50068/76 (Serial 60 No 1570341), from which this application ahs been divided, 3806/78 (Serial No.
1570342) and 5203/78 (Serial No 1570343) all of which claim various aspects of the information storage and retrieval system disclosed herein.
306 1,570,344 306 1,570,344 APPENDIX A INDEX OF TABLES Description
2 A 2 B 4 A-E 9 A 9 B 9 C 9 D 9 E 9 F 13 Example of word layer 0 Example of event clock Example of absolute coded occurrence vectors from layers 0 of Table 1
Example of sentence layer 1 Example of iso-entropicgram Example of one line revolve from line 0 to line 1 of Table 4 Example of Delta Example of iso-entropicgram without O ‘s Example of occurrence vectors in “bit string” and “absolute coded form Example of hybrid encoding Changing hypothetical event “X” Example of Revolve Inverted Delta from Table 6 Example of Revolve Example of Del operation Example of alternate DEL operation Symbols used to identify module originating signals on input/output control lines Primary inputs and outputs for modules of DPM SYSTEM of Fig I ENCODE MODULE list of registers, counters and flip flops DECODE I MODULE list of registers, counters, flip flops and multivibrators DELTA MODULE example of operation DELTA MODULE list of principal registers, counters, flip flops and multivibrators 311 311 311 312 312-314 314 315 315 316.
316 317 318 319 319 319 320 321 25 321-326 327 328 329 329 307 Table
No.
307 Page No.
APPENDIX A INDEX OF TABLES (Continued) Table
No Description Page No.
16 SEED MODULE list of principal registers, counters, flip flops and multivibrators 330 17 OUTPUT MODULE list of principal 5 registers, counters, flip flops and multivibrators 331 18-32 Examples for PIPE MODULE 332-339 33 PIPE MODULE list of principal registers, counters, flip flops and 10 multivibrators 339 _ 340 34-40 Examples of the operation associated with the B RIGHTNESS MODULE 340-343 41 Example of the operation of the BRIGHTNESS MODULE 344-348 15 42 DPM INTERFACE MODULE states of flip flops m I and m 2 and corresponding areas of MEMORY MODULE selected 348 43 DPM INTERFACE MODULE states 20 of flip flops m 1 and m 2 and areas of P/B MEMORY selected 348 44 Example of revolve through an isoentropicgram using the SWITCH -25 MATRIX and MEMORY MODULE 349 25 Example of the operation of the SWITCH MATRIX and MEMORY MODULE 350-351 46 Example of revolve for alternate compaction and retrieval machine of 30 Fig61 351 3 47 Iso-entropicgram for example of Table 46 352
48 DELTA 2 MODULE example of operation 352 35 49 DELTA 2 MODULE list of principal registers, counters and flip flops 353 A DELTA 2 MODULE list of inputs/outputs 353 50 B REVOLVE 2 MODULE list of inputs/outputs 354 40 308 I 1,570,344 308 APPENDIX A INDEX OF TABLES (Continued) Table
No Description Page No.
i O C REVOLVE 3 MODULE list of inputs/outputs 354 D SEED 2 MODULE list of inputs/outputs 354 5 E OUTPUT 2 MODULE list of inputs/outputs 355 OF CHANGE 2 MODULE list of inputs/outputs 355 5 OG AUXILIARY MEMORY II list of inputs/outputs 356 10 51 REVOLVE 2 MODULE example of iso-entropicgram 35652 REVOLVE 2 MODULE example of revolve operation for iso-entropicgram of Table 51 357 15 53 REVOLVE 2 MODULE principal registers, counters and flip flops 357 54 not used 55 REVOLVE 3 MODULE example of 20 revolve operation for iso-entropicgram of Table 51 358-359 56 SEED 2 MODULE list of principal registers, counters and flip flops 360 57 OUTPUT 2 MODULE list of registers, counters and flip flops 361 25 58 OUTPUT 2 MODULE example of operation 362-363 58 A CHANGE 2 MODULE list of registers, counters and flip flops 364 30 59 Hardware and software flags, registers and memory areas used for PARSER program 365 366 A Example of form of word layer 0 request and sentence layer 1 request 366 35 B-600 Example of operation of PARSER, PIPE, and BRIGHT programs -367-374 61 Hardware and software flags, registers and memory areas used for PIPE program 375-378 40 309 1,570,344 309 1,570,344 APPENDIX A INDEX OF TABLES (Continued) Table
No.
Description
Page No.
Hardware and software flags, registers and memory areas used for B RIGHT program Hardware and software flags, registers and memory areas used for OUTPUT subroutine Hardware and software flags, registers and memory areas used for MEMDPMN subroutine 379-381 382 383 Hardware and software flags, registers and memory areas used for DPMMEM subroutine Hardware and software flags, registers and memory areas used for DECODE I subroutine 383 384 20 Hardware and software flags, registers and memory areas for INSERT subroutine 65 385.
310 310 1,570,344 TABLE 1 “THIS IS A TEST” POSSIBLE OCCURRENCE VALUES OR EVENT TIMES THIS IS A TEST LINES EVENTS 0 X I T 2 H 3 I 4 S A 6 E 0 1 2 3 1 1 4 56 7 8 9 O 1 1 1 1 1 2 34 5 0 1 O 0 0 000 00 O I O O 1 O 0 0 1 O O O O O O O O O O O O O 0 O O 1 00 10 O O O O 00 O 0 O O 100 1 O O O O O 0 1 O O 0 O O 0 O 0 0 O O 1 O 0 0 0 O O 0 O 0 O 0 O 0 O 0 O 0 O TABLE 2 A
1 1 1 1 1 11 0 1 2345678 90 1 2 3 4 5 6 ‘ T H I S X I S X A X T E S T / # TABLE 2 B
Data Events OCCURRENCE VECTORS /< blank > T H I S A E l 0, 5, 8, 10, 15 l l 1, 11, 141 l 21 l l 3, 6 l l 4, 7, 13 l l 9 l l 121 clock input 311 311 312 Line No.
0 Ph 1 TH 2 IS 3 A 4 TE (ne i’ im; allow ‘ INPUT LINE -) O SEED 2 7 INPUT,’ OUTPUT LINE > 8 1,570,344 TABLE 3
LAYER 1 FOR SEQUENCE “THIS IS A TEST” POSSIBLE OCCURRENCE VALUES OR EVENT-TIMES EVENTS rase delimiter Iis -____ ST xt new word) 312 0 1 2 3 4 5 1 0 0 0 0 1 0 1 0 0 0 0 0 O 1 0 0 0 0 O 0 1 0 0 0 O O O 1 0 0 O O O O O )lied pointer 1 2 3 45 < biased (by + 1) to , layer 1 TABLE 4-A EXAMPLE OF ISO-ENTROPICGRAM POSSIBLE OCCURRENCE VALUES OR EVENT-TIMES 0 1 2 3 4 5 6 7 1 1 1 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1,570,344 3 1 3 3 13 FABLE 4-13 OCCURRENCE VALUES LINES v lit O (seed) 7 1 1 1 1 0 1 2 3 4 5 6 7 1 1 1 O 1 O 1 O 1 O O 1 1 1 1 1 1 1 O 1 O O O O 1 O 1 1 1 O O O 1 1 1 O O 1 O O 1 O O 1 O 1 l -0, 1 1 O 1 1 1 O 1 1 O 1 1 O O 1 1 1 1 1 O 1 O 1 O 1 O O 1 1 1 1 1 1 1 O 1 O O O O 1 O 1 1 1 O O O 1 1 1 O O 1 O O 1 O O 1 O 1 1 O 1 1 O 1 1 1 O 1 1 O 1 i O O 1 1 1 1 8 9 O 1 0 1 1 O 0 1 O 1 -1 J 1 1 1 1 1 1 O O O 1 1 O O 1 O 1 O 1 1 1 1 1 1 1 1 2 3 4 5 1 1 1 O 1 ( L1 1 1 1 p O O O 1 O O O 1 1 O O 1 O 1 O 1 1 1 1 2 apart) look 2 1 past edge)down U rl apart Mook 5 t r past edge) down 1 apart) look 9 f F 9 past edge) down Wrap around Inp 0 O O O O O O O 1 O O O 1 1 ' O O 0 O 1 O 0 O 1 1 0 O 1 O 0 O 1 1 0 O 1 O 1 O 1 1 0 O 0 O 0 O 0 O 1 O 1 1 0 O 0 O put Input/Oul 16 1 1 1 O 1 O 1 O O 1 1 O 1 O 1 O Would wrap around Stop. * Row 7 ( 10110011) shortest representation of input. TABLE 4-C 1 16 wide 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 is LINE 7 1 O 1 1 O O 1 1 TABLE 4-D Line 7 shifted by 0 Line 7 shifted by 8 Result of XOR Line 15 Result shifted by I 1 O 1 1 O O 1 1 1 O 1 1 O 0 1 1 1 O 1 1 O O 1 1 1 O 1 1 O O 1 1 1 0 1 1 0 0 1 1 1 0 1 1 01 O 1 Result of XOR Line 16 1 1 1 O 1 O I O O 1 1 O 1 TABLE 4-E Row 7 shifted by 0 Row 7 shifted by 8 Result of XOR Row 15 Result shifted by 1 Result of XOR Row 16 0, 2, 3, 6, 7 8 10, 11 _ 14 15 0, 2, 3, 6, 7, 8, 10, 11, 14, 15 1, 3, 4, 7, 8, 9, 11, 12, 15, 16 8, 1, 2, 4, 6, 9, 10, 12, 14 TABLE 5 1 1 1 O 1 1 1 1 0 1 0 0 1 1 1 l::. -Truncate here 1 O 0 1 1 1 1 0 1 O Line 0 314 1,570,344 314 POSSIBLE OCCURRENCE VALUES OR EVENT-TIMES 0 1 2 3 4 5 6 7 1 O O O O O O O 1 1 O O O O O O 1 O 1 O O O O O 1 1 1 1 O O O O 1 O O O 1 O O O 1 1 O O 1 1 O O 1 O 1 O 1 O 1 O 1 1 1 1 1 1 1 1 3 15 1,570,344 TABLE 6 DELTA 3 15 TABLE 7 3 4 5 6 7 \ 1 1 2 1 1 1 1 3 1 7 0 1 2 1 1 1 1 1 1 1 1 1 1 1,570,344 TABLE 8 0 1 2 3 4 5 6 7 ( 1) 1 1 1 0 1 0 1 0 ( 0 1 2 4 6 POSSIBLE OCCURRENCE VALUES OCCURRENCE VECTOR BIT STRING FORM OCCURRENCE VECTOR -ABSOLUTE FORNA TABLE 9 EXAMPLE OF HYBRID ENCODING TYPE BIT bit string form absolute form 1 lii 1 1 I 1 1 O X l,11 olo 1 o o o 1 ol 119 121 123 118 120 122 124 o O 1 O 1 ol 114 116 Wi 115 117 11 ii 1 0 0 1 0 1 1 0 1 1 1 0 A Io O O Io 1 O 1 ol 87 89 91 86 88 90 92 -125 Absolute -Binary string occurrence 123, 119 -Binary string occurrence 116, 114 -100 Absolute -93 Absolute -Binary string occurrence 90, 88, 87 7 etc. Word 316 316 317 CHANGING a) Occurrence of 'X': Changes: b) Deletions: c) Insertions: d) Change Vector: e) XOR of a) and d): f) Seed of X' after changes 1,570,344 TABLE 9-A HYPOTHETICAL EVENT "X" 0 2 6 10 12 6 12 1 3 8 9 1 1 3 6 8 0 1 2 3 Line Line Value g) Seed of 'X': Line 11 12 9 10 Line Value 0 6 12 h) Change Vector i) XOR of g) and h): Line Line Line j) Seed i): Line Value 1 6 12 0 1 Line Value 317 318 1,570,344 TABLE 9-B 318 lNE 10. 0 1 11 100 00 11 1 1 00 010 00 10 2 1 10 011 00 11 3 1 01 010 10 10 4 1 11 111 11 11 1 00 000 00 00 Ll N OCCURRENCE, VALUES Seed Line > 0 1 2 3 4 5 6 7 8 9 101 112131415 1 1O O O O 0O 1O O O 0O 11 O O 1O 1 O 1 O 11 1 1 1 1 0O O O O ot 6 11 000 000 00 100 000 00 8 1 1 1 1 O O O O O O 9 10 001 000 00 11 001 100 00 11 10 101 011000 12 11 111 111 00 13 10 000 000 10 14 11 000 000 11 is 10 100 000 10 0O O O O O 0O O O O O 0O O O O O aO O O O O 0O O O O O 0O O O O O 0-0O O O O 0O O O O O 0O O O O O 1O O O O O 6 + 15 = 21 = 1 5 mod 16 1 Line Line Value O New Seed Line:
New Seed:
1,570,344 TABLE 9-C
INVERTED DELTA FROM TABLE 6 r POSSIBLE OCCURRENCE VALUES 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 O O 1 O O 0 1 0 O O 0 1 1 1 1 0 O O -0 0 1 0 1 0 O O O O 0 1 1 0 O O O O O 0 1 Seed Line 2 Table 4-A Seed Line shifted 2 TABLE 9-D
0 1 2 3 4 1 1 0 1 0 0 0 1 1 O XOR (Line 4 -Table 4-A) 0 1 2 3 4 1 0 0 1 1 1 0 0 TABLE 9-E
6 7 possit 0 1 line 4 1 0 0 ble occurrence values of delta Table 9-C 4 apart v 1 1 1 0 0 1 0 0 line 4 of Table 4-A XOR Indicates the presence of occurrence value 6 in the input line for Table 4-A
LINE 1 6 7 0 O 0 O 319 319 1 0 30 1 1,570,344 TABLE 9-F
Original input line Seed Difference between seed line and end of iso-entropicgram 5 0 1 2 3 4 5 1 O O 1 1 O 1 1 0 1 O 1 1 O 1 1 1 1 1 O O 1 1 11 1 O O O 1 O O 1 O O 1 1 0 1 1 O 1 O 1 1 O 1 1 1 1 O 1 1 1 O O 1 1 O 6 7 0 1 0 1 1 1 shifted delta line 5 0 O 0 O 0 O 0 O 1 0 0 1 To check column 5:
Seed line Shifted delta line 5 AND 1 1 Therefore the original input line column 5 is a 0.
11 1 O O 11 O O 1 0 O O O =even parity X= To check column 3 Seed line Shifted delta line 8 AND 0 O 1 1 1 O 1 1 O O 1 1 0 O O O 1 0 “odd parity == Therefore the original input column 3 is a 1.
320 320 TABLE 10
BRIGHTNESS MODULE CHANGE MODULE DPM INTERFACE MODULE ENCODE MODULE DECODE I MODULE DECODE II MODULE DELTA MODULE OUTPUT MODULE PIPE MODULE REVOLVE MODULE SEED MODULE SWITCH MATRIX B CM no special mnemonic used EM DIM D 2 M DM OM Pl RM SM S TABLE 11
MODULE INPUT/OUTPUTS ENCODE MODULE INPUTS ETL ( 8 bits) EB L ( 8 bits) EIR ( 8 bits) EHW ( 8 bits) EFIRST flip flop ELAST flip flop OUTPUTS EOP ( 1 flag bit + 7 bits) MLN 3 ( 8 bits) -top clipping limit loaded from TL of IPRF by OUTPUT MODULE bottom clipping limit loaded from BL of IPRF by OUTPUT MODULE -interval value loaded from IR of IPRF by OUTPUT MODULE iso-entropicgram width loaded from HW of IPRF by SEED, CHANGE or OUTPUT MODULES set to 1 to initialize set to l to force write of final hybrid coded hybrid coded word being written into MEMORY MODULE (flag bit = 0 identifies bit string word; flag bit = 1 identifies absolute coded word) -to DECODE I and II MODULES to indicate number of hybrid coded word written into MEMORY MODULE 321 I 1,570,344 321 1,570,344 TABLE 11 (Continued) OUTPUTS ENOC ( 8 bits) to SEED MODULE to identify number of occurrence values encoded into hybrid coded form and stored in MEMORY MODULE 5 DECODE I MODULE INPUTS MLN I ( 8 bits) DIFST Hybrid coded word in one of MEMORY MODULE areas OUTPUTS D Ol ( 8 bits) EOF 1 ( 1 bit) -physical length of input in words stored in MEMORY MODULE area being read Loaded by calling module from LNI or LN 2 of IPRF or MLN 3 of ENCODE MODULE or ORT 2 of OUTPUT MODULE -calling module (via signals applied to gate 228 sets D 1 FST to a 1 state on first call to DECODE I MODULE for conversion of one hybrid word to indicate the first call counter which indicates absolute coded word value of occurrence in question flip flop which indicates when the number of words specified by MLNI has been decoded by DECODE I MODULE DECODE II MODULE INPUTS/OUTPUTS are similar to DECODE I MODULE DELTA MODULE INPUTS DELI ( 8 bits) DELFST (I bit) number of lines to be revolved loaded by calling module from TI of SEED MODULE or CLINE of CHANGE MODULE or D 56 of OUTPUT MODULE initialization flip flop is set when new process is desired by calling module OUTPUTS DELO ( 8 bits) DELEND ( 1 bit) contains component power for 2 for value in DELI and its output to calling module flip flop which in I state indicates that value stored in DELI has been completely transformed into its component power of 2 i 5 322 322 1,570,344 TABLE 11 (Continued) SEED MODULE INPUTS SMHW ( 8 bits) SMLI ( 8 bits) iso-entropicgram width loaded from HW of IPRF -line # of seed line loaded from line # of IPRF or from CLINE of CHANGE MODULE MEMORY MODULE current seed (NLI words) LNI ( 8 bits) OUTPUTS SLINE ( 8 bits) SLN ( 8 bits) MEMORY MODULEcurrent seed in hybrid code is ( 1) stored in MEMORY MODULE area I if MINI COMPUTER via user program calls SEED MODULE, or ( 2) stored in MEMORY MODULE area N (n = 1, 2, 3) if CHANGE MODULE calls SEED MODULE the number of words or physical length of the current seed received from MLNI or MLN 2 of the DECODE I and II MODULES line number of new seed line -physical length in words of the new seed new seed (SLN words) OAR ( 2 bits) ONOC ( 8 bits) the new seed contained in MEMORY MODULE areas designated by OAR contains the number of the MEMORY MODULE area which contains the new seed contains the number of actual occurrence values in the new seed REVOLVE MODULE INPUTS/OUTPUTS for other modules CHANGE MODULE INPUTS change line value (L Nl-words long)-line value of the change vector from MEMORY MODULE area I seed line value (LN 2-words long) CLINE ( 8 bits) CLN ( 8 bits) line value of the seed which is to be changed, from MEMORY MODULE area -line # of seed from line # of IPRF physical length of line value for seed from LN 2 of IPRF 323 323 324 1,570,344 TABLE 11 (Continued) MLNI of DECODE I & II ( 8 bits) physical length of line value for change vector from LNI of IPRF OUTPUTS Same as that given for seed module OUTPUT MODULE INPUTS MLN 2 of DECODE II MODULE, MLNI of DECODE I MODULE ( 8 bits) length of seed line value from LNI of IPRF ORT 3 ( 8 bits) length of line value of the reference line from LN 2 of IPRF OHW ( 8 bits) OLINE ( 8 bits) DELOP ( 1 bit) ETL of ENCODE MODULE EBL of ENCODE MODULE EIR of ENCODE MODULE line value of seed line value of reference vector OUTPUTS OAR MEMORY MODULE areadesignated by OAR OLN PIPE MODULE INPUTS PW ( 8 bits) LNRQR ( 8 bits) iso-entropicgram width for seed from HW of IPRF -line number of line value of seed from LINE # ox IPRF -set DELOP from DPM INTERFACE MODULE top limit from TL of IPRF bottom limit from BL of IPRF interval value from IR of IPRF -from MEMORY MODULE area -from MEMORY MODULE area number of MEMORY MODULE area containing output -output length of output in MEMORY MODULE area designated by OAR -pipe width loaded from PW of IPRF on first call; contains width of pipe length of request (in events) loaded from LNRQ of IPRF on first call 324 1,570,344 TABLE 11 (Continued) INPUTS MLNI of DECODE I MODULE ( 8 bits) length of line value of seed loaded from LNI of IPRF Line value of line 0 (LN 1 -words) MLN 2 of DECODE II MODULE ( 8 bits) Delim (LN 2-words) PFIRST(I bit) PLAST (I bit) INTERMEDIATE OUTPUT P Mn (n =_ 1,2) vi vii line value of seed located in MEMORY MODULE area 1 length of delimiter event occurrence vector loaded from LN 2 of IPRF and PSAU -delimiter event occurrence value located in MEMORY MODULE area 2 initialization flip flop set prior to first call only end flip flop, set prior to last call onlycontains values for each occurrence processed in each event occurrence vector the occurrence value after bias 1 subtracted the “hit count”, i e number of times this occurrence number has been computed during piping process the last value in area is set to -I FINAL OUTPUT MEMORY MODULE area 3 contains the final output.
There are the following two values for each entry in the request:
vi Vii BRIGHTNESS MODULE INPUTS LNRQR ( 8 bits) -the best candidate occurrence value to be the beginning occurrence of the request in this entry hit count; if sign bit is set (-I) this indicates an exact hit The last value in the area is set to -1.
-length of the request (in events) from LNRQ of IPRF 325 325 TABLE 11 (Continued) INPUTS MLNI of DECODE I MODULE Line value of seed MLN 2 of DECODE II MODULE delim -length of line value of current event occurrence vector from LN 1 of IPRF from MEMORY MODULE area I length of delimiter event occurrence vector from LN 2 of IPRF delimiter event occurrence vector in MEMORY MODULE area 2 PM-data BFIRST flip flop BLAST FINAL OUTPUTS MEMORY MODULE area 3 for the best entry in layer 0:
1 beginning delimiter of entry 2 # of hits N 3 dmin the beginning event occurrence values of the request in certain entries on this layer which are to be checked and stored in P/B MEMORY area 1 set by DPM INTERFACE MODULE to initialize prior to first call set by DPM INTERFACE MODULE prior to last call for this request only.
contains the following sets of four values 4 do 326 1.570344 2 “):1 1,570,344 TABLE 12
ENCODE MODULE REGISTERS EBL EHW ETL EI EIR EO EOP ET ER BSW EFRST ELAST bottom limit iso-entropicgram width top limit current Input entry interval previous input entry Output previous and current entry difference Remaining available number of bits in bit string word under formation Memory Address Register MAR 3 COUNTERS CTR NOC MLN 3 bit string number of occurrences pnysical length of output FLIP FLOPS bit string switch first time through last time through 327 327 1,570,344 TABLE 13
DECODE I MODULE REGISTERS Input and shift register for hybrid COUNTERS BCTRI DOI MARI MLNI DIEND DI FRST DISW D 1 END EOFI MSB 1 DIGO DIMEND indicates bits remaining in bit string forms absolute word output indicates MEMORY MODULE addresses indicates remaining words in MEMORY MODULE area to be converted FLIP FLOPS end of input first hybrid word input read control ( 0) last absolute word to calling module end of operation most significate bit, or flag bit, of bit string word in INR 1 ONE-SHOT MULTI-VIBRATORS decode module go absolute word ready or output 328 INRI 328 329 FIRST REGISTER 1,570344 TABLE 14
DELTA MODULE EXAMPLE OF OPERATION SECOND REGISTER 329 NO OF SHIFTS 128 b 4 32 16 8 4 2 I 0 O O 0 1 1 0 O 0 1 1 O 1 0 0 1 1 O 1 0 I 10 1 1 1 O 1 1 0 1 0 1 128 64 32 0 O O 1 O O 0 1 O 0 O 1 0 O O 0 O O 0 O O 0 O O 0 O O 16 8 4 2 1 0 O 0 O 0 O 0 O 1 O 0 1 0 O 0 O 0 O 0 O 0 O 0 O 0 O 0 O 0 O 1 O 0 1 0 O TABLE 15
DELTA MODULE REGISTERS DELI DELO DELEND input register ( 8 bits) output register ( 8 bits) 5 FLIP FLOPS 1 state indicates DELI is completely transformed to component powers of 2 1 state indicates first call on DELTA MODULE I X 6 X 8 X DELFST 1,570,344 TABLE 16
SEED MODULE REGISTERS OAR ONOC SDN SLINE SLN SMHW SMLI TO Tl T 3 SCE CNG SMB SMEND SMGO Memory output area register contains number of MEMORY OUTPUT area with current seed line value; Number of occurrences in current possible seed line; Current number of lines revolved relative to input line; Current possible seed line number; Current possible seed line length; Iso-entropicgram width (and length); Current line number; Largest and next largest occurrence value difference Iso-entropicgram width and largest occurrence difference value or the larger of the largest and next largest occurrence value difference or the iso-entropicgram width and largest occurrence value difference; Temporary storage for largest occurrence value; FLIP FLOPS Clock enable; Inhibits clock to SWITCH MATRIX; Inhibits DECODE I MODULE from clocking down MLN 3 while computing for SEED MODULE; ONE-SHOT MONOSTABLE MULTI-VIBRATORS Set at end of seed finding operation; SEED MODULE go.
330 330 331 OHW ORI ORTI OLINE OR 2 ORSN ORT 2 ORT 3 OAR OLN DELOP Ss SW OPSW 1,570,344 TABLE 17
OUTPUT MODULE REGISTERS Iso-entropicgram width; Output Register 1 for occurrence value of revolved seed line value from DECODE I MODULE:
Output Register Temporary I for test occurrence value from DECODE II MODULE; Contains the seed line number; Output Register 2 contains the output of DECODE 1 I MODULE and the results of the subtraction in Step 8:
Holds the largest component power of 2 (OHW OLINE) i.e the distance the seed line value must be revolved to reach the input line; Temporary Register-holds the length of the seed line value after it has been revolved the first time; Temporary Register 3 contains the physical length of the reference line in MEMORY MODULE area 2; Output Area Register contains the number of the memory area which holds the final output which is the occurrence values that are found to be present; Contains the physical length of the final output.
FLIP FLOPS DELOP = I causes DEL function; Toggle f/f used to determine cycle information i e, each input must be checked against; Used to determine output If set to 1 at the end of cycle 2, then output ORTI; Used to indicate to ENCODE MODULE that clipping circuitry is in effect.
331 TABLE 18
EVENT TIMES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Events 1 0 0 0 0 1 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 O 0 1 0 0 1 0 0 O 1 0 0 0 O O O O O O O O O O 0 O 0 1 0 0 1 0 0 0 0 O O O O 0 O O 0 1 0 0 1 0 0 0 0 0 1 0 O 0, 5, 8, 10, 15 delimiter E O vector 1, 11, 14 3,6 4,7, 13 The event occurrence vectors for events T-H-I-S as they appear in the data base.
-b T H S S C 4 LP .i -.i ,J TABLE 19
EVENT TIMES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Events /:’i’ o O O O 1 O O 1 O 1 O O O O 1 T O 1} O O O O O O O O O 1 O O 1 O 1, 11,14 (Bias = 0) H O I O O O O O O O O O O O O O 0 1 (Bias 1) I O 1 O O O O O O O O O O O O O 1,4 (Bias= 2) S O O 100 t O O O 00 00 1 1, 4, 10 (Bias 3) the occurrence of “IS” is shown here a “bit” in each row, exact entry E.O vectors for T-H-I-S biased to the left | leading delimiter leading delimiter U.a TABLE 20
EVENT TIMES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Events X 1 0 0 0 0 1 0 0 1 0 1 0 0 0 0 1 0,5,8, 10, 15 S O O O O 1 0 0 1 0 0 0 0 0 1 0 0 4,7, 13 I O O O 1 0 0 1 0 0 0 0 0 0 0 0 0 3,6 T 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1,11, 14 The event occurrence vectors for the events S-I-T as they appear in the data base of Table 1.
TABLE 21
EVENT TIMES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Events X 1 O O O O 1 O O 1 O 1 O O O O 1 S O O O O 1 O 0 1 O O O O 0 1 O 0 4, 7, 13 (bias = O I 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 2, 5 (bias= 1 T 1 O O O O O O O O O ‘i O O 1 O O O -1,9,12 (bias = 2 E.O vectors for S-I-T biased to the left ,: delimiter boundary crossed 334 1.570 344 1; 14 1,570,344 TABLE 22
EVENT 11 12 1 O O O 1 0 0 0 0 0 O 1 o O o 0 O 1 1 0 0 0 O O 0 0 0 total pipe width deals with word “test’ Center of Pipe Events X S I T No of Hits in Pipe TABLE 23
EVENT TIMES 8 9 10 1 0 1 1 0 O 0 O 0 O Total pipe width there are no hits 335 TIMES 14 15 Events t S I T 335 336 1,570,344 336 TABLE 24
EVENT TIMES 6 7 8 Events 1 O 0 1 l I I S O 0 1 1 1 0 0 T 0 0 0 Total pipe width deals with the word “is” Piper Center No of Hits 7 1 6 2 TABLE 25
EVENT TIMES 0 1 2 3 4 5 Event X I 1 0 O 0 O 1 I’ I I S O O O 0 1 I 0 0 1 0 0 T 0 0 0 0 0 Total pipe width deals with the word “this’ Pipe Center No of Hits 4 1 3 2 1 1 1 1,570,344 TABLE 26
Translation of Table 19 Into Linear Notation PASS 1 T I 11 14 represents line T HIT 1 1 1 PASS 2 TH 1 11 14 represents line T, H, i e, HIT 2 1 1 J H event was biased by 1 and added to PASS I PASS 3 THI 1 4 11 14 represents line T, H, I, HIT 3 1 1 1 i e, I event was biased by 2 and added to PASS 2 PASS 4 THIS HIT 4 10 11 14 2 1 1 1 represents line T, H, I, S, i.e, S event was biased by 3 and added to PASS 3.
TABLE 27
Translation of Table 20 PASS 1 S 4 7 13 HIT 13 13 HIT 1 1} into Linear -Form represents row S PASS 2 SI 2 4 5 7 13 HIT 1 1 1 1 1 PASS 3 SIT 2 4 5 7 12 13 HIT 1 1 1 1 1 I represents rows S, I, i e, I even was biased by 1 and added to PASS represents rows S, I, T, i e, T event was biased by 2 and added to PASS 2; NOTE: values -1 and 9 fell outside the pipe width and were dropped.
337 337 1,570,344 Event time O 1 No of hits 2 3 TABLE 28 ( pipe motion l total pipe width 4 5 6 7 8 9 10 11 12 13 14 15 1 1 1 1 1 Pipe starts centered on the rightmost event time and moves left one column (time occurrence) at a time Each time the number of hits are added and a maximum hit count is kept for each entry Upon processing an entry, if the maximum hits is greater than 0, then the center pipe for the entry and its maximum hit count is output TABLE 29
Translation of Table 22 to Linear Form < pipe direction 11 12 13 14 15 1 1 Center of Pipe No. of Hits center pipe output 13 2 TABLE 30 Translation of Table 23 to Linear Form Center of Pipe No. of Hits output -1 0 TABLE 31 Translation of Table 23 to Linear Form Center of Pipe No. of Hits 6 2 output 6 2 l I I 8 9 10 567 6 7 1 1 338 338 1,570,344 TABLE 32 Translation of Table 24 to Linear Form Center of Pipe No. of Hits l l l 0 1 2 3 4 5 1 1 output 3 2 TABLE 33 PIPE MODULE REGISTERS, COUNTERS & FLIP FLOPS Registers and Counters Ml M 2 M 3 OUT PSAV MAX N DI T P/B MEMORY "read" address counter; P/B MEMORY 'write" address counter; MEMORY MODULE area 3 "write" address counter; Register contains "center pipe" value if there is a "hit" for an entry; contains a-l if there are no hits for the entry being considered; Temporary save register for LN 2 from the IPRF; Register used as temporary storage to hold the current maximum number of hits within a pipe in an entry: Counter that always contains a "hit" count for an associated time occurrence contained in RH; Register containing current beginning delimiter value; Register used in the first part to hold the minimum time occurrence to be considered for a given entry In the second part, it is used to determine if a time occurrence lies within a pipe; Register used for storage of a time occurrence read from P/B MEMORY; Register for storage of value read from the event occurrence vector under consideration; RII RI Counter used in part two to keep track of the center of the pipe; 339 339 I CV TABLE 33-Continued PIPE MODULE REGISTERS, COUNTERS & FLIP FLOPS Registers and Counters S PW PWC BIAS LNRQ Pl-P 35 Register to keep a running tally of the hits within a pipe during part two; Register that contains pipe width; Register that contains pipe width -1. When this value is subtracted from the beginning delimiter, it gives the minimum time occurrence which will be considered for the current entry; Counter that contains bias count which is the number to be subtracted from the time occurrences of the event under consideration; Register that stores the length of request; Control counter. Set when the event to be processed is the first event of a request to be processed; PLAST ET GT SGN PFLG Set when the event to be processed is the last event of a request to be processed; The "equal to" set when two values being compared in the ALU are equal; The "greater than" set when two values being compared in the ALU are such that value I > value 2; Used as the sign bit for the MAX registerset when an exact occurrence has been found, reset otherwise; A flag flip flop which tells when to clock M l during pulse P 32 TABLE 34
BRIGHTNESS MODULE Shift P O I S S O N 0 P R I S O N 3 P R I S O N 6 P RI S O N 7 P R I S ON P R I S O N Flip Flops PFIRST 340 1,570,344 340 341 Do = 6 D, 3 D 6= O D = 1 D, = 3 ON C 1,570,344 TABLE 35
PRISON 46 6 6 + 6 3-3 -6 O + O -6 + 1 -1 + 6 3 + 3 341 + 7 + 7 = t 4 4 4 = 1-1 + O + O = + 2 + 2 = TABLE 36
BRIGHTNESS MODULE O M P R O M I S E 12 13 i 4 15 16 17 18 19 20 event times BIAS J O t TABLE 37
BIAS t ( 3) t + BIAS Sorted 3 values P 6 14 20 18 R 5 15 20 20 I 4 18 22 20 S 3 19 22 22 O 2 16 18 22 N I P RI S Request Events 342 1,570,344 342 TABLE 38
BRIGHTNESS MODULE FINAL INTERMEDIATE OUTPUT IN MEMORY MODULE 18 (CP) 14 (min) 5 (n) 18 ( 8) (a) ( 8) 8 mid (mid point for sorted values) 10 22 ( 8) 22 ( 8) TABLE 39
FINAL OUTPUT OF BRIGHTNESS MODULE STORED IN MEMORY MODULE (AREA 3) 15 (BD) beginning delimiter for entry (n) # of matching events which request and respond -‘ (# of hits) 6 (drin) sum of offsets to a mid 32 (do) sum of offsets to first event of response 20 1,570,344 TABLE 40
BRIGHTNESS MODULE Example: assume the following words dredged up by piping 1 PRISON 2 IMPRISONMENT 3 PRISONER 4 PRISM POISON 6 POISSON 7 IMPERSONATE 8 OPINIONATED 9 PRINCESS SIREN 11 RIPEN 12 REASON 13 NOSIRP 14 NONPROSIT If the request is “PRISON”, function of the system would order the above as follows:
1 PRISON 2 PRISONER 3 POISON 4 POISSON IMPRISONMENT 6 IMPERSONATE 7 PRINCESS 8 NONPROSIT 9 PRISM REASON 11 OPINIONATED 12 RIPEN 13 NOSIRP 14 SIREN INCL length % 99.1 % 83.3 % 78.86 % % 73.1 % 70.1 % 69.96 % 66.6 % 62.8 % 57.7 % 570/ % 49.9 % W/O length % % 83.3 % 78.95 % % 85.1 % 70.3 % 72.22 % 66.7 % 62.8 % 66.7 % 57.1 % %o % 343 343 344 1,570,344 344 TABLE 41
BRIGHTNESS MODULE EXAMPLE
Part 1 Initial conditions for first call on BRIGHTNESS MODULE for event “S” 5 Content of IPRF:
LNRQ = 3 length of request “SIT” LNI = 3 length of”S” E Ovector LN 2 = 4 length of delimiter occurrence vector 10 MEMORY MODULE AREA I 10001101 0 O l 01 0 0 O O “S”E O vectorl 13,7,4 l J MEMORY MODULE AREA 2 15 1000 1 1 11 0 1 O 1 0000 delimiter occurrence vector l 15, 10, 8, 5, O l 0 O O O O 1 00 20 00000001 Part I P/B MEMORY AREA 1 Value Address Content Name of Value 0 13 pipe center 25 1 6 pipe center 2 3 pipe center 3 -1 end of field
Set BFIRST 1 BLAST -0 n TV 345 1,570,344 TABLE 41 (Continued) Part 2 Content of P/B MEMORY area 2 processed.
Value Address Content 3 345 after FIRST EXIT after “S”E O vector is Name of Value CP MIN # hits I -1 CP MIN entry # hits “IS” CP MIN entry t “THIS” # hits 85, end of field
Part 3 Initial conditions for second call on BRIGHTNESS MODULE for event “I” Content of IPRF length of”I” E O vector length of delimiter occurrence vector MEMORY MODULE area I 1 0000 1 1 O O “I” E O vector 0 O O O O 1 O O J ( 6,3) MEMORY MODULE area 2 same as shown in Part I of Table 41 P/B MEMORY area 2 same as shown min Part 2 of Table 41 set BLAST O 8 LNI = 2 LN 2 = 4 1,570,344 TABLE 41 (Continued) Part 4 Content of P/B MEMORY after second exit processed P/B MEMORY area I Address Value Content 2 I 7 after “I”E O vector is Name of Value CP MIN -,I, # hits CP MIN en#hits ry hits “I 115 ” CP 1 12 MIN #hits -1 Part 5 Initial conditions for third call Content of IPRF LNRQ = 3 LNI = 3 LN 2 = 4 end of field on BRIGHTNESS MODULE for last event “T” length of request “SIT” length of “T” E O vector length of delimiter occurrence vector MEMORY MODULE area 1 1000 1 1 1 O “T” E O vector ( 14, 11, 1) MEMORY MODULE area 2 same as shown in Part I of Table 41 entry “THIS” 346 346 347 1,570,344 347 TABLE 41 (Continued) P/B MEMORY area 1 same as shown in Part 4 of Table 41 set BLAST 1 5 Part 6 Content of P/B MEMORY area 2 after third exit after “T” E O vector is processed Value Address Content Name of Value 0 14 CP 10 1 13 min 2 2 of hits Tentry TEST” 3 15 8 4 16 8 5 7 CP 15 6 6 min entry 7 2 # of hits s”S, 8 8 8 9 10 8 10 4 CP ‘ 20 11 I min 12 3 #of hits F entry “THIS” 13 2 8 14 5 8 15 7 8, 25 16 -1 end of field
Part 7 Content of MEMORY MODULE area 3 afterfourth exit Address Value Name of Value 0 10 beginning delimiter 30 entry 1 2 # of hits (N) “TES Ty 2 1 dmin “TEST2 1 dmin do 1,570,344 TABLE 41 (Continued) beginning delimiter # of hits (N) d entry dm In “IS” do J beginning delimiter # of hits (N) entry dmin “THIS” do 348 TABLE 42
DPM INTERFACE MODULE Mle (D 51 MEMORY MODULE area 1) M 2 e (D 52 MEMORY MODULE area 2) M 3 e (D 53 MEMORY MODULE area 3) TABLE 43
DPM INTERFACE MODULE For P/B MEMORY m 1 m 2 0 I Mle (D 52 P/B MEMORY area 1) 1 0 M 2 e(D 51 P/B MEMOR Yarea 2) 348 6 11 flip flops m 1 m 2 0 1 0 O 1 1 349 1,570,344 349 TABLE 44
Line 1 2 3 0123456789012345678 ‘)012345678901 0 11101010011010100000101110001011 Input Revolve 1 1 100111110101111100 ( 01110 ( 1001110 2 1101000011110 ( 001000100101101001 Revolve 2 3 10111000100010001100110111011101 4 11100100110011001010101100110011 Revolve 3 10010110101010101111111010101010 6 11011101111111111000000111111111 Revolve 4 7 10110011000000000100000100000000 8 11101010111111111110000110000000 9 10011111110000000101000101000000 11010000001000000111100111100000 11 10111000001100000100010100010000 Revolve 5 12 11100100001010000110011110011000 13 iooioiioooiiiioooioio 1000101010 ( 14 11011101001000100111111001111110 1011001110110011010000010100000 16 1110101001101010111000011110000117 10011111010111111001000100010001 18 11010000111100000101100110011001 19 10111000100010000111010101010101 Revolve 6 1110010011001100010011111111 <21 1001011010101010011010000000 -,22 11011101111111110101110000000000 23 10110011000000001111001000000000 24 11101010100000001000101100000000 10011111110000001100111010000000 26 11010000001000001010100111000000 27 10111000001100001111110100100000 28 11100100001010001000001110110000 19 10010110001111001100001001101000 11 ( 11101001000101010001101011100 3 ' 10110011101100111111001011110010 32 11101010011010100000101110001011 output TABLE 45 Memory Module SP Area 1 SMI assert SMS RMS RM 12 Revolve SM 5 8 Sl Sll I 522 521 531 532 line O Initial Line best seed 512 513 not asserted 511 Sil RMI 2 523 533 0 Inhibit enable -4 a 4:x. Save 7 15 16 C oj Signal Decode Routing Flip Flop Encode Lti Comments (Continued) Rou Lting l euable 20 21 HALT with in MEMORY MODULE area (line 21) 46 Possible Occurrence Values> 0 1 2 3 4 5 6 Delta Line 6 >) 1 0, 2, 4, 6 0 1 O 1 O 1 01 0 1 1 1 O O 1 O O 2 1 1 1 O O 1 4 1 1 1 O 6 1 1 O 00 1 00 1 1 0 1 0 0 0 O Coollm ellts 2L^ 41.
41.
No of Shifts Line 6 > 352 ^ O 1,570,344 TABLE 47
1 1 1 O O 1 O O 1 O 1 1 0 1 1 1 0 1 1 O 1 1 1 O 1 1 O 0 1 1 1 1 O 1 O 1 0 1 1 1 8 1 1 1 O O DELRO = 5 ( 101) Possible Occurrence Value TABLE 48
DELCOL = 0 ( 000) Line Implies (DELCOL + DELRO) 0 000 101 111 + 101 111 ( 7) 1 0 1 001 101 110 + 101 111 ( 7) 1 1 2 010 101 101 + 101 101 ( 5) 0 3 011 101 100 + 101 101 ( 5) O 4 100 101 011 + 101 111 ( 7) 1 4 101 101 010 101 111 ( 7) 1 5 Therefore the results 1100011 identify the possible occurrence values 0, 1, 4, and 5.
This is row five of the delta (Table 6).
352 1 O 1 1 1 O 0 1 0 1 1 1 0 O 0 O 1 O O Bit-Wise AND Result 1,570,344 TABLE 49
DELTA 2 MODULE REGISTERS & COUNTERS DELCOL ( 8 bits) DELHW ( 8 bits) DELRO ( 8 bits) DELO ( 8 bits) DELV ( 8 bits) DELEND DELFST DELOVL PI-P 5 -Possible occurrence (column) value counter.
Iso-entropicgram store.
Delta line value store.
Occurrence value output register.
Possible occurrence value column or shifted possible occurrence value counter.
FLIP FLOPS -” 1 ” state indicates entire DELTA line has been generated.
” 1 ” state indicates the first entry to flow of Fig 63.
-” 1 ” state indicates shifted line exceeds width of iso-entropicgram.
Control counter 1513.
TABLE 50 A
DELTA 2 MODULE INPUTS DELV DELRO DELHW DELFST flip flop OUTPUTS DELO DELEND DELOVL Shift value which is possible occurrence value of given line from OP of OUTPUT 2 MODULE or DOI of DECODE I MODULE.
-No of lines to be revolved which is line number of DELTA from RIL of REVOLVE 3 MODULE or OP of OUTPUT 2 MODULE or RIL of REVOLVE 2 MODULE.
Iso-entropicgram width value from HW of IPRF.
Set to ” 1 ” by DPM INTERFACE MODULE on first call.
Occurrence values making up line of DELTA specified by DELRO.
-” I ” state indicates end of DELTA line.
-” 1 ” state indicates shifted occurrence values of line exceed width of iso-entropicgram.
353 353 TABLE 50 B
REVOLVE 2 MODULE INPUTS MEMORY MODULE SWITCH MATRIX 2 DECODE I MODULE ENCODE MODULE RIL line to be revolved in proper area -all have been properly initialized contains number of lines to be revolved OUTPUTS MEMORY MODULE one of areas contains new encoded line (new line number is in SEED 2 MODULE) TABLE 50 C
REVOLVE 3 MODULE SEED 2 MODULE INPUTS Current seed in DPM MEMORY area 1 SMHW ( 8 bits) SMLI ( 8 bits) CNG (I bit) Same as TABLE 50 B TABLE 50 D iso-entropicgram width loaded from IPRF the line # of the information contained in DPM MEMORY area 1 bistable used to reflect a call from the CHANGE 2 MODULE OUTPUTS NOC ( 8 bits) number of I’s in seed line SLINE ( 8 bits) the new line number of the seed SLN ( 8 bits) the physical length of the seed in words OAR ( 2 bits) -the number of the memory area containing the seed New seed in DPM MEMORY area 3.
DCA 354 1,570344 355 1,570,344 355 TABLE 50 E
OUTPUT 2 MODULE INPUTS Seed line is in MEMORY MODULE area 1; If necessary, the reference line is MEMORY MODULE area 2 5 OHW ( 8 bits) iso-entropicgram width from IPRF OLINE ( 8 bits) line number of seed from IPRF DELOP (I bit) -bistable set to I if DEL function is desired OUTPUTS OLN ( 8 bits) length of seed line 0 OAR ( 2 bits) memory area containing the seed ( 3 line 0 representation of the seed in MEMORY MODULE area 3.
TABLE 50 F 15
CHANGE 2 MODULE INPUTS The change line is in MEMORY MODULE area I; The seed line is in MEMORY MODULE area 2; CLINE contains the line number of the seed line loaded from IPRF 20 OUTPUTS Same as for SEED 2 MODULE.
TABLE 50 G
AUXILIARY MEMORY II INPUTS MAR ( 8 bits) MAR ( 8 bits) MIR ( 8 bits) OUTPUTS MDRI ( 8 bits) MDR 2 ( 8 bits) memory address register for memory area A l Loaded from D 55/WBP of REVOLVE 2, or D 55/WBP of REVOLVE 3 or D 54 of DPM INTERFACE, or M 1/M 2 of PIPE, or DSI/M 2 of BRIGHTNESS MODULES.
memory address register for memory area A 2.
Loaded from the same modules as for MAR of memory A Additionally it receives signals from WP/WT of OUTPUT 2 MODULE.
-the memory input register It receives its input from D 54 of REVOLVE 2, D 54 of REVOLVE 3, RII of OUTPUT 2, D 53 of DPM INTERFACE, D 52 of PIPE, or D 54 of BRIGHTNESS MODULES.
-the memory data register for memory area 1.
Its output is sent to the REVOLVE 2, REVOLVE 3, OUTPUT 2, DPM INTERFACE, PIPE and BRIGHTNESS MODULES.
-same as for MDR 1.
TABLE 51
Possible Occurrence Values Line Given or No.
Input Line > O 0 12 3 4 5 6 7 1 0 1 1 0 1 0 0 ( 1 2, 3, 5) 1 1 1 O 11 1 O 1 O O 1 10 O 1 1 1 O 1 O 1 O 1 1 O 1 1 11 1 1 1 1 O 00 O O 0 O 1 O O O O 1 O 1 1 O O O 356 1.570 344 11;f 1,570,344 CYCLE I CYCLE 2CYCLE 3 _ TABLE 52
0 1 2 3 4 5 6 7 8 I I 1 1 1 1 1 1 1 1 1 1 0 0 1 1 O O 1 1 1 1 1 000 10 O 1 O 1 < Possible occurrence values E F O vector of input line to iso-entropicgram ( 0, 2 3 5) r l Line 3 of delta offset 5 (values 5 6 7) Line 3 of delta offset 3 (values 3, 4 5, 6) (, After first XOR (values 3, 4 7) Line 3 of delta offset 2 (values 2, 3, 4, 5) < After 2nd XOR (values 2, 7) 1 1 1 1 O 1 O 1 O 1 Line 3 of delta offset 0 (values 0, 1, 2, 3) < Line 3 of the iso-entropicgram (values 0, 1, 3, 5, 7) Ignore all beyond possible occurrence value 7. TABLE 53 REVOLVE 2 MODULE REGISTERS RIL WBP WAP WAS WAT RI RII FLIP FLOPS FF PI-1-P 10 -Number of lines to be revolved from SEED 2 MODULE or OUTPUT 2 MODULE; Write pointer register for AM II MEMORY; Read pointer register for AM II MEMORY; Reverse read pointer register for AM II MEMORY; -Pointer register for number of reads from AM II MEMORY; Intermediate occurrence value from AM l I MEMORY; -Delta line occurrence value store from DELTA 2 MODULE; -Halt; -Control counter. CYCLES <4, S L 357 357 1,570,344 TABLE 55 REVOLVE 3 MODULE EXAMPLE Initial Conditions: Register T 3 of SEED MODULE= 3 MEMORY MODULE area = 0, 2, 3, 5 (No of lines to be revolved) (EO Vector of input line) Conditions After Cycle 1: AM II MEMORY AREA I WAS=WAT= 3 Conditions After Cycle 2: AREA 2 Address AM II MEMORY AREA 1 Address Value 0 3 1 4 2 7 WAS = WAT = 3 AREA 2 358 Value 358 1,570,344 TABLE 55 (Continued) Conditions After Cycle 3: AM-II MEMORY AREA I AREA 2 Address Value WAS = WAT = 3 Conditions After Cycle 4 & EXIT: AM-II MEMORY AREA 1 Address AREA 2 Value Nl = 7 N 2 = 5 359 359 360 1,570,344 TABLE 56 SEED 2 MODULE REGISTERS AND COUNTERS TI TO T 3 SN SMHW SMLI NOC SLN SLINE FLIP FLOPS CNG SMB Pl-Pl 3 -Temporary store; Stores difference between largest and next largest occurrence values; Keeps running tally of number of lines which the REVOLVE 3 MODULE has revolved; Stores largest occurrence value of seed line; Stores iso-entropicgram width value; Stores the line number for the input line of the isoentropicgram; Stores number of occurrences in seed line; Stores the length in words of the seed line; Stores the length of the current seed line whose number is stored into T 3 Indicates a call from CHANGE MODULE; Indicates when length registers are to be counted down; control counters. 360 361 1,570,344 361 TABLE 57 OUTPUT 2 MODULE COUNTERS/REGISTERS DESCRIPTION WB Count up counter for AM-11 MEMORY read 5 pointer; WP Count up counter for AM-I MEMORY write pointer; WT Count down pointer for AM-11 MEMORY read pointer; OHW Iso-entropicgram width; 10 OLINE Given line value; DO Shifted delta line value; N Difference value indicating number of lines to be revolved; RI Occurrence value to be checked at input Is line; RII Stores occurrence value from given line, value from AM-II MEMORY and maximum value 255; R 2 Difference value indicating minimum occurence value that can be effected by shifted delta 20 values; M 3 MEMORY MODULE area 3 write address pointer; COUNTERS/REGISTERS(Cont'd) DESCRIPTION SLN Contains the physical length of the regenerated line; 25 FLIP FLOPS DELOP Set to "I" if the DEL function is desired; EFF Used to determine when a DECODE I read is necessary during the DEL function T Used to monitor parity of the DEL function 30 output; PI-Pl 1 Control counter 2022. 362 v I,5734 TABLE 58 EXAMPLE OF OUTPUT 2 MODULE OPERATION Line Col. 0 1 23 4 5 6 7 1 O 1 1 O 1 1 1 O 1 1 O O 1 1 1 1 O 1 O 1 O 1 1 1 1 1 1 O O 1 O O 1 O 1 1 O 1 1 0 O 1 O 0 1 0 1 1 1 0 O 0 O 0 O -Input line t E Seed line Iso-entropicgram of Example 1 O O 0 1 1 MEMORY M, Line # 5 HW 8 LN 1 2 IPRF values 0 O O 1 O 0 O O O O DODULE area 1 OUTPUT 2 1 O O O O 1 1 MODULE 4 0 1 1 O 1 O O O area 3 OUTPUT 2 MODULE not using DEL function 362 1,570,344 3 A 2 363 1 O O O O O 1 O 0 1 1 O O O O O area I 1,570,344 TABLE 58 (Continued) 1 O O O O 1 1 O 1 O O O O O 1 O area 2 content of MEMORY MODULE prior to call HW Lint 8 -5 = 3 first cycle col ( 1) ( 2) ( 3) e; = I of lines to be revolved line of delta to be generated by DELTA 2 MODULE 0 1 2 3 4 5 6 7 1 1 1 O O O O O seed line 0 O 0 = parity of ( 3 1 1 1 1 aligned and shifted delta line 0 0 0 0 0 AND of ( 1) and ( 2) ) hence no value written to MEMORY MODULE area 3 second cycle col ( 1) ( 2) ( 3) 0 1 2 3 1 1 1 O 1 1 1 1 1 1 O I = parity of ( 3) Don t care area 1 Don't c area 4 5 6 7 0 O 0 O seed line aligned and shifted delta line 0 0 0 0 AND of ( 1) and ( 2) hence value ( 2) is written to MEMORY MODULE area 3 are 10000010 area 3 contents of MEMORY MODULE after call OUTPUT 2 example using DEL function 363area 364 1,570,344 TABLE 58 A CHANGE 2 MODULE COUNTERS /REGISTERS RI RII CLINE FLIP FLOPS PI-P 6 register used to store values read by DECODE I MODULE register used to store values read by DECODE II MODULE register used to store line number of the seed line from IPRF SN 7474 's used to create a pulse generator 364 TABLE 59 HARDWARE AND SOFTWARE FLAGS, REGISTERS AND MEMORY AREAS USED FOR PARSER PROGRAM GENERAL REGISTERS RO Contains address of the two word area PNBPTRI RO -4 I PNBOUT list PNBCNT This allows the calling module to obtain the results of the request. RI Unused by PARSE. R 2 Contains the representation of the current character in the PSTRING containing the request. R 3 Points to a stack ESTAK This stack contains the pointers to the seed headers of the events to be processed. R 4 Points to the request string which was built by the REQUEST subroutine. R 5 Subroutine register. R 6 (SP) Hardware stack register. FLAGS Li SW 0 if the request is from layer 0, 1 if the request is from layer 1. EXIT A loop control flag which is used while scanning letters to make a word. ESCAPE A loop control flag which is used while scanning words to make a sentence, i e, as long as ESCAPE is not set, control goes back to JOIN 2 and another word seed header pointer is stacked on ESTAK. BRSW The brightness flag It is set to 1 if the BRIGHT module is to be called, If BRIGHT is not to be called, the BRSW flag is set to 0. 365 I 1,570,344 365 366 1,570,344 366 TABLE 59 (Continued) HARDWARE AND SOFTWARE FLAGS, REGISTERS AND MEMORY AREAS USED FOR THE PARSER PROGRAM STORAGE VARIABLES RLNO This word is used to keep a running tally of the length of the current word being parsed The length is given by the number of letters in the word. RLN 1 This word is used to keep a running tally of the length of the current sentence being parsed The length is given in the number of words. WDEL A constant containing a binary representation of the word delimiter. SDEL A constant containing a binary representation of the sentence delimiter. PNBPTR A constant whose value is the beginning address of a list that is to contain the results of the PIPE and B Ri GHT process. TABLES LOET Table containing the pointers to the seed headers for all events on layer 0. Ll ET Table containing the pointers to the seed headers for all events on layer 1. TABLE 60 A EXAMPLE OF FORM OF WORD LAYER 0 REQUEST AND SENTENCE LAYER 1 REQUEST Sentence request Word request Where # is a sentence delimiter; Ad (blank) is a word delimiter. Entry > Possible Occurrence Value THIS 0 1 2 TABLE 60 B
Example for PARSER, PIPE, BRIGHT programs Layer Diagram for the Sample Data Base 2 3 4 5 IS 3 4 5 6 7 A TEST 8 9 10 11 12 13 14 WHICH 16 17 18 19 20 21 22 THE 23 24 BEST 26 27 28 29 30 31 1 I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1; 1 1 1 1,1 1 1 1 1 Layer 0 Layer 0 Event Nos.
Event / T H I S A E W C B A-,.
-.
5:> La P 4 h l 1,570,344 TABLE 60 B (Continued) Entry Possible Occurrence Value Layer 1 Event Nos Event 1 THIS 2 IS 3 A 4 TEST WHICH 6 THE 7 BEST THIS IS A TEST WHICH THE BEST 0 1 2 3 4 5 6 7 8 9 10 THIS IS BEST 11 12 13 14 15 Layer 1 TABLE 60 C
BETTER,:
–< input string pointer > = < REQUEST > PW = 1 ESTAK PNBOUT \ \i << NULL > PCO = 3 BVCO = 0 50 368 368 369 1,570,344 TABLE 60 D
Meaningful main memory locations after the request has been scanned PSTRING BETTER /: = R 4 ESTAK RLNO 240 top-of-stack 224 PNBOUT l 204 204 224 236 (LOET’s) TABLE 60 E
AFTER PIPE PROGRAM CONTENT MAIN MEMORY RLN O PNBOUT 1 CONTENT P -1 /B MEMORY area 1 center pipe values for layer 0, entries to be checked by BRIGHT program 369 ESTAK ? 240 224 204 204 224 236 (LOET’ s) 1,570,344 TABLE 60 F
MAIN MEMORY AFTER BRIGHT PROGRAM IS CALLED PNBPTR PNBCNT PNBCNT 1 (No of entrie s) 370 7 Entry No < "BEST" > 699 Brightness Value TABLE 60 G
R 4 will act as a pointer during processing of ESTAK from 236 (‘B’) to 240 (‘R’) The top-of-stack pointer, ESTAK, remains unchanged.
370 RNL O ESTAK 240 224 204 204 224 236 R 4 ESTAK (:240 224 204 204 224 371 1,570,344 371 TABLE 60 H
After PIPE MODULE has processed first event ”B” of data base MEMORY MODULE area 1 area 2 area 3 26 30 P/B MEMORY area 2 26 (biased occurrence value) 1 (No of hits) -1 (end of field)
TABLE 601
After processing second event “E” MAIN MEMORY P/MEMORY area 1 ESTAK 2 240 2 y 6 224 2 204 23 204 1 224 11 236 1 -1 1,570,344 TABLE 60 J
After PIPE program completes MAIN MEMORY ESTAK R 4 > 240 224 204 204 224 236 MEMORY -1 -1 -1 -1 MODULE area 3 (CP) (No of hits) (CP) (No of hits) (CP) No of hits (CP) No of hits (CP) No of hits (CP) (No of hits) (CP) (No of hits) TABLE 60 K
Memory prior to BRIGHT program call MAIN MEMORY P/B MEMORY area 1 ESTAK R 4 26 4 240 12 224 -1 204 204 224 236 372 372 1,570,344 TABLE 60 L
After first pass of BRIGHTNESS module P.’B MEMORY area 2 27 center pipe for “BEST” 26 current leftmost entry in response 1 No of hits 32 adjusted entry 255 -1 TABLE 60 M
After second pass of BRIGHTNESS MODULE P,’B MEMORY area 1 28 current center pipe 26 current leftmost entry 2 No of hits 32 > adjusted entries -1 373 373 1,570,344 TABLE 60 N
After BRIGHTNESS MODULE completes last pass P/B MEMORY area 1 beginning delimiter No of hits 4 8 ($-min) 28 d O At ESTAK 240 224 no 204 longer > needed 204 224 236, TABLE 600 fter BRIGHT program completes PNBPTR A, PNBOUT 7 (entry No) 699 (BV) 374 374 1,570,344 TABLE 61
GENERAL PURPOSE REGISTERS R O HARDWARE AND SOFTWARE FLAGS, REGISTERS AND MEMORY AREAS USED FOR PIPE PROGRAM Parameter register; 1 Points to a seed header as the OUTPUT subroutine is called; 2.Points to DAREA if memory management subroutines DPMMEM/MEMDPM are called to manipulate a delimiter seed; 3.Points to WAREA if memory management subroutines DPMMEM/MEMDPM are called to manipulate a non delimiter seed; Parameter register; 1 I.Points to the two word area at DOAR if calling the OUTPUT, DPMMEM, or MEMDPM subroutines to manipulate a delimiter seed; 2.Points to the two word area at WOAR if calling the OUTPUT, DPMMEM, or MEMDPM subroutines to manipulate a non delimiter seed; Used in PI 22 as a temporary pointer to delimiter seed; Points to the event stack ESTAK; R 2 R 3 Points to the LXET address PTR in ESTAK which is currently being processed; after PI 22 it points to the output list PNBOUT; Return instruction pointer; R 7 FLAGS LISW ESCAPE BRSW Instruction pointer; Is 0 if the events on ESTAK are from layer 0; is I if the events on ESTAK are from layer 1; Is 0 if the events being processed are from layer 0 and the response is to be given from layer 1; is 1 if the events on ESTAK are from layer 0 and the response is to be made from layer 0 or the events on ESTAK are from layer I and the response is to be made from layer 1; The BRIGHT program schedule flag; 0 if the BRIGHT program is not to be scheduled; 1 if the BRIGHT program is to be scheduled.
Rl R 4 R 5 375 375 À, À TABLE 61 (Continued) #1 OCTAL constants used mainly to set bits in the STATUS and AI registers of the DPM INTERFACE MODULE #6 #10 #30 J FIRST LAST DPM PIPGO PBM BDONE, #DOAR #DAREA #WOAR # WAREA # PNBOUT OCTAL constants used to set bits in the DPM INTERFACE MODULE STATUS register The address of the area beginning at DOAR.
This value is loaded into register R 1 prior to calling the OUTPUT, DPMMEM, or MEMDPM routines to manipulate a delimiter seed; The address of the area beginning at DAREA.
This value is loaded into register R O prior to calling DPMMEM, MEMDPM routines to manipulate a delimiter seed; The address of the area beginning at WOAR.
This value is loaded into Rl prior to calling the OUTPUT, DPMMEM, or MEMDPM routines to manipulate a non-delimiter seed; The address of the area beginning at WAREA.
This value is loaded into R O prior to the calling of the DPMMEM or MEMDPM routines to manipulate a non-delimiter seed; The address of the area beginning at PNBOUT.
This value is loaded into R 4 at PI 22 It is a pointer to the output list whose entries are the ordered pairs vi entry # vii brightness value 376 1,570344 174 #2 TABLE 61 (Continued) HARDWARE AND SOFTWARE FLAGS, REGISTERS AND MEMORY AREAS USED FOR PIPE PROGRAM MEMORY STORAGE 5 LIPTR The beginning address of the layer header for layer 1:
HWI The iso-entropicgram width for layer 1:
This is the second word of the layer 1 header; RLNI A one word area used to maintain the length of a request (in words) which is directed at layer 10 LOPTR The beginning address of the layer 0 header; HW O The iso-entropicgram width for layer 0; this value is the second word of the layer 0 header; 15 RLN O A one word area used to maintain the length of a request (in letters) which is directed at layer 0; LPTR A common word which points to LOET if Ll SW is O; 20 Ll E Tif LIS Wis 1; HW A common word which contains HWO if LISW is O; HWI if LISW is 1; RLN A common word which contains 25 RLN O if L 1 SW is 0; RLNI if LISW is 1; DNOC A word which holds the number of l’s contained in the delimiter line O; NOC A word used to reflect the number of the entry 30 on the layer currently being processed; WOLN The second word of the area beginning with WOAR.
It contains the length of the line 0 representation of the non-delimiter seed currently being processed; 35 DOLN The second word of the area beginning with DOAR.
It contains the length of the line 0 representation of the delimiter currently being processed; PW A constant representing the width of the pipe; PCO A constant representing the pipe cutoff value; 40 i.e, the minimum number of hits need in a pipe; PNPCNT The second word of an area beginning with PNBPTR It contains the number of entries in the output list PNBOUT; 45 A 2 AD A one word value which keeps track of the address in P/B MEMORY area I for writing; 377 1,570,344 377 TABLE 61 (Continued) HARDWARE AND SOFTWARE FLAGS, REGISTERS AND MEMORY AREAS USED FOR PIPE PROGRAM MEMORY STORAGE 5 (Continued) M 3 AD A one word value which monitors the address in MEMORY MODULE area 3 for reading; B RCNT A tally counter which monitors the number of writes made to P/B MEMORY area 1; 10 OV A single word area which contains a center pipe value read from MEMORY MODULE area 3; NH A single word area which contains the number of hits in the pipe just read from MEMORY MODULE area 3; 15 DPM INTERFACE MODULE REGISTERS STATUS This register is read, written, and monitored by the software package The bit configuration sets in this register 20 determine the sequence of events in the DPM machine; AI This is an address registerThe areas that it addresses are controlled by bits in the STATUS register; 25 DATAI This is the input registerAll reads (except STATUS) on the DPM machine are gated through this register; DATAO The output registerAll writes (except STATUS and AI) are gated through this register 30 378 1,570,344 378 1,570,344 TABLE 62
HARDWARE AND SOFTWARE FLAGS, REGISTERS AND MEMORY AREA USED FOR BRIGHT PROGRAM RO Parameter register 1 Points to a seed header if OUTPUT subroutine is called.
2 Points to DAREA if memory management routines DPMMEM/MEMDPM are called to manipulate a delimiter seed.
3 Points to WAREA if memory management routines DPMMEM/MEMDPM are called to manipulate a nondelimiter seed.
R 1 Parameter register R 2 R 3 R 4 FLOATING POINT REGISTERS ACO-AC 4 1 Points to the two word area at DOAR if a call is made to the OUTPUT, DPMMEM, or MEMDPM routines to manipulate a delimiter seed.
2 Points to the two word area at OUTPUT, EPMMEM, or MEMDPM routines to manipulate a non-delimiter seed.
Not used by the BRIGHT module.
Points to the top of ESTAK.
Points to the address of the seed header of the current seed being processed.
Registers which are internal to the floating point package on the PDP-1 1/45 Are used to store a number of temporary and intermediate values These can be obtained by looking at the flow chart, description and code of the BRIGHT module.
FLAGS 0 if the lengths of the request and possible responses are NOT to be used in computing a brightness value; 1 if the lengths of the request and possible responses are to be used in computing a brightness value.
LNGSW 379 379 so so 1,570,344 TABLE 62 (Continued) IITERALS, #1 #2 #6 #30 D 9 Octal constants Decimal constant 9 FIRST LAST BMGO DPM PBM DIINIT BDONE #WOAR Octal constants used to set the various bits in the STATUS REGISTER of the INTERFACE MODULE The address of WOAR This value is loaded into register RI if the OUTPUT, DPM, MEM, MEM DPM subroutines are called to manipulate a non-delimiter seed.
WAREA # DOAR # DAREA The address of WAREA This value is loaded into register R O if the DPM, MEM, MEM DPM subroutines are called to manipulate a non delimiter seed.
The address of DOAR This value is loaded into register R O if the OUTPUT, DPM, MEM, or MEM DPM subroutines are called to manipulate a non delimiter seed.
The address of DAREA This value is loaded into register R O if the DPM MEM or MEM DPM subroutines are called to manipulate a delimiter seed.
e Its 380 380 1,570344 TABLE 62 (Continued) MEMORY STORAGE A one word area containing the length of the request currently being processed.
A tally counter This word contains the number of entries contained in the output list PNBOUT.
The second word of the area beginning with WOAR.
It contains the length of the line 0 representation of the non-delimiter seed currently being processed.
The second word of the area beginning with DOAR It contains the length of the line 0 representation of the delimiter seed for this request.
A word which holds the number of I’s contained in the delimiter line 0 representation.
A word used to reflect the current layer entry number being processed.
*AICNT DI N A word used as an address pointer to DPM MEMORY area 3 when reading the results of the brightness process.
The first value of a four value set read from DPM memory area 3 This value contains a beginning delimiter value for the entry whose brightness status is reflected in the three values that follow.
The second value read from DPM memory area 3.
This value contains the number of events in the request that also appeared in this entry.
S DO The third value read from DPM memory area 3.
This value reflects the minimum degree of closeness between the events in the request and the events in this entry.
The fourth value read from the DPM memory area 3.
This value represents a maximum separation value between the events in the request and the events in this entry This value will be used as a normalizing value.
A word used to hold the beginning delimiter of the entry about to be processed.
A word used to hold the ending delimiter of the entry about to be processed.
TDI TD 2 LS A word used to hold the length of the entry being processed.
INTERFACE REGISTERS Same as for the PIPE MODULE RLN PNBCNT DOLN DNOC NOC 381 381 1,570,344 TABLE 63
HARDWARE AND SOFTWARE FLAGS, REGISTERS AND MEMORY AREAS USED FOR OUTPUT SUBROUTINE GENERAL REGISTERS RO RI R 2 R 3 R 4 LITTERALS #0 #10 #6 J DPM OMGO BDONEJ MEMORY’ STORAGE HW INTERFACE REGISTERS Same as with PIPE MODULE.
Points to the seed header of the seed to be output; Points to a two word area; Loaded with the physical length of the seed; Loaded with the address of the seed; Not used.
Octal constants i S Octal constants used to set bits in STATUS register of DPM INTERFACE MODULE The word which contains the iso-entropicgram width of the layer associated with this seed.
382 382 TABLE 64
HARDWARE AND SOFTWARE FLAGS, REGISTERS AND MEMORY AREAS USED FOR MEMDPM SUBROUTINES GENERAL 5 REGISTERS RO Points to main memory save area (DAREA or WAREA) from which transfer is to be made; RI Points to a two word area (DOAR or WOAR); R 2 Loaded from RO; 10 R 3 Loaded with the first word (MEMORY MODULE area number) pointed to by RI, i e, the area to which transfer is to be made; R 4 Loaded with the second word (physical length of seed in words in DOLN or WOLN) pointed to 15 INTERFACE by RI; REGISTERS Same as described in the PIPE MODULE.
TABLE 65 20
HARDWARE AND SOFTWARE FLAGS, REGISTERS AND MEMORY AREAS USED FOR DPMMEM SUBROUTINES GENERAL REGISTERS 25 RO Points to main memory save area (DAREA or WAREA) to which transfer is to be made; Rl Points to two word area (DOAR or WOAR); R 2 Loaded from RO; R 3 Loaded with the first word (MEMORY MODULE 30 area number) pointed to by RI; R 4 Loaded with the second word (physical length of seed in words in DOLN or WOLN) from the area pointed to by RI; INTERFACE REGISTERS Same as for the PIPE MODULE.
383 1,570,344 383 1,570,344 TABLE 66
HARDWARE AND SOFTWARE FLAGS, REGISTERS AND MEMORY AREAS USED FOR DECODE I SUBROUTINE GENERAL REGISTERS R O RI R 2 Used to hold the value just read from the hardware DECODE I MODULE; -Not used; -Not used; Not used; -Not used.
LITTERALS #10 Octal constant used to prime interface register AI.
Al will, in turn, cause the results from DECODE I MODULE stored in MEMORY MODULE to be gate to DATAI.
DPM l DIGO BDONE DPM INTERFACE REGISTER STATUS Al DATAI J Octal values used to set ml 1, m 2, m 3 bits in the DPM INTERFACE STATUS register.
Same as described in the PIPE MODULE.
R 3 R 4 384 384 TABLE 67
HARDWARE AND SOFTWARE FLAGS, REGISTERS AND MEMORY AREAS FOR INSERT SUBROUTINE GENERAL REGISTERS R O RI R 2 R 3 R 4 Not used; Not used; Contains the current entry # to be inserted; Points to the memory area PNBOUT; Contains the number of entries in PNBOUT, i.e, R 4 = PNBOUT; FLOATING POINT PACKAGE REGISTERS AC O ACI MAIN MEMORY PNBPTR PNBCNT Contains the brightness value (BV) of the current entry in PNBOUT; Contains the current brightness value (BV) to be inserted in PNBOUT; Contains the beginning address of the memory area PNBOUT; Contains the number of entries in PNBOUT.
APPENDIX B Index of Program Listings B-I B-2 B-3 B-4 B-5 B-6 B-7 B-8 B-9 B-10 B-11 B-12 B-13 B-14 B-15 B-16 B-17 B-18 B-19 B-20 B-21 PARSER Program PIPE Program B RIGHT Program OUTPUT Subroutine MEMDPM Subroutine DPMMEM Subroutine DECODE I Subroutine INSERT Subroutine FORMATER Program COMMAND, GET INTEGER GET FLOATING POINT Subroutines REQUEST Subroutine PROCOUT (Process Output) Subroutine SETUP Subroutine GENERATE Subroutine SORT Subroutine PRINTR (Printer) Subroutine PRNTC (Print a Character) Subroutine GETC (Get a Character) Subroutine FORMATER DATA STRUCTURE DATA STRUCTURES Constants Defined by FORMATER Program Page No.
386 387389 391 392393 393 393 394394 396 397399 400 401 402 402 402 403 404 405 385 1,570,344 1 R 55 386 1,570,344 6 B-22 Code for the DATABAS Program A LAYER INITIALIZATION B LAYER BUILDING C LAYER REQUEST D PROCESS A LAYER 0 ENTRY E ADD N EVENTS F PUT NEW SEED IN STORAGE G SEARCH FREE SPACE H GARBAGE COLLECTION I RELEASE SPACE J ASH (Adjust Seed Header) K Additional Variables Demanded by the Layer Building Method B-i 1 PARSER PROGRAM PARSE this is the parser for performing PIPING and BRIGHTNESS it is assumed that R 4 points to a request string that has been preprocessed for form and correctness Register usage in this module -R O parameter register -R 1 parameter register R 2 work register R 3 pointer to event stack (ESTAK) R 4 pointer to request string -SP register to the stack register PARSE:
(P Al) (P Al) (PA 2) (PA 3) (PA 4) PFI:
(PA 5) JOIN 1:JOIN 2:
(PA 6) JOIN 3:
(PA 7) (PA 12) (PAS) PF 2:
(P Al I) (PA 9) PF 3:
MOV MOV MOV MOV MOV CLR CLR CLR MOV MOV CMP BEQ CLR TST BR INC INC CLR CLR MOV CMP BNE INC INC INC JMP CMP BNE INC JMP MOV R 0,-(SP) Ri,-(SP) R 2,-(SP) R 3,-(SP) R 4,-(SP) Li SW ESCAPE BRSW #ESTAK,R 3 (R 4)+,R 2 R 2,WDEL PFI RLN 1 (R 4)+ JOIN 1 ESCAPE LNGSW RLN O EXIT (R 4)+,R 2 R 2,SDEL PF 2 LISW EXIT ESCAPE JOIN 5 R 2,WDEL PF 3 EXIT JOIN 4 LOET(R 2),-(R 3) (PA 10) INC save volatile registers reset decision switches R 3 points to event stack get a character is the character a word delimiter true exit i e is a word delimiter set layer 1 request length to 0 skip over word delimiter exit decision set escape decision switch clear layer 0 request length indicator get another character compare with sentence delimiter false exit, i e, not equal true exit; set layer 1 decision switch set exit and escape decision switches decision exit is the character a word delimiter false exit; not a word delimiter set exit decision exit (decision) push pointer to seed header for this event on ESTAK increment layer 0 request length 405 406 409 412 412 413 415 415 417 418 419 420 386 1,570,344 386 1 1 1 RLN O 387 (PA 13)JOIN 4:JOIN 5:
(PA 14) (PA 15) (PA 17) (PA 16) P A 16:
(PA 18) JOIN 6:
(PA 19) and (PA 21) (PA 20) PA 20:
(PA 22) (PA 23) PEXIT:
TST BNE JMP JSR TST BEQ JSR BR ADD TST BNE TST BEQ MOV BR MOV NEG MOV INC JMP MOV MOV MOV MOV MOV MOV RTS 1,570,344 EXIT + 2 JOIN 3 R 5,PIPE B RSW PA 16 R 5,B RIGHT JOIN 6 RLN,R 3 ESCAPE PEXIT PNBCNT PA 20 @PNBPTR,R 2 + 3 #2,R 2 R 2 Li ET(R 2),-(R 3) RLNI JOIN 3 (SP)+,R 4 (SP)+,R 3 (SP)+,R 2 (SP)+,RI (SP)+,R O #PNBPTR,R O R 5 387 is exit flag set true exit false exit recycle perform piping is there a need for brightness false exit perform brightness decision exit adjust stack test escape switch if set then exit anything in list no get “best” hit event number stack layer I event’s seed header pointer on ESTAK increment layer I request length repeat the cycle restore context set up output parameter return to caller B-2 PIPE PROGRAM process This process performs the PIPING hardware function and performs the setup for the BRIGHT process if that is necessary The BRIGHT process will not be scheduled if the following two conditions are met:
a an exact hit is found b escape is not set.
MOV MOV MOV MOV MOV TST BEQ MOV MOV MOV MOV BR MOV MOV MOV MOV LDCIF MULF ADDF STCFI R 0,-(SP) Ri,-(SP) R 2,-(SP) R 3,-(SP) R 4,-(SP) LISW BF 1 @LIPTR,R O LIPTR,LPTR HW 1,HW RLNI,RLN JOINI @LOPTR,R O LOPTR,LPTR HW 0,HW RLN 0,RLN AC 0,RLN AC 0,FPCO AC 0,FRND AC 0,PCO save context check layer 1 switch false exit, i e, on layer 0 R O contains pointer to sentence delimiter seed header initialize layer pointer initialize hologram width initialize request length exit decision RO-pointer to word delimiter seed length save proper layer pointer hologram width is layer 0 value initialize request length float request length multiply by pipe cutoff round up store integer in pipe cutoff PIPE (Pl) PIPE:
(PI 2) (PI 5) (P 16) (PI 3) BFI:
(PI 4) JOIN 1:
(PI 7 1) 388 (PI 7 2) MOV JSR MOV MOV JSR (PI 8) (PI 9) (PI 10) (PI 11)JOIN 2:
(PI 12) (Pl 13) (Pl 13 1)JOIN 3:
(Pl 13 2) (PI 14) (PI 15) (PI 16) (PI 17) (PI 18) (PI 21) (PI 22)PIPADJ:
MOV MOV MOV ADD MOV MOV JSR CMP BEQ MOV JSR MOV JSR CMP BNE ADD MOV MOV MOV JSR MOV MOV MOV MOV MOV ADD BIT BEQ MOV CMP BEQ JMP MOV MOV 1,570,344 #DOAR,R 1 R 5,OUTPUT 2 (RO),DNOC #DAREA,RO R 5,DPMMEM FIRST,STATUS #1,BRSW R 3,R 4 RLN,R 4 -(R 4),RO #WOAR,R 1 R 5,OUTPUT #I,WOAR JOIN 3 #WAREA,RO R 5,DPMMEM #l,(R 1) R 5,MEMDPM R 4,R 3 + 2 LAST,STATUS #DAREA,RO #DOAR,Rl #2,(RI) R 5,MEMDPM #6,AI DOLN,DATAO PW,DATAO RLN,DATAO DPM+PIPGO,STATUS BDONE,STATUS -l #O,STATUS R 4,R 3 + 2 JOIN 2 #PNBOUT,R 4 @LPTR,R 2 MOV 6 (R 2),NOC DEC NOC CLR CLR CLR (PI 23)JOIN 5:
(PI 24) (PI 25) (PI 29) MOV MOV MOV MOV ADD TST BMI TST BMI CMP BLT A 2 AD M 3 AD B RCNT #30,STATUS M 3 AD,AI DATAI,OV DATAI,NH #2,M 3 AD OV JOIN 9 NH PF 2 NH,PCO JOIN 6 388 set up for OUTPUT function generate delimiter seed row O save # of l’s in row O prepare for transfer transfer the seed from memory area in DPM to DAREA set FIRST bit in STATUS register set BRIGHT process schedule flag R 4 pointer to top-of-stack R 4 points to the first entry to be processed RO is seed header pointer for current event area to receive output values generate seed’s row O is the seed in DPM memory area 1 yes no action needed set up work area for the transfer transfer from DPM to WAREA assure transfer to area 1 transfer from WAREA to DPM area 1 set up to move delimiter line O to DPM area II set up to write to IPRF write LN 1 write LN 2 write the pipe width write LNRQ call PIPING module test for completion loop until done clear STATUS register check for last or completion loop back R 4 points to output list pointer to seed header for proper delimiter NOC is no of l’s in delimiter row O adjust NOC to use as an implied event # pointer addr pointer AUXILIARY MEMORY II addr pointer MEMORY area 2 counter to keep track of number of events sent to BRIGHT prepare for read from MEMORY area 3 memory address to read from read two values from MEMORY area 3 OV center pipe, NH # of hits address memory address pointer is center pipe negative yes, ignore entry is number of hits negative negative exit, i e, exact hit compare with cutoff value less than ignore 389 (P 130) JOIN 6:
(PI 26) PF 2:
(P 128) (P 127) PF 3:
(P 131)JOIN 6:
JOIN 7:
JOIN 8:
JOIN 9:
(PI 32) (P 133)JOIN 10:
(P 134) (PI 33 1) (PI 33 2) (PI 35) 1,570,344 MOV 10 +PBM,STATUS MOV MOV INC INC JMP TST BEQ MOV MOV MOV INC INC JMP CLR MOV MOVF MOV INC CLR DEC BMI JMP TST BNE CLR CLR BR TST BEQ MOV MOV MOV MOV MOV MOV MOV RTS A 2 AD,AI OV,DATAO A 2 AD BRCNT JOIN 8 ESCAPE PF 3 +PBM,STATUS A 2 AD,AI OV,DATAO A 2 AD BRCNT JOIN 7 BRSW NOC,-(R 4) Fl,-(R 4) #1,B RCNT PNBCNT NOC NOC + 2 JOIN 5 B RCNT + 3 BRSW PNBCNT + 5 BRSW + 2 A 2 AD,AI -I,DATAO (SP)+,R 4 (SP)+,R 3 (SP)+,R 2 (SP)+,R 1 (SP)+,R O R 5 389 prepare to write to AUXILIARY MEMORY set up address register write out center pipe increment memory address pointer increment bright count decision exit is escape set false exit write out center pipe to AUXILIARY MEMORY up the bright count decision exit reset bright switch stack the event number stack BV = 100 %/o set hit count at I assure loop exit is request finished yes exit no loop back restore context return B-3 BRIGHTNESS PROGRAM BRIGHT (BR I)BRIGHT:
(BR 2) -This process performs the BRIGHTNESS function on the RLN events on the stack It then computes a brightness value (BV) If the ESCAPE is set all brightness values above a specified cutoff are ordered and returned to the requestor If ESCAPE is not set, the best value is saved in BVMAX and this is returned to the requestor.
MOV R 0,-(SP) MOV R 1,-(SP); save registers MOV R 2,-(SP) MOV R 3,-(SP) MOV R 4,-(SP) MOV R 3,R 4; R 4-top of ESTAK ADD RLN,R 4; R 4-first entry + 1 MOV FIRST,STATUS; initialize the FIRST flip flop MOV t D 9,AI; set up for IPRF transfer MOV RLN,DATAO; initialize LNRQ CLR PNBCNT; clear the output list 1,570,344 (B R 3)JOIN 1:
(BR 4) (BR 5) (BR 6)JOIN 2:
(BR 7) (BR 7 1) (BR 7 2) (BR 8) (BR 9) (B RI 12)BVADJ:
(BRI 13) (BR 14) (BR 15)JOIN 4:
(BR 16)JOIN 5:
(BR 17) (BR 18) BR 19)CMBV:
(BR 20) MOV MOV JSR CMP BEQ MOV JSR MOV JSR MOV MOV MOV JSR MOV MOV MOV CMP BNE ADD ADD BIT BEQ MOV CMP BEQ JMP MOV MOV MOV JSR MOV MOV MOV CLR MOV DEC JSR MOV MOV MOV MOV MOV MOV MOV ADD MOV JSR MOV SUB MOV DEC CMP DEC BEC BR LDCIF LDCIF.
LDCIF SUBF MULF LDCIF ADDF -(R 4),RO; Rb-current entry seed header #WOAR,RI; results go here R 5,OUTPUT; revolve back to row O #Il,WOAR result in DPM area I JOIN 2 yes no transfer necessary #WAREA,RO prepare for the transfer R 5,DPMMEM; transfer from DPM to WAREA #I,WOAR; assure a transfer to DPM area I R 5,MEMDPM transfer from WAREA to DPM area I #2,DOAR setupand #DOAR,R 1; move delimiter row O #DAREA,RI; expansion to DPM R 5,MEMDPM; memory area II #6,AI; set for move to IPRF DOLN,DATAO move in LN 2 R 3,R 4; is this the last event to be processed + 2;no LAST,STATUS; yes set LAST bit in the STATUS register DPM+BRGO,STATUS; startthe hardware BRIGHTNESS module BDONE,STATUS -1 I; loop until done #O,STATUS; clear STATUS R 4,R 3; check for completion + 2; not the last JOINI; loop back #I,DOAR; move the delimiter into #DOAR,RI; DPM memory area I so that #DAREA,RO; it can be decoded R 5,MEMDPM #6,AI; put in length value DOLN,DATAO; for DECODE I MODULE DIINIT,STATUS; initialize the hardware module AICNT; initialize address counter DNOC,NOC; initialize NOCthis counter NOC; will be used to compute current event g R 5,DCODEI; call DECODE I MODULE RO,TDI; save as previous value #30,STATUS; prepare to read DPM memory area IAICNT,AI; set up address pointer DATAI,DI; beginning delimiter DATAI,N; of hits DATAI,S; dmin DATAI,DO; Do #4,AICNT; adjust address counter TDI,TD 2 R 5,DCODE 1; read another delimiter value RO,TDI; save the value TDI,TD 2 TD 2,LS; LS 1 TD 2-TD l LS; save current value TDI,D 1: has proper place been reached CMBV; equal thus compute bright value NOC; not equalgo back JOIN 5 ACO,RLN; convert length to floating point AC 1,RLN; save length in ACI AC 2,N; convert # of hits to floating ACO,AC 2; ACO LN-N ACO,AC 1 AC O O-(LN-N)LN AC 2,DO; convert Do to floating point ACO,AC 2; AC O(LN-N)LN+Do 390 390 391 (BR 21) (BR 22) (B R 23) (BR 25) (BR 26) (B R 28) (B R 27)B FX 6:
(B R 24)B FX 7:
(B R 29)JOIN 6:
JOIN 7:
(BR 30) (BR 31) (BR 32)JOIN 8:
(BR 33) (BR 34) LDCIF SUB F DIVF TST BEQ LDCIF SUBF ABSF MOVF DIVF MOVF MULF MULF CMPF CFCC BLOS LDCIF DIVF BR LDF MULF MULF MULF LDCIF SUBF BR LDCIF MULF CMPF CFCC BLT JSR DEC BLT JMP MOV MOV ADD MOV MOV MOV RTS 1.570,344 AC 3,S AC 2,AC 3 AC 2,AC O LNGSW B FX 7 AC 0,LS AC 0,ACI AC O AC 0,AC 4 AC 0,AC 1 AC 0,AC 3 AC 0,AC 3 AC 0,AC 3 AC 4,AC I BFX 6 ACI,#1 AC 1,AC O JOIN 6 ACI,ALPHA AC 1,ALPHA ACI,ALPHA AC 0,AC 1 ACI,#1 ACI,AC O JOIN 6 ACI,#1 AC 1,AC 2 ACI,BVCO JOIN 8 R 5,INSERT BRCNT + 2 JOIN 4 (SP)+,R 4 (SP)+,R 3 RLN,R 3 (SP)+,R 2 (SP)+,Rl (SP)+,RO R 5 391 convert dmin to floating point AC 2 ±Do-dmin where dmin = S AC 2 I-(Do-dmin)/((LN-N)LN+Do) test length switch length not to be taken into account convert LS to floating point : AC O ILS-LN i AC 4 = A = LS-LN I AC 0,-A/LN AC 3 = A/LN AC Of-(A/LN)3 compare A:LN copy condition codes get a floating I ACI 1/(A/LN)3 get alpha value (a) AC 1 -a 3 AC 0-(aa/LN)3 get floated I ACII (a/LN)3 decision exit length is not to be considered ACI = BVL compare to cutoff value ; copy condition code do not insert insert the value request finished? no loop back restore R 4 restore stack pointer adjust to reflect current status return B-4 OUTPUT SUBROUTINE This routine causes row 0 of the seed specified in the input parameter to be generated.
R O points to seed header RI two word output block MOV R 0,-(SP) MOV RI,-(SP) MOV R 2,-(SP); save conte MOV R 3,-(SP) MOV R 4,-(SP) MOV 4 (R 0),R 2; get physic MOV #10,STATUS; prepare tc MOV #0,AI; initialize a MOV (R 0)+,R 3; pointer to MOV (R 3)+,DATAO; output am DEC R 2 BNE -2; loop until ext al length of seed write to DPM area I address register seed goes to R 3 iord finished OUTPUT ( 01)OUTPUT:
( 02) 1,570,344 MOV MOV MOV MOV MOV MOV MOV MOV MOV TST BEQ ADD ADD BIT BEQ CLR MOV MOV MOV MOV MOV MOV MOV MOV RTS #0,STATUS #0,AI HW,DATAO #10,DATAO #0,DATAO HW,DATAO (RO)+,DATAO (RO)+,DATAO #2 DELOP,STATUS DPM+OMGO,STATUS BDONE,STATUS -1 STATUS #6,AI DATAI,(R 1)+ DATAI,(RI)+ (SP)+,R 4 (SP)+,R 3 (SP)+,R 2 (SP)+,R 1 (SP)+,RO R 5 prepare IPRF TL-HW BL-O IR-O HW-HW LINE#±row # of seed LN 1 ±length of seed LN 24-WOLN do hardware OUTPUT function loop until function complete prepare for output values get OAR OLN restore context return B-5 MEMPDM (MAIN MEMORY TO MEMORY MOD) SUBROUTINE transfer from main memory to DPM (MEMORY MOD) parameters RO points to main memory save area Rl points to two word area i) DPM memory area to which transfer is to be made ii) length of the transfer in words (MD 1)MEMDPM:
(MD 2) (MD 3) (MD 4) (MD 5) (MD 6) (MD 7) MOV MOV MOV MOV MOV _MOV MOV MOV ROL ROL ROL MOV MOV MOV DEC BNE MOV MOV MOV MOV MOV RTS RO,-(SP) Rl,-(SP) R 2,-(SP) R 3,-(SP) R 4,-(SP) RO,R 2 (Rl)+,R 3 (R 1)+,R 4 R 3 R 3 R 3 R 3,STATUS #0,AI (R 2)+,DATAO R 4 -2 (SP)+,R 4 (SP)+,R 3 (SP)+,R 2 (SP)+,R 1 (SP)+,RO R 5 save context R 2 contains from area DPM memory area # of words to be transferred adjust R 3 for STATUS register prepared for transfer transfer a word loop until done restore context return ( 03) ( 03 1) ( 03 2) ( 04) ( 05) ( 06) 392 392 393 1,570,344 B-6 DPMMEM (MEM MOD TO MAIN MEMORY) SUBROUTINE : Transfer from DPM MEMORY MOD to main memory.
Parameters (DM I)DPMMEM:
(DM 2) (DM 3) (DM 4) (DM 5) (DM 6) (DM 7) 393 R O points to main memory save area R I points to two word area i) DPM memory area from which transfer is to be made ii) length of transfer in words MOV R 0,-(SP) MOV R 1,-(SP) MOV R 2,-(SP); save context MOV R 3,-(SP) MOV R 4,-(SP) MOV R 0,R 2; R 2 points to main memory area MOV (R 1)+,R 3; R 3 contains DPM memory area MOV (Rl)+,R 4; R 4 contains # of words to be transferred ROL R 3 ROL R 3; adjust R 3 for STATUS register ROL R 3 MOV R 3,STATUS; prepare for transfer MOV #0,AI MOV DATAI,(R 2)+; transfer a word DEC R 4; decrement count of words BNE -2; branch back until 0 MOV (SP)+,R 4 MOV (SP)+,R 3 MOV (SP)+,R 2; restore context MOV (SP)+,R 1 MOV (SP)+,R O RTS R 5 B-7 DECODE I SUBROUTINE (D I)DCODEI:
(D 2) (D 3)JOIN 1:
J Oi N 2:
MOV MOV MOV MOV MOV BIT BEQ CLR MOV MOV MOV MOV MOV MOV RTS Ri,-(SP) R 2,-(SP) R 3,-(SP) R 4,-(SP) DPM+D 1 GO,STATUS BDONE,STATUS -1 STATUS #10,AI DATAI,R O (SP)+,R 4 (SP),R 3 (SP)+,R 2 (SP)+,R 1 R 5 save context call the DECODE I module loop until finished read result into RO restore context B-8 INSERT SUBROUTINE (IN 1)INSERT:
(IN 2) MOV MOV MOV MOV MOV MOV MOV MOV R 0,-(SP) RI,-(SP) R 2,-(SP) R 3,-(SP) R 4,-(SP) PNBPTR,R 3 PNBCNT,R 4 NOC,R 2 save context R 3 points to PNBOUT list R 4 contains # of entries in list R 2 contains entry # 1,570,344 get the brightness value compare current value to list value copy condition codes less no exchange necessary save list event # insert current old list becomes current save list value insert current in list old list value becomes current are we finished yes loop back insert final entry reflect another entry restore context return B-9 FORMATER PROGRAM FORMAT:
(FI) (F 2) JOIN 10:
(F 3) (F 4) (F 5) (F 6) (F 7) JOIN 20:
(F 8) JOIN 30:
(F 9) MOV MOV MOV MOV MOV CLR JSR JSR CMP BEQ CMP BEQ JSR BR JSR TST BEQ MOV MOV MOV MOV MOV RTS R 0,-(SP) Ri,-(SP) R 2,-(SP) R 3,-(SP) R 4,-(SP) ENDFL R 5,PRINTR CRLFA R 5,GETC R 0,SDEL JOIN 20 R 0,WDEL JOIN 20 R 5,COMMAND JOIN 30 R 5,REQUEST ENDFL JOIN 10 (SP)+,R 4 (SP)+,R 3 (SP)+,R 2 (SP)+,Rl (SP)+,R O R 5 save context reset end flag output a carriage return line feed asterisk get a character and store in RC sentence delimiter? yes yes try for a command process a request done? no yes restore context COMMAND, GET INTEGER AND GET FLOATING POINT SUBROUTINE COMMAND:
(Cl) (C 2) (C 3) MOV MOV MOV MOV MOV CLR CMPB BNE JMP R 0,-(SP) RI,-(SP) R 2,-(SP) R 3,-(SP) R 4,-(SP) ERRSW R 0,E + 2 C 40 save context clear the error switch is the character an E no yes (IN 3)JOINI:
(IN 4) (IN 5) (IN 6)JOIN 2:
(IN 7) (IN 7 1) (IN 8) LDF CMPF CFCC BLOS MOV MOV MOV LDF MOVF LDF DEC BLT JMP MOV MOVF INC MOV MOV MOV MOV MOV RTS AC 0,2 (R 3) ACI,AC O JOIN 2 (R 3),R I R 2,(R 3)+ R 1,R 2 AC 2,AC O ACI (R 3)+ ACI,AC 2 R 4 + 2 JOIN R 2,(R 3)+ ACI,(R 3)+ PNBCNT (SP)+,R 4 (SP)+,R 3 (SP)+,R 2 (SP)+,R 1 (SP)+,R O R 5 394 394 1,570,344 (C 4) (C 5) (C 6) C 6:
(C 7) (C 8) (C 9) (C 10) (Cll) (C 12) (C 13) C 13:
(C 14) (C 15) (C 16) (C 17) C 17:
(C 18) (C 19) (C 20) C 20:
(C 21) (C 22) C 22:
(C 23) (C 24) (C 25) (C 26) C 26:
(C 27) (C 28) C 28:
(C 30) CJOIN 6:
(C 31) (C 32) C 32:
(C 33) (C 340) C 340:
(C 341) (C 342) (C 343) C 343:
(C 344) CMPB BEQ INC JMP JSR JSR CLR CLR CMPB BNE JSR INC MOV JMP CMPB BNE JSR INC MOV JMP CMPB BNE JSR MOV JMP CMPB BEQ INC JMP JSR CMPB BNE MOVB JSR MOV INC JMP CMPB BNE MOV BR INC TST BEQ JSR JSR JMP JSR TST BNE JSR CMPB BEQ CLR CMPB BGT CMPB BLT R 0,C C 6 ERRSW CJOIN 7 R 5,PRINTR CNGMSG R 5,GETC FLTSW BVFLG R 0,A C 13 R 5,PRINTR ALPHMSG FLTSW #ALPHA,RI CJOIN 6 R 0,B C 17 R 5,PRINTR BVCOMSG BVFLG #BVCO, R I CJOIN 6 R 0,L C 20 R 5,PRINTR LNGMSG #LNGSW,Rl CJOIN 6 R 0,P C 22 ERRSW CJOIN 6 R 5,GETC R 0,C C 26 O,R O R 5,PRNTC #FPCO, R I BVFLG CJOIN 6 R 0,W C 28 #PW,RI CJOIN 6 ERRSW ERRSW C 32 R 5,PRINTR CRLF R 5,PRINTR ERRSMG CJOIN 10 R 5,PRINTR TOMSG FLTSW C 380 R 5,GETC R 0, B LANK C 340 R 2 ZERO,R O C 35 NINE,R O C 35 character a “C” yes otherwise flag as error print out “HANGE” read another character clear the float switch and the BVFLG was the character an “A” no print out the string “LPHA” set the float switch set pointer to ALPHA is character a “B” no print out “VCO” set BVFLG set pointer to BVCO is character an “L” no print out the message “NGSW” set pointer to LNGSW character a “P” ; yes no set error read another character is character a “C” no move letter O to RO go print the character set pointer to PCO set for floating point is the character a “W” no set pointer to PW set error switch test the error switch not set output a carriage return line feed output an error message print out “TO” check for floating flag set get a character is it blank yes clear accumulator register make sure we have a number i e.
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