GB1570549A - Creation of Inventions and Patents with Artificial Intelligence

GB1570549A – Flipflop circuit
– Google Patents

GB1570549A – Flipflop circuit
– Google Patents
Flipflop circuit

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Publication number
GB1570549A

GB1570549A
GB49841/77A
GB4984177A
GB1570549A
GB 1570549 A
GB1570549 A
GB 1570549A
GB 49841/77 A
GB49841/77 A
GB 49841/77A
GB 4984177 A
GB4984177 A
GB 4984177A
GB 1570549 A
GB1570549 A
GB 1570549A
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United Kingdom
Prior art keywords
logic
flip
master
flop
function
Prior art date
1976-12-10
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

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Application number
GB49841/77A
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NCR Voyix Corp

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NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1976-12-10
Filing date
1977-11-30
Publication date
1980-07-02

1977-11-30
Application filed by NCR Corp
filed
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NCR Corp

1980-07-02
Publication of GB1570549A
publication
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patent/GB1570549A/en

Status
Expired
legal-status
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Classifications

H—ELECTRICITY

H03—ELECTRONIC CIRCUITRY

H03K—PULSE TECHNIQUE

H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits

H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses

H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback

H03K3/037—Bistable circuits

H03K3/0372—Bistable circuits of the master-slave type

H—ELECTRICITY

H03—ELECTRONIC CIRCUITRY

H03K—PULSE TECHNIQUE

H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits

H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses

H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback

H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback

H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator

H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable

Description

PATENT SPECIFICATION
Application No 49841/77 ( 22) Filed 30 Nov 1977 Convention Application No 749490 Filed 10 Dec 1976 in () 1 570 549 ( 19) ( 33) United States of America (US) ( 44) Complete Specification published 2 July 1980 ( 51) INT CL 3 H 03 K 19/00 ( 52) Index at acceptance H 3 T 2 B 2 2 B 3 2 F 1 4 E 1 N 4 R BRS ( 54) FLIP-FLOP CIRCUIT ( 71) We, NCR CORPORATION of Dayton in the State of Ohio, and Baltimore in the State of Maryland, United States of America, a corporation organized under the laws of the State of Maryland, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:-
This invention relates to flip-flop circuits.
According to the invention, there is provided a flip-flop circuit responsive to first and second data input signals, including master logic means adapted to receive said first and second data input signals and slave logic means adapted to receive an output signal of said master logic means and including flip-flop output signal means adapted to provide at least one flip-flop output signal to said master logic means, said master and slave logic means each being responsive to true and complement clock signals, wherein said master logic means includes first gating means having an output of said master logic means coupled thereto and wherein said slave logic means includes second gating means having an input coupled to said flip-flop output signal means, said first and second gating means not having said clock signals applied thereto and thereby controlling the provision of said flip-flop output signal by said flip-flop output means in the event of a lack of synchronism between said true and complement clock signals.
A flip-flop circuit according to the immediately preceding paragraph has the advantage of providing the capability of a construction having a restricted number of cascaded gating means, whereby high speed operation can be achieved.
One embodiment of the invention will now be described by way of example with reference to the accompanying drawings, in which:Fig I shows a schematic block diagram of a master/slave flip-flop circuit; and Figs 2 A to 2 F are waveforms useful in describing the operation of the flip-flop circuit shown in Fig 1.
Referring now to Fig 1, a flip-flop circuit includes a master portion 10 including four OR gates 12, 14, 16, 18 and a slave portion including three OR gates 22, 24, and 26, each of which provides complimentary outputs (OR/NOR).
The master portion 10 and the slave portion 20 are interconnected such that the Q output of the master portion provides an input to the slave portion 20; more specifically, at an input to gates 22 and 24 thereof, and the Q and Q O outputs (true and complementary outputs) of the slave portion 20 provide feedback latching input inputs to the master portion 10; more specifically, at an input to gate 16 in the first instance and gates 12 and 14 in the second.
The Q output of the master portion 10 provides an additional feedback latching input to the master portion, more specifically at an input to gates 14 and 18.
The Q output of the slave portion 20 provides an additional feedback latching input to the slave portion at an input to gates 24 and 26 thereof Gates 12 and 16 provide inputs for the data signals to be operated upon, viz, K and J respectively.
Master portion inputs for CL/CL clock signals are provided at gates 12 and 18; while slave portion inputs for these clock signals are provided at gates 22 and 26 Gate 14 additionally provides an input for the data signal K.
Each of the gates 12-18, 22-26 of the master portion 10 and the slave portion 20 is provided with a transistor (not shown) having an open collector The provision of the open collector permits logic association of the respective outputs of the gates 12, 14, 16 and 18 of the master portion 10 by direct electrical connection, which technique may be referred to as “collector dotting” since it is outputs taken from transistor collectors that are connected To be noted, with a focus on that referenced by reference ( 21) ( 31) ( 32) 2 1,570,549 2 numeral 30, is the combination of the diamond and ampersand intended to denote a “wire-AND” function achieved by connecting an open collector of a respective transistor of each of the gates 12, 14, 16 and 18 In a similar manner, the true outputs of the gates 22, 24 and 26 of the slave portion are AND’ed as shown at 32 to provide the true output, Q 0, of the flip-flop, while the complementary outputs are “wireOR’ed” as indicated by the diamond in combination with a “I” and referenced by the reference numeral 34.
Functionally, in the preferred embodiment, the master portion 10 is a JK flip-flop or latch, i e, one the clocking of which provides a 1 output when the J input is 1 and the K input is 0, a 0 when the J input is 0 and the K input is 1, and the opposite of its instant setting when both are 1, and, the slave portion 20 is a D latch, or, equivalently, one whose output is a function of the input that appeared one clock pulse earlier.
The maxterm logic equation i e.
equations wherein a logical function is expressed as a product of sums, are written with the maxterms in the order of reference numerals 12 to 18 corresponding to the OR gates of the master portion 10, and 22 to 26 corresponding to the OR gates of the slave portion 20.
( 2) Qt+ 1 =(QL+K+CL) (Qt+K+Qt)) ( +QC) (CL+Qt) (CL+Qt) ( 2) Q (,,,)=(CL+Q) (Qt+Q,) (j L_+Qot) Where:
Q,, and Q,,, are the Q and Q functions after clock transition and:
Qt and Q%, are the Q and Q functions before a clock transition.
It should be under stood that the flip-flop of Fig 1 is triggered on the falling edge of a clock pulse In order that the opposite be true it would be simply a matter of reversing the CL and CL inputs at each of the gate inputs shown, notably the inputs to gates 12, 18, 22 and 26.
By way of further clarification, all signals shown are readily available in a digital system of which the flip-flop of Fig 1 forms a part Thus, K, which is required in the instant implementation would be derived as a complementary output of another circuit in the system.
From an examination of expression ( 1), it is seen that there exists a maxterm for which there exists no requirement in order that the traditional functions associated with a J-K flip-flop be performed Such is the expression:
(Q 0,+K+Qt) which corresponds to the term of the Boolean expression contributed by gate 14.
Thus, gate 14 is a redundant gate, the purpose of which will be made apparent hereinafter in connection with a discussion of Figs 2 A to 2 F.
From an examination of expression ( 2), it is seen that there exists a maxterm for which there exists no requirement in order that the traditional function associated with a D latch be performed Such is the expression:
(Qt+Q) which corresponds to the term of the Boolean expression contributed by gate 24.
Thus, gate 24 is a redundant gate, the purpose of which will be made apparent hereinafter in connection with the discussion of Figs 2 A to 2 F.
There will be described the combination of a J-K function and a D function implemented by the master/slave technique which may be realized by interconnecting the outputs from logic elements such as gates 12, 16 and 18 such that an AND function is distributed over the maxterms represented thereby, similar activity as respects logic elements such as gates 22, 24, and 26, and the interconnection of a master portion 10 and a slave portion 20 It will be apparent to one skilled in the art that the instant discussion is included herein merely for purposes of providing a background for a discussion of the technical problems encountered in certain systems incorporating such master/slave flipflops, notably those wherein requirements for speed of propagation of data pulses may introduce timing hazards associated with system clock skew This clock skew is associated with transition of CL/CL pulses in at least those systems wherein timing of operation of logic elements may be in the 0.5 to 5 nanosecond range.
Briefly, clocked J-K master latch, i e, SET/RESET (S/R), HOLD (H), and TOGGLE (T) functions are realized by the AND of the maxterms previously associated with gates 12, 16 and 18 Gate 12 is the K input gate, gate 16 is the J input gate and gate 18 performs the saving function which may define a J-K flip-flop as a latch The latching function is referenced by the term “HOLD” (H).
Essentially, gate 18 saves the state of the master latch 10, i e, Q, in the absence of a 1,570,549 1,570,549 clock pulse, as will be apparent from inspection of the maxterm for such gate, i.e, (CL+Q).
Both gates 22 and 26 are necessary to effect the latch function in the slave portion The slave portion 20, standing alone, may be regarded as a D latch In this instance, the Q output of the master latch 10 provides at gate 22 the D or data input normally associated with such latches, while the state saving gate is, in this instance, gate 26.
The basic functions of the J-K flip-flop 10 will now be discussed with reference to the timing diagrams of Figs 2 A to 2 F Again, a brief exposition will be presented, and, merely for purposes of demonstration of the normal function thereof, in an operating environment wherein system clock skew is not present First, it should be noted that the term “J function” is synonymous with “SET function”, “K function” is synonymous with “RESET function” and that “J-K TOGGLE function”, as the term suggests, requires that certain specified input conditionsexist at both the J input to gate 16 and the K input to gate 12 Thus, one will perceive readily the correlation with clocked S-R (set-reset) latches In a modified embodiment, S-R latches are employed in the master portion 10 and the slave portion 20.
The term of expression ( 1) which effects the J function is (J+Q O t) That which effects the K function is (Q O t+K+CL) TOGGLE is accomplished when both J and K are logic I so that both maxterms are required in order that that function be performed (CL+Q,), as previously stated, serves as the latch for the J-K portion 10, so that, as shown in Figs.
2 A to 2 F, the inclusion of this maxterm is effective to hold the condition of the flipflop in either a 1 or 0 logic state All three maxterms are employed to effect the TOGGLE function as will become apparent hereinafter in connection with a more detailed discussion of Figs 2 A to 2 F.
In Figs 2 A to 2 F, it will be noted that the synchronized CL/CL pulses are numbered consecutively from left to right by the reference numerals 40, 42, 44 and 46 to designate the first, second, third and fourth CL and CL pulses Skewed clock (CL) conditions for the first and third CL pulses 40 and 44 respectively, are indicated by the reference numerals 48 and 50 At 52 there is demonstrated a consequence of the skewed clock pulse 50; while the consequence of skewed pulse 48 is somewhat difficult to demonstrate pictorially, there being a continued effect over a relatively long time period The conseqeunce will be described hereinafter.
There will first be described the creation of a SET output condition of the flip-flop of 65 Fig 1 As shown in the timing diagrams 2 C and 2 D, K is high at logic 1 before the arrival of CL pulse 40, and J, initially at logic 0, is brought high before the presence of the CL pulse Since J at logic level I and 70 K at logic level 1 (K= 0) are the conditions permitting a J-K flip-flop to assume the SET condition, this will occur during the presence of the CL pulse, more precisely one gate delay after the changing of CL to a 75 logic 1, as best appreciated with reference to Figs 2 A, 2 E and the reference scale whereat “one gate delay” is shown by reference 54 This may also be seen with reference to Boolean expression ( 1) In the 80 event that Q output of the J-K master portion 10 had previously been at the 1 level, it would have remained at that level upon inputting of a CL pulse.
Q for the master/slave flip-flop is 85 unaffected as seen with reference to the waveform of Fig 2 F Q, remains unaffected until CL drops again to the logic 0 level, or, more precisely, one gate delay after falling clock Thus, for the master/slave flip-flop 90 Fig 1, the characterization as a falling edge triggered flip-flop of one gate delay, is demonstrated for the SET condition In terms of reflection of Q input to the slave latch 20 to Q output thereof, Q input 95 becomes Q, one gate delay after a falling CLOCK transition As respects latching, it is seen with reference to the waveform of Fig 2 F, the Q will remain at the SET condition, i e, logic 1, until a second pair of 100 J and K input conditions exists and a second clocked output is called for thereby.
The creation of the RESET output condition R will now be demonstrated with reference to the waveforms of Fig 2 The J 105 input becomes a logic 0, and K becomes a logic 0 (K=l) The Q output of the J-K master latch goes to logic 0 coincident with J, i e, Q is independent of the clock CL for this condition Upon arrival of clock pulse 110 42, it is seen that Q is not reflected as Q, of the slave portion 20 A Q input of logic 0 maintains Q at its present output logic state until a negative going or falling CLOCK transition, which transition does occasion 115 a change in output logic state as demonstrated with reference to the waveforms of Figs 2 A and 2 F, notably the accomplishment of the RESET function R one gate delay after negative clock 120 transition shown at 42.
The HOLD function H will now be demonstrated with reference to the waveforms of Fig 2 With J input at the zero logic level, K at I (K= 0) and Q slave 125 input at the zero logic level, the arrival of the clock pulse 44, Q slave input remains at the zero logic level Thus, under these 1,570,549 conditions, there is no change in the output of the flip-flop Hence, the output is held at the Q existing prior to the arrival of the clock pulse 44.
the conditions for a TOGGLE function T are J at the logic level 1, K at logic level 0 (K= 1), and Q reflecting the output of the flip-flop from the previous conditions fed back to master latch input gates 12 and 14, which output is at the 0 logic level Upon arrival of clock pulse 46, the Q input goes high, to logic level 1 Now there exists a complete set of conditions for a change in logic level of Q, in this instance, from a logic 0 to a logic 1 This occurs one gate delay after the negative going transition of clock pulse 46 In order to appreciate the function of the mater/slave J-K flip-flop in toggling from logic I to logic 0, one need only invert the prior Q feedback signal In some applications it may be desirable to permanently set K to a logic 0 (K=l), J equal to a logic 1 and derive the opposite Q.
from the previously available upon the passage of each clock pulse.
There will now be described the function of the gates 14 and 24 of Fig 1, in relation to the alleviation of problems arising from hazard conditions associated with skew i e.
lack of synchronism between the clock signals CL and CL First consider the signal CL to be at the high or logic 1 level upon the transition of CL to the logic 1 level, a condition indicated by the reference numeral 48 For the sake of simplicity, the skew will be considered to be approximately equal to one gate delay 54 The skew 48 is illustrative of the case where difficulty would be caused in the sense of causing a change of the logic output, Q,, to a state distinct from that which normally would result, given the inputs previously discussed in connection with setup for the SET function of the flip-flop This is readily seen by noting that K would have made its transition from a logic 1 to a logic 0 state prior to the time interval during which the SET condition would occur, notably, one gate delay after a falling transition of the signal CL Thus, the SET condition, and subsequent conditions, would never be assumed.
With reference to the Boolean expression ( 1), it is seen that provision of the redundant gate 14 will permit the SET condition to occur This is readily appreciated when one considers that the maxterm is satisfied by Q at logic 1 (Q O = 0) or Q, at logic 1 One or the other will always be the case upon there having been a negative going clock transition This may be appreciated most readily by considering that at that time Qt output of the master portion 10, as determined by the definition of ‘J-K” flipflop appearing hereinabove, becomes Q for the slave portion 20 (or, equivalently, the master/slave flip-flop as a whole Thus the conditions imposed by the maxterm corresponding to gate 14 are satisfied by a logic statement as simple as: “A logic variable that must always be either 1 or 0, is either 1 or O ” (One gate delay after falling clock transition, they are the same logic variable) Thus, K at logic level 0 will not prevent the proper functioning of the flipflop of Fig 1, under the conditions depicted, by virtue of the provision of redundant gate 14.
There will now be demonstrated, with reference to Boolean expressions (I) and ( 2), a solution to a second timing hazard, notably, that demonstrated by a second clock signal skew indicated by the reference numeral 50 Shown at 52 is the consequence of the skewed pulse 50, in the absence of the redundant gate 14 In certain cases Q output of the master portion 10 having been forced high to logic 1, may occasion forcing Q of the slave portion 20 to a logic 1 The input conditions previously discussed in connection with a demonstration of circuit operation in the HOLD output condition are illustrative of one instance wherein this would occur The desired result was the retention of a previous latched output upon occurrence of a falling CLOCK transition.
As shown, at 52, and, again, with reference to Boolean expression ( 2), this condition cannot be maintained if the Q output of master portion 10 has risen to a logic level of 1 This may be appreciated by noting that the conditions imposed by the maxterm definitions for both gates 22 and 26 are satisfied simultaneously upon a skewed clock condition, or, equivalently, when CL and CL are at logic level 1 simultaneously.
The solution to this problem is seen by a consideration of the functions of both gates 14 and 24 As discussed previously, gate 14 functions to prevent the change in state of the master portion 10 to the outputting of a logic 1 shown at 52 responsive to the clock skew shown at 50 Given that Q output of the master portion 10 has remained at the 0 logic level, the conditions imposed by the maxterm corresponding to gate 24 are not met, viz, that one or the other of Q, or Q O t must be at logic level 1 Thus, the output of the flip-flop remains at logic level 0 or, equivalently, the integrity of the output for the HOLD function is ensured.
No change has been made to the waveform of Fig 2 F to emphasize that a single skewed clock pulse may give rise to propagation of error so that many erroneous outputs of the master/slave flip-flop of Fig 1 would obtain Once a single skew had occurred it could be the case that no 1,570,549 predictable result could be obtained at the output of the flip-flop of Fig 1 For example, one might consider the case where immediately after CLOCK skew, conditions were set up for the TOGGLE function to be performed indefinitely Incorrect Q, logic levels would be produced indefinitely More specifically, with reference to Fig 2, the consequence of clock pulse skew 50 is master latch output Q prematurely rising to the logic level I, as shown at 52, thereby immediately causing the TOGGLE, again, prematurely By logical extension of the previously discussed TOGGLE function, the output of the circuit would be incorrect indefinitely, or until a second clock skew occurs Thus, it is seen that the immediate error in failure to maintain the HOLD function, causing the waveform of Fig 2 F to go to high logic level before the arrival of clock pulse 46, would cause both a TOGGLE from logic level 1 to logic level 0, the opposite of that desired, and indefinite error for as long as the data inputs J and K were set for TOGGLE.
Various modifications are possible In these modifications the various inputs to the master section are combined by logic gates effecting a first type logical function, the outputs of these gates being combined by a second type logical function The same statement applies to the slave portion insofar as determining its true output Its complementary output derives from logic association opposite to that determining the true output For example, an alternative arrangement of logic elements useful in implementing a master/slave J-K flip-flop is one wherein AND gates are substituted for OR gates, “wire-AND’s” and “wire-OR’s” reversed, and the inputs arranged accordingly, viz J, CL, K and CL, from top to bottom in Fig 1 As will be apparent, negative logic (I=low level and O =high level) would be required for this implementation.
In each alternative embodiment, there are provided the redundant gates to ensure hazard-free flip-flop opreation The redundant gates, in each instance define maxterms imposing conditions which are satisfied irrespective of the simultaneous presence of a clock pulse and its compliment Equivalently, the redundant gates define maxterms in the Boolean equations for both the master portion and the slave portion having neither a CLOCK nor a CLOCK complement input defined.
Thus, integrity of the output is ensured upon a skew in a CLOCK pulse.
It should be understood that the described embodiment can conveniently be implemented in emitter coupled logic (ECL), and further that such an implementation can readily be incorporated in large scale integrated semiconductor devices.
(LSI)

Claims (8)

WHAT WE CLAIM IS:-

1 A flip-flop circuit responsive to first and second data input signals, including 70 master logic means adapted to receive said first and second data input signals and slave logic means adapted to receive an output signal of said master logic means and including flip-flop output signal means 75 adapted to provide at least one flip-flop output signal to said master logic means, said master and slave logic means each being responsive to true and complement clock signals, wherein said master logic 80 means includes first gating means having an output of said master logic means coupled thereto and wherein said slave logic means includes second gating means having an input coupled to said flip-flop output signal 85 means, said first and second gating means not having said clock signals applied thereto and thereby controlling the provision of said flip-flop output signal by said flip-flop output means in the event of a 90 lack of synchronism between said true and complement clock signals.

2 A flip-flop circuit according to Claim 1, wherein said flip-flop output signal means is adapted to provide true and complement 95 flip-flop output signals and wherein said master logic means includes a plurality of logic gates adapted to effect a first type logic function and having inputs adapted to receive said data input signals, said clock 100 signals, said true and compliment flip-flop output signals and a master output signal of said master logic means, said first gating means including an additional logic gate adapted to effect said first type logic 105 function, outputs of all of said logic gates being connected together to effect a second type logic function and thereby provide said master output signal.

3 A flip-flop circuit according to Claim 2, 110 wherein said additional logic gate is adapted to receive as input signals thereto one of said data input signals, said master output signal and said complement flip-flop output signal 115

4 A flip-flop circuit according to Claim 3, wherein said slave logic means includes a further plurality of logic gates adapted to effect said first type logic function and having inputs adapted to receive said master 120 output signals, at least one of said flip-flop output signals and said clock signals, said second gating means including a further logic gate adapted to effect said first type logic function, outputs of all the logic gates 125 in said slave logic means being connected together to effect said second type logic function and thereby provide said flip-flop output signals.

1,570,549 A flip-flop circuit according to Claim 4, wherein said further logic gate is adapted to receive as input signals thereto said master output signal and said true flip-flop output signal.

6 A flip-flop circuit according to any one of Claims 2 to 5, wherein said master logic means includes four logic gates adapted to effect said first type logic functions and wherein said slave logic means includes three logic gates adapted to effect said first type logic function.

7 A flip-flop circuit according to Claim 6, wherein said first type logic function is an OR function and said second type logic function is an AND function.

8 A flip-flop circuit substantially as hereinbefore described with reference to the accompanying drawings.
D MILLICHAP, Chartered Patent Agent, Agent for the Applicants.
Printed for Her Majesty’s Stationery Office, by the Courier Press, Leamington Spa, 1980 Published by The Patent Office, 25 Southampton Buildings, London, WC 2 A IAY, from which copies may be obtained.

GB49841/77A
1976-12-10
1977-11-30
Flipflop circuit

Expired

GB1570549A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

US05/749,490

US4072869A
(en)

1976-12-10
1976-12-10
Hazard-free clocked master/slave flip-flop

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1980-07-02

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GB49841/77A
Expired

GB1570549A
(en)

1976-12-10
1977-11-30
Flipflop circuit

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US4072869A
(en)

JP
(1)

JPS5372558A
(en)

DE
(1)

DE2755070C2
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FR
(1)

FR2393469A1
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International Business Machines Corporation
Single clocked latch circuit

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Device for monitoring the phase shift between two clock signals.

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1976

1976-12-10
US
US05/749,490
patent/US4072869A/en
not_active
Expired – Lifetime

1977

1977-11-30
GB
GB49841/77A
patent/GB1570549A/en
not_active
Expired

1977-12-01
JP
JP14334577A
patent/JPS5372558A/en
active
Pending

1977-12-09
FR
FR7737112A
patent/FR2393469A1/en
active
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1977-12-10
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DE2755070A
patent/DE2755070C2/en
not_active
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DE2755070A1
(en)

1978-06-15

US4072869A
(en)

1978-02-07

JPS5372558A
(en)

1978-06-28

DE2755070C2
(en)

1982-03-25

FR2393469B1
(en)

1982-10-22

FR2393469A1
(en)

1978-12-29

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