GB1574525A – Method of manufacturing semiconductor devices and semiconductor devices manufactured by the method
– Google Patents
GB1574525A – Method of manufacturing semiconductor devices and semiconductor devices manufactured by the method
– Google Patents
Method of manufacturing semiconductor devices and semiconductor devices manufactured by the method
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Publication number
GB1574525A
GB1574525A
GB15291/77A
GB1529177A
GB1574525A
GB 1574525 A
GB1574525 A
GB 1574525A
GB 15291/77 A
GB15291/77 A
GB 15291/77A
GB 1529177 A
GB1529177 A
GB 1529177A
GB 1574525 A
GB1574525 A
GB 1574525A
Authority
GB
United Kingdom
Prior art keywords
iii
compound
molecular beam
semiconductor device
elements
Prior art date
1977-04-13
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB15291/77A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1977-04-13
Filing date
1977-04-13
Publication date
1980-09-10
1977-04-13
Application filed by Philips Electronic and Associated Industries Ltd
filed
Critical
Philips Electronic and Associated Industries Ltd
1977-04-13
Priority to GB15291/77A
priority
Critical
patent/GB1574525A/en
1978-04-03
Priority to DE2814245A
priority
patent/DE2814245C2/en
1978-04-10
Priority to JP4136178A
priority
patent/JPS53128273A/en
1978-04-10
Priority to IT22167/78A
priority
patent/IT1096105B/en
1978-04-12
Priority to US05/895,705
priority
patent/US4218271A/en
1978-04-12
Priority to FR7810775A
priority
patent/FR2387514A1/en
1978-04-13
Priority to CA301,038A
priority
patent/CA1097431A/en
1980-09-10
Publication of GB1574525A
publication
Critical
patent/GB1574525A/en
Status
Expired
legal-status
Critical
Current
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Classifications
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
H01S5/00—Semiconductor lasers
H01S5/30—Structure or shape of the active region; Materials used for the active region
H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/02104—Forming layers
H01L21/02365—Forming inorganic semiconducting materials on a substrate
H01L21/02367—Substrates
H01L21/0237—Materials
H01L21/02387—Group 13/15 materials
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/02104—Forming layers
H01L21/02365—Forming inorganic semiconducting materials on a substrate
H01L21/02367—Substrates
H01L21/0237—Materials
H01L21/02387—Group 13/15 materials
H01L21/02395—Arsenides
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/02104—Forming layers
H01L21/02365—Forming inorganic semiconducting materials on a substrate
H01L21/02436—Intermediate layers between substrates and deposited layers
H01L21/02439—Materials
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/02104—Forming layers
H01L21/02365—Forming inorganic semiconducting materials on a substrate
H01L21/02436—Intermediate layers between substrates and deposited layers
H01L21/02439—Materials
H01L21/02491—Conductive materials
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/02104—Forming layers
H01L21/02365—Forming inorganic semiconducting materials on a substrate
H01L21/02518—Deposited layers
H01L21/02521—Materials
H01L21/02538—Group 13/15 materials
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/02104—Forming layers
H01L21/02365—Forming inorganic semiconducting materials on a substrate
H01L21/02518—Deposited layers
H01L21/02521—Materials
H01L21/02538—Group 13/15 materials
H01L21/02546—Arsenides
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/02104—Forming layers
H01L21/02365—Forming inorganic semiconducting materials on a substrate
H01L21/02518—Deposited layers
H01L21/0257—Doping during depositing
H01L21/02573—Conductivity type
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/02104—Forming layers
H01L21/02365—Forming inorganic semiconducting materials on a substrate
H01L21/02518—Deposited layers
H01L21/0257—Doping during depositing
H01L21/02573—Conductivity type
H01L21/02576—N-type
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 – H01L21/268
H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L29/107—Substrate region of field-effect devices
H01L29/1075—Substrate region of field-effect devices of field-effect transistors
Description
PATENT SPECIFICATION
( 11) 1 574 525 ( 21) Application No 15291/77 ( 22) Filed 13 April 1977 ( 19) ( 44) Complete Specification published 10 Sept 1980 ( 51) INT CL 3 H Ol L 21120 21/443 ( 52) Index at acceptance HIK 1 CB 1 EA 9 E 9 N 2 9 N 3 MW ( 72) Inventor COLIN EDWIN CONISBEEWOOD ( 54) METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES MANUFACTURED BY THE METHOD ( 71) We PHILIPS ELECTRONICS AND ASSOCIATED INDUSTRIES LIMITED of Abacus House, 33 Gutter Lane, London, EC 2 V 8 AH a British Company do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following
statement:
The invention relates to a method of manufacturing a semiconductor device which includes a III-V compound stratum and to a semiconductor device manufactured by such a method This method may be used for manufacturing devices, for example field effect transistors, microwave diodes or laser diodes, in which charge carriers flow in a thin (of the order of 1 micron thick) layer of a high conductivity.
This method may also be used to obtain improved ohmic contacts formed on grown III-V compound strata.
United Kingdom Patent Specification
1,270,550 describes a method of forming an epitaxial film of a III-V compound on a substrate surface at a subatmospheric pressure, the substrate surface being preheated to a temperature in the range from 450 to 650 ‘C, and a collimated molecular beam or beams comprising the constituent components of the film is or are directed at the preheated substrate surface for a sufficient period to form an epitaxial film of a desired thickness Such an epitaxial film may form part of a field effect transistor.
A field effect transistor comprises, for example a semi-insulating Ga As substrate bearing an epitaxially deposited doped Ga As film, together with source gate and drain electrodes extending from the film.
It was found when using a Schottky diode gate that the current falls off linearly as the voltage applied between the gate and source electrodes was increased When such a device was operated at 10 G Hz, it was found that the gain associated with the minimum noise of the device was significantly less than the maximum available gain of the device.
One advantage of the invention is that it 50 makes it possible to manufacture a field effect transistor in which the gain associated with the minimum noise is not significantly less than the maximum available gain Another advantage of the invention is that it Ss makes it possible to make semiconductor devices in which the ohmic contacts have lower contact resistances than in similar known devices.
The invention provides a method of 60 manufacturing a semiconductor device including a III-V compound stratum, the method comprising the step of depositing a layer consisting of one of the elements Sn, Ge, Si, Be, Mn or Mg by a molecular 65 beam process on an exposed surface of the III-V compound stratum.
According to one aspect of the invention, the method includes the steps of depositing a coating of from 10 ‘s to 101 ‘ atoms/sq cm 70 of one of the elements Sn, Ge, Si, Be, Mn or Mg by a molecular beam process on an exposed surface of a semi-insulating III-V compound substrate, and depositing a 0 05 to 1 5 um thick film of a doped III-V com 75 pound on the coating by a molecular beam process, wherein the dopant in the doped III-V compound is the element constituting the coating, and the doped III-V compound contains from 1 x 1016 to 3 X 10 ‘7 atoms/ 80 cm 3 of dopant The semiconductor device manufactured by this method, may be, for example a field effect transistor or a laser diode.
According to another aspect of the in 85 vention, the method includes the steps of depositing a contacting film of from 1014 to 1011 atoms/sq cm of one of the elements Sn, Ge, Si, Be, Mn or Mg by a molecular beam process on an exposed surface of an 90 V) tn 1574525 epitaxially grown 111-V compound stratum, and depositing a contact layer consisting of Sn, Be, Mg, Mn or an alloy of Pt, Ag or Au with any of the elements Sn, Ge, Si, Be, Mg or Mn on to the contacting film.
The contact layer together with the subjacent contacting film constitute an ohmic contact to the 111-V compound stratum.
During the investigations which led to the invention, it was found that the limitation on the performance of a gallium arsenide F E T occurs when all the current is passing through a very thin part of the layer adjoining the substrate, which part of the layer is the first grown part, since the electrical resistance in this first grown part of the layer is significantly higher than the resistance in the remainder of the layer.
The increase in resistance may be due to a reduction in carrier density or to a reduction in carrier mobility in the layer of doped gallium arsenide.
Experiments were conducted to determine the carrier loss from 0 3 1 m thick gallium arsenide layers doped with 1 x 1017 tin atoms/cm 2 and deposited by molecular beam epitaxy on semi-insulating gallium arsenide substrates There was found to be a loss from the layers of from 2 to 4 X 1012 donors/cm 2 A film consisting of 3 X 1012 atoms of tin 1 cm 2 was deposited on a semi-insulating gallium arsenide substrate, and a 0 31 xm thick layer of gallium arsenide doped with 1017 atoms of tin/cm 2 was deposited over the film It was found that the carrier density in the layer was now uniform throughout the thickness of the layer.
It was found that with gallium arsenide F E T ‘s manufactured using a method according to the invention that although there was no improvement in the minimum noise of an F E T compared with an F E T in which there was no deposit of dopant between the semi-insulating gallium arsenide substrate and the grown layer, in fact the noise in the former F E T was up to 10 % more than the noise of the latter F E T, the gain associated with minimum noise for a gallium arsenide F E T made by a method according to the invention was approximately 50 % larger than the gain associated with minimum noise in a similar gallium arsenide F E T which had no dopant deposit interlayer.
It was also found that the method according to the invention could be used for improving the quality of ohmic contacts formed on grown III-V compound strata.
An embodiment of the invention will now be described with reference to the following Example, and to the accompanying schematic drawing in which:Figure 1 is a side-elevation of molecular beam epitaxy system used to perform the method according to the invention, and Figures 2 to 6 are sectional elevations of a semiconductor assembly at successive stages of formation of the assembly.
EXAMPLE 70
Figure 1 shows a semi-insulating Ga As substrate 1 doped with 1 p p m of chromium and which is mounted on the radiationtype heater 2 in a vacuum chamber 3 The substrate 1 was heated at 580 ‘C for 10 75 minutes in the vacuum chamber at a pressure of 10-6 torr in an atmosphere consisting mainly of water vapour in order to remove carbon present on the surface of the substrate 80 Tin was produced in atomic beam form from a Knudsen effusion cell 4 at 8000 C and was allowed to impinge for 5 minutes upon the substrate 1 which was maintained at a temperature of 5500 C, the pressure in 85 the vacuum chamber being 10-6 Torr A tin coating 5 (Figure 2) which consisted of x 1011 atoms of tin per sq cm was produced on the substrate 1 by this treatment.
The temperature of the substrate was 90 maintained at 5500 C during the deposition of a tin-doped gallium arsenide layer 6 (Figure 3) was deposited over the tin coating 5 An arsenic (As) flux was generated in a Knudsen effusion cell 7 which was 95 heated at 300 C, a tin flux was generated by maintaining the Knudsen cell 4 at 760 C and a gallium flux was generated by means of a Knudsen effusion cell 8 heated at 11200 C The growth rate of the tin-doped gal 100 lium arsenide produced is set by the Ga flux as an excess of As 4 flux is used, the excess As 4 being reflected from the deposition surface, while all the tin and gallium incident on the deposition surface stick A 105 0.3 um thick layer of gallium arsenide having a donor concentration of 5 x 1016/cm 1 was grown in 18 minutes This assembly was used to make field effect transistor chips, a source contact, a drain contact and 110 a gate contact being formed by techniques which are conventional in the art These chips were operated at 10 G Hz and were found to have a maximum available gain of 9 2 d B, a minimum noise of 4 7 d B, and 115 a gain associated with the minimum noise of 9 d B A similar set of field effect transistor chips made from a gallium arsenide assembly which was identical with that used to make the first-mentioned field effect 120 transistor chips except that the assembly contained no tin coating 5, had a maximum available gain of 8 5 d B, a minimum noise of 4 4 d B, and a gain associated with the minimum noise of 6 d B 125 An ohmic contact layer was formed over the gallium arsenide assembly shown in Figure 3 using the apparatus shown in Figure 1 When deposition of the gallium arsenide layer 6 had been completed, the 130 1 574 525 shutters of the Knudsen cells 7 and 8 were closed, the temperature of kthe Knudsen cell 4 was then raised to 11000 C and the temperature of the assembly on the support 2 was reduced to 180 WC which is below the melting and alloying temperature of tin Tin deposition is continued for 10 minutes giving a 200 A thick contacting film 9 (Figure 4) An ohmic contact layer 10 was formed by evaporation over the tin contacting film 9 (Figure 5) Ohmic contacts at the required areas were defined by etching away the contact layer 10 and contacting film 9 at the areas where ohmic contacts were not required.
Claims (1)
WHAT WE CLAIM IS: –
1 A method of manufacturing a semiconductor device including a III-V compound stratum, the method comprising the step of depositing a layer consisting of one of the elements Sn, Ge, Si, Be, Mn or Mg by a molecular beam process on an exposed surface of the III-V compound stratum.
2 A method as claimed in Claim 1, wherein a coating of from 1011 to 1011 atoms/sq cm of one of the elements Sn, Ge, Si, Be, Mn or Mg is deposited on an exposed surface of a semi-insulating III-V compound substrate by a molecular beam process and a 0 05 to 1 5 um thick layer of a doped III-V compound is deposited by a molecular beam process on the coating, wherein the dopant in the doped III-V compound is the element constituting the 35 coating, and the doped III-V compound contains from 1 X 1016 to 3 X 1017 atoms/ cm 3 of dopant.
3 A method as claimed in Claim 2, in which the semiconductor device is a field 40 effect transistor.
4 A method as claimed in Claim 2, in which the semiconductor device is a laser diode.
A method as claimed in any of Claims 45 1 to 3, wherein a contacting film of from 1011 to 1011 atoms/sq cm of one of the elements Sn, Ge, Si, Be, Mn or Mg is deposited by a molecular beam process on an exposed surface of an epitaxially grown 50 III-V compound stratum, and depositing a contact consisting of Sn, Be, Mg, Mn or an alloy of Pt, Ag or Au with any of the elements Sn, Ge, Si, Be, Mg and Mn on to the contacting film 55 6 A method as claimed in Claim 1, substantially as herein described with reference to the Example and to the accompanying drawing.
7 A semiconductor device manufactured 60 by the method as claimed in any preceding Claim.
R J BOXALL, Chartered Patent Agent, Century House, Shaftsbury Avenue, London, WC 2 H 8 AS.
Agent for the Applicants.
Printed for Her Majesty’s Stationery Office by The Tweeddale Press Ltd, Berwick-upon-Tweed, 1980.
Published at the Patent Office, 25 Southampton Buildings, London, WC 2 A l AY, from which copies may be obtained
GB15291/77A
1977-04-13
1977-04-13
Method of manufacturing semiconductor devices and semiconductor devices manufactured by the method
Expired
GB1574525A
(en)
Priority Applications (7)
Application Number
Priority Date
Filing Date
Title
GB15291/77A
GB1574525A
(en)
1977-04-13
1977-04-13
Method of manufacturing semiconductor devices and semiconductor devices manufactured by the method
DE2814245A
DE2814245C2
(en)
1977-04-13
1978-04-03
Method for producing a semiconductor body for a field effect transistor
JP4136178A
JPS53128273A
(en)
1977-04-13
1978-04-10
Method of producing semiconductor
IT22167/78A
IT1096105B
(en)
1977-04-13
1978-04-10
METHOD OF MANUFACTURE OF SEMICONDUCTIVE DEVICES AND SEMICONDUCTIVE DEVICES PRODUCED WITH SUCH METHOD
US05/895,705
US4218271A
(en)
1977-04-13
1978-04-12
Method of manufacturing semiconductor devices utilizing a sure-step molecular beam deposition
FR7810775A
FR2387514A1
(en)
1977-04-13
1978-04-12
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING PROCESS
CA301,038A
CA1097431A
(en)
1977-04-13
1978-04-13
Molecular beam deposition process
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
GB15291/77A
GB1574525A
(en)
1977-04-13
1977-04-13
Method of manufacturing semiconductor devices and semiconductor devices manufactured by the method
Publications (1)
Publication Number
Publication Date
GB1574525A
true
GB1574525A
(en)
1980-09-10
Family
ID=10056459
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB15291/77A
Expired
GB1574525A
(en)
1977-04-13
1977-04-13
Method of manufacturing semiconductor devices and semiconductor devices manufactured by the method
Country Status (7)
Country
Link
US
(1)
US4218271A
(en)
JP
(1)
JPS53128273A
(en)
CA
(1)
CA1097431A
(en)
DE
(1)
DE2814245C2
(en)
FR
(1)
FR2387514A1
(en)
GB
(1)
GB1574525A
(en)
IT
(1)
IT1096105B
(en)
Families Citing this family (14)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US4366186A
(en)
*
1979-09-27
1982-12-28
Bell Telephone Laboratories, Incorporated
Ohmic contact to p-type InP
JPS5667974A
(en)
*
1979-10-26
1981-06-08
Ibm
Method of manufacturing semiconductor device
EP0031180A3
(en)
*
1979-12-19
1983-07-20
Philips Electronics Uk Limited
Method of growing a doped iii-v alloy layer by molecular beam epitaxy and a semiconductor device comprising a semiconductor substrate bearing an epitaxial layer of a doped iii-v alloy grown by such a method
US4398963A
(en)
*
1980-11-19
1983-08-16
The United States Of America As Represented By The Secretary Of The Navy
Method for making non-alloyed heterojunction ohmic contacts
US4447276A
(en)
*
1981-06-15
1984-05-08
The Post Office
Molecular beam epitaxy electrolytic dopant source
US4385946A
(en)
*
1981-06-19
1983-05-31
Bell Telephone Laboratories, Incorporated
Rapid alteration of ion implant dopant species to create regions of opposite conductivity
JPS58188128A
(en)
*
1982-04-27
1983-11-02
Fujitsu Ltd
Method for growth of molecular beam crystallization
DE3318683C1
(en)
*
1983-05-21
1984-12-13
Telefunken electronic GmbH, 7100 Heilbronn
Alloyed contact for n-conducting GaAlAs semiconductor material
US4634474A
(en)
*
1984-10-09
1987-01-06
At&T Bell Laboratories
Coating of III-V and II-VI compound semiconductors
JPH0666454B2
(en)
*
1985-04-23
1994-08-24
インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション
Group III-V semiconductor devices
JP2659714B2
(en)
*
1987-07-21
1997-09-30
株式会社日立製作所
Semiconductor integrated circuit device
US4952527A
(en)
*
1988-02-19
1990-08-28
Massachusetts Institute Of Technology
Method of making buffer layers for III-V devices using solid phase epitaxy
US5164040A
(en)
*
1989-08-21
1992-11-17
Martin Marietta Energy Systems, Inc.
Method and apparatus for rapidly growing films on substrates using pulsed supersonic jets
JPH10341039A
(en)
*
1997-04-10
1998-12-22
Toshiba Corp
Semiconductor light emitting element and fabrication thereof
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Assignee
Title
US3386867A
(en)
*
1965-09-22
1968-06-04
Ibm
Method for providing electrical contacts to a wafer of gaas
US3615931A
(en)
*
1968-12-27
1971-10-26
Bell Telephone Labor Inc
Technique for growth of epitaxial compound semiconductor films
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Motorola Inc
Aluminum-zinc metallization
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Germanium doped epitaxial films by the molecular beam method
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Bell Telephone Labor Inc
Molecular beam epitaxy method for fabricating magnesium doped thin films of group iii(a)-v(a) compounds
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(en)
*
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1977-07-29
Radiotechnique Compelec
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1973-06-25
1975-10-28
Bell Telephone Labor Inc
MBE technique for fabricating semiconductor devices having low series resistance
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*
1975-03-28
1976-03-02
Bell Telephone Laboratories, Incorporated
Sn-Doped group III(a)-v(a) Ga-containing layers grown by molecular beam epitaxy
1977
1977-04-13
GB
GB15291/77A
patent/GB1574525A/en
not_active
Expired
1978
1978-04-03
DE
DE2814245A
patent/DE2814245C2/en
not_active
Expired
1978-04-10
IT
IT22167/78A
patent/IT1096105B/en
active
1978-04-10
JP
JP4136178A
patent/JPS53128273A/en
active
Granted
1978-04-12
US
US05/895,705
patent/US4218271A/en
not_active
Expired – Lifetime
1978-04-12
FR
FR7810775A
patent/FR2387514A1/en
active
Granted
1978-04-13
CA
CA301,038A
patent/CA1097431A/en
not_active
Expired
Also Published As
Publication number
Publication date
IT1096105B
(en)
1985-08-17
JPS53128273A
(en)
1978-11-09
JPS5628373B2
(en)
1981-07-01
DE2814245A1
(en)
1978-10-26
DE2814245C2
(en)
1985-01-17
CA1097431A
(en)
1981-03-10
FR2387514B1
(en)
1982-09-17
US4218271A
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1980-08-19
IT7822167D0
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1978-04-10
FR2387514A1
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1978-11-10
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1980-11-26
PS
Patent sealed [section 19, patents act 1949]
1985-12-18
PCNP
Patent ceased through non-payment of renewal fee
