GB1576276A – Data processing system comprising a plurality of processor
– Google Patents
GB1576276A – Data processing system comprising a plurality of processor
– Google Patents
Data processing system comprising a plurality of processor
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Publication number
GB1576276A
GB1576276A
GB665177A
GB665177A
GB1576276A
GB 1576276 A
GB1576276 A
GB 1576276A
GB 665177 A
GB665177 A
GB 665177A
GB 665177 A
GB665177 A
GB 665177A
GB 1576276 A
GB1576276 A
GB 1576276A
Authority
GB
United Kingdom
Prior art keywords
processor
command
instruction
processors
cpu2
Prior art date
1976-02-25
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB665177A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1976-02-25
Filing date
1977-02-17
Publication date
1980-10-08
1977-02-17
Application filed by Siemens AG
filed
Critical
Siemens AG
1980-10-08
Publication of GB1576276A
publication
Critical
patent/GB1576276A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
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Classifications
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F9/00—Arrangements for program control, e.g. control units
G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
Abstract
So that the difference between the processors (CPU1 and CPU2) actually existing can no longer be detected at the programming level of the machine language, a processor which cannot execute a command of its command sequence due to its lack of a function unit directly calls on a second processor which executes the command and reports the results back to the first processor, whereupon both processors continue processing their own command sequences.
Description
(54) IMPROVEMENTS IN OR RELATING TO
A DATA PROCESSING SYSTEM COMPRISING
A PLURALITY OF PROCESSORS
(71) We, SIEMENS AKTIENGESELL- SCHAFT, a German Company, of Berlin and Munich, Federal Republic of
Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed to be particularly described in and by the following state ment-: This invention relates to a data processing system comprising a plurality of processors which differ from one another in respect of the availability of hardware devices for particular functions, and in which when a processor encounters a command requiring facilities the processor does not possess, the command can be transferred to another processor for execution.
Arrangements which operate in this way are known for example from U.K. Patents
No. 1,327,779, 1,150,110 and 1,183,158.
These known arrangements however need the assistance of a superordinate operating programme or a superordinate control system in order to delegate commands not executable by one processor to another processor which is capable of executing them. In the case of the assistance of a superordinate operating programme one has the disadvantage that the inequality of the individual processors must be taken into account at the machine-language programming level. This means, for different system configurations, an adaptation of the operating system to the processors being used. On the other hand, superordinate control systems, which operate with or without the assistance of the operating programme, require an additional outlay.
A frequently occurring example of processors having different function units are those with integrated input-output control units. Whereas independent input-output control units can generally be reached direct from any processor, an integrated input-output control unit can only be approached via the processor which it is assigned.
According to the presnet invention there is provided a data processing system including a pair of processors which differ from one another in respect of the availability of hardware devices for particular functions, wherein the sytem is arranged, in operation, so that when a processor of the pair recognises a command requiring such a device not available therein but available in the other processor of the pair, it passes to said other processor an instruction and all the necessary parameters for execution of the required function, and said other processor interrupts the processing of its own programme at the next interrupt point, executes the instruction in accordance with the command parameters and returns the results to the first processor, communication of said instruction, parameters and results taking place directly without the participation of any superordinate control system, whereby the differences between the processors of the pair is not apparent at machine language level even in the execution of commands requiring such hardware devices.
In a preferred embodiment the system is arranged in operation so that in the event of an overlapping occurrence in both processors of a command requiring the facilities of the other processor the command counter of one processor is retarded so as to abandon execution of the command occurring therein, and said one processor executes the command transmitted by the other processor and repeats the transmission of said abandoned command to the other processor.
The invention will be further understood from the following description by way of example of an embodiment thereof, in which the processors have integrated inputoutput control units, with reference to the accompanying drawing, in which: Figure 1 schematically illustrates a simplified block diagram of a multiprocessor system; and
Figures 2, 3a, and 3b are time diagrams of command sequences.
Figure 1 illustrates a multi-processor system having two processors CPU1 and
CPU2, each of which is permanently assigned a respective one of input-output control units IOC1 and IOC2. It is assumed that each input-output control unit is integrated into the processor which it is assigned, this being illustrated in
Figure 1 by a broken boundary line between each processor and its assigned input-output control unit. Each inputoutput control unit is assumed to be able to supply four input-output channels I01 to I04 and 105 to I08. The processors
CPU1 and CPU2 have common access to a working or main store MM, and exchange information with one another via a multiple link IF.
If for example in a command sequence being processed by the processor CPU1 there occurs a command which the processor CPU1 interprets as being able to be handled only via for example the inputoutput channel I08, then the processor
CPUI emits to the processor CPU2 an instruction (request signal) together with all the command parameters which the latter requires to execute the command. The processor CPU2 generally receives this instruction at the next interruptable point of its own command sequence, executes the command with the parameters which it has been given until the desired results are achieved, and reports these results to the processor CPU1. It does not use the results itself, and in particular does not store them. The processor CPU1, which has been in a waiting state from the emission of the instruction until the report-back of the results, employs the fed-back results as if they were its own results, stores them for example, and completes the execution of the command.
The described sequences are schematically illustrated in Figure 2, in which vertical lines under headings CPU1 and
CPU2 represent commands or programme components in machine language which are executed by the processors. The interruptable points in the command sequences are marked by short transverse lines. It has been assumed that after a time T1, the processor CPU1 recognises that the complete execution of a command Bln requires a particular function unit which is integrated in the processor CPU2. Therefore the processor CPU1 transmits an instruction to the other processor CPU2 which, following the next interruptable point in its command sequence, is received and executed by the latter. The processor CPU2 supplies the results of the command execution to the processor CPU1 which then completes the command execution. Both processors can then continue with the processing of their own command sequences.
If, as is assumed here, two processors each possess a particular function unit, the situation can occur that each processor approaches the other processor with an instruction within the length of time required for the execution of corresponding commands. If no special provisions were made, in this situation both processors would wait for their instructions to be processed by the other processor. This would then lead to a mutual blocking of the two processor.
Two such conflict situations are represented in Figures 3a and 3b. In accordance with Figure 3a, after a time T1 which the processor CPU1 requires to interpret a command, this processor recognises that it is necessary to use a particular function unit in the processor
CPU2 to execute the command. However, the relevant instruction to the processor
CPU2 does not arrive there until an analogous command is already in progress in this processor, which command itself requires a particular function unit in the processor CPU1. Therefore the processor
CPU2 directs an instruction to the processor CPUI after the expiration of its own interpretation time T2.
In order to avoid a mutual blocking of the processors in such a conflict situation the following measures are adopted: a) For example by appropriate microprogramming, it is ensured that during the periods of time Tl and T2 which the processors require for the interpretation of commands, no irreversible changes occur in data, i.e. no data are modified either in the store MM or in registers; and
b) One of the two processors, for example the processor CPU1, having emitted an instruction, waits for at least the period of time T2 which the other processor CPU2 requires to interpret a command. If during this period of time the one processor CPU1 receives no instruction from the other processor CPU2 or if it receives back the results of its own instruction, the one processor CPU1 realises that the other processor CPU2 has not submitted an instruction. However, if an instruction arrives from the other processor
CPU2 during the additional waiting time
T2 of the one processor CPU1, the one processor CPU1 decrements its command counter. The one processor CPU1 thus arrives at an interruptable point in its command sequence and can process the instruction from the other processor CPU2.
When this instruction has been executed, it again emits its own instruction to the other processor CPU2. Generally, having reached an interruptable point in its command sequence, this processor CPU2 is now in a position to execute this command. Otherwise the above-described process is repeated.
Another example of the occurrence of a conflict situation is shown in Figure 3b, in which shortly after an interruptable point in the command sequence of the processor
CPU1, the processor CPU2 recognises a command which triggers an instruction to the processor CPU1. The latter recognises the alien instruction immediately following the emission of its own instruction. Therefore it can, as before, immediately turn back its command counter, and thus return to the previous interruptable point in its command sequence without an additional waiting time.
It should be expressly mentioned that the turning back of the command counter is only allowed to occur in one processor in a conflict situation.
WHAT WE CLAIM IS:
1. A data processing system including a pair of processors which differ from one another in respect of the availability of hardware devices for particular functions, wherein the system is arranged, in operation, so that when a processor of the pair recognises a command requiring such a device not available therein but available in the other processor of the pair, it passes to said other processor an instruction and all the necessary parameters for execution of the required function, and said other processor interrupts the processing of its own programme at the next interrupt point, executes the instruction in accordance with the command parameters and returns the results to the first processor, communication of said instruction, parameters and results taking place directly without the participation of any superordinate operating programme or superordinate control system, whereby the differences between the processors of the pair is not apparent at machine language level even in the execution of commands requiring such hardware devices.
2. A data processing system according to claim 1, arranged in operation so that in the event of an overlapping occurrence in both processors of the pair of a command requiring the facilities of the other processor the command counter of one processor is retarded so as to abandon execution of the command occurring therein, and said one processor executes the command transmitted by the other processor and repeats the transmission of said abandoned command to the other processor.
3. A data processing system substantially as herein described with reference to the accompanying drawing.
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (3)
**WARNING** start of CLMS field may overlap end of DESC **. arrives at an interruptable point in its command sequence and can process the instruction from the other processor CPU2. When this instruction has been executed, it again emits its own instruction to the other processor CPU2. Generally, having reached an interruptable point in its command sequence, this processor CPU2 is now in a position to execute this command. Otherwise the above-described process is repeated. Another example of the occurrence of a conflict situation is shown in Figure 3b, in which shortly after an interruptable point in the command sequence of the processor CPU1, the processor CPU2 recognises a command which triggers an instruction to the processor CPU1. The latter recognises the alien instruction immediately following the emission of its own instruction. Therefore it can, as before, immediately turn back its command counter, and thus return to the previous interruptable point in its command sequence without an additional waiting time. It should be expressly mentioned that the turning back of the command counter is only allowed to occur in one processor in a conflict situation. WHAT WE CLAIM IS:
1. A data processing system including a pair of processors which differ from one another in respect of the availability of hardware devices for particular functions, wherein the system is arranged, in operation, so that when a processor of the pair recognises a command requiring such a device not available therein but available in the other processor of the pair, it passes to said other processor an instruction and all the necessary parameters for execution of the required function, and said other processor interrupts the processing of its own programme at the next interrupt point, executes the instruction in accordance with the command parameters and returns the results to the first processor, communication of said instruction, parameters and results taking place directly without the participation of any superordinate operating programme or superordinate control system, whereby the differences between the processors of the pair is not apparent at machine language level even in the execution of commands requiring such hardware devices.
2. A data processing system according to claim 1, arranged in operation so that in the event of an overlapping occurrence in both processors of the pair of a command requiring the facilities of the other processor the command counter of one processor is retarded so as to abandon execution of the command occurring therein, and said one processor executes the command transmitted by the other processor and repeats the transmission of said abandoned command to the other processor.
3. A data processing system substantially as herein described with reference to the accompanying drawing.
GB665177A
1976-02-25
1977-02-17
Data processing system comprising a plurality of processor
Expired
GB1576276A
(en)
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
DE19762607685
DE2607685C3
(en)
1976-02-25
1976-02-25
Method for operating processors in a multiprocessor system
Publications (1)
Publication Number
Publication Date
GB1576276A
true
GB1576276A
(en)
1980-10-08
Family
ID=5970849
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB665177A
Expired
GB1576276A
(en)
1976-02-25
1977-02-17
Data processing system comprising a plurality of processor
Country Status (8)
Country
Link
AT
(1)
AT353363B
(en)
BE
(1)
BE851840A
(en)
CH
(1)
CH610122A5
(en)
DE
(1)
DE2607685C3
(en)
FR
(1)
FR2342530A1
(en)
GB
(1)
GB1576276A
(en)
IT
(1)
IT1078233B
(en)
NL
(1)
NL7701537A
(en)
Cited By (3)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
EP0843254A2
(en)
*
1990-01-18
1998-05-20
National Semiconductor Corporation
Integrated digital signal processor/general purpose CPU with shared internal memory
WO2000026772A1
(en)
*
1998-10-30
2000-05-11
Telefonaktiebolaget Lm Ericsson
Processing arrangements
GB2391968A
(en)
*
2002-05-09
2004-02-18
Nec Corp
Running function expansion modules on parallel processors
Families Citing this family (1)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
DE3486464D1
(en)
*
1983-04-18
1998-02-19
Motorola Inc
Method and device for coordinating the execution of instructions by an additional data processing unit
Family Cites Families (2)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
BE625673A
(en)
*
1961-12-04
US3631405A
(en)
*
1969-11-12
1971-12-28
Honeywell Inc
Sharing of microprograms between processors
1976
1976-02-25
DE
DE19762607685
patent/DE2607685C3/en
not_active
Expired
1977
1977-01-13
CH
CH40477A
patent/CH610122A5/en
not_active
IP Right Cessation
1977-01-25
FR
FR7701981A
patent/FR2342530A1/en
active
Granted
1977-01-27
AT
AT50677A
patent/AT353363B/en
not_active
IP Right Cessation
1977-02-14
NL
NL7701537A
patent/NL7701537A/en
not_active
Application Discontinuation
1977-02-17
GB
GB665177A
patent/GB1576276A/en
not_active
Expired
1977-02-22
IT
IT2055377A
patent/IT1078233B/en
active
1977-02-25
BE
BE175270A
patent/BE851840A/en
not_active
IP Right Cessation
Cited By (8)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
EP0843254A2
(en)
*
1990-01-18
1998-05-20
National Semiconductor Corporation
Integrated digital signal processor/general purpose CPU with shared internal memory
EP0843254A3
(en)
*
1990-01-18
1999-08-18
National Semiconductor Corporation
Integrated digital signal processor/general purpose CPU with shared internal memory
WO2000026772A1
(en)
*
1998-10-30
2000-05-11
Telefonaktiebolaget Lm Ericsson
Processing arrangements
AU763319B2
(en)
*
1998-10-30
2003-07-17
Telefonaktiebolaget Lm Ericsson (Publ)
Processing arrangements
US7197627B1
(en)
1998-10-30
2007-03-27
Telefonaktoebolaget Lm Ericsson (Publ)
Multiple processor arrangement for conserving power
GB2391968A
(en)
*
2002-05-09
2004-02-18
Nec Corp
Running function expansion modules on parallel processors
GB2391968B
(en)
*
2002-05-09
2006-10-11
Nippon Electric Co
Application parallel processing system
US7464377B2
(en)
2002-05-09
2008-12-09
Nec Corporation
Application parallel processing system and application parallel processing method
Also Published As
Publication number
Publication date
FR2342530A1
(en)
1977-09-23
FR2342530B1
(en)
1983-09-30
DE2607685B2
(en)
1980-04-30
IT1078233B
(en)
1985-05-08
BE851840A
(en)
1977-08-25
CH610122A5
(en)
1979-03-30
DE2607685C3
(en)
1981-01-15
DE2607685A1
(en)
1977-09-01
AT353363B
(en)
1979-11-12
ATA50677A
(en)
1979-04-15
NL7701537A
(en)
1977-08-29
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Legal Events
Date
Code
Title
Description
1980-12-31
PS
Patent sealed
1988-10-12
PCNP
Patent ceased through non-payment of renewal fee
