GB1581597A – Computer system
– Google Patents
GB1581597A – Computer system
– Google Patents
Computer system
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Publication number
GB1581597A
GB1581597A
GB21737/77A
GB2173777A
GB1581597A
GB 1581597 A
GB1581597 A
GB 1581597A
GB 21737/77 A
GB21737/77 A
GB 21737/77A
GB 2173777 A
GB2173777 A
GB 2173777A
GB 1581597 A
GB1581597 A
GB 1581597A
Authority
GB
United Kingdom
Prior art keywords
processing unit
bus
unit
gate
control unit
Prior art date
1976-05-25
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB21737/77A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
Original Assignee
Honeywell Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1976-05-25
Filing date
1977-05-24
Publication date
1980-12-17
1977-05-24
Application filed by Honeywell Inc
filed
Critical
Honeywell Inc
1980-12-17
Publication of GB1581597A
publication
Critical
patent/GB1581597A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
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Classifications
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F1/00—Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
G06F1/10—Distribution of clock signals, e.g. skew
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F13/14—Handling requests for interconnection or transfer
G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F13/14—Handling requests for interconnection or transfer
G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
Description
PATENT SPECIFICATION ( 11)
1 581 597 ( 21) Application No 21737/77 ( 22) Filed 24 May 1977 ( 19) ( 31) Convention Application No 689 822 ’32) Filed 25 May 1976 in ( 33) United States of America (US) ( 44) Complete Specification published 17 Dec 1980 ( 51) INT CL ‘ G 06 F 9/00 ( 52) Index at acceptance G 4 A FT ( 72) Inventors ROBERT J HANDLY and ROBERT H DOUGLAS ( 54) COMPUTER SYSTEM ( 71) We, HONEYWELL INC, a Corporation organised and existing under the laws of the State of Delaware, United States of America, of Honeywell Inc, Honeywell Plaza, Minneapolis, Minnesota 55408, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: –
The present invention relates to a microprogrammed computer apparatus, and more particularly to a synchronizing scheme for such a computer.
In the field of the computer technology, there has evolved a system of hierarchical or distributed computer operation In such a system there is provided a main memory or storage unit or units and a plurality of processor units The processor units communicate with the storage units and possibly with other processor units by way of a communication Bus The processor units perform operations such as instruction decoding, computational activity, and interfacing with input/output instrumentalities.
It is essential, however, for such processors to effectively communicate by way of the Bus Heretofore, whenever such communication was necessary, the processor unit issued a request for access to be granted before any further action occurred.
Such waiting has proven to be time consuming to the extent of significantly slowing the overall processing of data.
It is accordingly, an object of the present invention to provide an improved processor unit for a computer system which alleviates the aforementioned shortcomings of the prior art.
Accordingly, the present invention provides a computer system comprising:
a processing unit; a storage unit; a communication Bus providing communication channels between said processing unit and said storage unit; and a Bus controller for controlling access to said Bus by said processing unit; and wherein:
the processing unit includes a plurality of functional components and a micropro 55 gram control unit; the microprogram control unit includes storage means for storing operational control instructions for the processing unit and means to issue the operational instructions 60 in a desired sequence, the plurality of functional components being controlled by the microprogram control unit; and the processing unit further includes clock means which clocks the operation of the 65 functional components and the microprogram control unit and has means responsive to the coincidence of a first control signal from the microprogram control unit and a second control signal from the Bus con 70 troller to interrupt the operation of the clock means.
A computer system embodying the invention will now be described, by way of example, with reference to the accompany 75 ing drawing, which is a block diagram of the system.
Before discussing the system in detail, it will be briefly summarized The system includes a processor unit which includes its 80 own microprogram control unit The microprogram control unit includes a storage means for operational instructions in a desired sequence The processor unit includes a number of clock controlled func 85 tional elements as well as means for requesting access to the Bus A clock signal generating means is controlled by signals from the microprogram control unit When a request has been made for access to the 90 Bus, the processor continues to operate until a point is reached when the access to the Bus must be accomplished before continuing The microprogram control unit issues a control signal which effectively 95 stops the operation of the clock signal generating means until the Bus access routine has been accomplished The generation of clock signals will resume when the access operation has been accomplished 100 t_00.
1,581,597 Referring to the drawing, a communication Bus 2 provides a communication channel between a Bus Controller 4, memory unit 1, and any of several Processing Units 6 which may be served by the Bus 2 The Processing Unit 6 shown is an instruction execution unit which includes an Arithmetic and Logic Unit (ALU) 8 and a Microprogram Unit (MPU) 10 which is a firmware control center for the Processing Unit 6 The MPU 10 includes a memory 11 in which is stored a set of microinstructions for controlling the operation of the Processing Unit 6, and an instruction register 13 for issuing the instructions to the components of the Processing Unit 6.
A plurality of functional units or operation registers, such as a Bus Address register 12, a Data Output register 14, a Data Input Register 16, and a Bus Operate register 18 are included in the Processing Unit 6 and are connected through suitable gating (not shown) to the Bus 2 and to the ALU 8 Each of the registers 12, 14, 16 and 18 operated under control of the instructions issued by the MPU 10 through suitable gating means For example, a “load address” instruction from the MPU is applied through an AND gate 20 to control the operation of the Bus Address register 12 A “load data out” instruction from the MPU 10 is applied through an AND gate 22 to control the operation of the Data Output register 14 Similarly, the Data Input register 16 is controlled by a “load-read” instruction from the MPU 10 applied through an AND gate 24 The Bus Operate register 18 is controlled by a “read-write” instruction from the MPU 10 applied thereto through an AND gate 26.
Each of the gates 20, 22, 24 and 26 is enabled by “clock” signals from a clock circuit 28 Thus the registers are loaded only on the transition of the clock signal.
The clock circuit 28 includes a controllable solid state oscillator comprising an AND gate 30, a feedback delay means 32, and a control NAND gate 34 The NAND gate 34 has one input terminal connected to the MPU 10 which issues a “Wait” signal when Bus synchronization is desired The other terminal of the NAND gate 34 is connected to an output from the Bus Controller 4.
It will be appreciated that the processing unit 6 can operate internally at a much higher speed than can the Bus/Memory.
As previously mentioned, in the prior art structures, the processing units were dependent from the Bus Controller and were accordingly, limited by the Bus Controller/ Memory when accessing them In the present structure, the local MPU 10 provides intelligent control of the Bus synchronization at the local level, allowing the Processing Unit 6 to operate at its own speed, asynchronously with respect to the Bus 2 until synchronization is required.
Since there must be reference to the Bus 2 for some functions, a part of the instruc 70 tion issued by the MPU 10 as, for example, by way of the Bus Operate register 18, includes a request for access to a memory unit 1 or other Processing Unit 6 by way of the Bus 2 As noted, in the previous 75 systems, when such a request for access to the Bus is made by the processing unit, all action at the procesing unit stops, awaiting such access and the completion of the access routine In the present system, with 80 the local control exercised by the MPU 10, the request for access to the Bus may be issued early in the procedure of a routine, while the Processing Unit 6 continues with all of the functions of which it is capable 85 Then, when the access to the Bus is essential to further processing, the activity in the Processing Unit is stopped until the access to the Bus has been accomplished.
To that end, the several functions of the 90 Processing Unit 6 are clocked by signals from the clock circuit 28 The clock circuit 28 comprises an interruptible, freerunning oscillator operating at a predetermined clock rate Included with the in 95 structions from the MPU is a “wait” signal bit which is applied to one of the input terminals of the control NAND gate 34, before the MPU 10 advances to the next instruction If a request for access to the 100 memory 1 has been issued but not yet serviced, the Bus Controller 4 will issue a “Bus busy” signal which is applied to the other input terminal of the NAND gate 34 The coincidence of the two signals at 105 the input of the NAND gate 34 causes the ouput thereof to go to a logical “low”, stopping the operation of the clock circuit 28 With the stopping of the operation of the clock circuit 28, no “clock” 110 signals are applied to the several operational elements of the Processing Unit 6.
Accordingly, the further operation of those clocked elements is stopped until the Bus access has been accomplished 115 If, in the course of performing the previous instruction from the MPU 10, a second request for access to the Storage Unit 1 through the Bus is required, that second request would, of course, be held up until 120 the completion of the first request With the clock stopped and the Processing Unit 6 in the WAIT mode, the completion of the first request restarts the clock 28 The restarting of the clock will, in turn, im 125 mediately effect the issuance of the second request Meanwhile, the Processing Unit 6 continues with its internal processing of data until it again comes to the point where no further processing can be 130 1,581,597 performed without the requested access.
Again, the clock is stopped, as before, until the access is completed.
On the other hand, if when the “wait” signal is issued by the MPU 10, either no access request has been made, or, if made, has already been completed, the “wait” signal will not stop the clock 28 and the processing in the Processing Unit 6 will continue uninterrupted to and into the next instruction from the MPU 10.
Claims (3)
WHAT WE CLAIM IS: –
1 A computer system comprising:
a processing unit; a storage unit; a communication Bus providing communication channels between said processing unit and said storage unit; and a Bus controller for controlling access to said Bus by said processing unit; and wherein:
the processing unit includes a plurality of functional components and a microprogram control unit includes storage means for storing operational control instructions for the processing unit and means to issue the operational instructions in a desired sequence, the plurality of functional components being controlled by the microprogram control unit; the processing unit further includes clock means which clocks the operation of the functional components and the microprogram control unit and has means responsive to the coincidence of a first control signal from the microprogram control unit and a second control signal from the Bus controller to interrupt the operation of the clock means.
2 A computer system according to Claim 1 wherein the clock means comprises a first gate having two input terminals and an output terminal, a signal delay connected between the output terminal and one of the input terminals, an enabling circuit comprising a second gate having an output terminal connected to the other input terminal of the first gate, the second gate having a first input terminal connected to receive said first control signal from the microprogram control unit and a second input terminal connected to receive said second control signal from the Bus controller.
3 A computer system substantially as herein described with reference to the accompanying drawings.
M G HARMAN, Chartered Patent Agent.
Printed for Her Majesty’s Stationery Office by Burgess & Son (Abingdon), Ltd -1980.
Published at The Patent Office, 25 Southampton Buildings, London, WC 2 A l AY from which copies may be obtained.
GB21737/77A
1976-05-25
1977-05-24
Computer system
Expired
GB1581597A
(en)
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
US05/689,822
US4084233A
(en)
1976-05-25
1976-05-25
Microcomputer apparatus
Publications (1)
Publication Number
Publication Date
GB1581597A
true
GB1581597A
(en)
1980-12-17
Family
ID=24770008
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB21737/77A
Expired
GB1581597A
(en)
1976-05-25
1977-05-24
Computer system
Country Status (6)
Country
Link
US
(1)
US4084233A
(en)
JP
(1)
JPS52144244A
(en)
CA
(1)
CA1130462A
(en)
DE
(1)
DE2722775A1
(en)
FR
(1)
FR2353100A1
(en)
GB
(1)
GB1581597A
(en)
Families Citing this family (15)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
JPS5427741A
(en)
*
1977-08-03
1979-03-02
Toshiba Corp
Information processing organization
US4231087A
(en)
*
1978-10-18
1980-10-28
Bell Telephone Laboratories, Incorporated
Microprocessor support system
FR2480969A1
(en)
*
1980-04-16
1981-10-23
Dshkhunian Valery
Microprocessor data exchange control – operates with bidirectional buses connected to multichannel counter by commutator switching
US4466079A
(en)
*
1981-02-17
1984-08-14
Pitney Bowes Inc.
Mailing system peripheral interface with communications formatting memory
US4434465A
(en)
1981-04-13
1984-02-28
Texas Instruments Incorporated
Shared microinstruction states in control ROM addressing for a microcoded single chip microcomputer
US4467412A
(en)
*
1981-05-18
1984-08-21
Atari, Inc.
Slave processor with clock controlled by internal ROM & master processor
DE3212401C2
(en)
*
1982-04-02
1985-01-17
Otto 7750 Konstanz Müller
Circuit arrangement for controlling the priority of the connection of various units to a system bus of a digital computer system
US4494193A
(en)
*
1982-09-30
1985-01-15
At&T Bell Laboratories
Deadlock detection and resolution scheme
US4660169A
(en)
*
1983-07-05
1987-04-21
International Business Machines Corporation
Access control to a shared resource in an asynchronous system
US4686620A
(en)
*
1984-07-26
1987-08-11
American Telephone And Telegraph Company, At&T Bell Laboratories
Database backup method
JPS61156338A
(en)
*
1984-12-27
1986-07-16
Toshiba Corp
Multiprocessor system
JPH0823859B2
(en)
*
1990-09-28
1996-03-06
インターナショナル・ビジネス・マシーンズ・コーポレイション
Data processing system
US5251305A
(en)
*
1991-04-04
1993-10-05
Unisys Corporation
Apparatus and method for preventing bus contention among a plurality of data sources
JPH0877035A
(en)
*
1994-09-06
1996-03-22
Toshiba Corp
Central processing unit and microcomputer
RU2143726C1
(en)
*
1997-07-15
1999-12-27
Козлов Михаил Кириллович
Formula processor with instruction-like logical control gates
Family Cites Families (10)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3404378A
(en)
*
1965-10-29
1968-10-01
Automatic Telephone & Elect
Computers
US3740722A
(en)
*
1970-07-02
1973-06-19
Modicon Corp
Digital computer
US3736567A
(en)
*
1971-09-08
1973-05-29
Bunker Ramo
Program sequence control
FR2185066A5
(en)
*
1972-05-15
1973-12-28
Philips Nv
IT964669B
(en)
*
1972-07-14
1974-01-31
Olivetti & Co Spa
ELECTRONIC TABLE CALCULATOR WITH MOS CIRCUIT LOGIC
GB1426749A
(en)
*
1973-06-05
1976-03-03
Burroughs Corp
Micro programme data processor having parallel instruction flow streams for plural level of subinstruction sets
FR2250448A5
(en)
*
1973-11-06
1975-05-30
Honeywell Bull Soc Ind
US3919695A
(en)
*
1973-12-26
1975-11-11
Ibm
Asynchronous clocking apparatus
CA1027249A
(en)
*
1973-12-26
1978-02-28
Richard A. Garlic
Microprocessor with parallel operation
US3914711A
(en)
*
1974-02-25
1975-10-21
Rca Corp
Gated oscillator having constant average d.c. output voltage during on and off times
1976
1976-05-25
US
US05/689,822
patent/US4084233A/en
not_active
Expired – Lifetime
1977
1977-02-08
CA
CA271,314A
patent/CA1130462A/en
not_active
Expired
1977-05-20
DE
DE19772722775
patent/DE2722775A1/en
active
Granted
1977-05-23
FR
FR7715783A
patent/FR2353100A1/en
active
Granted
1977-05-24
GB
GB21737/77A
patent/GB1581597A/en
not_active
Expired
1977-05-25
JP
JP5998777A
patent/JPS52144244A/en
active
Pending
Also Published As
Publication number
Publication date
DE2722775C2
(en)
1988-02-11
FR2353100B1
(en)
1984-10-26
JPS52144244A
(en)
1977-12-01
CA1130462A
(en)
1982-08-24
US4084233A
(en)
1978-04-11
DE2722775A1
(en)
1977-12-08
FR2353100A1
(en)
1977-12-23
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Legal Events
Date
Code
Title
Description
1981-03-04
PS
Patent sealed [section 19, patents act 1949]
1996-01-24
PCNP
Patent ceased through non-payment of renewal fee
Effective date:
19950524
