GB1584807A – Current control circuits
– Google Patents
GB1584807A – Current control circuits
– Google Patents
Current control circuits
Download PDF
Info
Publication number
GB1584807A
GB1584807A
GB44169/77A
GB4416977A
GB1584807A
GB 1584807 A
GB1584807 A
GB 1584807A
GB 44169/77 A
GB44169/77 A
GB 44169/77A
GB 4416977 A
GB4416977 A
GB 4416977A
GB 1584807 A
GB1584807 A
GB 1584807A
Authority
GB
United Kingdom
Prior art keywords
current
transistor
constant current
circuit
collector
Prior art date
1976-10-28
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB44169/77A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1976-10-28
Filing date
1977-10-24
Publication date
1981-02-18
1977-10-24
Application filed by Sony Corp
filed
Critical
Sony Corp
1981-02-18
Publication of GB1584807A
publication
Critical
patent/GB1584807A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
239000003990
capacitor
Substances
0.000
claims
description
19
230000004044
response
Effects
0.000
claims
description
3
238000009877
rendering
Methods
0.000
claims
description
2
101000986989
Naja kaouthia Acidic phospholipase A2 CM-II
Proteins
0.000
description
27
230000001276
controlling effect
Effects
0.000
description
5
230000003321
amplification
Effects
0.000
description
4
238000003199
nucleic acid amplification method
Methods
0.000
description
4
230000001105
regulatory effect
Effects
0.000
description
4
230000007423
decrease
Effects
0.000
description
3
238000010586
diagram
Methods
0.000
description
3
230000009471
action
Effects
0.000
description
2
230000009699
differential effect
Effects
0.000
description
2
230000000977
initiatory effect
Effects
0.000
description
2
230000001960
triggered effect
Effects
0.000
description
2
XUIMIQQOPSSXEZ-UHFFFAOYSA-N
Silicon
Chemical compound
[Si]
XUIMIQQOPSSXEZ-UHFFFAOYSA-N
0.000
description
1
230000005669
field effect
Effects
0.000
description
1
238000002955
isolation
Methods
0.000
description
1
238000000034
method
Methods
0.000
description
1
230000004048
modification
Effects
0.000
description
1
238000012986
modification
Methods
0.000
description
1
230000009467
reduction
Effects
0.000
description
1
230000004043
responsiveness
Effects
0.000
description
1
229910052710
silicon
Inorganic materials
0.000
description
1
239000010703
silicon
Substances
0.000
description
1
230000007704
transition
Effects
0.000
description
1
Classifications
H—ELECTRICITY
H03—ELECTRONIC CIRCUITRY
H03F—AMPLIFIERS
H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
H03F3/34—Dc amplifiers in which all stages are dc-coupled
H03F3/343—Dc amplifiers in which all stages are dc-coupled with semiconductor devices only
H—ELECTRICITY
H03—ELECTRONIC CIRCUITRY
H03G—CONTROL OF AMPLIFICATION
H03G1/00—Details of arrangements for controlling amplification
H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
H03G1/0035—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements
H03G1/0082—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements using bipolar transistor-type devices
H—ELECTRICITY
H03—ELECTRONIC CIRCUITRY
H03G—CONTROL OF AMPLIFICATION
H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
H03G3/20—Automatic control
H03G3/30—Automatic control in amplifiers having semiconductor devices
H03G3/34—Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems
Description
PATENT SPECIFICATION ( 11) 1 584 807
1 ( 21) Application No 44169/77 ( 22) Filed 24 Oct 1977 __ ( 31) Convention Application No 51/129689 ( 19) ( 32) Filed 28 Oct 1976 in + ( 33) Japan (JP) ( 44) Complete Specification published 18 Feb 1981 ( 51) INT CL 3 H 03 F 3/04 H 03 G 3/34 _ ( 52) Index at acceptance H 3 T 2 B 8 2 T 2 X 2 T 3 F 3 X 4 D 4 E 1 N 4 E 2 N 5 E AM H 3 Q BLA ( 72) Inventor MITSUO OHSAWA ( 54) CURRENT CONTROL CIRCUITS ( 71) We, SONY CORPORATION, a corporation organised and existing under the laws of Japan, of 7-35 Kitashinagawa-6, Shinagawa-ku, Tokyo, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: 5
This invention relates to current control circuits.
Embodiments of the invention are particularly, but not exclusively, suitable for use as selective muting circuits.
In general, a current control circuit is a particular type of circuit wherein an output current which may be supplied to various circuitry, such as an amplifier, a 10 tuner, a modulator, a demodulator, and the like is selectively controlled in accordance with various desired functions or operating conditions For some applications, it is preferred that some form of isolation exist so that the circuit which generates the output current does not unnecessarily load the controlling circuit, which loading could influence and deleteriously affect the output current 15 value.
An example of a previously proposed muting circuit will now be discussed In our US Patent No 4 149 918, a multiplexed stereo demodulator is disclosed for deriving left (L) and (R) audio information from a received, multiplexed stereo signal The demodulator includes a differential amplifier having the usual constant 20 current source for amplifying the received monophonic (L+R) signal The received signal, which also includes the stereo component (L-R) modulated onto a carrier, is amplified by another differential amplifier, this other amplifier also including the usual constant current source This second differential amplifier is connected to a multiplier, the latter being supplied with an unmodulated carrier, and this 25 multiplier is further supplied with the amplified output derived from the first differential amplifier The resultant output of the multiplier is the individual L and R channels of audio information In the event that a muting operation is to be performed, for example, if the multiplexed demodulator is used in an FM broadcast receiver wherein inter-station noise is to be muted while the tuning 30 section is tuned from one broadcast station to another, a muting signal is produced and supplied to the aforementioned constant current sources of the individual differential amplifiers This muting signal effectively de-activates the constant current sources such that no current flows through the differential amplifiers As is appreciated, this effectively mutes the output of the multiplexed demodulator 35 When a muting operation no longer is desired, such as when the tuning section of the FM receiver is tuned correctly to a broadcast channel, the constant current sources are promptly reactivated and current once again flows through the differential amplifiers However, this abrupt initiation of current flow may result in a loud, sudden noise in the loudspeaker system which is supplied from the 40 demodulator This so-called pop noise is, at best, unpleasant to a listener and may result in damage to the loudspeaker system.
The foregoing problem can be overcome by a “soft” muting control That is, if the constant current flow is re-initiated in a relatively gradual manner, a pop noise would not be produced 45 According to the present invention there is provided a current control circuit comprising:
current mirror means having first and second transistor devices, one of said transistor devices being operative to receive a controllable current and the other of said transistor devices being operative to conduct a current whose value is determined by and changeable with the current received by said one transistor device, said other transistor device being arranged to be connected to a load such 5 that the current in said load is equal to the current conducted by said other transistor device, and means coupled to said one transistor device for supplying said controllable current thereto; constant current generating means for generating a substantially constant current, said means for supplying said controllable current being coupled to said 10 constant current generating means and being operative to establish the level of said controllable current in accordance with the constant current applied thereto; and variable current conducting means coupled to said constant current generating means for conducting a selectively variable amount of said constant current such that said level of said controllable current is established in accordance 15 with the difference between said constant current and the amount of said constant current conducted by’ said variable current conducting means, and said controllable current varies substantially linearly with said difference.
According to the present invention there is also provided a current control circuit comprising: 20 a first current mirror circuit including first and second transistors of substantially identical characteristics having their base electrodes connected to each other and their emitter electrodes respectively coupled to a source of reference potential, the base electrode of said first transistor being connected to the collector electrode thereof and the collector electrode of said second transistor 25 being arranged to be connected to a load; a third transistor having its collectoremitter circuit connected in series with the collector-emitter circuit of said first transistor to supply a controllable current to said first transistor; a constant current generator for supplying at an output thereof a substantially constant current; 30 means for connecting the base electrode of said third transistor to said constant current generator output; a second current mirror circuit including fourth and fifth transistors of substantially identical characteristics having their base electrodes connected to each other and their emitter electrodes respectively coupled to said source of 35 reference potential, the base electrode of said fourth transistor being connected to the collector electrode thereof and the collector electrode of said fifth transistor being connected to said constant current generator output such that the current supplied to the base electrode of said third transistor is proportional to the difference between said constant current and the current conducted by said fifth 40 transistor; control means coupled to said fourth transistor for controlling the currents conducted by said fourth and fifth transistors, respectively; and means for linearly increasing the current supplied to said collector electrode of said first transistor when said control means renders said fourth and fifth transistors 45 non-conductive.
The invention will now be described by way of example with reference to the accompanying drawings, in which:
Fig l is a schematic diagram of a preferred embodiment of the invention; Fig 2 is a graphical representation of the relationship between various 50 parameters and is useful in understanding the operation of the embodiment; Fig 3 is a graphical depiction of the relation between other operating parameters in the circuit of Fig 1 and is useful in understanding the operation of the embodiment; and Figs 4 A and 4 B are waveform diagrams showing the relation between a 55 control signal and the output current produced by the circuit of Fig 1.
The current control circuit described below admits of general application and can be used for controlling the current flowing through a device, such as a load, in response to certain control input signals In order to best appreciate some of the advantageous features of this current control circuit, it will be described in 60 conjunction with one particular application thereof, viz, to control a muting operation In particular, this muting operation may be performed in, for example, a frequency modulation (FM) radio receiver so as to mute noise which may be 1,584,807 produced when the tuning section of the receiver is between broadcast channels.
This untuned condition is typically detected at the output of the intermediate frequency (IF) section of the FM receiver When this IF output is less than a threshold level, a proper tuning condition is not established and a muting operation should be performed Suitable circuits are known for detecting this untuned 5 condition and for generating a muting control signal Conversely, when a proper tuning condition exists, the muting control signal terminates and the muting operation no longer is performed If this muting operation is to be carried out in apparatus as described in the aforementioned U S Pat No 4,149,918, a muting condition is initiated by interrupting the current flow in a differential amplifier, and 10 the muting condition is terminated by resuming such current flow In this regard, the following description of an embodiment of current control circuit in accordance with the invention demonstrates how this current flow is controlled, thereby controlling the muting operation.
Turning now to Fig 1, a current control circuit 1 is shown as being connected 15 to a load la for selectively controlling the current flowing through load la Load la may be an amplifier, such as the IF amplifier or the audio amplifier of an FM receiver, or load la may be a tuning circuit of the FM receiver It will be assumed that when current control circuit 1 establishes a current through load la, an operating mode (such as amplification) is maintained; whereas when current 20 control circuit I interrupts the current flowing through load la, a muting operation is performed This means that load circuit la will not amplify or otherwise reproduce the signal which then is supplied thereto.
Fig 1 also shows that current control circuit 1 is connected to and controlled by a current regulating circuit 2, this current regulating circuit being coupled to a 25 further control circuit 4 In addition, a muting defeat and control circuit 3 is coupled to current regulating circuit 2 Each of these circuits now will be described.
Current control circuit 1 includes a current mirror circuit CM 1 formed of transistors Q, and Q 2 having their base electrodes connected to each other and 30 their respective emitter electrodes connected to a source of reference potential T.
via resistors R, and R 2 In the illustrated embodiment, ground potential may be applied to source of reference potential T Transistor Q 2 additionally has its base electrode connected directly to its collector electrode If transistors Q, and Q 2 are of substantially identical characteristics and are of the same conductivity type (as 35 an example, these transistors are shown as NPN transistors), then a current will flow through the collector-emitter circuit of transistor Q, which is substantially equal to the current which flows through the collector-emitter circuit of transistor Q 2 Furthermore, the current flowing through transistor Q 1 will vary as the current flowing through transistor Q 2 varies However, if a load, such as load la, is 40 connected to transistor Q,, the particular operating characteristics and parameters of this load generally will not influence the current flowing through transistor Q 2.
Accordingly, as shown, load la is connected to the collector electrode of transistor Q 1, and a source of energizing voltage T 2 (+ 12 V) is coupled to load la.
A transistor Q 3 has its collector-emitter circuit connected via a resistor R 3 to 45 the collector electrode of transistor Q 2 Transistor Q 3 is a current responsive device and establishes the current flowing through transistor Q 2 in accordance with a controllable current which is applied to the base electrode of transistor Q 3 Thus, the current responsiveness of transistor Q 3 determines the currents in current mirror circuit CM,, and thus establishes the current flowing through load la As 50 shown, the collector electrode of transistor Q 3 is coupled to energizing voltage source T 2.
Current regulating circuit 2 comprises a constant current transistor Q 4 and another current mirror circuit CM 2 Constant current transistor Q 4 is shown as a PNP transistor whose emitter electrode is coupled via a resistor R, to a source T 3 of 55 energizing voltage (+ 4 V) The base electrode of transistor Q 4 is connected directly to a bias voltage, shown as source T 4 (+ 2 V) Since transistor Q 4 is shown as a PNP transistor, it is appreciated that the voltage applied to its base electrode should be less than the voltage applied to its emitter electrode so as to suitably bias the baseemitter junction thereof Accordingly, a substantially constant current flows 60 through the emitter-collector circuit of transistor Q 4.
The collector electrode of transistor Q 4 is connected to the base electrode of transistor Q 3 and also through a diode D to current mirror circuit CM 2 If the potential (+ 4 V) applied to source T 3 is less than the potential (+ 12 V) applied to 1,584,807 4 1,584,807 4 source T,, then the maximum bias voltage applied by transistor Q 4 to transistor Q 3 (relative to ground reference potential) will be less than the collector voltage of transistor Q 3 As will become apparent, the base voltage of transistor Q 3 thus may vary from approximately zero volts up to the maximum voltage which can be provided at the collector electrode of transistor Q 4 Current mirror circuit CM 2 is 5 formed of transistors Q 5 and Q 6 whose base electrodes are connected to each other and whose emitter electrodes are connected to source T 1 In addition, the base and collector electrodes of transistor Q 6 are connected in common The output of constant current transistor Q 4 is connected to the collector electrode of transistor Q 5 The collector electrode of transistor Q 6 is connected to an output transistor Q 7 10 of control circuit 4, to be described It may be appreciated that the current flowing through transistor Q 5 is determined by the current supplied to transistor Q 6 Since the current applied to transistor Q 5 is generated by constant current transistor Q 4, it is necessary for this constant current to divide between transistors Q 3 and Q 5 depending upon the current level through current mirror circuit CM 2, as 15 determined by transistor Q 6 That is, if the conductivity of current mirror circuit CM 2, as determined by transistor Q 7, is less than that required to conduct all of the constant current, then a portion of this constant current is applied to transistor Q%.
Conversely, if the conductivity of current mirror circuit CM 2 is high enough such that all of the constant current can flow therethrough, then substantially none of 20 the constant current produced by transistor Q 4 is applied to transistor Q 3.
Muting defeat and control circuit 3 includes a capacitor C connected in parallel with the collector-emitter circuit of transistor Q 5, and the junction defined by capacitor C and the collector electrode of this transistor is connected through a switch SW and a resistor R 4 to energizing voltage source T 2 The capacitance of 25 capacitor C is relatively large and its charging condition is selectively determined by the conductivity of current mirror circuit CM 2 and also by the selective operation of switch SW That is, if current mirror circuit CM 2 is conductive such that the collector-emitter impedance of transistor Q 5 is relatively low, current from transistor Q 4 which also flows to diode D will flow to ground via transistor Q 5 30 Hence, capacitor C will receive a relatively small charge If current mirror circuit CM 2 is not conductive, the current flowing from transistor Q 4 and through diode D will not pass through transistor Q 5 Rather, this current now will charge capacitor C If switch SW is closed, capacitor C is charged from energizing voltage source T 2 through resistor R 4 and the closed switch SW Since the energizing voltage (+ 12 V) at 35 source T 2 is assumed to be greater than the energizing voltage (+ 4 V) at source T 3, when switch SW is closed, capacitor C will charge to a voltage ( 12 V) which is greater than the maximum voltage which can be applied to the collector electrode of transistor Q 4 Hence, when diode D is poled in the indicated direction, the closing of switch SW serves to reverse bias this diode As will be explained below, 40 diode D is substantially forward biased at other times.
Control circuit 4 is shown as a hysteresis gate pulse generator In addition to output transistor Q 7, described briefly above, whose collector-emitter circuit is connected via a resistor R,, to transistor Q 6 of current mirror circuit CM 2 so as to supply a current derived from energizing voltage source T 2 to this current mirror 45 circuit, the hysteresis gate pulse generator includes a transistor Q%, a transistor Q 9, a current mirror circuit CM 3 formed of transistors Q,0 and Q, a differential amplifier formed of transistors Q,2 and Q,3 and a triggering transistor Q 14.
Transistors Q,2 and Q,3 are of substantially identical characteristics and are connected in differential amplifier configuration wherein their emitter electrodes 50 are connected in common via a current source IK to ground potential The base electrode of transistor Q,2 is coupled to the emitter electrode of transistor Q 9, and the base electrode of transistor Q,3 is coupled to the emitter electrode of trigger transistor Q 14 The collector electrode of transistor Q,2 is coupled through transistor Q, of current mirror circuit CM 3 to a source T, of energizing voltage 55 (+ 6 V) The collector electrode of transistor Q,3 is connected directly to source T,.
The junction defined by the emitter electrode of transistor Q, and the base electrode of transistor Q,2 is coupled to source T, via a resistor R,, and the similar junction defined by the emitter electrode of transistor Q 14 and the base electrode of transistor Q 13 is coupled to this source T, by a resistor R,, Resistors R, and R,, have 60 equal resistance values, such as 15 kilohms An input terminal t is coupled to the base electrode of transistor Q,4 and receives a muting control signal, represented by the pulse shown in Fig 1 This muting control signal, which may be produced in response to the output of an IF stage in an FM receiver, determines the conductivity of current mirror circuit CM, in current control circuit 1 Hence, 65 1,584,807 5 when used to control a muting operation, the pulse applied to terminal t determines whether that operation is performed.
Transistors Q-0 and Q 11 forming current mirror circuit CM 3 are shown as PNP transistors and exhibit substantially identical characteristics The base electrodes of these transistors are connected to each other and their emitter electrodes are 5 connected respectively to source T 5 In addition, the base electrode of transistor Q 11 is connected to the collector electrode thereof As may be appreciated, the current through transistor Q,, is determined by the particular conductivity of the differential amplifier formed of transistors Q 12 and Q,3, and a substantially equal current flows through transistor Q,0 This output current of current mirror circuit 10 CM 3 is applied to the base electrodes of transistors Q 7 and Q 8, these base electrodes being connected in common to the collector electrode of transistor Q,0.
A bias circuit formed of voltage divider resistors R 6, R 7 and R 8 is connected in series between source T 5 and ground potential The junction defined by resistors R, and R 8 is connected to the base electrode of transistor Q 9, thereby establishing the 15 level at which transistor Q% is rendered conductive whereby the relative conductivity of transistors Q 12 and Q 13 is determined The collectoremitter circuit of transistor Q 8 is connected between energizing voltage source T 2 and the junction defined by resistors R 6 and R 7 As may be appreciated, when transistor Q 8 is conductive, resistor R 6 is effectively removed from the voltage divider circuit 20 which then exists from source T 2 through transistor Q 8 and resistors R 7 and R 8.
The operation of the circuit illustrated in Fig I now will be described.
Resistors R, and R 2 in current mirror circuit CM, of current control circuit l serve as current feedback resistors to improve the linearity of this current mirror circuit.
In one example, these resistors have equal resistance values of approximately 300 25 ohms Resistor R 3 in current control circuit 1 limits the direct current flowing through the current mirror circuit, and thus the dc flowing through load la, to a predetermined level If the dc flowing through load la, and thus through transistor Q, is represented as 101, and if the dc supplied to transistor Q 2 by transistor Q 3 is represented as 102, then, because of current mirror operation, 101 equals 102, and 30 these currents may be represented as:
VI-(VBE 2 +VBE 3) r 2 +r 3 =( 1 +h FE)Icolt ( 1) -h FE ‘ Cont where Vi is the base voltage at the base electrode of transistor Q 3, VBE 2 and VBE 3 are the base-emitter voltages of transistors Q and Q, respectively, r, and r, are the resistance values of resistors R 2 and R 3, respectively, h FE is the current 35 amplification factor of transistor Q 3 for the grounded emitter configuration, and I Cont is the base current supplied to transistor Q 3 By rearranging terms, the base voltage V, of transistor Q 3 may be expressed as:
VI=I 12 (r 2 +r 3)+(VBE 2 +VBE 3) =( 1 +h FE)(r 2 +r 3)Ic Ont+(VBE 2 +VBE 3) ( 2) Transistors Q, Q 2 and Q 3 may be selected such that the current amplification 40 factor h FE thereof is relatively high Accordingly’ the base-emitter voltage of transistor Q 2 and the base-emitter voltage of transistor Q 3 may be expressed as a function of the collector current Io 2 thereof as follows:
k T ___ O VE 2 E 3 3 (I) k T Jn h FE \T| () in I 6 ontj wherein k is Boltzmann constant, T is the absolute temperature, q is the electric charge on an electron, and Is is the saturation current of each of transistors Q 2 and Q 3 As a practical example, the saturation current Is may be about 0 2 x 10-15 at 3000 K.
If equation ( 3) is substituted into equation ( 2), and maintaining the assumption 5 that the current amplification factor h FE is relatively large (h FE>>I), then the base voltage V, of transistor Q 3 will be:
V = I FE(r+ 1)IJI N + ( t N f( h IS)I ont} ( As is appreciated, the second term in equation ( 2) has been replaced by its equivalent value in equation ( 3) wherein the base-emitter voltages of transistors Q 2 10 and Q 3 are equal Thus, the second term in equation ( 4) is:
2 FE) 2 V E ‘ en {(I Cont BE q Referring to Fig 2, a graphical representation of equation ( 5) is illustrated.
The numerical values provided in the ordinate of this graph are typical base-emitter voltage values for a silicon transistor Now, if the base voltage V, of transistor Q 3 is 15 much greater than twice the base-emitter voltage (Vi>> 2 VBE), then the second term in equation ( 4), that is, the value 2 VBE, may be disregarded and the base voltage V, may be closely approximated by:
V,-h FE(r 2 +r 3)IC Of L ( 6) Similarly, the second term in equation ( 2) may be disregarded, and if (h FE+ 1) is Nh FE, 20 then the currents flowing through current mirror circuit CM 1 may be expressed as:
V, 102 =I 101 =h FE ‘ cont 7 r 2 +r 3 The manner in which base voltage V, varies with base current 1 cant and the manner in which currents 101 and 102 vary with base current I ont is graphically depicted in Fig 3 As shown, current 102, and thus output current 101 of current 25 mirror circuit CM,, varies linearly with input current lcont over a defined range of the input current The broken curve shown in the left-hand portion of Fig 3 represents the condition that the base voltage V, is not much greater than the baseemitter voltage VBE The voltage VB represents the maximum base voltage which can be applied to transistor Q 3 in the configuration shown in Fig 1 Hence, this 30 maximum value is the energizing voltage (+ 4 V) provided by source T 3 When input current Ircnt reaches the value such that the base voltage of transistor Q 3 is equal to VB, the currents through current mirror circuit CM, reach their maximum level To avoid saturation of transistor Q 3, the energizing voltage applied to its collector electrode should be equal to or greater than the maximum voltage which can be 35 applied to its base electrode If the energizing voltage (+ 12 V) provided by source T, is represented as Vc, then the foregoing condition is satisfied if VCC>VB As further shown in Fig 3, the overall range of base voltage V, of transistor Q 3 is between zero volts and VB Hence, O
