GB1586323A - Creation of Inventions and Patents with Artificial Intelligence

GB1586323A – Semiconductor data storage devices
– Google Patents

GB1586323A – Semiconductor data storage devices
– Google Patents
Semiconductor data storage devices

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Publication number
GB1586323A

GB1586323A
GB20086/78A
GB2008678A
GB1586323A
GB 1586323 A
GB1586323 A
GB 1586323A
GB 20086/78 A
GB20086/78 A
GB 20086/78A
GB 2008678 A
GB2008678 A
GB 2008678A
GB 1586323 A
GB1586323 A
GB 1586323A
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United Kingdom
Prior art keywords
transistor
storage
zone
transistors
emitter
Prior art date
1977-08-27
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB20086/78A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

International Business Machines Corp

Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1977-08-27
Filing date
1978-05-17
Publication date
1981-03-18

1978-05-17
Application filed by International Business Machines Corp
filed
Critical
International Business Machines Corp

1981-03-18
Publication of GB1586323A
publication
Critical
patent/GB1586323A/en

Status
Expired
legal-status
Critical
Current

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Classifications

G—PHYSICS

G11—INFORMATION STORAGE

G11C—STATIC STORES

G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor

G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements

G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices

G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors

G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger

G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only

G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors

G—PHYSICS

G11—INFORMATION STORAGE

G11C—STATIC STORES

G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor

G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements

G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices

G11C11/4116—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL

H—ELECTRICITY

H03—ELECTRONIC CIRCUITRY

H03K—PULSE TECHNIQUE

H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits

H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses

H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback

H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback

H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator

H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable

H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit

H—ELECTRICITY

H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

H10B—ELECTRONIC MEMORY DEVICES

H10B10/00—Static random access memory [SRAM] devices

H10B10/10—SRAM devices comprising bipolar components

Description

PATENT SPECIFICATION ( 11) 1 586 323
M ( 21) Application No 20086/78 ( 22) Filed 17 May 1978 tit ( 31) Convention Application No 2738678 ( 32) Filed 27 Aug 1977 in CD ( 33) Federal Republic of Germany (DE) ( 44) Complete Specification published 18 March 1981 ( 51) INT CL 3 HOIL 27/10 G 1 IC 11/40 ( 52) Index at acceptance HIK 11 A 3 A 11 B 3 11 B 4 11 CIA 11 C 4 I 1 Dl li D IAAI IAA 9 4 C 11 9 E GAH ( 72) Inventor SIEGFRIED KURT WIEDMANN ( 54) SEMICONDUCTOR DATA STORAGE DEVICES ( 71) We, INTERNATIONAL BUSINESS MACHINES CORPORATION, a Corporation organized and existing under the laws of the State of New York in the United States of America, of Armonk, New York 10504, United States of America do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in 5 and by the following statement:-
This invention relates to integrated semiconductor data storage devices consisting of a flip-flop with two cross-coupled bipolar switching transistors and two load elements each connected by one of its two terminals to the collector of a respective one of the switching transistors, said storage device being controlled via l 10 a word line connected to the other terminal of both load elements and via one bit line each of a bit line pair connected to the emitter of each switching transistor.
Such storage devices are used in particular in storage arrangements of digital data processing systems, whereby the storage devices are arranged in a matrix, so that each individual device can be addressed via corresponding selections means, 15 with binary data being written into or read from it.
In the field of logical circuits with bipolar transistors considerable progress has been made during the past few years, which has attracted great attention on the part of the experts and which under the term MTL (Merged Transistor Logic) or 12 L (Integrated Injection Logic) has become widely known in technical literature 20 Attention is drawn, for example, to articles in the IEEE Journal of SolidState Circuits, Vol SC-7, No 5, October 1972, pp 340 ff and 346 ff Relevant patent specifications, are, for example, US-PS 3 736 477 and 3 816 758 This injection logic concept is essentially based on inverting single or multiplecollector transistors which by the direct injection of minority charge carriers inside the 25 semiconductor body are fed close to their emitter-base junctions (order of magnitude one diffusion length) This bipolar logic concept has very short switching times In addition, it is suitable for the manufacture of extremely highly integrated, large-scale logical circuits with a great number of logical elements producible on a single semiconductor chip For the manufacture of logical circuits 30 in highly integrated technology, essentially three prerequisites have to be fulfilled.
The basic circuits must be as simple and space-saving as possible, so that as great a number of them as possible can be arranged on a single semiconductor chip In addition, the layout of the circuits must be such that an adequate speed does not lead to an excessive increase in the power dissipation on the semiconductor chip, 35 which is tantamount to the requirement that the product of the factors delay time and power dissipation per logical function should be as small as possible Finally, to obtain a good yield and thus for economical and also for technological reasons the manufacturing process required must be as simple and readily applicable as possible The inverting logical circuits described are not only outstandingly suitable 40 for the manufacture of logical circuits but they can also be advantageously used as a component for monolithically integrated storage cells, utilizing the fact that in the case of inverting logical circuits two stages each are required to obtain storage cells in the manner of flip-flops Thus, a storage cell consists of two such basic circuits which are symmetrically designed and whereby the output of one basic circuit is 45 connected to the input of the other circuit to fulfil the feedback condition In this manner the necessary cross-coupling, as exists with conventional flipflops, is obtained From DT-OS 2 307 739 a storage cell is known which is made up of two of the logical circuits described and whereby the collector of the inverting transistor of one circuit is in each case cross-coupled with the base of the inverting transistor of the other circuit The two inverting transistors, in their turn, are inversely operated, forming the actual flip-flop transistors or switching transistors.
The complementary transistor of each basic circuit, which is connected via a 5 separate line and via which the minority charge carriers are injected, serves as a load element for both switching transistors For the purpose of addressing, i e for writing and reading the storage cell, the base of each switching transistor is additionally connected to the emitter of an associated additional addressing transistor which is also complementary and whose collector and base are 10 respectively connected to the associated bit line and the address line Thus, in addition to the injecting transistor forming the load element, an addressing transistor is required which in turn is formed by a lateral transistor structure.
By laterally arranging the two circuits forming a storage cell and by merging the zones connected to the same potential, the desired simple semiconductor 15 structure is obtained By means of this known storage cell a storage matrix can be produced in which the storage cells are arranged at least in two horizontal lines and in at least four vertical columns A first vertical address line is associated with the first and second column, and a second vertical address line is associated with the third and the fourth column Furthermore, a first horizontal address line is associated 20 with the first line, and a second horizontal address line is associated with the second line Finally, a first, second and third bit line pair is respectively associated with the first, the second and the third, and the fourth column For this purpose each bit line pair extends preferably in a vertical direction between the associated columns The bit lines are in each case connected to the collectors of the addressing transistors, 25 the first address line is connected to the emitters of the transistors forming the load elements, and the second address line is connected to the bases of the addressing transistors.
According to the invention, we provide an integrated semi-conductor storage device consisting of a flip-flop with two cross-coupled, bipolar switching transistors 30 and two load elements each connected by one of its two terminals to the collector of a respective one of the switching transistors, said storage device being controlled via a word line connected to the other terminal of both load elements and via one bit line each of a bit line pair connected to the emitter of each switching transistor characterized in that the flip-flop consists of two E 2 L structures integrated in two 35 separate isolation pockets of the semiconductor body and comprising in a known manner one in jector and one associated inverting transistor each, and that in each case the injector of one of the inverting transistors used as switching transistors simultaneously forms the load element of the other switching transistor.
The invention will be described in detail below by means of two embodiments 40 shown in the drawings, of which Fig IA is the equivalent circuit diagram of the known 12 L basic structure serving as a component of the storage cell embodying the invention, Fig I B shows a plan view of one of the known embodiments of the E 2 L basic structure shown in the equivalent circuit diagram of Fig IA, 45 Fig IC is a sectional view of the known E 2 L basic structure in accordance with Fig I B, Fig 2 is the equivalent circuit diagram of a storage cell embodying the invention, Fig 3 A is a plan view of a section of the structure of a first embodiment of a 50 storage matrix made up of storage cells embodying the invention, Fig 3 B is a first sectional view of the structure in accordance with Fig 3 A, Fig 3 C is a second sectional view of the structure in accordance with Fig 2 A, and Fig 4 is a plan view of a section of the structure of a second embodiment of a 55 storage matrix made up of storage cells embodying the invention.
Initially, the 12 L basic structure shown in the equivalent circuit diagram the plan view, and the sectional view of Figs IA, IB, and IC will be described briefly.
This E 2 L structure realizes the injection principle and is known, for example, from the afore-mentioned US Patent Specifications 3 736 477 and 3 816 758 The layout 60 and the operation of this structure are described in detail in the aforementioned literature, so that merely a summarizing description need be given here The designations are chosen in such a manner that they simultaneously indicate the conductivity type of the individual zones In addition, the semiconductor zones 1,586,323 merged in the actual structure and connected to the same potential are provided with the same references.
It is pointed out at this juncture that several modifications and further developments of the 12 L basic structure described here have become known, by means of which the storage cell in accordance with the invention can be 5 advantageously realized.
As may be seen from Figs, IB and IC a lowly doped semiconductor substrate P of a first conductivity type, for example, of the P-conductivity type, serves as a starting material On the semiconductor substrate P a highly doped, buried zone N+ of the opposite conductivity type is arranged Over the buried zone N+ and N 10 doped epitaxial layer NI is arranged In the epitaxial layer NI the oppositely doped zones Pl and P 2 are embedded at a certain distance from each other In zone P 2 there is a further zone N 2 doped oppositely thereto The zones P 1, P 2, and N 2 are provided with contacts via terminals I, B, and C To the buried zone N+ a terminal E is connected The equivalent circuit diagram of this structure is shown in Fig 15 IA, the identical designations of the individual zones permitting a direct comparison between structure and equivalent circuit diagram.
Thus, the inverting logical basic circuit used in accordance with the invention essentially consists of an inverting transistor Ti with the zone sequence N 2 P 2 NI, which is fed by the direct injection of minority charge carriers 20 The inverting transistor TI is designed as an inversely operated, vertical transistor For the purpose of minority charge carrier injection, transistor T 2 is provided which is complementary to transistor Ti Transistor T 2 has the zone sequence Pl NI P 2 and is laterally designed in the structure described Both transistors are integrated with each other at the highest degree of integration, 25 utilizing common semiconductor zones The epitaxial layer NI simultaneously serves as the base zone of the lateral transistor T 2 and as the emitter of the vertical transistor Tl The zone Pl forms the emitter of the lateral transistor T 2 The zone P 2 simultaneously forms the base of the vertical, inverting transistor Tl and the collector of the injecting lateral transistor T 2 The zone N 2 forms the collector of 30 the inverting transistor TI At zone Pl forming the emitter of the injecting transistor T 2 an injector terminal I is provided, via which a current is externally introduced in the direction of the arrow This current supplies the operating current for the inverting transistor Ti To zone P 2 forming the base of this transistor a control terminal B is connected, via which the state of the inverting 35 transistor Tl is switchable At the zone N 2 collector terminal C is arranged which simultaneously forms the output of the inverting basic circuit At the buried zone N+ the emitter terminal E of the vertical transistor Ti is arranged.
In accordance with the invention, the 12 L basic circuit described is optimally used in all the essential points by merging two such basic circuits in accordance with Fig I to 40 ( give a highly integrated storage cell, as shown in the equivalent circuit diagram of Fig 2 The individual semi-conductor zones are provided with the same references as in Fig 1, the designations of one of the two basic circuits being line indexed to permit ready distinction.
The storage cell in accordance with the invention is, in principle, designed in 45 the manner of a flip-flop, the two inverting transistors Ti and Ti’ forming the actual flip-flop transistors or switching transistors As load elements the collector circuits of these switching transistors comprise complementary transistors T 2 ‘ and T 2, respectively For realizing the flip-flop function, the collector of one of the switching transistors is to be connected in each case to the base of the other 50 switching transistor, so obtaining the required mutual feedback An essential feature in accordance with the invention consists in the load element of one branch of the flip-flop simultaneously forming the injector for the switching transistor of the other branch, utilizing the injection principle described above The injecting transistor T 2 forms both the load element of the switching transistor Tl’ and the 55 injector for the switching transistor TI The injecting transistor T 2 ‘ forms the load element of the switching transistor Ti and the injector of the switching transistor T ‘ A further essential feature of the storage cell in accordance with the invention consists in the two injector terminals of the two injecting transistors T 2 and T 2 ‘ being jointly connected to a word line WL, while the emitter of each switching 60 transistor T I and T ‘, respectively, is connected to an associated bit line BO and B I, respectively, of a bit line pair It is significant for the storage cell in accordance with the invention that the emitter zones NI and NI’ of the two transistors TI and Ti’ at different switching states of these transistors and at an identical current or voltage value applied have a very small voltage or current difference When the two 65 1,586,323 12 L structures are integrated in separate isolation pockets, the switching state of the storage cell can be read respectively via said isolation pockets and the emitter zones NI and NI’ embedded therein.
As during the addressing of the storage cell the emitter zones NI and NI’ of the two switching transistors thus are connected to different potentials, the two 5 switching transistors are to be arranged in separate isolation pockets in an integrated monolithic design, as may be seen from the subsequent description of the structural layout As the switching transistor of one branch together with the complementary transistor of the other branch, which serves as a load element, form one 12 L circuit each in accordance with the invention, said two transistors are to be 10 arranged in one common isolation pocket in accordance with the known 12 L basic structure described by means of Fig I An essential advantage of the storage cell in accordance with the invention is due to the fact that only one word line WL connected to the two injecting transistors T 2 ‘ and T 2 is required as an external line.
The necessary cross-coupling is effected by means of short lines M l and M 2 which 15 connect the collector zone N 2 and N 2 ‘, respectively, of one switching transistor to the base zone P 2 and P 2 ‘, respectively, of the other switching transistor As will be described below, the two bit lines BO and BI, connected to the emitter zones NI and NI’, respectively, of the two switching transistors T I and T I’, respectively, are preferably realized by means of buried, highly doped zones N’ arranged in the 20 associated isolation pockets All further conductive connections shown in the equivalent circuit diagram do not exist in the monolithic structure which in accordance with the 12 L basic structure is realized by merging the zones bearing the same designations For the purpose of explaining the function, parallel to the two injecting transistors T 2 ‘ and T 2 two further transistor structures for the respective 25 inverse current direction are shown by broken lines in the equivalent circuit diagram of Fig 2 These transistors for the inverse current direction do not exist in the structure, since they are identical with the injecting transistor structure These additional transistor structures in the equivalent circuit diagram are justified, since with a conductive switching transistor TI or Tl’, a current IER 2 ‘ or IER 2 is 30 injected back into the respective appertaining injector This back injected current superimposes the actual injection current IE 2 ‘ and 1 E 2, respectively.
The monolithic layout of a storage matrix made up of the storage cells in accordance with the invention is shown by way of a plan view in Fig 3 A and by way of sectional views in Figs 3 B and 3 C The section shown in Fig 3 A comprises two 35 lines and two columns, that means four storage cells of a storage matrix Each storage cell is made up of two of the 12 L basic structures shown in Figs IA to IC.
The two basic structures forming one storage cell are separated from each other by an isolation zone IZ The monolithic layout consist in an epitaxial layer NI being applied to a semiconductor substrate P- This epitaxial layer NI is subdivided into 40 strips by means of isolation zones IZ extending in line direction Thus, one line of the matrix comprises two such strip-shaped regions NI which are isolated from each other by an isolation zone IZ These isolation zones may be,Tfor example, dielectric zones or PI-doped zones extending right into the substrate P- In each region NI there is a continuous buried zone N+ which extends in line direction and which is 45 common to one half of the total number of cells making up a line These buried zones N+ serve as bit lines B 10, B l I, B 20, and B 21 The two 12 L basic structures forming a storage cell are arranged one below the other in column direction, comprising, as shown in Figs IA to IC, two laterally arranged zones Pl and P 2 in the epitaxial layer NI and a further zone N 2 within the zone P 2 In this manner a 50 storage cell is obtained which is made up of vertical transistors TI and TI’ with a zone sequence of N 2 P 2 NI and N 2 ‘ P 2 ‘ Nl’, respectively, and of associated lateral transistors T 2 and T 2 ‘ with a zone sequence of Pl NI P 2 and PI’ NI’ P 2 ‘, respectively, which effect the injection Cross-coupling is established by two lines Ml and M 2 which extend on top of an isolation layer IL covering the whole 55 arrangement, and which contact the zones N 2 and P 2 ‘ and N 2 ‘ and P 2, respectively.
In addition, one word line WL I, WL 2 is provided for each column of the matrix By means of this word line all the Pl and P 1 ‘ zones of the various storage cells of a column, which form the emitters of the lateral, injecting transistors T 2 and T 2 ‘, respectively, are connected to each other Adjacent storage cells of a line can be 60 isolated from each other by a suitable blocking zone BZ This blocking zone prevents parasitic couplings between the cell components of two adjacent cells of a line The blocking zone can be either an N±diffusion of a P-diffusion connected to a fixed potential, or a passive zone The blocking zone reduces the effective area required for a storage cell 65 1,586,323 An advantageous modification of the storage matrix shown in Fig 3 A is depicted in Fig 4 In the structure considered here the negative influence of the blocking zones on the area requirements is reduced Two successive storage cells in the line are arranged mirror-inverted in relation to each other, the injection zones Pl and P 1 ‘, respectively, of the adjacent cells being spaced from each other at a 5 minimum distance, so that the area requirements for the blocking zone occur only every other storage cell During the selection of the word line WL 2 it must merely be ensured that the adjacent word line W Ll is connected to a fixed potential which is chosen in such a manner that from the injection zones Pl and P 1 ‘, respectively, associated with the word line WLI no charge carriers are injected 10 With regard to all other points, the storage arrangement in accordance with Fig 4 corresponds to that of Fig 3 A.
The operation of a storage cell in accordance with the invention will be described in detail below by means of the equivalent circuit diagram of Fig 2 showing the designations of the operating data necessary for the description of the 15 operational mode For a practical embodiment typical operating data have been assumed.
In the standby state the two bit lines BO and B 1 are kept at the same potential (about 0 Volt) The emitters Pl and PI’ of the two transistors T 2 and T 2 ‘ acting as load elements preferably receive a very low standby current via the word line WL, 20 so that the storage cell operates at very low standby power As the baseemitter voltages VBE and VBE’ of the two transistors T 2 and T 2 ‘ are of the same magnitude, the emitter currents 1 E 2 and 1 E 2 ‘ are likewise of the same magnitude, so that for the stability of the storage cell the current amplification of the switching transistors TI and 11 ‘ must merely be larger than one All storage cells connected to 25 a common word line WL are fed with current IWL from a common current source.
Because of the good tracking characteristics of the PNP-transistors T 2 and T 2 ‘ the current is nearly uniformly distributed to all cells.
For addressing the storage cell, the potential of the word line WL is raised by several hundred millivolts 30 For reading the information, there are essentially two different operational modes which can also be combined with each other.
With the first mode, the two bit line potentials VBE and VBE’ on the two bit lines BO and Bl are kept at the same value, so that the emitter currents I El and IEI’ are also identical (As the potential on the word line is raised by several 35 hundred millivolts, the bit line potentials increase correspondingly) In order to obtain a higher read speed, the current IWL on the word line in increased over that in the standby state During this process, the nonselected cells on the same bit line pair BO, Bl are practically cut off from the power supply, as the baseemitter voltages of the load transistors T 2 and T 2 ‘ are reduced by about 500 m V However, 40 the information is maintained for a long time (in comparison with the read time) as a result of the charge stored in the switching transistor capacitances As the nonselected storage cells carry practically no current during reading, they cannot supply any current to the bit lines BO, B 1 either The selected storage cell, however, supplies different currents 10 and Ii to the bit lines as a function of the 45 storage state of the cell, so that by means of a differential current, amplifier connected to the bit lines BO and B 1 the storage state of the cell can be determined.
The current difference 10-Il will be calculated in the following paragraph, assuming the Ti’ is conductive and that TI is blocked This switching state can be associated with a stored binary one, for example As mentioned above, the two bit so lines BO and Bl are connected to the same potential, so that VBE=VBE’ and IE 2 ‘=IE 2 =IE The bit line current 10 is derived solely from the base current IB 2 of the transistor T 2 in accordance with (l) 10 =(l-a 2) IE, since the current IER 2 injected back via the load transistor T 2 in the inverse 55 direction is zero, and since the switching transistor Tl carries no current The bit line current I is composed of ( 2) Il=(l-a 2 ‘) IE+(l-a R 2 ‘)+IER 2 ‘+IEL.
In many practical cases the base current IB l’ is low in relation to the emitter current IE 2 ‘, so that 60 ( 3) IER 2 ‘a 2 ‘ IE 2 ‘=a 2 ‘ IE.
1,586,323 s 1,586,323 6 In such a case the emitter current IEI’ is about the same as the collector current ICI’ of the transistor Tl’, which is equal to the collector current of the transistor T 2 in accordance with ( 4) IEI’,ICI’=a 2 IE.
When equations ( 3) and ( 4) are inserted into equation ( 2) the following 5 equation is obtained:
( 5) Il I(l-a 2 ‘)IE+( 1-a R 2 ‘) 2 ‘ IE+a 2 i E.
With symmetrical load transistors T 2 and T 2 ‘, a 2 and a 2 ‘ are of the same value, so that from equation ( 5) the following equation is derived:
( 6) Illl 1 +(l-a R 2 ‘)a 21 IE 10 With regard to the current ratio I 1/I 0, the following is obtained from equations (I) and ( 6):
1 +a 2-a 2 a R 2 ‘ ( 7) Il /I O l-a 2 a 2 ( 2-a R 2 ‘) = 1 + or 1-a 2 l/I O; 1 +/32 ( 2-cr R 2 ‘) 15 This current ratio can be indicated by means of a low-resistivity differential amplifier on the bit lines B 0, B 1, thus permitting the determination of the state of the storage cell.
With the second read method the bit line currents I 0 and 11 are kept at the same value, and the resulting bit line voltage difference VBE-VBE’ is used to determine 20 the state of the storage cell This voltage difference is calculated below From equation (I) the following equation is obtained:
( 8) IE 2 =-I 0/l-a 2.
From equation ( 2) the following equation is obtained:
( 9) I O = 1 l=( 1-a 2 ‘)IE 2 ‘+( 1 l-a R 2 ‘)IER 2 ‘+IEI’ 25 By means of equations ( 3) and ( 4) the following is obtained after corresponding conversion:
1-2 a 2 ( 10) IE 2 ‘=I 0.
( 1-2 a 2 ‘+a 2 a R 2 ‘) (l-a 2) At the same current amplifications of the load transistors T 2 and T 2 ‘, thus at a 2 =a 2 ‘, the following is obtained: 30 1-2 a 2 ( 10) IE 2 ‘=I 0.
( 1-2 a 2 +a 2 a R 2 ‘) (l-a 2) With regard to the current ratio IE 2/IE 2 ‘, the following equation is obtained from equations ( 8) and ( 10):
a 2 a R 2 ‘ ( 11) IE 2/IE 2 ‘= 1 + 1-2 a 2 I 7 1,586,323 7 As VBE=VT In IE 2 ‘/IS (VT k T/q= 26 m V at 251 C being the thermal voltage and IS the inverse saturation current), the value AV=VT In 1 E 2/IE 2 ‘ or ( 12) Av = VT 1 N |+ 2 IR L -2 o 22 is obtained for the voltage difference AV=VBE-VBE’.
This voltage difference is sensed on both bit lines by means of a highresistivity 5 differential amplifier.
If the signal amplifier in the case of the current measurement lequation in ( 7)1 has a non-neglectable internal reistance or if the value of the input resistance of the differential amplifier in the case of the voltage measurement lequation ( 12)1 is inadequate, an operating mode results which lies between the two extremes 10 “constant current” and “constant voltage”.
For the storage cell embodying the invention a voltage difference of ac 2 a R 2 A Vz 26 m V.
1-2 a 2 is obtained in a practical example according to equation ( 12) with a R 2 ‘=a R 2 and a 2 a R 2 ‘a R 2 and a 2 = 0 3, and a 2 ‘= 0 2 this results in a voltage 15 difference of AV= 3 9 m W.
This value of AV is fully sufficient to be amplified with the aid of a tolerable number of technical means.
This write process is relatively simple As during reading, the word line potential is raised by about 0 5 V If, for example, the switching transistor Ti’ is to 20 be cut off, the potential on bit line B 1 is raised to an extent that no emitter current 1 E 2 ‘ and thus no base current IB 1 ‘ can flow into the switching transistor TI’.
Figs 3 and 4 show that the storage cell can be realized at very low space requirements In particular with modern isolation techniques (passive isolation by means of oxide, for example,) the storage cell density is considerably increased 25 over that of known storage cells, because only one metal line, namely the word line WL, is required to wire the cell in a storage matrix As a result of the reduced number of metal lines, the reliability is considerably increased, and the blocking zones employed prevent two adjacent storage cells of a bit line from being coupled.

Claims (8)

WHAT WE CLAIM IS: 30

1 An integrated semiconductor storage device consisting of a flip-flop with two cross-coupled, bipolar switching transistors and two load elements each connected by one of its two terminals to the collector of a respective one of the switching transistors, said storage device being controlled via a word line connected to the other terminal of both load elements and via one bit line each of a bit 35 line pair connected to the emitter of each switching transistor characterized in that the flip-flop consists of two IFL structures integrated in two separate isolation pockets of the semiconductor body and comprising in a known manner one inlector and one associated inverting transistor each, and that in each case the injector of one of the inverting transistors used as switching transistors 40 simultaneously forms the load element of the other switching transistor.

2 A device as claimed in claim 1, characterized in that each 12 L structure comprises as an inverting transistor one inversely operated, vertical transistor structure, and a zone arranged laterally to the base of said transistor structure and serving as an injection zone and an emitter zone of a complementary lateral 45 transistor, whose collector simultaneously forms the base and whose base simultaneously forms the emitter of the inverting transistor.

3 A device as claimed in claim 1, or 2, characterized in that the word line of a storage cell is connected to both injection zones, and that each bit line consists of a highly conductive, buried zone within the isolation pocket containing the emitter of 50 the associated switching transistor.

4 An integrated semiconductor data storage matrix consisting of storage devices each as claimed in any of claims 1 to 3, characterized in that the corresponding 12 L structures of all storage devices, which have one bit line pair in common, are strung together in two isolation pockets extending in line direction, 55 8 1,586,323 8 and that the injection zones of the storage cells strung together in column direction are connected by a common word line.
A storage matrix as claimed in claim 4, characterized in that the 12 L structures following each other in line direction are separated from each other by one blocking zone each

6 A storage matrix as claimed in claim 4, characterized in that two 12 L structures each adjoining each other in line direction are arranged mirror-inverted in relation to each other, and that only between the adjacent bases of the switching transistors blocking zones are arranged.

7 An integrated semiconductor storage device substantially as described with 10 reference to Fig 2 of the accompanying drawings.

8 An integrated semiconductor data storage matrix substantially as described with reference to Figs 3 A to 3 C or Fig 4 of the accompanying drawings.
F J HOBBS Chartered Patent Agent Agent for the Applicants.
Printed for Her Majesty’s Stationery Office, by the Courier Press, Leamington Spa, 1981 Published by The Patent Office, 25 Southampton Buildings, London, WC 2 A IAY, from which copies may be obtained.

GB20086/78A
1977-08-27
1978-05-17
Semiconductor data storage devices

Expired

GB1586323A
(en)

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DE2738678A

DE2738678C3
(en)

1977-08-27
1977-08-27

Monolithically integrated storage cell

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GB1586323A
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1981-03-18

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GB20086/78A
Expired

GB1586323A
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1977-08-27
1978-05-17
Semiconductor data storage devices

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US
(1)

US4158237A
(en)

DE
(1)

DE2738678C3
(en)

FR
(1)

FR2401489A1
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GB1586323A
(en)

Families Citing this family (14)

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Title

US4221977A
(en)

1978-12-11
1980-09-09
Motorola, Inc.
Static I2 L ram

DE2944141A1
(en)

1979-11-02
1981-05-14
Ibm Deutschland Gmbh, 7000 Stuttgart

MONOLITHICALLY INTEGRATED STORAGE ARRANGEMENT

JPS594787B2
(en)

1979-12-28
1984-01-31
インタ−ナショナルビジネスマシ−ンズコ−ポレ−ション

A memory device that has a low impedance sense amplifier and can be used as a read-only memory or as a read/write memory.

US4404662A
(en)

1981-07-06
1983-09-13
International Business Machines Corporation
Method and circuit for accessing an integrated semiconductor memory

US4555776A
(en)

1982-04-19
1985-11-26
International Business Machines Corporation
Voltage balancing circuit for memory systems

IT1212765B
(en)

1983-07-27
1989-11-30
Ates Componenti Elettron

RAM TYPE MEMORY CELL WITH ELECTRICALLY PROGRAMMABLE NON VOLATILE MEMORY ELEMENT.

JPS6048090A
(en)

1983-08-26
1985-03-15
伊勢電子工業株式会社
Fluorescent display unit

US4813017A
(en)

1985-10-28
1989-03-14
International Business Machines Corportion
Semiconductor memory device and array

US4992981A
(en)

1987-06-05
1991-02-12
International Business Machines Corporation
Double-ended memory cell array using interleaved bit lines and method of fabrication therefore

US5040145A
(en)

1990-04-06
1991-08-13
International Business Machines Corporation
Memory cell with active write load

US5020027A
(en)

1990-04-06
1991-05-28
International Business Machines Corporation
Memory cell with active write load

US5276638A
(en)

1991-07-31
1994-01-04
International Business Machines Corporation
Bipolar memory cell with isolated PNP load

US5297089A
(en)

1992-02-27
1994-03-22
International Business Machines Corporation
Balanced bit line pull up circuitry for random access memories

JP2002048098A
(en)

2000-08-02
2002-02-15
Mitsubishi Heavy Ind Ltd
Routing guide for bulk material

Family Cites Families (4)

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US3815106A
(en)

1972-05-11
1974-06-04
S Wiedmann
Flip-flop memory cell arrangement

DE1817498C3
(en)

1968-12-30
1979-11-22
Ibm Deutschland Gmbh, 7000 Stuttgart

Monolithically integrated storage cell

US4021786A
(en)

1975-10-30
1977-05-03
Fairchild Camera And Instrument Corporation
Memory cell circuit and semiconductor structure therefore

US4032902A
(en)

1975-10-30
1977-06-28
Fairchild Camera And Instrument Corporation
An improved semiconductor memory cell circuit and structure

1977

1977-08-27
DE
DE2738678A
patent/DE2738678C3/en
not_active
Expired

1978

1978-05-17
GB
GB20086/78A
patent/GB1586323A/en
not_active
Expired

1978-07-12
FR
FR7821335A
patent/FR2401489A1/en
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1978-07-13
US
US05/924,116
patent/US4158237A/en
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(en)

1979-03-23

DE2738678A1
(en)

1979-03-08

DE2738678B2
(en)

1981-06-19

US4158237A
(en)

1979-06-12

FR2401489B1
(en)

1982-02-05

DE2738678C3
(en)

1982-03-04

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