GB1588805A

GB1588805A – Distributed power system for a multiprocessor system
– Google Patents

GB1588805A – Distributed power system for a multiprocessor system
– Google Patents
Distributed power system for a multiprocessor system

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Publication number
GB1588805A

GB1588805A
GB3058/80A
GB305880A
GB1588805A
GB 1588805 A
GB1588805 A
GB 1588805A
GB 3058/80 A
GB3058/80 A
GB 3058/80A
GB 305880 A
GB305880 A
GB 305880A
GB 1588805 A
GB1588805 A
GB 1588805A
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GB
United Kingdom
Prior art keywords
power
device controller
supplies
bus
power supply
Prior art date
1976-09-07
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB3058/80A
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Tandem Computers Inc

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Tandem Computers Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1976-09-07
Filing date
1977-06-17
Publication date
1981-04-29

1977-06-17
Application filed by Tandem Computers Inc
filed
Critical
Tandem Computers Inc

1981-04-29
Publication of GB1588805A
publication
Critical
patent/GB1588805A/en

Status
Expired
legal-status
Critical
Current

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Classifications

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled

G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data

G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F11/00—Error detection; Error correction; Monitoring

G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance

G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes

G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9’s or 11’s

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F11/00—Error detection; Error correction; Monitoring

G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance

G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes

G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9’s or 11’s

G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9’s or 11’s in individual solid state devices

G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9’s or 11’s in individual solid state devices with specific ECC/EDC distribution

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F11/00—Error detection; Error correction; Monitoring

G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance

G06F11/16—Error detection or correction of the data by redundancy in hardware

G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant

G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F11/00—Error detection; Error correction; Monitoring

G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance

G06F11/16—Error detection or correction of the data by redundancy in hardware

G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

G06F11/2015—Redundant power supplies

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F11/00—Error detection; Error correction; Monitoring

G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance

G06F11/16—Error detection or correction of the data by redundancy in hardware

G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant

G06F11/2023—Failover techniques

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F11/00—Error detection; Error correction; Monitoring

G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance

G06F11/16—Error detection or correction of the data by redundancy in hardware

G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant

G06F11/2035—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant without idle spare hardware

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F11/00—Error detection; Error correction; Monitoring

G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance

G06F11/16—Error detection or correction of the data by redundancy in hardware

G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant

G06F11/2043—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share a common memory address space

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F11/00—Error detection; Error correction; Monitoring

G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance

G06F11/16—Error detection or correction of the data by redundancy in hardware

G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

G06F11/2097—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F12/00—Accessing, addressing or allocating within memory systems or architectures

G06F12/02—Addressing or allocation; Relocation

G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F12/00—Accessing, addressing or allocating within memory systems or architectures

G06F12/14—Protection against unauthorised use of memory or access to memory

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F12/00—Accessing, addressing or allocating within memory systems or architectures

G06F12/14—Protection against unauthorised use of memory or access to memory

G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

G06F13/10—Program control for peripheral devices

G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor

G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

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G06F13/14—Handling requests for interconnection or transfer

G06F13/20—Handling requests for interconnection or transfer for access to input/output bus

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

G06F13/14—Handling requests for interconnection or transfer

G06F13/20—Handling requests for interconnection or transfer for access to input/output bus

G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

G06F13/287—Multiplexed DMA

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

G06F13/14—Handling requests for interconnection or transfer

G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

G06F13/366—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

G06F13/38—Information transfer, e.g. on bus

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F15/00—Digital computers in general; Data processing equipment in general

G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F15/00—Digital computers in general; Data processing equipment in general

G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

G06F15/163—Interprocessor communication

G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F15/00—Digital computers in general; Data processing equipment in general

G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

G06F15/163—Interprocessor communication

G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled

G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Description

PATENT SPECIFICATION
( 21) Application No 305 ( 62) Divided out of No.
( 31) ( 33) ( 44) ( 51) 58/80 1588803 ( 22) Filed 17 June 1977 ( 11) ( 19) Convention Application No 721043 ( 32) Filed 7 Sept 1976 in United States of America (US) Complete Specification published 29 April 1981
INT CL 3 G 06 F 11/20 ( 52) Index at acceptance G 4 A 12 T ES ( 54) DISTRIBUTED POWER SYSTEM FOR A MULTIPROCESSOR SYSTEM ( 71) We, TANDEM COMPUTERS INCORPORATED, a Corporation of the State of California, United States of America, of 20605 Valley Green Drive, Cupertino, California 95014, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:-
The present invention relates to a distributed power system for a multiprocessor system of the kind in which separate processor modules are interconnected for parallel processing and relates particularly to a distributed power system for a multiprocessor system which can support high transaction rates to large on-line data bases and in which no single component failure can stop or contaminate the operation of the system.
There are many applications which require on-line processing of large volumes of data at high transaction rates For example, such processing is required in retail applications for automated point of sale, inventory and credit transactions and in financial institutions for automated funds transfer and credit transactions.
In computing applications of this kind it is important, and often critical, that the data processing not be interrupted A failure of an on-line computer system can shut down a portion of the related business and can cause considerable loss of data and money.
Thus, an on-line system of this kind must provide not only sufficient computing power to permit multiple computations to be done simultaneously, but it must also provide a mode of operation which permits data processing to be continued without interruption in the event some component of the system fails.
The system should operate either in a failsafe mode (in which no loss of throughput occurs as a result of failure) or in a fail-soft mode (in which some slowdown occurs but full processing capabilities are maintained) in the event of a failure.
Furthermore, the system should also operated in a way such that a failure of a single component cannot contaminate the operation of the system The system should provide fault-tolerant computing For faulttolerant computing all errors and failures in the system should either be corrected auto 55 matically, or if the failure or error cannot be corrected automatically, it should be detected, or if it cannot be detected, it should be contained and should not be permitted to contaminate the rest of the system 60 Since a single processor module can fail, it is obvious that a system which will operate without interruption in an on-line application must have more than one processor module 65 Systems which have more than one processor module can therefore meet one of the necessary conditions for non-interruptible operation However, the use of more than one processor module in a system does not by 70 itself provide all the sufficient conditions for maintaining the required processing capabilities in the event of component failure, as will become more apparent from the description to follow 75 Computing systems for on-line, high volume, transaction oriented, computing applications which must operate without interrupton therefore require multiprocessors as a starting point But the use of multiprocessors 80 does not guarantee that all of the sufficient conditions will be met, and fulfilling the additional sufficient conditions for on-line systems of this kind has presented a number of problems in the prior art 85
The prior art approach to uninterrupted data processing has proceeded generally along two lines either adapting two or more large, monolithic, general purpose computers for joint operation or intercon 90 necting a plurality of minicomputers to provide multiprocessing capabilities.
In the first case, adapting two large monolithic general purpose computers for joint operation, one conventional prior art ap 95 proach has been to have the two computers share a common memory Now in this type of multiprocessing system a failure in the shared memory can stop the entire system.
Shared memory also presents a number of 100 00 00 1588805 I,588,O 05 other problems including sequencing accesses to the common memory This system, while meeting some of’ the necessary conditions for uninterrupted processing, does not meet all of the sufficient conditions.
Furthermore, multiprocessing systems using large general purpose computers are quite expensive because each computer is constructed as a monolithic unit in which all components (including the packaging, the cooling system, etc) must be duplicated each time another processor is added to the system even though many of the duplicated components are not required.
The other prior art approach of using a plurality of minicomputers has (in common with the approach of using large general purpose computers) suffered from the drawback of having to adapt a communications link between computers that were never originally constructed to provide such a link.
The required links were, as a result, usually made through the input/output channel.
Connections through the input/output channel are necessarily slower than internal transfers within the processor itself, and such interprocessor links have therefore provided relatively slow interprocessor communication.
Furthermore, the interprocessor connections required special adapter cards that added substantially to the cost of the overall system and that introduced the possibility of single component failures which could stop the system Adding dual interprocessor links and adapter cards to avoid problems of critical single components failures increased the overall system cost even more substantially.
Providing dual links and adapter cards between all processors generally became very cumbersome and quite complex from the standpoint of operation.
Another problem of the prior art arose out of the way in which connections were made to peripheral devices.
If a number of peripheral devices are connected to a single input/output bus of one processor in a multiprocessor system and that processor fails, then the peripheral devices will be unavailable to the system even though the failed processor is linked through an interprocessor connection to another processor or processors in the system.
To avoid this problem, the prior art has provided an input/output bus switch for interconnecting input/output busses for continued access to peripheral devices when a processor associated with the peripheral devices on a particular input/output bus fails.
The bus switches have been expensive and also have presented the possibility of single component failure which could down a substantial part of the overall system.
Providing software for the prior art multiprocessor systems has also been a major problem.
Operating systems software for such multiprocessing systems has tended to be nonexis 70 tent Where software had been developed for such multiprocessor systems, it quite often was restricted to a small number of processors and was not adapted for the inclusion of additional processors In many cases it was 75 necessary either to modify the operating system or to put some of the operating system functions into the user’s own program -an expensive time-consuming operation.
The prior art lacked a satisfactory stan 80 dard operating system for linking processors.
It also did not provide an operating system for automatically accommodating additional processors in a multiprocessing system constructed to accommodate the modular addi 85 tion of processors as increased computering power was required.
According to the present invention there is provided a distributed power system for multiprocessor system of the kind in which 90 separate processor modules each have a central processing unit are interconnected for parallel processing, said distributed power system comprising: a plurality of separate processor modules; a plurality of device 95 controllers for controlling the transfer of data between a plurality of processor modules and a plurality of peripheral devices; multiple ports in each device controller and multiple input/output buses for connecting each de 100 vice controller for access by different processor modules; and, distributed power supply means for insuring non-stop operation of the remainder of the multiprocessor system in the event of a failure of a single power supply 105 to a part of the multiprocessor system, said distributed supply means including a separate power supply for each processor module and connecting means for connecting a plurality of the separate power supplies to 110 each device controller and effective to supply power to each device controller from the remaining separate power supplies in the event of the failure of one of the power supplies connected to any device controller 115 Preferably in a multiprocessor system incorporating the present invention every major component is modularized so that any major component can be removed or replaced without stopping the system In addi 120 tion, the system can be expanded in place (either horizontally by the addition of standard processor modules or in most cases vertically by the addition of peripheral devices) without system interruption or modifi 125 cation to hardware or software.
Preferably the distributed power system includes power-on circuit means for establishing that power levels are within certain established limits and which are effective to 130 I’ 3 1,588,8053 function in four states-power-off, power going from off to on, power-on and power going from on to off.
In one preferred embodiment of the present invention all the processor modules may be connected by an interprocessor bus and preferably a power-on circuit means is located in each central processing unit and in each device controller.
The power-on circuit means may control interface circuits which drive all the interprocessor and input-output buses in the multiprocessor system and may present a signal in the event of a variation of logic power which signal establishes the level of power applied to the related processor module or device controller The signal output may be used to directly disable appropriate interface signals of the processor module or device controller in which the power-on circuit is located, if the power-on is not within the certain established limits which will ensure correct logic operation.
A second interprocessor bus may interconnect all of the processor modules and the power-on circuit means may, for example, coact with a multi-path system provided, in a preferred embodiment, by the interprocessor buses and the multiple port device controllers and associated input/output buses to give a mode of operation in which a failing power supply for one processor or a multiple port device controller does not affect any other processor module or dual port controller on any of those paths.
Desirably the connecting means includes a diode switch arrangement which supplies power to the device controller from a plurality of power supplies when those associated power supplies are operative and which supplies power from the remaining power supplies in the event of a failure of one of the associated power supplies and in a changeover which is without interruption or pulsation so that ‘operation of the device controller is never interrupted.
Preferably the separate power supplies are interconnected by a power bus having a plurality of lines with selected ones of the lines connected to selected ones of the power supplies and including taps on the power bus adjacent each device controller for permitting the device controller to be connected to any selected plurality of the power supplies by easy connection to related taps in the power.
In a preferred embodiment of the present invention any processor module or device controller can be powered down so that online maintenance can be performed in a powered off condition while the rest of the multiprocessor system incorporating the present invention is on-line and functional.
An embodiment of the present invention will now be described by way of example, with reference to the accompanying drawings in which:FIGURE 1 is an isometric, block diagram view of a multiprocessor system incorporating one embodiment of the present inven 70 tion Figure 1 shows several processor modules connected by two interprocessor buses (an X and a Y bus) with each bus controlled by a bus controller Figure 1 also shows several dual-port device controllers with each 75 device controller connected to the input/output (I/O) buses of two processor modules.
FIGURE 2 is a schematic view showing the details of the power on circuit (PON).
FIGURE 3 is a block diagram of a power 80 distribution system Figure 3 shows how a plurality of independent and separate power supplies are distributed and associated with the dual port device controllers for ensuring that each device controller has both a pri 85 mary and an alternate power supply.
FIGURE 4 is an enlarged, detailed view of the switching arrangement for switching between a primary power supply and an alternative supply for a device controller 90 The switching structure shown in Figure 4 permits both automatic switching in the event of a failure of the primary power supply and manual switching in three different modes off, auto and alternate 95 FIGURE 5 is a block diagram showing details of one of the separate and independent power supplies 303 illustrated in Figure 3.
FIGURE 6 is a block diagram view 100 showing details of the vertical buses and the horizontal buses for supplying power from the separate power supplies shown in Figure 3 to the individual device controllers The particular bus arrangement shown in Figure 105 6 permits easy selection of any two of the individual power supplies as the primary and the alternate power supply for a particular device controller.
Fig I is an isometric diagrammatic view of 110 a part of a multiprocessor system incorporating one embodiment of the present invention In Figure 1 the multiprocessor system is indicated generally by the reference numeral 31 115 The multiprocessor system 31 includes individual processor modules 33 Each processor module 33 comprises a central processing unit 105, a memory 107, an input/output channel 109 and an interprocessor control 55 120 The individual processor modules are interconnected by interprocessor buses 35 for interprocessor communications.
In a specific embodiment of the multiprocessor system 31, up to sixteen processor 125 modules 33 are interconnected by two interprocessor buses 35 (indicated as the X bus and the Y bus in Figure 1).
Each interprocessor bus has a bus controller 37 associated with that bus 130 1,588,805 The microprocessor 113 and microprogram 115 of the central processing unit 105 and an input/output control table 140 in the main memory 107 of each processor module 33 are operatively associated with the I/O channel 109.
The multiprocessor system includes a power distribution system 301 which distributes power from separate power supplies to the processor modules 33 and to the device controllers 41 in a way that permits on-line maintenance and also provides redundancy of power on each device controller.
As illustrated in Figure 3, the power distribution system of the present invention includes separate and independent power supplies 303.
A separate power supply 303 is provided for each processor module 33, and a bus 305 supplies the power from the power supply 303 to the central processing unit 105 and memory 105 of a related processor module 33.
The bus controllers 37, interprocessor buses 35 and interprocessor controls 55 (Figure I), together with associated microprocessors 113, microprograms 115 and bus receive tables provide an interprocessor bus system.
The multiprocessor system 31 has an input/output (I/O) system for transferring data between the processor modules 33 and peripheral devices, such as the discs 45, terminals 47, magnetic tape drives 49, card readers 51, and line printers 53 shown in Figure 1.
The I/O system includes one I/O bus 39 associated with each I/O channel 109 of a processor module and one or more multiport device controllers 41 may be connected to each I/O bus 39.
In the specific embodiment illustrated, each device controller 41 has two ports 43 for connection to two different processor modules 33 so that each device controller is connected for access by two processor modules.
The I/O system includes a microprocessor 119 and a microprogram 121 in the I/O channel 109 which are dedicated to input/ output transfers.
As also illustrated in Figure 3, each device controller 41 is connected for supply of power from two separate power supplies 303 through an automatic switch 311 If one power supply 303 for a particular device controller 41 fails, that device controller is supplied with power from the other power supply 303; and the changeover is accomplished smoothly and without any interruption or pulsation in the power supplied to the device controller.
The power distribution system coacts with the dual port system of the device controller to provide nonstop operation and access to the peripheral devices in the event of a failure of either a single port 43 or a single power supply 303.
The multiprocessor system includes a power on (PON) circuit 182 (the details of 70 which are shown in Figure 2) in several components of the system to establish that the power to that particular component is within certain acceptable limits.
For example, the PON circuit 182 is 75 located in each CPU 105, in each device controller 41, and in each bus controller 37.
The purpose of the PON circuit is to present a signal establishing the level of power applied to that particular component; 80 and if the power is not within certain predetermined acceptable limits, then the signal output is used to directly disable the appropriate bus signal of the component in which the PON is located 85 The power-on circuit functions in four states-power off; power going from off to on; power on; and power going from on to off.
The power-on circuit initializes all of the 90 logic states of the system as the power is brought up; and in the present invention, the power-on circuit provides an additional and very important function of providing for a fail-safe system with on line maintenance To 95 do this, the power-on circuit in the present invention is used in a unique way to control the interface circuits which drive all of the intercommunication buses in the system.
The construction and operation of the 100 power distribution system according to the present invention are illustrated in Figs 3-6 and are described in detail below under the subtitle Power Distribution System.
The multiprocessor system includes a 105 memory system in which the physical memory is divided into four logical address areas-user data, system data, user code and system code.
The memory system includes a map and 110 control logic for translating all logical addresses to physical addresses and for indicating pages absent from primary storage bit present in secondary storage as required to implement a virtual memory system in which 115 the physical page addresses are invisible to users.
The memory system incorporates a dual port access to the memory by the central processing unit 105 and the I/O channel 109 120 The I/O channel 109 can therefore access the memory 107 directly (without having to go through the central processing unit 105) for data transfers to and from a device controller 41 125 An error detection system is incorporated in the memory system for correcting all single bit and detecting all double bit errors when semiconductor memory is used in the memory system This error detection system 130 1,588,805 utilizes a 16 bit data field and a 6 bit check field and includes a data bit complementer for correcting single bit errors.
Before going into the detailed description of the distributed power system, it should be noted that certain terminology will have the following meanings as used in this application.
The term “software” will refer to an operating system or a user program instructions; the term “firmware” will refer to a microprogram in read only memory; and the term “hardware” will refer to actual electronic logic and data storage.
The operating system is a master control program executing in each processor module which has primary control of the allocation of all system resources accessible to that processor module The operating system provides a scheduling function and determines what process has use of that processor module The operating system also allocates the use of primary memory (memory management), and it operates the file system for secondary memory management The operating system also manages the message system This provides a facility for information transfer over the interprocessor bus.
The operating system arrangement parallels the modular arrangement of the multiprocessor system components described above, in that there are no “global” components.
At the lowest level of the software system, two fundamental entities are implemented-processes and messages.
A process is the fundamental entity of control within a system.
Each process consists of a private data space and register values, and a possibly shared code set A process may also access a common data space.
A number of processes coexist in a processor module 33.
The processes may be user written programs, or the processes may have dedicated functions, such as, for example, control of an I/O device or the creation and deletion of other processes.
A process may request services from another process, and this other process may be located in the same processor module 33 as a process making the request, or the other process may be located in some other processor module 33.
The processes work in an asynchronous manner, and the processes therefore need a method of communication that will allow a request for services to be queued without “races” (a condition in which the outcome depends upon the sequence of which process started first)-thus the need for “messages” (an orderly system of interprocessor module communication described in more detail below).
Also, all interprocessor module communication should appear the same to the processes, regardless of whether the processes are in the same or in different processor modules 70 As will become more clear from the description to follow, the software structure parallels the hardware; and different processes can be considered equivalent to certain components of the hardware in arrangement 75 and function.
For example, just as the I/O channel 109 communicates over the I/O bus 39 to the device controller 41, a user process can make a request (using the message system) to the 80 process associated with that device controller 41; and then the device process returns status back similar to the way the device controller 41 returns information back to the I/O channel 109 over the I/O bus 39 85 The other fundamental entity of the software system, the message, consists of a request for service as well as any required data When the request is completed, any required values will be returned to the 90 requesting process.
When a message is to be sent between processes in two different processor modules 33, the interprocessor buses 35 are used.
However, as noted above, all communication 95 between processes appears the same to the processes, regardless of whether they are in the same or in different processor modules 33.
This software organization provides a 100 number of benefits.
This method of structuring the software also provides for significantly more reliable software By being able to compartmentalize the software structure, smaller module sizes 105 can be obtained, and the interfaces between modules are well defined.
The system is also more maintainable because of the compartmentalization of function 110 The well defined modules and the well defined interfaces in the software system also provide advantages in being able to make it easily expandible-as in the case of adding additional processor modules 33 or device 115 controllers 41 to the multiprocessor system.
Furthermore, there is a benefit to the user of the multiprocessor system and software system in that the user, writing his program, need not be aware of either the actual 120 machine configuration or the physical location of other processes.
Just as the hardware provides multiple functionally equivalent modules with redundant interconnects, so does the software 125 For example, messages going between processes in different processor modules 33 may use either interprocessor bus 35 Also, device controllers 41 may be operated by processes in either of the processor modules 130 1,588,805 33 connected to the device controller 41.
POWER DISTRIBUTION SYSTEM:
The multiprocessor system shown in Figure I and discussed above incorporates an embodiment of the power distribution system of the present invention.
In many prior art systems it was necessary to stop the processor system in order to perform required maintenance on a component of the system Also, in many prior art systems, a failure in the power supply could stop the entire processor system.
The power distribution system embodying the present invention incorporates a plurality of separate and independent power supplies and distributes the power from the power supplies to the processor modules and to the device controllers in a way that permits online maintenance and also provides redundancy of power on each device controller.
In this regard “on-line” is used in the sense that when a part of the system is on-line, that part of the system is not only powered on, but it is also functioning with the system to perform useful work.
The term “on-line maintenance” therefore means maintaining a part of the system (including periodic preventative maintenance or repair work) while the remainder of the system is on-line as defined above.
In the present invention any processor module or device controller can be powered down so that on-line maintenance can be performed in a power off condition on that processor module or a device controller while the rest of the multiprocessor system is online and functional The on-line maintenance can be performed while fully meeting Underwriters Laboratory safety requirements.
Also, in the power distribution system of the present invention each device controller is connected for supply of power from two separate power supplies and by a diode switching arrangement that permits the device controller to be supplied with power from both power supplies when both power supplies are operative and to be supplied with power from either one of the power supplies in the event the other power supply fails; and the changeover in the event of failure of one of the power supplies is accomplished smoothly and without any interruption or pulsation in the power supply so that an interrupt to a device controller is never required in the event of a failure of one of its associated power supplies.
A power distribution system for insuring both a primary supply and an alternate power supply for each individual dual port device controller 41 is illustrated in Fig 30.
The power distribution system is indicated generally by the reference numeral 301 in Figure 3.
The power distribution system 301 insures that each dual port device controller 41 has both a primary power supply and an alternate power supply Because each device controller does have two separate and inde-pendent sources of power supply, a failure of 70 the primary power supply for a particular device controller does not render that device controller (and all of the devices associated with that controller) inoperative Instead a switching arrangement provides for an auto 75 matic switchover to the alternate power supply so that the device controller can continue in operation The power distribution system thus coacts with the dual port system of the device controller to provide 80 non-stop operation and access to the devices in the event of a failure of either a single port or a single power supply.
The power distribution system 301 shown in Figure 3 provides the further advantage 85 that each processor module 33 and associated CPU 105 and memory 107 has a separate and independent power supply which is dedicated to that processor module With this arrangement, a failure of any one power 90 supply or a manual disconnection of any one power supply for repair or servicing of the power supply or associated processor module is therefore limited in effect to only one particular processor module and cannot af 95 fect the operation of any of the other processor modules in the multiprocessor system.
The power distribution system 301 shown in Figure 3 thus works in combination with 100 the individual processor modules and the dual port device controllers to insure that a failure or disconnection of any one power supply does not shut down the overall system or make any of the devices ineffective 105 The power distribution system 301 includes a plurality of separate and independent power supplies 303, and each power supply 303 has a line 305 (actually a multiline bus 305 as shown in Figure 6) which is 110 dedicated to supplying power to the CPU and memory of a particular, related processor module.
Each device controller 41 is associated with two of the power supplies 303 through a 115 primary line 307 and an alternate line 309 and an automatic switch 311.
A manually operated switch 313 is also associated with each device controller 41 between the device controller and the pri 120 mary line 307 and the alternate line 309.
The switches 311 and 313 are shown in more detail in Figure 4.
Figure 5 shows details of the component construction of a power supply 303 125 As shown in Figure 5, each power supply 303 has an input connector 315 for taking power from the mains The input 315 is connected to an AC to DC converter 317, and the output of the AC to DC converter 130 1,588,805 provides, on a line 319, a five volt interruptable power supply (IPS) This five volt interruptable power supply is supplied to the CPU 105, the memory 107 and the device controller 41 See also Figure 6.
The AC to DC converter 317 also provides on a second output line 321 a sixty volt DC output which is supplied to a DC to DC converter 323 See Figure 5.
The DC to DC converter in turn provides a five volt output on a line 325 and a twelve volt output on a line 327.
The outputs from the lines 325 and 327 are, in the system of the present invention, uninterruptable power supply (UPS) outputs in that these power supply outputs are connected to the CPU and memory when semiconductor memory is used The power supply to a semiconductor memory must not be interrupted because a loss of power to a semiconductor memory will cause loss of all data stored in the memory.
The five volt interruptable power supply on line 319 is considered an interruptable power supply because this power is supplied to parts of the multiprocessing system in which an interruption of power can be accepted Thus, the five volts interruptable power is supplied to parts of the CPU other than semiconductor memory and to only those parts of the memory which are core memory (and for which a loss of power does not cause a loss of memory) and to the device controller (which as will be described in more detail below) is supplied with an alternate source of power in the event of a failure of the primary power supply.
Since the power supply on lines 325 and 327 must be an uninterruptable power supply, the present invention provides a battery back-up for the input to the DC to DC converter 323 This battery back-up includes a battery and charger module 329 The module 329 is connected to the DC to DC converter 323 by a line 331 and a diode 333.
In a particular embodiment of the present invention the battery 323 supplies power at 48 volts to the converter 323, which is within the input range of the converter 323.
The diode 333 insures that power from the battery is supplied to the converter 323 if the voltage on the line 321 drops below 48 volts.
The diode 333 also stops the flow of current from the battery and the line 333 when the output of the AC to DC converter on line 321 exceeds 48 volts.
Each power supply 303 also includes a power warning circuitry 335 for detecting a condition in the AC power input on line 315 that would result in insufficient power out on the output lines 319, 325 and 327 The power warning circuit 335 transmits a power failure warning signal on a line 337 to the related CPU 105.
Because of the capacity storage in the power supply 303, there is enough time between the power warning signal and the loss of the five volts interruptable power on line 319 for the CPU to save its state before the power is lost 70 However, the uninterruptable power supply on lines 325 and 327 must not be interrupted, even for an instant of time; and the battery back-up provided by the arrangement shown in Figure 5 insures that there is 75 no interruption in the power supply on lines 325 and 327 in the event of a power failure in the input line 315.
One particular power supply 303 itself can fail for some reason with the other power 80 supplies 303 still operating In that event, the power distribution system 301 of the present invention limits the effect of the failure of the power supply 303 to the loss of one particular, associated CPU and memory; and the 85 automatic switch 311 provides for an automatic switchover from the failed power supply to the alternate power supply to keep the associated device controller 41 in operation The device controller 41 which had 90 been connected to the failed power supply therefore continues in operative association with the other processor modules and components of the multiprocessor system, because the required power is automatically 95 switched in from the alternate power supply.
As best illustrated in Figure 4, each automatic switch 311 includes two diodes-a diode 341 associated with the primary power line 307 and a diode 343 associated with the 100 alternate power line 309.
The function of the diodes 341 and 343 is to permit power to be supplied to a device controller 41 from either the primary power line 307 and a related power supply 303 or 105 the alternate power line and its related power supply 303 while keeping the supplies isolated This prevents a failed power supply from causing its associated alternate or primary from failing 110 In normal operation each diode permits a certain amount of current to flow through the diode so that the power to each device controller 41 is actually being supplied by both the primary and alternate power sup 115 plies for that device controller.
In the event that one of the power supplies fails, the full power is supplied by the other power supply, and this transition occurs without any loss of power at all 120 Since there is a small voltage drop across the diodes 341 and 343, the voltage on the lines 307 and 309 must be enough higher than five volts to accomodate the voltage drop across the diodes 341 and 343 and still 125 supply exactly five volts to the device controller 41 The lines 305 are in parallel with the lines 307 and 309, and the power actually received at the CPU in memory must also be five volts; so balancing diodes 339 are located 130 1,588,805 in the lines 305 to insure that the voltage after the diodes 339 as supplied to each CPU is exactly five volts.
The manual switch 313 permits a device controller 41 to be disconnected from both the primary and the alternate power sources when the device controller needs to be disconnected for removal and service.
Details of the construction of the switch 313 are shown in Figure 4 As shown in Figure 4, the switch 313 includes a manual switch 345, a transistor 347, a capacitor 348 and a resistor 350 and a resistor 352.
The manual switch 345 is closed to turn on the transistor 347 which then supplies power to the device controller 41.
It is important that both the turn on and the turn off of power to the device controller 41 be accomplished in a smooth way and without fluctuations which could trigger the PON circuit 182 more than once The feedback capacitor 348 acts in conjunction with the resistor 352 to cause the required smooth ramp build-up of power when the switch 345 is closed to turn the transistor 347 on.
When the transistor 347 is turned off by opening the switch 345, the feedback capacitor 348 acts in conjunction with resistor 350 to provide a smooth fall off of power.
In a preferred embodiment of the invention all of diodes 341, 343 and 339 are Schottky diodes which have a very low forward voltage drop, and this reduces power dissipation.
Each device controller 41 has a power on circuit (PON) 182 for detecting when the five volt power is below specifications The PON circuit 182 is shown in more detail in Figure 2 and resets the device controller 41 to lock everything off of the device controller and holds the device controller itself in a state that is known when the power is turned off by the switch 313 The PON circuit 182 also releases the device controller and returns it to operation after the power is turned on by switch 313 and five volt power supply at the proper specification is supplied to the device controller 41.
The power on circuit 182 acts in association with transceivers to control the behavior of the transceivers as the device controller 41 is powered up or powered down, in a way which prevents erroneous signals from being placed on the I/O bus while power is going up or down This feature is particularly significant from the standpoint of on line maintenance.
Each transceiver comprises a receiver 198 and a transmitter 200.
The transmitter is enabled by an enable line 202.
There are several terms which are on the enable line 202 These include the select bit 173, a required input function on the T bus, and a signal from the PON circuit 182.
The signal from the PON circuit, in a particular embodiment of the present invention, is connected in a “wire or” connection to the output of the gate which combines the other terms so that the output of the PON 70 circuit overrides the other terms by pulling down the enable line 202 This insures that the transmitter 200 (in one specific embodiment, an 8 T 26 A or 7438) is placed in a high impedence state until the PON circuit detects 75 that the power is at a sufficient level that the integrated circuits will operate correctly The PON circuit output stage is designed to take advantage of a property of the specific transceiver integrated circuit used On this 80 particular type IC if the driver enable line 202 is held below two diode drops above ground potential, the transmitter output transistors are forced into the off state regardless of the level of power applied to the 85 integrated circuit This insures that the driver cannot drive the bus.
This particular conbination of features provides a mode of operation wherein the output of the integrated circuit is controlled 90 as power comes up or goes down, whereas normally the output of an integrated circuit is undefined when power drops below a certain level.
This same circuit is used on the X and Y 95 buses of the interprocessor bus system to control the transceivers and control signals generated by the interprocessor control 55.
As indicated in Figure 3, each central processor unit (CPU) 105 has a PON circuit 182 100 which is similar to the PON circuit 182 in the device controller The PON circuits therefore control the transmitters for all of the device controllers 41 and all of the interprocessor controls 55 105 Details of the power-on (PON) circuit are shown in Figure 2 where the circuit is indicated generally by the reference numeral 182.
The purpose of the PON circuit is to sense 110 two different voltage levels of the five volt supply.
If power is failing, the circuit senses the point at which the power drops below a certain level which renders the logic in the 115 device controller or CPU an indeterminate state or condition At this point the circuit supplies signals to protect the system against the logic which subsequently goes into an undefinable state 120 The second voltage level which the PON circuit will sense is a value that is perceived when power is coming up This second level at which power is sensed will be greater than the first level by roughly 100 millivolts to 125 provide hysteresis for the system to eliminate any conditions of oscillation.
The PON circuit stays in a stable condition after it senses one of the voltage conditions until it senses the other voltage condition, at 130 1,588,805 which point it changes state The state at which the PON circuit is in at any particular time determines the voltage level at which the transition to the other state will be made.
The power on circuit 182 thus presents a signal establishing an indication that the power is within predetermined, acceptable operating limits for the device controller 41.
If the power is not within those predetermined, acceptable operating limits, the signal output of the power-on circuit 182 is used to directly disable the appropriate bus signals of the device controller 41.
The output of the PON circuit 182 is a binary output If the output is a one, the power is within satisfactory limits If the output of the PON circuit is a zero, this is an indication that the power is below the acceptible limit.
The power-on circuit 182 shown in Figure 3 and to be described in detail below is used with the device controller 41 and has seven output driver stages which are used in the application of the power-on circuit 182 to the device controller 41 However, the same power-on circuit 182 is also used with the CPU 105 and the bus controller 37, but in those applications the power-on circuit will have a lesser number of output driver stages.
As illustrated in Figure 2, the PON circuit 182 comprises a current source 184 and a differential amplifier 186.
The differential amplifier 186 has, as one input, a temperature compensated reference voltage input on a line 188 and has a second input on a line 190 which is an indication of the voltage that is to be sensed by the poweron circuit.
The reference voltage on line 188 is established by a zener diode 192.
The differential amplifier 186 comprises a matched pair of transistors 194 and 196.
The voltage applied on the line 190 is determined by resistors 198, 200 and 202.
The resistors 198, 200 and 202 are metal film resistors which provide a high degree of temperature stability in the PON circuit.
The outputs on lines 204 and 206 of the differential amplifier 186 are applied to a three transistor array (the transistors 208, 210 and 212), and this three transistor array in turn controls the main output control transistor 214.
The main output control transistor 214 drives all output drivers that are attached.
For example, in the application of the PON circuit 182 for the device controller 41 (as illustrated in Figure 2), the main output transistor 214 drives output stages 216 through 228 The output stage 216 is used to clear the logic, the output stages 218, 220 and 222 are used in combination with the interface devices of one port 43 of the device controller 41, and the output stages 224, 226 and 228 are used in combination with the interface device of the other port 43 of the device controller 41.
Finally, the PON circuit 182 includes a hysteresis control 230 The hysteresis control 230 includes resistors 232, 234 and a transis 70 tor 236.
In operation, assuming that operation is started from a power off state to a power on condition, the power is applied through the current source 182 to the differential ampli 75 fier 186 and to the main output control transistor 214 At this time the voltage on the line 190 is less than the voltage on the line 188 so the differential amplifier 186 holds the output of the main output control transistor 80 214 in the off state This, in turn, will force the output stages 216 through 228 on.
This asserts the output of the PON circuit 182 in the zero state, the state indicating that power is not within acceptable limits 85 As voltage rises, the input voltage on line will increase until it equals the reference voltage on line 188 At this point the differential amplifier 186 drives the main output control transistor 214, turning it on This 90 removes the base drive from the output stages 216 through 228, forcing these output stages off The output of the PON circuit 182 is then a one, indicating that the power is within acceptable limits 95 At this point the hysteresis control circuit 230 comes into play While power was coming on, the transistor 236 of the hysteresis control circuit 230 was on When the transistor 236 is on, the resistance value of the 100 resistor 202 appears to be less than the resistance value of this resistor 202 is when the transistor 236 is off.
The point at which the main output control transistor 214 turns on is the point at 105 which the hysteresis transistor 236 turns off.
Turning off the hysteresis transistor 236 causes a slight voltage jump in the line 190 which further latches the differential amplifier 186 into the condition where the differen 110 tial amplifier 186 sustains the main output transistor 214 in the on state.
The state of the PON circuit will remain stable in this condition with the main output control transistor 214 on and the output 115 drivers 216 through 228 off until the plus five volts drops below a lower threshold point, as determined by the voltage applied on the line 190.
As the voltage on the line 190 decreases 120 below the reference voltage on the line 188, (because the five volts supply is going down in a power failure condition), then the differential amplifier 186 turns off the main output control transistor 214 This, in turn, 125 turns on the output driver stages 216 through 228.
Since the hysteresis transistor 236 was off as power dropped, the voltage applied to the input of the PON circuit 182 must drop 130 1,588,805 somewhat farther than the point at which the PON circuit 182 sensed that power was within the acceptable limits during the power-u Lp phase of operation.
This differential or hysteresis is used to inhibit any noise on the five volt power supply from causing any oscillation in the circuit that would erroneously indicate that power is failing.
The PON circuit 182 shown in Figure 2 provides very accurate sensing of the two voltages used by the PON circuit to determine its state (whether a one or a zero output of the PON circuit).
In order to sense these two voltages very accurately the PON circuit must have the capability of compensating for initial tolerances of the different components and also the capability to compensate for changes in temperature during operation In the PON circuit 182, the zener diode 192 is the only critical part that must be compensated for because of its initial tolerance, and this compensation is provided by selecting the resistor 198.
Temperature compensation is achieved because the zener diode 192 is an active zener diode and is not a passive zener diode.
Effective temperature compensation is also achieved because the two transistors in the differential amplifier 186 are a matched pair of transistors and the resistors 198, 200 and 202 are metal film resistors.
With reference to Figure 6, the power from each power supply 303 is transmitted to a related CPU by the vertical bus 305, and each vertical bus 305 is a laminated bus bar which has five layers of electrical conductors.
As indicated by the legends in Figure 6, each vertical bus 305 has two different conductors connected to ground.
One conductor provides the ground for both the five volt interruptable power supply (IPS) and the five volt uninterruptable power supply (UPS).
A separate conductor provides a ground for the memory voltage This separate ground for the memory voltage insures that the relatively large fluctuations in current to the memory will not have any effect on either the five volt IPS or the five volt UPS supplied to the CPU.
The horizontal bus 305, 307 includes the primary and alternate power supply lines 307 and 309 (as indicated by the reference numerals in Fig 30) In a particular embodiment of the present invention the bus 305, 307 is actually a nine layer laminated bus which has a single ground and eight voltage layers (VI through V 8 as indicated by the legends and notations in Figure 6).
Each voltage layer is connected to the five volt interruptable output of a different power supply 303 Thus, the layer Vl is connected at 351 to the five volt IPS power for the power supply 303 and related processor module farthest to the left as viewed in Figure 6, and the layer V 2 is connected at 353 to the five volt IPS power supply 303 for the processor module at the center as viewed 70 in Figure 6, and so on.
Since there are eight layers (VI through V 8) and a common ground available to each device controller in the horizontal bus, upstanding vertical taps 355 to these eight 75 layers at spaced intervals along the horizontal bus permit each device controller 41 to be associated with any two of the power supplies 303 merely by connecting the primary line 307 and the alternate line 309 to a 80 particular set of taps By way of example, the device controller 41 on the lefthand side of Fig 33 is shown connected to the taps VI and V 2 and the device controller 41 on the righthand side of Figure 6 is shown con 85 nected to the taps V 2 and V 3.
Thus, any device controller 41 can be connected to any two of the power supplies 303 with any one of the power supplies serving as the primary power supply and any 90 one of the other power supplies serving as the alternate power supply.
The power distribution system of the present invention thus provides a number of important benefits 95 The power distribution system permits on line maintenance to be performed because one processor module or device controller can be powered down while the rest of the multiprocessor system is on line and func 100 tional.
The power distribution system fully meets all Underwriter Laboratory safety requirements for doing on line maintenance of a powered down component while the rest of 105 the multiprocessor system is on line and in operation.
Each device controller is associated with two separate power supplies so that a failure in one of the power supplies does not cause 110 the device controller to stop operation Instead, the electronic switch arrangement of the present invention provides such a smooth transition of power from the two power supplies to only one of the power supplies 115 that the device controller is maintained in continuous operation without an interrupt.
Reference is directed to our co-pending Application No 25490/77 (Serial No.
1,588,803) from which the present Applica 120 tion is divided and to Applications Nos.
3057/80 (Serial No 1,588,804), 3072/80 (Serial No 1,588,806) and 3073/80 (Serial No 1,588,807).

Claims (9)

WHAT WE CLAIM IS:-

1 A distributed power system for multiprocessor system of the kind in which separate processor modules each having a central processing unit are interconnected for paral 130 lo 1,588,805 lel processing, said distributed power system comprising: a plurality of separate processor modules; a plurality of device controllers for controlling the transfer of data between a plurality of processor modules and a plurality of peripheral devices; multiple ports in each device controller and multiple input/ output buses for connecting each device controller for access by different processor modules; and distributed power supply means for insuring non-stop operation of the remainder of the multiprocessor system in the event of a failure of a single power supply to a part of the multiprocessor system, said distributed supply means including a separate power supply for each processor module and connecting means for connecting a plurality of the separate power supplies to each device controller and effective to supply power to each device controller from the remaining separate power supplies in the event of the failure of one of the power supplies connected to any device controller.

2 A system according to claim 1, including power-on circuit means for establishing that power levels are within certain established limits and effective to function in four states-power-off, power going from off to on, power-on and power going from on to off.

3 A system according to claim 2, wherein an interprocessor bus interconnects all of the processor modules and wherein a power-on circuit means is located in each central processing unit, and in each device controller.

4 A system according to claim 3 wherein the power-on circuit means controls interface circuits which drive all of the interprocessor and input/output buses in the multiprocessor syste.

A system according to claim 2, 3 or 4 wherein the power-on circuit means presents a signal in the event of a variation of logic power which signal establishes the level of power applied to the related processor module or the device controller and wherein the signal output is used to directly disable appropriate interface signals of the processor module or device controller in which the power-on circuit is located if the power-on is not within the certain established limits which will ensure correct logic operation.

6 A system according to claim 3, 4 or 5, including a second interprocessor bus interconnecting all of the processor modules and wherein the power-on circuit means coacts with a multi-path system provided by the interprocessor buses and the multiple port device controllers and associated input/output buses to give a mode of operation in which a failing power supply for one processor or a multiple port device controller does not affect any other processor module or dual port controller on any of those paths.

7 A system according to any preceding claim, where the connecting means includes a diode switch arrangement which supplies power to the device controller from a plurality of power supplies when those associated 70 power supplies are operative and when supplies power from the remaining power supplies in the event of a failure of one of the associated power supplies and in a changeover which is without interruption or pulsa 75 tion so that operation of the device controller is never interrupted.

8 A system according to any preceding claim, wherein the separate power supplies are interconnected by a power bus having a 80 plurality of lines with selected ones of the lines connected to selected ones of the power supplies and including taps on the power bus adjacent each device controller for permitting the device controller to be connected to 85 any selected plurality of the power supplies by easy connection to related taps in the power bus.

9 A system according to any preceding claim, wherein each device controller is 90 associated with two separate power supplies.
A distributed power system according to claim 1 substantially as hereinbefore described with reference to, and as shown in the accompanying drawings 95 FORRESTER, KETLEY & CO, Chartered Patent Agents, Forrester House, 52 Bounds Green Road, London N 1 2 EY, also at Rutland House, 148 Edmund St, Birmingham B 3 2 LD, and Scottish Provident Building, 29 St Vincent Place, Glasgow G I 2 DT.
Agents for the Applicants.
Printed for Hcr Majesty’s Stationery Office by Burgess & Son (Abingdon) Ltd -1981 Published at The Patent Office.
Southampton Buildings London, WC 2 A l AY, from which copies may be obtained.
1 1

GB3058/80A
1976-09-07
1977-06-17
Distributed power system for a multiprocessor system

Expired

GB1588805A
(en)

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US05/721,043

US4228496A
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1976-09-07
1976-09-07
Multiprocessor system

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GB1588805A
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1981-04-29

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1976-09-07
1977-06-17
Distributed power system for a multiprocessor system

GB3073/80A
Expired

GB1588807A
(en)

1976-09-07
1977-06-17
Power interlock system for a multiprocessor

GB3057/80A
Expired

GB1588804A
(en)

1976-09-07
1977-06-17
Processor module for a multiprocessor system

GB25490/77A
Expired

GB1588803A
(en)

1976-09-07
1977-06-17
Multiprocessor system

GB3072/80A
Expired

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1976-09-07
1977-06-17
Input/output system for a multiprocessor system

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1976-09-07
1977-06-17
Power interlock system for a multiprocessor

GB3057/80A
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(en)

1976-09-07
1977-06-17
Processor module for a multiprocessor system

GB25490/77A
Expired

GB1588803A
(en)

1976-09-07
1977-06-17
Multiprocessor system

GB3072/80A
Expired

GB1588806A
(en)

1976-09-07
1977-06-17
Input/output system for a multiprocessor system

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1977

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CA
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not_active
Expired

1977-06-17
GB
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Expired

1977-06-17
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1977-06-17
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GB3057/80A
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Expired

1977-06-17
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Expired

1977-06-17
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patent/GB1588806A/en
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1977-09-06
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patent/FR2473197B1/en
not_active
Expired

1977-09-06
DE
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active
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1977-09-06
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1980

1980-05-06
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Expired – Lifetime

1980-05-06
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1980-05-06
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1980-05-06
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patent/US4365295A/en
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Expired – Lifetime

1981

1981-09-04
FR
FR8116834A
patent/FR2485227B1/en
not_active
Expired

1981-09-04
FR
FR8116835A
patent/FR2485228B1/en
not_active
Expired

1981-12-17
HK
HK622/81A
patent/HK62281A/en
unknown

1981-12-17
HK
HK626/81A
patent/HK62681A/en
unknown

1981-12-17
HK
HK625/81A
patent/HK62581A/en
unknown

1981-12-17
HK
HK623/81A
patent/HK62381A/en
unknown

1981-12-17
HK
HK624/81A
patent/HK62481A/en
unknown

1982

1982-03-24
BE
BE0/207664A
patent/BE892627Q/en
not_active
IP Right Cessation

1982-04-08
JP
JP57057424A
patent/JPS5850062A/en
active
Granted

1982-12-30
MY
MY205/82A
patent/MY8200205A/en
unknown

1982-12-30
MY
MY209/82A
patent/MY8200209A/en
unknown

1982-12-30
MY
MY208/82A
patent/MY8200208A/en
unknown

1982-12-30
MY
MY206/82A
patent/MY8200206A/en
unknown

1982-12-30
MY
MY207/82A
patent/MY8200207A/en
unknown

1983

1983-06-17
US
US06/504,596
patent/US4484275A/en
not_active
Expired – Lifetime

1984

1984-03-29
FR
FR8404937A
patent/FR2547082A1/en
active
Pending

1984-09-05
JP
JP59184756A
patent/JPS60100254A/en
active
Granted

1984-09-05
JP
JP59184759A
patent/JPS60100257A/en
active
Granted

1984-09-05
JP
JP59184757A
patent/JPS60100255A/en
active
Granted

1984-09-05
JP
JP59184760A
patent/JPS60100258A/en
active
Granted

1984-09-05
JP
JP59184755A
patent/JPS60100253A/en
active
Granted

1984-09-05
JP
JP59184758A
patent/JPS60100256A/en
active
Granted

1984-09-05
JP
JP59184754A
patent/JPS60100252A/en
active
Granted

1985

1985-03-18
US
US06/713,583
patent/US4672535A/en
not_active
Expired – Lifetime

1985-04-29
US
US06/727,614
patent/US4672537A/en
not_active
Expired – Lifetime

1986

1986-06-11
JP
JP61135874A
patent/JPS61286962A/en
active
Pending

1987

1987-05-18
US
US07/052,095
patent/US4807116A/en
not_active
Expired – Lifetime

1987-05-19
US
US07/052,094
patent/US4817091A/en
not_active
Expired – Lifetime

Also Published As

Publication number
Publication date

FR2485227A1
(en)

1981-12-24

FR2485228B1
(en)

1985-11-29

JPS6122335B2
(en)

1986-05-31

JPS5925257B2
(en)

1984-06-15

MY8200207A
(en)

1982-12-31

HK62681A
(en)

1981-12-24

HK62581A
(en)

1981-12-24

GB1588804A
(en)

1981-04-29

US4807116A
(en)

1989-02-21

FR2473197B1
(en)

1985-12-13

JPS60100254A
(en)

1985-06-04

US4228496A
(en)

1980-10-14

JPS60100255A
(en)

1985-06-04

GB1588807A
(en)

1981-04-29

JPS60100253A
(en)

1985-06-04

MY8200206A
(en)

1982-12-31

JPS6120017B2
(en)

1986-05-20

JPS6218951B2
(en)

1987-04-25

FR2485227B1
(en)

1985-11-29

JPS6120018B2
(en)

1986-05-20

US4817091A
(en)

1989-03-28

JPS5850062A
(en)

1983-03-24

US4484275A
(en)

1984-11-20

FR2473197A1
(en)

1981-07-10

US4356550A
(en)

1982-10-26

JPS6124740B2
(en)

1986-06-12

US4365295A
(en)

1982-12-21

JPS6129028B2
(en)

1986-07-03

DE2740056C2
(en)

1992-03-19

JPS60100252A
(en)

1985-06-04

HK62281A
(en)

1981-12-24

MY8200208A
(en)

1982-12-31

HK62481A
(en)

1981-12-17

JPS61286962A
(en)

1986-12-17

JPS6120016B2
(en)

1986-05-20

US4639864A
(en)

1987-01-27

GB1588803A
(en)

1981-04-29

BE892627Q
(en)

1982-07-16

GB1588806A
(en)

1981-04-29

MY8200209A
(en)

1982-12-31

US4672537A
(en)

1987-06-09

FR2547082A1
(en)

1984-12-07

JPS5333027A
(en)

1978-03-28

US4672535A
(en)

1987-06-09

JPS60100257A
(en)

1985-06-04

JPS60100258A
(en)

1985-06-04

JPS60100256A
(en)

1985-06-04

US4378588A
(en)

1983-03-29

FR2485228A1
(en)

1981-12-24

JPS6122336B2
(en)

1986-05-31

CA1121481A
(en)

1982-04-06

DE2740056A1
(en)

1978-03-16

HK62381A
(en)

1981-12-24

MY8200205A
(en)

1982-12-31

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Legal Events

Date
Code
Title
Description

1981-07-15
PS
Patent sealed [section 19, patents act 1949]

1997-07-09
PE20
Patent expired after termination of 20 years

Effective date:
19970616

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