GB2028044A - Creation of Inventions and Patents with Artificial Intelligence

GB2028044A – Precharge circuit for memory array
– Google Patents

GB2028044A – Precharge circuit for memory array
– Google Patents
Precharge circuit for memory array

Download PDF
Info

Publication number
GB2028044A

GB2028044A
GB7927384A
GB7927384A
GB2028044A
GB 2028044 A
GB2028044 A
GB 2028044A
GB 7927384 A
GB7927384 A
GB 7927384A
GB 7927384 A
GB7927384 A
GB 7927384A
GB 2028044 A
GB2028044 A
GB 2028044A
Authority
GB
United Kingdom
Prior art keywords
transistor
bit line
point
cell
vfp
Prior art date
1978-08-07
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Granted

Application number
GB7927384A
Other versions

GB2028044B
(en

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

RCA Corp

Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1978-08-07
Filing date
1979-08-06
Publication date
1980-02-27

1979-08-06
Application filed by RCA Corp
filed
Critical
RCA Corp

1980-02-27
Publication of GB2028044A
publication
Critical
patent/GB2028044A/en

1982-10-27
Application granted
granted
Critical

1982-10-27
Publication of GB2028044B
publication
Critical
patent/GB2028044B/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

Classifications

G—PHYSICS

G11—INFORMATION STORAGE

G11C—STATIC STORES

G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor

G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements

G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices

G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors

G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger

G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

G11C11/419—Read-write [R-W] circuits

G—PHYSICS

G11—INFORMATION STORAGE

G11C—STATIC STORES

G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor

G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements

G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices

G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

G—PHYSICS

G11—INFORMATION STORAGE

G11C—STATIC STORES

G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Description

1 1 10 GB 2 028044 A 1
SPECIFICATION
Precharge circuit for memory array This invention relates to means for placing the bit lines of a memory array at, a potential, or potentials, which enables information to be quickly and safely written into, or read-out of, selected cells of the array without disturbing the unselected cells.
In the design of large memory arrays, a critical parameter is the largest number of memory cells that can be put on a chip, i.e. the packing density. To achieve a high packing density, the number of devices per memory cell must be small, the devices themselves must be as small as possible, and the number of lines to access the cells must be as few as possible.
A known static memory cell which satisfies these general requirements includes five (5) transistors per cell and is shown, for example, in FIGURE 5 of U.S. Patent 3,521,242 entitled, “Complementary Transistors Write and NDRO for Memory Cell” and incorporated herein by reference. Four of the five transistors are connected to form a flip-flop. The fifth transistor referred to herein as the “gating” transistor functions as a transmission gate. Its conduction path is connected between a single input-output (1/0) point of the flip flop and an 1/0, or bit, line and it is used either to sense the state of the cell or to write infor- mation into the cell. The cell has many advantages in 95 that it is small, it can be selected by one word line connected to the control electrode of the gating transistor, and information can be written into the cell and. its contents can be sensed by means of one bit line.
However, many problems and conflicting design requirements accompanying these advantages. To write into the cell, the impedance of the gating transistor must be made as low as possible to enable the cell to accept new information (i.e. change state). But, when reading the information contained in the cell, the gating transistor must have a relatively high impedance to prevent residual voltages on the bit line from overriding and altering the contents of the memory cell.
A prior art technique for minimizing the above problems is to control the ON impedance (43) of the conduction path of the gating transistor so it is much higher during a read cycle than during a write cycle.
During read, ZN3 is made high relative to the ON impedance (Z,) of the transistors forming the flipflop, so the cell can be read out nondestructively. During write, ZN3 is made less than ZF to enable information to be written into the cell. However, making ZN3 low, during write, gives rise to a serious problem when it is realized that selected cells as well as unselected cells are then coupled to their corresponding bit lines.
For example, a large memory array (e.g. 16K RAM) having M – N (e.g. 16,384) memory cells is arranged in M (e.g. 128) rows and N (e.g. 128) columns with one row conductor (word line) per row and one column conductor (bit line) per column. The control electrodes of the N gating transistors of a row are connected to each word line and one end of their conduction paths are connected to their corresponding bit lines.
In such large arrays, information is normally written into (or read from) only a small number (e.g. 1, 4 or8) of cells atany onetime. But, all the N gating transistors of a row are concurrently driven into conduction. Due to the large size of the array the capacitance associated with the bit lines is substantial and the voltage levels of the unselected bit lines maybe held tightly at either the “0” or “l “voltage level. The combination of the low impedance of the gating transistors and the large bit line capacitance can result in the disturbance (“false-write”) of many unselected cells. Thus, although making ZN3 low dur- ing write enables the cells to be easily written, it gives rise to a serious disturb problem.
Furthermore, the ON impedance of the gating transistor is arranged to be normally high during read by making the gating transistor as small as possible. But, there are limits to how small the gating transistor can be made relative to the transistors forming the flip-flop. To achieve a high packing density the transistors forming the flip-flop are made as small as the design rules permit. In some cases the gating transistor cannot be made smaller, and consequently ZN3 is then not significantly greater than the ON impedance of the flip-flop transistors. For similar sized gating and flip-flop transistors, some unselected cells may be disturbed during read; and, due to the high impedance of Z,,,, the read-out is very slow. These problems are aggravated by the non-linear impedance characteristic of ZN3- Clearly, a problem exists in making a large high density memory array which can be reliably and quickly written and read. This problem is solved in circuits embodying the invention.
In memory arrays embodying the invention each memory cell has: a) an input-output (1/0) point to which a storage element is connected; b) a gating transistor for selectively connecting the 1/0 point and a bit line; and c) a flip pointwhich maybe defined as a voltage level at the 1/0 point at which the cell neither sinks (draws) nor sources (supplies) current into the 1/0 point.
The present invention resides in part in the recognition that for a voltage equal to or close to, the voltage level of the flip point applied to the bit line, the memory cell will not be disturbed (i.e. change state) even though the impedance of the gating transistor isverylow.
In the accompany drawings:
FIGURE 1 is a block diagram of a memory array embodying the invention; FIGURE 2A is a schematic diagram of a memory cell that may be used in the circuit of FIGURE 1; FIGURES 2B and 2C are idealized equivalents of the FIGURE 2A circuit fortwo different signal conditions; FIGURE 3 is a graph of states assumed by a cell of the type shown in FIGURE 2 in response to voltages applied to the bit and word lines; FIGURE 4 is a schematic diagram of a sense amplifier which may be used in the circuit of FIGURE 1; and 130 FIGURES 5, 6,7 and 8 are different precharge cir- 2 GB 2 028 044 A 2 cuits that may be used to practice the invention.
Insulated-gate field-effect transistors (IGFETs) are the active devices preferred for use in practicing the invention. Forthis reason, the circuit is illustrated in the drawing as employing such transistors and will be so described hereinafter. However, this is not intended to preclude the use of other suitable devices and to this end, the term “transistor”, when used without limitation in the appended claims, is used in a generic sense.
In the FIGURES, enhancement type IGFETs of P conductivity type are identified by the letter P fol lowed by a particular reference numeral; and enhancementtype IGFETs of N-conductivity type are identified by the letter N followed by a particular reference numeral. The characteristics of IGFETs are well known and need not be described in detail. But, for a clearer understanding of the description to fol low, definitions and characteristics of IGFETs perti nent to the invention are set forth in column 2 of U.S. 85 Patents 4,037,114 and 4,001,606, and are incorpo rated herein by reference.
The circuit of FIGURE 1 includes a memory array 8 of cells 9 arranged in rows (words) and columns (bits). Each memory cell, as shown in FIGURE 2A, includes a gating transistor N3 whose conduction path is connected between a bit line (BL) and the Input-Output (1/0) point (A) of a flip-flop 10 com prised of two cross-coupled complementary inver ters 11 and 12. Each one of inverters 11 and 12 includes 95 two IGFETs of complementary conductivity type hav ing their source drain paths connected in series bet ween VDD and ground. The drains of IGFETs P1 and N1, forming inverter 11, are connected in common with the gates of IGFET P2 and N2 to 1/0 point A also 100 defined as the “exterior” node of the cell. The drains of P2 and N2, forming inverter 12, are connected to the gates of P1 and Ni at node B also defined as the “interior” node of the cell. A word line is connected to the control (gate) electrode of N3. The potential (VWL) on the word line controls the conductivity of N3.
Before discussing the remainder of FIGURE 1 it will first be shown that for certain voltages on the bit line, the memory cell will not be disturbed.
Referring to the circuit of FIGURE 2A assume: (a) that the flip-flop transistors P1, N1, P2 and N2 have the same source-to-drain impedance for the same value of gate-to-source potential; (b) that the transi tion point of inverters 11 and 12 is V,,D/2, that is, for values of gate voltage more negative than VDD/2 the inverter output is high Jmore positive than V,,D/2) and for values of gate voltage more positive than VDI)/2 the inverter output is low (less positive than VDD/2); (c) that the “flip-point” (VFP) of the flip-flop is VDD/2, where the “flip-point” is defined as the voltage at node A for which the memory cell neither sinks (draws) current from, nor sources (supplies) current into, node A; and (d) that VDD/2 volts, is applied to the bit line.
Consider first the condition of the memory cell when storing a “V or “high”. In this state transistors P1 and N2 are ON and node A is connected to +VDD via the conduction path of P1 -ON. Assume now that gating transistor N3 is turned on very hard by the application OfVDDVOItStO its gate. The impedance VNJ of N3 is connected in series with the impedance (Zpj of Pi between the bit line at +VDD/2 and the power supply line at +VDD volts. For any value OfZN3 above zero ohms the potential at node A must remain above VDD/2 and the cell remains in the “high” state.
Consider nowthe condition of the memory cell when storing a “0” or “low”. In this state, transistors N1 and P2 are on and node A is connected to ground via the drain-to- source path through N1. Assume, as before, that N3 is turned on very hard. ZN3 is now connected in series with the impedance VNJ Of transistor N1 between the bit line which is at VDD/2 and ground. For any value Of ZN3 greater than zero the potential at node A must remain below VDD/2 and the cell remains in the “low” state. Thus, for the bit line precharged to VDD/2, the memory cell will not be disturbed even ifZN3 is much less than Zp, or ZN1. The impedance of N3 is no longer critical and can be varied over a wide range without causing a false write problem.
It is now shown thatforfinite values OfZN3 there is a-“safe-margin” which is defined herein as a range of voltage that may be applied to the bit line above or below VFP without causing the cell to change state when coupled via ZN3 to the bit line. By way of example, assume that, when N3 is turned on, ZN3 is one fourth (1/4) ZN1 or Zpj and that VDD is equal to 5 volts.
Examine first the condition when the cell is storing a “‘I “. Transistor P1 is on, and Zpj is then connected between VDD and node A. The remaining transistors of the flip-flop are either off or present a high impedance at node A. Transistor N3 is assumed to be turned on hard, and ZN3 assumed equal to Zpj/4 is connected between node A and the bit line. The idealized condition of Zpj and ZN3 is series between VDD and BL is shown in FIGURE 2B. The voltage (VBL) that must exist on the bit line to bring the voltage (VA) at node A down to VDD/2 (e.g. 2.5v) is, for the assumed values of impedances, equal to 3/8 VDD (e.g. 1.875 volts). Until VBL becomes more negative than this level the memory cell will not be disturbed when N3, whose ZN3 = Zpj/4, is turned on.
Examine now the condition when the cell is storing a “0”. N1 is ON, and ZN1 is connected between ground and node A. Transistor N3 is assumed to be turned on hard, and ZN3 equal to ZN1/4 is connected between node A and the bit line. The idealized condi- tion OfZN3 and ZNI in series between BL and ground is shown in FIGURE 2C. TheVBLto bring node A to V../2 (e.g. 2.5v) for the assumed values of impedances, is 5/8 VDD (e.g. 3.125v). Until VBL becomes more positive than this level the memory cell will not be disturbed. ForVFp equal to VDD/2 and VBL precharged to VDD/2 the margin of safety lies within a range between [.VDDI [1 +ZN3fZN1 2 1 VDD and 2 [1-ZN3fZP1].
(The general expression for the range of margin 130 safety may be obtained by replacing VDD/2 with VFP.) A, 3 GB 2 028 044 A 3 Thus, for the valueOf ZN3, ZN, and Z, assumed above there is a safety margin of V /8, as determined and the ratiosOf ZN3to each of the impedances of the flip-flop transistors P1 and P2. VBLcan be set within this margin of VDD/2 without disturbing the memory 70 cell even thoughVM/2 is the preferred level. This is shown in FIGURE 3 where, forVl3LatVl:)D/2, the word line voltage applied to the gate electrode of N3 can be increased considerably aboveVDD VOItS(andZN3 decreased considerably) without disturbing the memory cell. Regions Ul and U2 in FIGURE 3 define conditions for which the setting of the memory cell may vary due to variations in temperature, power supply voltages and the like. The lack of symmetry of the two regions is due to the gating transistor con ducting in the source follower mode when turned on with node A low andVE)Lat or more positive than VA, but conducting in the common source mode when node A is high andVBLis at or less positive than VA.
Maintaining the bit line at or near the flip point eliminates the problem of “false-write” or “disturb” of the unselected cells during the write or read mode. Furthermore,ZN3can be made a very small impedance without a disturb problem. Hence, N3 can be overdriven into conduction and information can be written safely and quickly into selected mem ory cells. Still further, the problem of disturbing the contents of the memory cell, during read, if ZN3 isa small impedance, is also eliminated. WithV13Lat VDD/2, a cell selected for read will either raise the bit line level if storing a “V or lower the bit line level if storing a “0”, but VA will remain within safe I imits.
Hence, ZN3 can safely be made a smaller impedance during read enabling faster read-out of the memory cell since more current can be sourced or sunk.
The greater freedom in the design of N3 enables the flip-flop transistors to be designed as small as possible. Hence, a smaller cell can be designed enabling the design of higher density memory arrays.
It will also be shown below that precharging bit lines enables the much faster sensing of cell states.
Sense amplifiers coupled to the bit lines are pre charged to their mid-point (highest gain and sensitiv ity) and are able to sense small excursion above or below the precharge point faster.
Referring back to the circuit of FIGURE 1, each row of cells has a word line (W1… W1 28) connected to the gate (control) electrodes of the gating transistors of that row. And each column of cells has a bit line (131… 13128) connected to one end of the conduction paths of the gating transistors of that column. A READ/WRITE voltage generator 12 is coupled to a level shift and word line decoder circuit 14 to which address lines 16 also couple. The address line information is derived from the output of transition detection circuit 17 which has external input memory address line signals 18 applied thereto as inputs. The information on the address lines determines the rows selected for write or read. The address line data 125 is decoded by the decoder portion of circuit 14 which couples the output of voltage generator”I 2 onto a selected one of the word lines (W1… W1 28). Vo I- tage generator 12 is preferably of the type which produces online 13 either a voltage OfVDD volts dur- 130 ing read or a voltage of +2VI, volts during write. Such a circuit, being shown for example, in U.S. Patent4,000,412 and in a co-filed application no. 7927386 Serial No. 2028046 titled MEMORY ORGANIZATION, need not be detailed. However, any other voltage generator which can produce suitable read and write voltages may be used to perform the function of generator 12. A preferred decoding and level shift arrangement is also shown in the above iden- tified co-filed application. But, it should be understood that any one of a number of known decoding and level shift circuits may be used to perform the decoding and level shift function of circuit 14.
A precharge circuit (201… 20128) is connected to each bit line (B1… B128) of the array. The precharge circuits are turned on and off concurrently by means of a control line 22 to which is applied an appropriate precharge pulse derived from transition detector 17. The precharge circuits (20i), where 1:5 i =5 128, func- tion to establish a predetermined voltage on the bit lines. By way of example, for cells with VFp at V,,,,12, the precharge circuits set the bit lines at approximately VDD/2. A number of circuits capable of performing this function are shown in FIGURES 5-8 dis- cussed below.
All the bit lines are fed to a bit line decoder 30 having 128 inputs, one input per bit line, and having 4 outputs which are connected to master bit lines M131, M132, MB3 and M134. Decoder 30 includes 128 decoding gates (DGi) shown as being of the complementary transistor transmission gate type, one gate being connected between each bit line and one of 4 master bit lines. Decoding means (not shown) provide the enabling signals ((ki, i) applied to the gate electrodes of the transmission gates. During read, four of the transmission gates are enabled (turned on) at a time thereby coupling 4 bit lines to the 4 master bit lines via the low “on” impedance of a complementary transistor transmission gate.
Other types of known decoding arrangements may be used. However, the transmission gates provide a low bidirectional conduction path when ON, and a high OFF impedance. Whenever the memory array is read the contents of 4 cells are read out onto the master bit lines. Each master bit line is coupled to a sense amplifier which maybe a simple complementary inverter of the type shown as Is in sense amplifier block 1 in FIGURE 1. For the simple inverter shown in FIGURE 1 the precharged bit line functions to charge the gate electrodes of transistors Ps and Ns, which gate electrodes define the input of inverter Is, to V,,,,/2 volts when one of the decoder gates connected to master bit line 1 is enabled. When a selected cell is subsequently read by the turn on of its gating transistor, its associated master bit line voltage rises above V,,12 or fails below VDD/2 giving a quick read-out of the cell contents. In this instance the precharge circuitry may thus be used to also precarge the sense amplifier input.
The sense amplifiers may also be of the type shown in FIGURE 4 and discussed in detail in co-filed application no. 7927385 Serial No. 2028045 entitled Asymmetrically Precharged Sense Amplifier. The sense amplifier of FIG URE 4 includes complementary transistors P1 0 and N1 0 forming inverter 110 4 GB 2 028 044 A 4 which is connected at its input to a master bit line (MB). The conduction paths of transistors PG ‘I and NG1, forming a selectively enabled transmission gate TG1, are connected between the input and output of inverter 110. Transmission gate TG1, when enabled by a precharge pulse, couples the input and output of 110 via a relatively low impedance path. (in FIGURE 4 the precharge pulse is shown as a negative going pulse but a positive going precharge pulse may be generated at the same time to drive the precharge circuits.) Transistors P10 and N10 may have the same ratio to each other astransistors P1 and N1 of the memory cells have to each other. Hence, the transition point of inverter 110 (assumed to beVDD/2) may be the same as that of inverter 11 of the memory cells. A transistor P5 whose conduction path is connected betweenVDDand the input of inverter 110 is responsive to a precharge pulse and chargesthe input of the inverter just above its transition point.
The FIGURE 4 sense amplifier also includes a transis- 85 tor P4 for maintaining the inverter input charged after the termination of the precharge pu Ise. An advantage of precharging all the bit lines to a voltage which is equal to or close to the precharge level on the master bit lines is that it avoids the problem of charge redistribution when any of the decode gates in bit line decoder 30 are enabled. This al lows the sense amplifier to respond almost instantaneously to information supplied to the bit lines from the memory cells. It should be appreciated that each sense amplifier only precharges the master bit line and the selected bit line connected to it. The unselected bit lines, which amount to 124 lines out of 128 for the example of FIGURE 1, are unaffected by the sense amplifiers. In the absence of the precharge 100 circuits 201… 201,,,, the unselected bit lines would float anywhere between zero volts and +VDD Volts giving rise to the problems discussed above.
Referring back to the precharge circuits, these cir- cuits function to place all the bit lines at a predetermined voltage, or within a range of value, for which the memory cell will not be disturbed.
The precharge circuitry of FIGURE 5 includes first (N 1 j) and second (N2j) IGFETs of the same conductiv- ity type per bit line or column, where i takes on values from 1 to 128. The conduction paths of the first (N1j) and second (N2j) IGFETs associated with each bit line are connected in series between V.. and a common line 310 which is connected to the output of a driving inverter ID. The gate electrodes of the first IGFETs of the precharge circuits are connected in common with the input of inverter],, to precharge inputterminal 312. The gate and drain electrodes of the second IGFETs of the precharge circuits are con- nected in common with the source electrode of the first IGFET to its associated bit line. Inverter],, is comprised of transistors PD and N. of complementary conductivity type. Transistor ND is made very large compared to IGIFETs N1i and N2j, to provide a relatively low impedance path between line 310 and ground.
When the precharge pulse applied to input 312 is low, transistors N11 are turned off and PD is turned on applying V.. to line 310 and ensuring the turn off of the N2i transistors. The precharge circuits then 130 appear as high impedances and have little effect on the bit lines. When the precharge pulse goes high (+VE)D), transistors Nli have +VDD volts applied to their gates as well as their drains and are turned on.
Transistor ND is also turned on and clamps line 310 at, or close to, ground potential turning on the transistor N2j whose gates and drains are connected to respective ones of the sources of transistors N1 i. The conduction paths of respective pairs of transistors Nli and N2j are then connected in series between VDD and line 310 and, when the transistors Nli and N21 in each pair are of similar size, the bit line (BL) connected to the junction of their conduction paths gets charged to a potential close to VD,:,/2 volts. At equilib- rium (bit lines at VDD/2) the current through N1 i is equal to the current through N2i and these transistors then have approximately equal VGS’s and VDS’S OfVDD/2. The drain-to-source conductances of transistors Nli and N2j will, therefore, be alike despite VDD variation and will reliably place the bit lines near VDD/2Significant features of the precharge circuit of FIGURE 5 are:
1. Only two transistors are required per (bit line) column of memory cells enabling the precharge circuit to fit on pitch with compact memory cells. This ensures a very compact layout (not shown) of the memory array.
2. Only the VDD line, the input line to the gates of transistors Nli, and the common line 310 have to be routed to the precharge circuitry.
3. The use of N-type transistors (Nli, N2j) having higher transconductance then comparably sized P-MOS transistors ensures rapid midpoint precharging. However, P-type transistors could be used instead of the N-type will allowance made forthe different polarity signals required to turn them on.
4. As long asVDD is greaterthan the sum of the threshold voltages (VT’s) of transistors Nli and N2i, the precharge circuit places the bit lines at a potential near VDD/2 independent of the VT’S of the transistors.
5. Once the precharge pulse is removed (i.e. point 312 returns low) the precharge circuit is rapidly decoupled from the bit line. IGFETs Nli with zero volts on their gate electrodes and V,,,)/2 attheir source electrodes (due to the capacitive precha rged bit lines) are quickly and sharplyturned off. Similarly IGFETs N2j with VDD/2 volts at their gates and drains are quickly turned off when transistor PD is turned on and a potential Of +VDD Volts is applied to their source electrodes via line 310.
6. Transistors Nli conduct in the source follower mode and can supply relatively large initial currents onto the bit lines.
The circuit of FIGURE 6 enables the setting of the bit line voltage closer to the transition point of the transistors forming the memory cell flip flop than does the circuit of FIGURE 5. Two complementary transistors (P8i and NJ are required per bit line (column of memory cells). The two transistors have their conduction paths connected in series between common lines 410 and 310 to which are respectively applied +VDD volts and ground. The gates and drains of the two transistors are direct current (d.c.) con- 7.
il GB 2 028 044 A 5 nected in common and to the bit line. The ratio of transistors P,,j to N,, i may be the same as the ratio of the P transistors to the N transistors of inverter 11 and/or inverter 12 of the memory cells. This enables the precharge circuit to track the flip point of the memory cells of array 8 over a wide range of voltage, temperature, and other conditions.
Assuming Zpaj ZN8i, the d.c. gate to drain connection sets their drain and gate potentials at a voltage which is one half the voltage applied between the two common lines. In response to a positive going precharge pulse at input terminal 312 transistor PD3 is turned on clamping line 410 at or close to, +VDD volts and transistor NDI is turned on clamping line 310 at, or close to, ground. PD3 and ND, are made very 80 large in comparison to transistors P8j and N8j and are made to have similar impedances when carrying equal currents. Hence, the bit line voltage of each precharge circuit is at, or very close to, V,,,,/2 volts.
FIGURE 7 is another precharge circuit suitable to practice the invention. An inverter 71 is connected at its input to a bit line. A transmission gate TG7 connected between the input and the output of inverter 71 provides a low impedance path therebetween in response to a precharge pulse charging the bit line to the transition point of the inverter. The conduction path of a high impedance (Zp, >> Z of TG7) transistor P7 is connected between VDD and the input to inverter 71. P7 has little, if any, effect on the pre- charge level. But, following precharge and read-out or write-in P7 provides a positive feedback path so that the bit line is not maintained at an intermediate level for which inverter 71 draws a continuous current.
FIGURE 8 is still another circuit for precharging the bit line to the transition point of a complementary inverter. The circuit includes two P-type transistors P91, P92 having their conduction paths connected in series with two N-type transistors (N91, N92) bet ween VDD and ground. The conduction paths of the two P type transistors are connected in series bet ween VDD and bit line, and the conduction paths of the two N-type transistors are connected in series between the bit line and ground. During precharge, transistors P92 and N92 are switched-on by F-re charge and precharge, respectively. P91 and N91 having their gates connected in common to the bit line function as a self-biased inverter and the bit line is driven to the transition point of the inverter. For similar size P and N-type transistors the bit line is driven to the mid point of the operating potential (VDD/2).

Claims (4)

1. A system comprising: a memory array of cells arranged in M rows and N columns, each cell having 120 a flip point (VFp) defining a level above which the cell is set to or stores one binary condition and below which the cell is set to or stores the other binary condition; N bit lines, a bit line per column of cells, all the cells of a column being coupled to a respec- 125 tive bit line; and N precharge means, each one of said precharge means being connected to a different one of said bit lines; each one of said precharge means being enabled 130 priorto the writing of information into, orthe reading of information out of, any of said cells for precharging its associated bit line to a potential approximately equal to the voltage of said flip point.

2. A system according to claim 1 wherein each one of said precharge means includes a first trans sistor connected between its corresponding bit line and a first point of operating potential, and a second transistor connected between its corresponding bit line and a second point of operating potential.

3. A system according to claim 2 wherein said first and second transistors are of the same conductivity type.

4. A system according to claim 3 wherein, with FET’S: the gate electrode of said first transistor is connected to an input terminal adapted-to receive a precharge signal, and the source electrode of said first transistor is connected in common with the gate and source electrodes of said second trans- istor to its corresponding bit line; the drain electrode of said first transistor is directly connected to said first point of potential; and 9. A system comprising: a memory cell having an input-output point and having a flip point (VFP) defining a level above which the cell is set to or stores a first binary condition and below which the cell is set to or stores a second binary condition; said memory cell presenting at said input-output point a first impedance (ZI) when at said first binary condi- tion and a second impedance (ZJ when at said second binary condition, and said cell including a gating transistor having a control electrode and having a conduction path connected between said inputoutput point and a bit line the conduction path of said gating transistor when enabled having a third impedance (Z3); and wherein the system includes:
means for precharging said bit line within a range of voltages prior to the enabling of said gating trans- istorto prevent disturbing the contents of the cell; said range of voltages being defined between VFP minus the ratio of said third impedance to said first impedance multiplied by VFP (i.e. VFP- (Z321) VFP) and VFP plus the ratio of said third impedance to said second impedance multiplied by VFP (i.e. VFP + (Z3/Z2) VFP)’ Printed for Her Majesty’s Stationery Office by The Tweeddale Press Ltd., Berwick-upon-Tweed, 1980. Published at the Patent Office, 25 Southampton Buildings, London, WC2A 1AY, from which copies may be obtained.
r A it
4. A system according to claim 3 wherein the gate electrode of said first transistor is connected to an input terminal adapted to receive a precharge signal, and the source electrode of said first transistor is connected in common with the gate and source electrodes of said second transistor to its cor- responding bit line; the drain electrode of said first transistor is directly connected to said first point of potential; and the source electrode of said second transistor is returned via a switching device to said second point of operating potential.
5. A system according to claim 2 wherein said first and second transistors are of complementary conductivity types, the conduction path of a third transistor is con- nected in series with the conduction path of said first transistor between its corresponding bit line and said first point of operating potential, and the conduction path of a fourth transistor is connected in series with the conduction path of said second transistor between its corresponding bit line and said second point of operating potential.
6. A system according to any preceding claim wherein each one of said memory cells has an input-output point and a gating transistor having a conduction path connected between the inputoutput point of the cell and its corresponding bit line.
7. A system according to claim 6 wherein each one of said memory cells includes first and second complementary inverters cross-coupled to form a flip-flop.
8. A system according to any preceding claim further including:
X master bit lines, where X is smallerthan N; a bit line decoder circuit coupled between said N bit lines and said X master bit lines for selectively coupling the signals on X of said N bit lines to respective ones of said X master bit lines; and X sense amplifying means coupled respectively to said X master bit lines, each one of said X sense amplifying means including means for precharging the one of said master bit lines, to which it is connected, to a voltage which is approximately equal to that to which the bit lines are precharged.
9. A system comprising: a memory cell having an input-output point and having a flip point (VFP) defining a level above which the cell is set to or stores a first binary condition and below which the cell is set to or stores a second binary condition; said memory cell having a first output impedance (Zi) when at said first binary condition and having a sec- 6 GB 2 028 044 A 6 ond output impedance (Z2) when at said second binary condition, and said cell including a gating transistor having a control electrode and having a conduction path connected between said input output point and a bit line the conduction path of said gating transistor when enabled having an impedance VJ; and wherein the system includes:
means for precharging said bit line within a range of voltages prior to the enabling of said gating transistor to prevent disturbing the contents of the cell; said range of voltages being defined between VFP minus the ratio of said third output impedance to said first output impedance multiplied by V,, [i.e. VFP – V321) VFpJ and VFP plus the ratio of said third output impedance to said second output impedance multiplied by VFP [i.e. VFp + V322) VFPI- 10. The system set forth in claim 9 wherein said memory cell includes a first and second inverters each having an input and an output, wherein the output of said first inverter and the input of said second inverterare connected to said input output point; and wherein the input of said first inverter and the out- put of said second inverter are connected in common.
11. The system set forth in claim 10 wherein each one of said first and second inverters includes first and second transistors of first and second conductiv- ity types and wherein said gating transistor is of one of said first and second conductivity types.
12. A memory system substantially as hereinbefore described with reference to the accompanying drawings.
New claims or amendments to claims filed on 7 Nov. 1979. Superceded claims 4 and 9.

GB7927384A
1978-08-07
1979-08-06
Precharge circuit for memory array

Expired

GB2028044B
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

US05/931,748

US4208730A
(en)

1978-08-07
1978-08-07
Precharge circuit for memory array

Publications (2)

Publication Number
Publication Date

GB2028044A
true

GB2028044A
(en)

1980-02-27

GB2028044B

GB2028044B
(en)

1982-10-27

Family
ID=25461290
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB7927384A
Expired

GB2028044B
(en)

1978-08-07
1979-08-06
Precharge circuit for memory array

Country Status (6)

Country
Link

US
(1)

US4208730A
(en)

JP
(1)

JPS5913115B2
(en)

DE
(1)

DE2932019C2
(en)

FR
(1)

FR2433224A1
(en)

GB
(1)

GB2028044B
(en)

IT
(1)

IT1122304B
(en)

Cited By (7)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

EP0058051A2
(en)

1981-02-06
1982-08-18
Fujitsu Limited
Static type semiconductor memory device

EP0071245A2
(en)

1981-07-27
1983-02-09
Kabushiki Kaisha Toshiba
Semiconductor memory device

EP0121217A2
(en)

1983-03-31
1984-10-10
Kabushiki Kaisha Toshiba
Output buffer circuit

GB2188505A
(en)

1986-03-24
1987-09-30
Motorola Inc
High speed write technique for a memory

FR2614743A1
(en)

1987-04-29
1988-11-04
Matra Harris Semiconducteurs
Digital integrated circuit with preloading

EP0434495A1
(en)

1989-12-21
1991-06-26
Bull S.A.
Memory bus precharge circuit

GB2242767A
(en)

1990-04-06
1991-10-09
Mosaid Inc
Precharging DRAM bit lines to half supply potential

Families Citing this family (36)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

JPS5575899U
(en)

1978-11-20
1980-05-24

US4423340A
(en)

1981-12-14
1983-12-27
Motorola, Inc.
Sense amplifier

JPS58121195A
(en)

1982-01-13
1983-07-19
Nec Corp
Producing circuit of precharging signal

US4577282A
(en)

1982-02-22
1986-03-18
Texas Instruments Incorporated
Microcomputer system for digital signal processing

US4494187A
(en)

1982-02-22
1985-01-15
Texas Instruments Incorporated
Microcomputer with high speed program memory

JPH0715798B2
(en)

1983-02-23
1995-02-22
株式会社東芝

Semiconductor memory device

US4558240A
(en)

1983-04-21
1985-12-10
Rca Corporation
Multi mode amplifier

US4567387A
(en)

1983-06-30
1986-01-28
Rca Corporation
Linear sense amplifier

US4608672A
(en)

1983-07-14
1986-08-26
Honeywell Inc.
Semiconductor memory

JPS60105320A
(en)

1983-11-14
1985-06-10
Nippon Telegr & Teleph Corp
Level converting circuit

DE3586736T2
(en)

1984-10-11
1993-02-18
Hitachi Ltd

SEMICONDUCTOR MEMORY.

US4646306A
(en)

1984-12-26
1987-02-24
Thomson Components – Mostek Corporation
High-speed parity check circuit

US4638462A
(en)

1985-01-31
1987-01-20
International Business Machines Corporation
Self-timed precharge circuit

US4649523A
(en)

1985-02-08
1987-03-10
At&T Bell Laboratories
Semiconductor memory with boosted word line

IT1214607B
(en)

1985-05-14
1990-01-18
Ates Componenti Elettron

PRELOAD CIRCUIT FOR LINE LINES OF A MEMORY SYSTEM, IN PARTICULAR TO PROGRAMMABLE CELLS.

US4750155A
(en)

1985-09-19
1988-06-07
Xilinx, Incorporated
5-Transistor memory cell which can be reliably read and written

EP0218747B1
(en)

1985-10-15
1991-05-08
International Business Machines Corporation
Sense amplifier for amplifying signals on a biased line

JPS62119818U
(en)

1986-01-20
1987-07-30

JPS62141319U
(en)

1986-03-03
1987-09-07

FR2608861A1
(en)

1986-12-23
1988-06-24
Labo Electronique Physique

READER AMPLIFIER CIRCUIT FOR STATIC RAM MEMORY

JPH01164811U
(en)

1988-05-10
1989-11-17

US4962326B1
(en)

1988-07-22
1993-11-16
Micron Technology, Inc.
Reduced latchup in precharging i/o lines to sense amp signal levels

KR910009444B1
(en)

1988-12-20
1991-11-16
삼성전자 주식회사
Semiconductor memory device

JPH0770221B2
(en)

1990-05-17
1995-07-31
インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン

Read / write / restore circuit for memory array

US5245578A
(en)

1992-08-12
1993-09-14
Micron Technology, Inc.
DRAM with a two stage voltage pull-down sense amplifier

US5986914A
(en)

1993-03-31
1999-11-16
Stmicroelectronics, Inc.
Active hierarchical bitline memory architecture

US5742544A
(en)

1994-04-11
1998-04-21
Mosaid Technologies Incorporated
Wide databus architecture

JP2728015B2
(en)

1995-03-24
1998-03-18
日本電気株式会社

Charge transfer device

US6081458A
(en)

1998-08-26
2000-06-27
International Business Machines Corp.
Memory system having a unidirectional bus and method for communicating therewith

US6046930A
(en)

1998-09-01
2000-04-04
International Business Machines Corporation
Memory array and method for writing data to memory

FR2874734A1
(en)

2004-08-26
2006-03-03
St Microelectronics Sa

METHOD FOR READING MEMORY CELLS PROGRAMMABLE AND EFFECTIVELY ELECTRICALLY, WITH ANTICIPATED PRECHARGE OF BIT LINES

US7755961B2
(en)

2006-07-07
2010-07-13
Rao G R Mohan
Memories with selective precharge

US7724593B2
(en)

2006-07-07
2010-05-25
Rao G R Mohan
Memories with front end precharge

US7995409B2
(en)

2007-10-16
2011-08-09
S. Aqua Semiconductor, Llc
Memory with independent access and precharge

US8095853B2
(en)

2007-10-19
2012-01-10
S. Aqua Semiconductor Llc
Digital memory with fine grain write operation

US8767493B2
(en)

2011-06-27
2014-07-01
Taiwan Semiconductor Manufacturing Company, Ltd.
SRAM differential voltage sensing apparatus

Family Cites Families (11)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3521242A
(en)

1967-05-02
1970-07-21
Rca Corp
Complementary transistor write and ndro for memory cell

US3747078A
(en)

1972-06-28
1973-07-17
Ibm
Compensation technique for variations in bit line impedance

DE2309192C3
(en)

1973-02-23
1975-08-14
Siemens Ag, 1000 Berlin Und 8000 Muenchen

Regenerating circuit in the manner of a keyed flip-flop and method for operating such a regenerating circuit

DE2317497C2
(en)

1973-04-06
1975-02-13
Siemens Ag, 1000 Berlin Und 8000 Muenchen

Method for operating a five-transistor memory element

US3909631A
(en)

1973-08-02
1975-09-30
Texas Instruments Inc
Pre-charge voltage generating system

US3995215A
(en)

1974-06-26
1976-11-30
International Business Machines Corporation
Test technique for semiconductor memory array

US3971004A
(en)

1975-03-13
1976-07-20
Rca Corporation
Memory cell with decoupled supply voltage while writing

US4063225A
(en)

1976-03-08
1977-12-13
Rca Corporation
Memory cell and array

US4044341A
(en)

1976-03-22
1977-08-23
Rca Corporation
Memory array

DE2630797C2
(en)

1976-07-08
1978-08-10
Siemens Ag, 1000 Berlin Und 8000 Muenchen

Function generator for generating a voltage at a node to which flip-flops of MOS transistors assigned to the bit lines of a MOS memory are connected

US4099265A
(en)

1976-12-22
1978-07-04
Motorola, Inc.
Sense line balance circuit for static random access memory

1978

1978-08-07
US
US05/931,748
patent/US4208730A/en
not_active
Expired – Lifetime

1979

1979-07-24
IT
IT24608/79A
patent/IT1122304B/en
active

1979-08-06
JP
JP54100674A
patent/JPS5913115B2/en
not_active
Expired

1979-08-06
GB
GB7927384A
patent/GB2028044B/en
not_active
Expired

1979-08-07
FR
FR7920225A
patent/FR2433224A1/en
active
Granted

1979-08-07
DE
DE2932019A
patent/DE2932019C2/en
not_active
Expired

Cited By (14)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

EP0058051A3
(en)

1981-02-06
1985-10-09
Fujitsu Limited
Static type semiconductor memory device

EP0058051A2
(en)

1981-02-06
1982-08-18
Fujitsu Limited
Static type semiconductor memory device

US4813021A
(en)

1981-07-27
1989-03-14
Tokyo Shibayra Denki Kabushiki Kaisha
Semiconductor memory device with delayed precharge signals

EP0071245A2
(en)

1981-07-27
1983-02-09
Kabushiki Kaisha Toshiba
Semiconductor memory device

EP0071245A3
(en)

1981-07-27
1985-01-23
Kabushiki Kaisha Toshiba
Semiconductor memory device

EP0121217A2
(en)

1983-03-31
1984-10-10
Kabushiki Kaisha Toshiba
Output buffer circuit

EP0121217A3
(en)

1983-03-31
1987-01-28
Kabushiki Kaisha Toshiba
Output buffer circuit

GB2188505A
(en)

1986-03-24
1987-09-30
Motorola Inc
High speed write technique for a memory

GB2188505B
(en)

1986-03-24
1989-12-28
Motorola Inc
High speed write technique for a memory

FR2614743A1
(en)

1987-04-29
1988-11-04
Matra Harris Semiconducteurs
Digital integrated circuit with preloading

EP0434495A1
(en)

1989-12-21
1991-06-26
Bull S.A.
Memory bus precharge circuit

FR2656455A1
(en)

1989-12-21
1991-06-28
Bull Sa

PRELOAD CIRCUIT OF A MEMORY BUS.

US5243571A
(en)

1989-12-21
1993-09-07
Bull S.A.
Memory bus precharging circuit

GB2242767A
(en)

1990-04-06
1991-10-09
Mosaid Inc
Precharging DRAM bit lines to half supply potential

Also Published As

Publication number
Publication date

IT7924608D0
(en)

1979-07-24

FR2433224B1
(en)

1984-12-28

JPS5913115B2
(en)

1984-03-27

FR2433224A1
(en)

1980-03-07

DE2932019C2
(en)

1984-11-08

GB2028044B
(en)

1982-10-27

IT1122304B
(en)

1986-04-23

DE2932019A1
(en)

1980-02-14

JPS5525897A
(en)

1980-02-23

US4208730A
(en)

1980-06-17

Contact information