GB2028067A

GB2028067A – Symbol generator and a method for drawing graphic symbols
– Google Patents

GB2028067A – Symbol generator and a method for drawing graphic symbols
– Google Patents
Symbol generator and a method for drawing graphic symbols

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Publication number
GB2028067A

GB2028067A
GB7917093A
GB7917093A
GB2028067A
GB 2028067 A
GB2028067 A
GB 2028067A
GB 7917093 A
GB7917093 A
GB 7917093A
GB 7917093 A
GB7917093 A
GB 7917093A
GB 2028067 A
GB2028067 A
GB 2028067A
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GB
United Kingdom
Prior art keywords
counter
generator
dots
modulo
memory
Prior art date
1978-05-18
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Granted

Application number
GB7917093A
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GB2028067B
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Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Thales SA

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Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1978-05-18
Filing date
1979-05-16
Publication date
1980-02-27

1979-05-16
Application filed by Thomson CSF SA
filed
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Thomson CSF SA

1980-02-27
Publication of GB2028067A
publication
Critical
patent/GB2028067A/en

1982-12-22
Application granted
granted
Critical

1982-12-22
Publication of GB2028067B
publication
Critical
patent/GB2028067B/en

Status
Expired
legal-status
Critical
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Classifications

G—PHYSICS

G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS

G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION

G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators

G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory

G09G5/39—Control of the bit-mapped memory

G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Description

1 1 50 GB 2 028 067 A 1
SPECIFICATION
A symbol generator and a method for drawing graphic symbols This invention relates to the technical field of graphic terminals. More precisely, the invention relates to a graphic function generator and, more particularly, to a generator for drawing graphic sym bols.
Display systems which enable graphic images composed of geometric figures, alphanumeric characters and various signs to be displayed on the screen of a console are known in the art as graphic terminals. Various types of console may be envis- 80 aged according to the nature of the light screen:
cathode ray tube (CRT) consoles, consoles equipped with a liquid crystal panel (LCP), consoles equipped with a matrix of electroluminescent diodes, plasma panel consoles. Although still at the development 85 stage, these las t three types may be envisaged when the definition (number of dots per image) of the image to be displayed is not very high. Graphic con soles of the high definition type (greaterthan 250 x 250 dots) use cathode raytubes. The graphic con soles may be divided into two classes according to the nature of the cathode ray tube: one of these clas ses includes consoles equipped with a cathode ray tube of which the cathode screen has an intrinsic memory and on which the data of the image are stored and erased as required; the other class includes consoles equipped with a cathode ray tube of which the cathode screen has a very low rema nence so that it is necessary to add an erasable image memory where the data of the image are stored and may be read repetitively in order to refresh the displayed image. The work of M. MORVAN et al entitled “Images et Ordinateurs”, published by Larousse, Paris 1976, maybe usefully consulted on this subject.
A graphic function generator is a wired system which is intended to draw graphic images on sensi tive support. In general, it comprises various generators, namely: an alphanumeric character or, more generally symbol generator; a vector generator and, optionally, a circle generator. The graphic images are produced in the form of a series of dots which may be stored and then erased either completely or selectively. The sensitive support may be formed by the screen of a cathode ray storage tube, a photosensitive film, a magnetic or electrical memory unit, etc. – Underthe action of a control instruction, a symbol generator has to:
-produce the image data corresponding to a sym bol specified by a data word, -store these image data on an optionally erasable support at an address determined by a data word or by the previously stored symbol, -subsequently erase all or some of the previously stored symbols under the action of an instruction.
The generator has to enable each of the symbols to be written very rapidly, above all if the graphic image displayed is animated. In addition, it is desir able to be able to modify the size (dimensions) of the symbols.
Symbol generators enabling alphanumeric characters to be generated in the form of a series of discrete dots are known in the art. One such character generator is described in Applicants’ French Patent Application No. 77.05254 relating to “A Processor for an Information Terminal using a Television Receiver—. Known character generators are either limited in terms of speed or are complex where they are capable of modifying the size of the characters. In addition, they do not afford all the possibilities required of an interaction terminal.
The object of the present invention is to obviate the disadvantages referred to above and, in particular, to provide a compact symbol generator which may be produced in the form of or as part of a large scale integrated circuit (LSI circuit) or even by assembling commercially available medium scale integrated circuits (MS1 circuits).
Accordingly, the invention relates to a method and an arrangement for drawing graphic symbols composed of alphanumeric characters, various symbols and particular figures, such as quadrilaterals which are referred to hereinafter in short as “QUADS’s”.
In addition, means are provided for modifying the format 1 xm of the symbols, 1 and m being respectively the width and the height of the format.
According to one aspect of the invention, the size of the symbols may be modified as required by program.
According to another aspect of the invention, the symbols are drawn in such a way as to reduce the drawing time and to minimize the complexity of the writing circuits.
The method according to the invention comprises: -forming a grid of I.P xm.Q dots composed of a matrix of 1 columns each comprising m spaces each space comprising P.Q dots, the method being characterised in that this grid of dots is formed by creating adjacent columns of m.Q dots following a so-called “Grecian- path; -reading in a character memory dots representing a selected character atthe addresses created by the matrix 1 xm.
-simultaneously drawing all the dots of the grid on a sensitive support, storing the content of the character memory on this support.
According to another aspect of the invention, the drawing of a symbol may be interrupted and resumed at any time.
According to another aspect of the invention, an already stored symbol may be erased by forming a grid of I.P xm.Q dots and forcing the output of the character memory to the “black” level.
According to another aspect of the invention, a grid of I.P xrn.G dots is formed and the output of the memory is forced to the “white” level for drawing QUAD’s. According to this same aspect of the inven- tion, the output of the character memory is forced to the “black” level, in addition to which the values of the parameters m and 1 may be independently modified.
The symbol generator according to the invention comprises:
2 -a two-way data bus connected to an external control element, -a programmable writing unit which enables a grid of LP xm.Q dotsto be formed, this unit being con5 nected to the data bus and to a sequencing clock, -a read-only memory in which the alphanumeric characters to be generated are stored in the form of memory dots, this memory being connected to the data bus and to the writing unit, writing pointer enabling a given symbol to be drawn on a sensitive support, this pointer being connected to the data bus and to the writing unit.
The writing unit comprises means forforming LP columns and a logic writing means so that the dot grid is stored along a “Grecian” path.
Other features and advantages afforded by the invention Will become apparent from the following description which, in conjunction with the accompanying drawings, describes purely by way of example one embodiment of the invention. In the drawings:
Figure 1 is a block diagram of the elements which make up a graphic TV console, namely the TV set and its image memory, the control signal generator and a graphic function generator.
Figures 2a, 2b, 2c and 2d show how a symbol is represented and written in the form of a grid of dots.
Figure 3 is a block diagram of the symbol generator showing its three main parts, namely a writing unit, a read-only character memory and a writing pointer.
Figures 4a and 4b diagrammatically illustrate a modulo M counter and the corresponding counting diagram.
Figures 5a, 5b and 5c show in a synoptic form the architecture of the counters of the writing unit and the means for modifying the format of the dot grid.
Figures 6a and 6b are logic diagrams of one embodiment of the graphic symbol generator as a whole.
Figures 7a and 7b show one embodiment of the means forforming the columns of the dot grid and the details of the associated state recognition circuits.
Figures 8a and 8b show one embodiment of the means for forming the dots of a column of the dot grid and the details of the associated state recognition circuit.
Figure 9 shows the connections between the sym- bol generator and the external elements.
Figures 10a, 10b and 10c show one embodiment of the symbol generator based on MSI modules.
Table 1 shows the ASCII code of the various symbols.
In the following description of the invention, a symbol generator is described in its application to a graphic console equipped with a lowremanence cathode ray tube which requires the presence of an image memory in which the symbols have to be stored to enable the image displayed on the screen of the cathode ray tube to be refreshed repetitively. Numerous specific details of the character generator, such, as the counters, the registers and the instruction decoders have not been described because these elements are known in the art and GB 2 028 067 A 2 would complicate the description and obscure the novel features of the invention. Equally, however, it will be understood that numerous specific details have been included in the description in order to explain the new features of the generator and that they are not specifically necessary for carrying out the invention as described.
Figure 1 shows in a block diagram the principal elements for forming a graphic display console. This console comprises in particular the following conventional elements: -a television (TV) set 10 which, at its input, receives a composite video signal (VC), optionally modulated by a radio frequency carrier wave. This TV set corn- prises a cathode raytube (CRT) 11 of the monochrome or colour type; an amplifierldemodulator 12 which delivers to the cathode ray tube the video signal and, via pulse separators, the line and frame synchronising signals of the TV scan; these signals are delivered to a circuit 13 which produces the signals for deflecting the electron beam; -a signal generator 20 which produces a signal SYNC for synchronising the TV scan; reading address signals (IMRA) and control signals CMD associated with an image memory 30; -an image memory 30 formed by a block of random access memory (RAM) modules (panels) which may advantageously be of the dynamic type; this memory is used for storing the data of the image to be displayed; it may be written or erased and read by addressing its lines and its columns and by testing its control inputs; -a video mixer 40 which is an optional element if the TV set is a monitor equipped with a SYNC input and a video input. It enables the video signal V supplied by the output of the image memory to be mixed with the signal SYNC supplied by the signal generator 20; -a symbol generator 60 for forming series of dots which are representative of the symbol to be written in the image memory 30; it delivers to the image memory writing address signals IMWA and control signals CS; from an external unit for example a microprocessor MPU (not shown), it receives data and control signals and, from the signal generator 20, a writing authorisation signal WE and a clock signal CILK.
The other elements, such as the dialogue tools (light pen, handle, rolling ball) do not form any part of the invention and, for this reason, will not be described. The signal generator 20 may be of a known type and, in particular, a signal generator of the type described in Applicants’ French Patent Application filed on the same date underthe title “A Signal Generatorfor a Graphic Console”.
In brief, the graphic display system which has just been described functions in two modes, namely: a writing mode in which the symbol generator 60 generates predetermined symbols and, at the same time, writes them in the form of memory dots in the image memory 30, and a reading/display mode in which the signal generator 20 reads the content of the image memory and produces a video signal which is delivered to the TV set.
Fig. 2 shows how the displayed symbols are rep- 1 v 3 GB 2 028 067 A 3 resented.
Fig. 2a shows a matrix of 1 xrn spaces where 1 and m are respectively the number of columns identified from 0 to 4 and the number of rows identified from 0 to 6.
The origin of the space matrix is determined by the values Xi, Yi which belong to the displayed graphic image, X and Y respectively representing the abs cissa and the ordinate of the original image X., Y,,. In orderto illustrate Fig. 2a, a particular symbol (letter 75 A) has been drawn. The symbol generator also enables particular figures to be drawn, for example a rectangle of dimensions Ixm which is particularly useful for erasing a previously stored character; and even a smaller rectangle of dimensions I’xrn’. It will 80 be noted that the parameters I’and Wmay be made identical which enables figures such as “chequer boards” to be drawn. The spacing between two con secutive characters may be equivalent to one col umn or more where a “space” instruction available 85 on a keyboard or generated by a control unit is used.
The size (dimensions) of the stored symbols may be modified by two scale factors P and Q and applied respectively along the abscissa and the ordinate of the space matrix. To this end, each space of the mat- 90 rix Ixtn forms a sub-matrix of PxQ dots as shown in Fig. 2b. The scale factors P and Q may e modified independently, for example 1 < P -- 16 and 1 < Q < 16 The matrix Km and the sub matrixes PxQ form a 95 grid of I.Pxtn.Q dots. A given symbol may be drawn in different ways according to the path or course of the grid of I.PxmQ. dots. The path may follow a "zig-zag" course in the same way as a television scan. This means that dots already traversed have to be traversed again, result ing in a reduction in the writing speed, in addition to which up/down counters (also known as directlinverse counters) have to be used. A different path is the so-called "Grecian" path where the grid successively covers all the dots 1.0. of one column in a given direction and then the dots LQ of the adjacent column in the opposite direction, as shown in Fig. 2c. Other paths may be considered, for example a Grecian path in the form of rows or even a Grecian spiral. Forthe purposes of the following description, the path selected will be a Grecian path in the form of columns which requires only a single up/down counter, the path beginning at Xi, Yi (sign D) and f inishing at the point A: (Xl + (1 + 1) P, Yi); in the example selected, the path finishes at the point A corresponding to Xi + 6P. It can be seen from Fig ures 2a and 2d that the path will be different accord ing to the parity of the scale factor P. The direction which the dots of a column are counted will always be able to be identified if the parity of the successive dot columns is detected. Fig. 3 shows in a block diagram a symbol generator according to the invention and the princi pal connections on the one hand with the elements forming the graphic console and, on the other hand, with a control unit, for example a microprocessor (MPU) which is not shown in Fig. 3. The symbol generator 60 comprises the following elements: -a writing unit 60 comprising a signal generator 61 connected to a logic means 64 for controlling the operation of the generator, -a read-only character memory (ROM) 65 compris- ing a decoder 650 forthe code word corresponding to the symbol to be drawn, a decoder 651 for the reading addresses, a memory dot matrix 652 in which alphanumeric characters and the usual symbols are stored. This memory delivers a writing signal CGPT, -a writing point 66 comprising two registers, namely an X register 67 and a Y register 68. These registers may be loaded to the respective values Xi and Yi and may be incremented by the writing unit 61. The following elements are also shown in the Figu re: -an image memory 30 which comprises in particular an actual memory element 31 and a multiplexer 33 for addressing the memory either in the reading mode or in the writing mode under the action of the writing authorisation signal CGWE; in the reading mode, the memory 31 delivers a signal VIDEO representative of all the symbols drawn in this memory. The principal connections of the symbol generator to the other elements are as follows: It receives from the signal generator 20: -a clock signal CLK referred to hereinafter as the signal CKIN, -a writing authorisation signal CGWE. It receives from the control unit MPU: -on a two-way data bus MPDB words corresponding to instructions, commands, data, such as the code of the character to be drawn, -on an address bus M PAB the words corresponding to the addresses of the registers in which the data words are to be stored or read, -a signal MPRM which corresponds to a writing or reading instruction of the registers. The reading words may be transferred to the unit MPU by the two-way bus MPD13. It delivers to the image memory 30: -a signal CGPT corresponding to the character dots effectively stored in the ROM 65, -on an address bus IMWA, the writing address signals delivered by the writing pointer 67. The symbol generator uses two types of modulo M counters, namely up counters and up/down counters. The basic diagram of an N-bit modulo M counter (M -- 2 N) is shown in Fig. 4a. It enables the frequency fin of an input signal to be divided by a factor M, the linking of a modulo P counter and a modulo Q counter enabling the frequency of the input signal to be divided by a factor P.Q. Fig. 4b shows a diagram indicating the various existing counting possibilities: Up counting: a) recognising the state M of the counter and loading it to the value 1, b) recognising the state -1 of the counter and loading it to value -M. Down counting: c) recognising the state 1 of the counter and loading to the value M, cl) recognising the state M of the counter and load- 4 GB 2 028 067 A 4 ing it to the value -1. Instead of selecting the values (-M and -1), it is possible by using the relation M + M = 24-, to select the values M and -2. It is also possible to use an up/down counter connected to recognition circuits for recognising the states 1 and M and to load this counterto the values M and 1, respectively. Fig. 5a shows in a simplified diagrammatic form the means according to the invention for generating alphanumeric characters such as those shown in Table I corresponding to the ASCII code. The grid of I.Pxm.Q dots is generated by synchronous counters which can be incremented by the clock signal CKIN; these synchronous counters may be conceptionally divided into two parts: -the low part 62 corresponding to the columns of the dot grid, -the high part 63 corresponding to the dots of a column. The low part comprises: a parity flip-flop 62C of which the output signal indicates the parity of the columns of the grid, a modulo P up counter 62A of which the output signal validates a modulo L up counter 62B which delivers the reading addresses (I. - 11) to a read-only character memory 65. The high part comprises: a modulo m up/down counter 63B which supplies the reading addresses (mo - mi) of the read-only memory. On the other hand, the read-only character mem- ory 65 is connected to the data bus MPDB which supplies the code of the character to be drawn. At its output D,,, it delivers data signals which are representative of the character selected. The counter 62B delivers a signal A corresponding to the state _- I and a signal B corresponding to the state I + 1. The counter 63A delivers a signal corresponding to the state Q and a signal corresponding to the state "'I". The counter 63B delivers a signal corresponding to the state 0 and a signal correspond- ing to the state m. The flip-flop circuit 62C of the T type delivers a signal PRT in the low state. When the parity of the column of dots to be drawn is even, this signal enables the counting direction of the counters 63a and 63b to be controlled. Logic means enable the following signals to be generated: a signal Efor validating the counter 62A and the flip-flop 62C, a signal E" for validating the counter 63A and a counting direction signal Up (up counting) corresponding to the columns of even order. These three signals E', E" and Up have to satisfy the following relations: E' - A. [[(C U p] + [(F.U p) 1 1 + B 1:11. ( EX p) + jr. u p) U p. (MA) where as indicated above: A --1 B = (1 + 1) C 0.1 F =m, Q PTR = column & even order. According to the invention, the format I of the matrix of character spaces may be modified. Fig. 51130 shows the means for modifying the number of rows m of the matrix. A state m'< m of the counter 63B is recognised and the corresponding signal is applied to a first input of an "AND" gate which, at a second input, receives an instruction QUADm'. The output signal of this gate is applied to a first input of an "OR" gate which, at a second input, receives the signal corresponding to the state m. Fig. 5.C shows the means for modifying the number 1 of columns of the matrix. A state l' < 1 of the counter 62B is recognised and the corresponding signal is applied to a first input of a logic "AND" gate (621) which receives on the one hand at a second input an instruction QUAD I'and, on the other hand, at a third input a signal corresponding to the state --2" of the counter 62A; the output of this AND gate is applied to an input of the counter 62B which enables this counter to be preset to the state (1 + 2), with the result that drawing of the dot matrix is stopped. In order to generate a grid of I.Pxrn.Q dots, a con trol pulse CMD enables the flip-flop circuit 62C to be positioned at the low level, the counter 62A to loaded to the value P and the counter 62B to be set to the zero value. After one drawing cycle, the state of the various counters is as follows: The flip-flop 63 is in a state corresponding to the parity of the last column drawn which depends on the product I.P, the counter 62A is in the state (P), the counter 62B is in the state (1 + 2), the counter 63A is in the state ('1 ") state and the counter 63B is in the state (zero). The rate at which the dot grid is generated and, hence, the time taken to draw a symbol is determined by the rate of the clock signal CKIN. This rate is limited by the electrical performance levels of the electronic circuits forming the generator, above all the read-only character memory. The time taken to draw one dot of the grid may be less than a fraction of a microsecond, the time taken to draw up a complete symbol being proportional to the product IP.mQ. Table 1 shows by way of illustration the ASCII codes of the words which specify the characters and the control signals: -the 95 characters are specified by the code words H "20" to H---71E- (H = hexadecimal), -the control signals are specified by code words placed from H'00to WOF', for example: zeroing of the writing pointer; X register WOD', Y register WOE. Fig. 7a shows in a block diagram the architecture of that part of the counter 62 which forms the I.P columns of the dot grid. The counter 62A is connected to a register 62E in which the value of the scale factor P is stored by the application of a cornmand to the input L. At its outputs, this register delivers the complemented value"P. The outputs of the counter 62A are connected to a state recognition circuit 62D which enables the state -2 of this counter to be recognised. The counter 62B is linked to the counter 62A. It outputs 1. - 1, are connected to a three-stage state recognition circuit 62F which enables the following states to be recognised: -- 4, 5 and 3. Fig. 7b shows in the form of a synoptic diagram the details of the state recognition circuits 62D and 62F. The output of the stage of the recognition circuit GB 2 028 067 A 5 62F, which recognises the state 3, is connected to a first input of a logic "ANW gate 621 which, at a second input, receives the control signal QUAD and, at a third input, the state -2 of the counter 62A. Fig. 8a shows in a block diagram the architecture of the counter 63 for generating the m.Q dots of a column of the dot grid. The inputs of the counter 63A are connected to the outputs of an operator 63C which enables these outputs to be forced to a state "ONE" (000%. The inputs of the operator 63C are connected to the inputs of a register 62D which enables the value of the scale factor Q to be stored through a loading input L. The outputs of the counter 63A are connected on the one hand to a comparator 63E which enables the state Q of this counterto be identified and, on the other hand, to a recognition circuit 63F which enables the state 1 to be recognised. The outputs S of the comparator and of the recognition circuit are applied to the inputs 1 and 0 of a multiplexer 63G controlled by the signal U/D generated by the above- mentioned logic writing means 64. The output S of this multiplexer is applied to a first input of an "ANW gate 630 of which the second input receives the validation signal E". The output of the gate 630 enables the counter 63A to be loaded to the value 1 when the counting direction is U (up) and inversely to the value Q when the counting direction is D (down). The forcing operator 63C is forced to the state---ONCwhen the counting direction is U (up). The outputs m.-m, of the counter 63B are connected to a state recognition circuit 63H comprising three stages which enable the states 0, 6 and 3 of this counter to be recognised. Fig. 81 shows in the form a synoptic diagram the structural details of the recognition circuits 63F and 63H. The output of the stage of the recognition circuit 62H which recognises the state 3 is connected to a first input of a logic "ANW gate 63 which, at a second input, receives the control signal QUADm' and, at a third input, a signal corresponding to the state Q of the counter 63A. Fig. 9 shows in a diagrammatic form the connections with the external elements, namely: -a two-way eight-bit data bus MPDB which sup- plies: -the signals specifying the character codes to the seven-bit read- only character memory 65, -the signals specifying the value of the scale factors P and Q to the registers P and Q of the counters 62A and 63A, the signals specifying the values Xi and Yi to the X and Y registers of the writing pointer 66, -the zeroing signal for the writing pointer, -the zeroing signals for the X and Y registers of the writing pointer, -the signal CIVIP for releasing the writing unit 61, - the control signal QUAD (7 x 5), -the signal QUAD (4 x 4) -a four-bit address bus MPAB which supplies in particular the addresses of the following registers: -X register and Y register of the writing pointer 66 -P register and Q register of the counters 62 and 63 -a clock signal CKIN, -a signal CGWE which authorises the operation of the symbol generator. The generator delivers the following signals: -on a bus IMWA the reading address signals to an image memory or to a sensitive support, -a signal CGBY indicating the busy state of the generator, -a dot writing signal CGPT. The signal CG PT is generated from the output signal of the read-only character memory which is connected to a first input of an---OWgate 653 which, at its second input, receives a control signal corresponding to an instruction QUAD (7 x 5). The output of this gate 653 is connected to the first input of an "ANW gate 654 which, at a second input, receives the signal CGWE and, at a third input, the signal A corresponding to the state 1 -- 4 of the counter 62B. The signals for incrementing the synchronous registers 67 and 68, which form the writing pointer incrementable by the signal CKIN, are the signals EN/X and EN/Y generated by the logic means 64; the signal which specifies the counting direction of the register 68 is the signal U6.Y. On the other hand, an "erasing" signal and a "marking" signal are available, enabling an already stored characterto be erased when the signal QUAD (7 X 5) is at the upper level. Fig. 6 shows the complete diagram of a symbol generator. The logic means 64, which enables the signals E', E" and U/DXfor controlling the counters to be generated from the state of the counters 62A, B and C and 6Mand B, isformed by inverters[, to I., logic gates of the "ANW type G, to G8 and logic gates of the "OR" type G,,, and G,,. The read-only character memory 65 receives the seven-bit character code words through a control register 100 CMD.REGIST. of which the inputs areconnected to the data bus NPD13. This register cornprises in particular a loading input L which receives a signal derived from the address bus MPAB. The registers 62C and 63D which enable the values of the scale factors P and G, respectively, to be recorded are connected to the data bus MPDB and, at their input L, receive a loading signal derived from the signals available on the address bus MPAB. It will be recalled that, in the reading mode, these registers 62C and 63D are accessible through the control unit MPU. The signal CGWE, which authorises the drawing of a graphic symbol, is applied to the input of the logic means 64 and enables drawing to be interrupted and resumed at any time. In addition, this signal CGWE is applied to an input of the gate 654 for validating the output signals of the read-only memory 65. The logic means 64 supplies a signal CGBY indicating occupation of the graphic symbol generator so that, if necessary, an interruption signal is delivered to the control unit MPU. Fig. 10 shows one embodiment of the graphic symbol generator formed by the assembly of commercially available MSI (medium scale integrated) circuits and SSI (small scale integrated) circuits. The counters 62A and 62B are LS 163 packages; the counters 63A and 63B are LS 169 packages; the parity flip-flop 62C is an LS 74 package; the recognition circuits 63D and 63F are combined in an SFC 71310 package; the recognition circuits 63H and 63F 6 GB 2 028 067 A 6 are combined in an SFC 71301 package; the forcing operator 63C is formed by an LS 157 package; the comparator 63E is an LS 85 package; the read- only character memory is a 3608 package associated with 5 an LS 151 package; the registers 62C and 63D are LS 175 packages. In addition, the Figure shows threestate barriers formed by DM 8097 packages which enable the registers 62C and 63D to be read. The additional elements, such as the logic gates and the inverters, are formed by SSI packages. In addition to the advantages already mentioned, the inventiosi as described in the foregoing has the advantage that it can be produced by an MOS (metal oxide semi-conductor) technique with very large scale integration (VI-SI) and the further advantage of enabling a dot grid of variable format to be produced. The invention is by no means limited to the described embodiment and may comprise other var- iants. In particular, the values of the parameters 1, m, P and Q may be modified, the number of symbols generated may be increased or reduced by changing the dimensions of the read-only character memory and the shape of the graphic symbols may be mod- ified by differently programming the read-only character memory. The invention may be used in numerous symbol display and writing systems and, in particular, in graphic consoles using a cathode ray storage tube, Claims (23) graphic X.Y plotters, plasma screens etc:.... in systems for recognising image forms or for spatially filtering an image. CLAIMS 1. A method for drawing graphic symbols on a sensitive support in which a series of discrete dots representing a given symbol is stored, characterised in that it comprises: -forming a grid of W=Q dots on a matrix of bun spaces each forming a sub-matrix of PxQ dots, -reading in a fixed memory the memory dots representing a selected character according to the addresses of the matrix Ixm, -drawing the dot grid on a sensitive support, -storing the dots representing the characters. 2. A method as claimed in Claim 1, in which the parameters land m determine the format of the symbols, characterised in that it comprises independently varying the value of these parameters for modifying the shape of the symbols. 3. A method as claimed in Claim 1, in which the parameters P and Q are scale factors, characterised in that it comprises varying the value of these factors for modifying the size of the symbols. 4. A method as claimed in Claim 1, characterised in that it comprises forming I.P adjacent columns of m.Q adjacent dots along a "Grecian" path. 5. Amethod as claimed in Claim 1, in which an already written symbol is erased, characterised in that it comprises forcing the output of the memory to the low level. 6. A symbol generator for drawing alphanumeric characters and simple geometric figures, characterised in that it comprises; -a two-way data bus connected to an external con- trol element, -a programmable writing unit for forming a grid of I.Pxm.G dots corresponding to I.P columns of dots each containing mQ dots, this unit being connected to the data bus and to a clock,. -a fixed memory in which the alphanumeric characters to be generated are stored in the form of memory dots, this memory being connected to the data bus and to the counting unit, -a writing pointer for drawing a given symbol on a sensitive support, this pointer being connected to the data bus and to the counting unit, -the writing unit comprising a counter, means for forming columns of dots, means for forming the dots of the columns and logic writing means so that the grid of dots is described along a -Grecian- path. 7. A generator as claimed in Claim 5, characterised in that the means for forming the columns of the dot matrix is a synchronous one-way counter comprising: a modulo P counter linked to a modulo 1 counter, recognition circuits for recognising states of these two counters and a parity counter for the columns. 8. A generator as claimed in Claim 5, characterised in that the means for forming the dots of a col- umn of the matrix isa synchronous up/down counter comprising: a modulo Q counter linked to a modulo m counter and recognition circuits for recognising states of these two counters. 9. A generator as claimed in Claim 6, character- ised in thatthe modulo P counter is ani-bit up counter connected to a register which contains the complemented value P and to a recognition circuit for recognising the -2 counting state. 10. A generator as claimed in Claim 6, character- ised in thatthe column parity counter is a flip-flop circuit of the "T" type. 11. A generator as claimed in Claims 6to 10, characterised in that the one-way counter comprises a release input for setting the "T" type flipflop cir- cuitto the "zero" state, for loading the modulo P counter to the value'- P" and for setting the modulo 1 counter to the "zero" state. 12. A generator as claimed in Claim 5, characterised in that the means for forming the dots of a col- umn of the matrix is a synchronous up/down counter comprising: a modulo Q counter linked to a modulo m counter and recognition circuits for recognising states of these two counters. 13. A generator as claimed in Claim 12, charac- terised in that the modulo Q counter is a synchronous i-bit up/down counter connected through a forcing operator for imposing the value '1 " to a register which contains the value Q and recognition circuits for recognising the "Q" and "V states. 14. A generator as claimed in Claim 12, characterised in that the modulo m counter is a synchronous up/down counter of which the outputs are connected to a recognition circuit for recognising them and 0 states. 15. A generator as claimed in Claim 9, characterised in that the modulo [counter comprises at least one recognition circuit for the state l' < 1 of which the output presets this counter to the value[+ 2. 16. A generator as claimed in Claim 14, charac- terised in that the module, m counter comprises at i 7 GB 2 028 067 A 7 least one recognition circuit for recognising a state m'< m of which the output is connected to the output of the recognition circuit for them state. 17. A generator as claimed in Claims 8 to 12, characterised in that the logic counting means comprises: a signal for validating the modulo P counter, a signal for validating the parity flip- flop, a signal for validating the counting of the modulo G and modulo m counters. 18. A generator as claimed in Claim 6, characterised in that the logic counting means comprises a signal input for interrupting the writing unit. 19. A generator as claimed in Claim 6, characterised in that the character memory comprises means for forcing its output to the upper level. 20. A generator as claimed in Claim 6, characterised in that the fixed memory is connected to an operator for forcing its output to the lower level. 21. A generator as claimed in Claim 6, character- ised in that the fixed memory is a read-only memory (ROM). 22. A generator as claimed in Claim 6, characterised in that the fixed memory is a programmable read-only memory (PROM). 23. A graphic generator substantially as hereinbefore described with reference to the figures of the accompanying drawings. 7 3 0 \7 0 0 1 1 1 0 1 1 1 1 6 1 1 0 0 1 1 1 0 0 1 1 1 0 1 0 1 0 1 1 0 1 0 1 Z- - 4 5 6 7 B D 11 F 3 0 c 60 0 0 p p 0 0 0 1 1 A Q 0 3_ 2 B it b L3 Cl--- 3 c c 0 1 0 0.1 C. 4 D T d t B U e U 19, 6 p v f v 7 G W 9 W 8 11 X II X m I Y i Y 0 1 0 A -X-. j Z j z 1 0 1 1 1, + 1; K E]c k L 1 1 m Printed for Her Majesty's Stationery Office by The Tweeddale Press Ltd., Berwick-upon-Tweed, 1980. Published at the Patent Office, 25 Southampton Buildings, London, WC2A 1 AY, from which copies may be obtained. GB7917093A 1978-05-18 1979-05-16 Symbol generator and a method for drawing graphic symbols Expired GB2028067B (en) Applications Claiming Priority (1) Application Number Priority Date Filing Date Title FR7814765A FR2426295A1 (en) 1978-05-18 1978-05-18 SYMBOL GENERATOR FOR GRAPHIC CONSOLE Publications (2) Publication Number Publication Date GB2028067A true GB2028067A (en) 1980-02-27 GB2028067B GB2028067B (en) 1982-12-22 Family ID=9208403 Family Applications (1) Application Number Title Priority Date Filing Date GB7917093A Expired GB2028067B (en) 1978-05-18 1979-05-16 Symbol generator and a method for drawing graphic symbols Country Status (6) Country Link US (1) US4297694A (en) JP (1) JPS5513495A (en) CA (1) CA1152661A (en) DE (1) DE2920229C2 (en) FR (1) FR2426295A1 (en) GB (1) GB2028067B (en) Families Citing this family (6) * Cited by examiner, † Cited by third party Publication number Priority date Publication date Assignee Title DE3014437C2 (en) * 1980-04-10 1982-05-27 Siemens AG, 1000 Berlin und 8000 München Arrangement for displaying alphanumeric characters on a screen of a display unit US4593278A (en) * 1982-09-28 1986-06-03 Burroughs Corp. Real time graphic processor DE3412714A1 (en) * 1983-04-06 1984-10-11 Quantel Ltd Image processing system US4622641A (en) * 1983-09-13 1986-11-11 International Business Machines Corp. Geometrical display generator JPH07501164A (en) * 1991-11-21 1995-02-02 イマジネイション テクノロジーズ リミテッド Video/graphics memory system US6022788A (en) * 1997-12-23 2000-02-08 Stmicroelectronics, Inc. Method of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed thereby Family Cites Families (11) * Cited by examiner, † Cited by third party Publication number Priority date Publication date Assignee Title US3457371A (en) * 1965-12-27 1969-07-22 Xerox Corp Dataphone driven remote graphic display system US3786478A (en) * 1972-08-17 1974-01-15 Massachusettes Inst Technology Cathode ray tube presentation of characters in matrix form from stored data augmented by interpolation DD107156A1 (en) * 1973-10-03 1974-07-12 US3893100A (en) * 1973-12-20 1975-07-01 Data Royal Inc Variable size character generator with constant display density method US3971044A (en) * 1974-11-11 1976-07-20 Ibm Corporation Electronic horizontal shifting and variable print width in a buffered printer DE2559627C3 (en) * 1975-02-03 1980-10-02 Canon K.K., Tokio Information recorder JPS526419A (en) * 1975-07-07 1977-01-18 Fuji Xerox Co Ltd Dot matrix convertor JPS5942309B2 (en) * 1975-09-12 1984-10-13 株式会社精工舎 Image forming method US4070710A (en) * 1976-01-19 1978-01-24 Nugraphics, Inc. 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Character generator for visual display devices JPS52105734A (en) * 1976-03-01 1977-09-05 Canon Inc Signal coverter 1978 1978-05-18 FR FR7814765A patent/FR2426295A1/en active Granted 1979 1979-05-16 GB GB7917093A patent/GB2028067B/en not_active Expired 1979-05-16 US US06/039,260 patent/US4297694A/en not_active Expired - Lifetime 1979-05-16 CA CA000327786A patent/CA1152661A/en not_active Expired 1979-05-17 JP JP6100979A patent/JPS5513495A/en active Granted 1979-05-18 DE DE2920229A patent/DE2920229C2/en not_active Expired Also Published As Publication number Publication date JPS6226471B2 (en) 1987-06-09 FR2426295A1 (en) 1979-12-14 CA1152661A (en) 1983-08-23 DE2920229A1 (en) 1979-11-22 GB2028067B (en) 1982-12-22 JPS5513495A (en) 1980-01-30 FR2426295B1 (en) 1981-09-11 DE2920229C2 (en) 1985-03-21 US4297694A (en) 1981-10-27 Similar Documents Publication Publication Date Title US4692757A (en) 1987-09-08 Multimedia display system US4129859A (en) 1978-12-12 Raster scan type CRT display system having an image rolling function US4266253A (en) 1981-05-05 Processor for a graphic terminal JPH0760305B2 (en) 1995-06-28 Video display control circuit US3952296A (en) 1976-04-20 Video signal generating apparatus with separate and simultaneous processing of odd and even video bits US3631457A (en) 1971-12-28 Display apparatus US4309700A (en) 1982-01-05 Cathode ray tube controller GB2028067A (en) 1980-02-27 Symbol generator and a method for drawing graphic symbols US4156238A (en) 1979-05-22 Display apparatus having variable text row formating US4205310A (en) 1980-05-27 Television titling apparatus and method JPH0616230B2 (en) 1994-03-02 Multi-screen display method JPS5872989A (en) 1983-05-02 Display font formation system JPS60251473A (en) 1985-12-12 Tabulation system JPS6060062B2 (en) 1985-12-27 color graphic display device US4511892A (en) 1985-04-16 Variable refresh rate for stroke CRT displays JP2687100B2 (en) 1997-12-08 On-screen display circuit US6249273B1 (en) 2001-06-19 Method of and device for displaying characters with a border JP2898482B2 (en) 1999-06-02 Computer game equipment JPS602670B2 (en) 1985-01-23 Display control method JPH02277097A (en) 1990-11-13 Automatic scrolling device JPS60134284A (en) 1985-07-17 Screen inversion display system JPS60502071A (en) 1985-11-28 Feedback vector generator and method JPH087547B2 (en) 1996-01-29 Display memory address device JPS6142683A (en) 1986-03-01 Crt display unit JPS6364085A (en) 1988-03-22 Display controller Legal Events Date Code Title Description 1999-06-09 PE20 Patent expired after termination of 20 years Effective date: 19990515
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