GB1025378A – Error-correcting data transfer system
– Google Patents
GB1025378A – Error-correcting data transfer system
– Google Patents
Error-correcting data transfer system
Info
Publication number
GB1025378A
GB1025378A
GB41290/64A
GB4129064A
GB1025378A
GB 1025378 A
GB1025378 A
GB 1025378A
GB 41290/64 A
GB41290/64 A
GB 41290/64A
GB 4129064 A
GB4129064 A
GB 4129064A
GB 1025378 A
GB1025378 A
GB 1025378A
Authority
GB
United Kingdom
Prior art keywords
word
bit
error
register
correction
Prior art date
1963-11-28
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB41290/64A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefunken Patentverwertungs GmbH
Original Assignee
Telefunken Patentverwertungs GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1963-11-28
Filing date
1964-10-09
Publication date
1966-04-06
1964-10-09
Application filed by Telefunken Patentverwertungs GmbH
filed
Critical
Telefunken Patentverwertungs GmbH
1966-04-06
Publication of GB1025378A
publication
Critical
patent/GB1025378A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
H—ELECTRICITY
H03—ELECTRONIC CIRCUITRY
H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
H03M13/13—Linear codes
H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H—ELECTRICITY
H03—ELECTRONIC CIRCUITRY
H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
H03M13/13—Linear codes
H03M13/17—Burst error correction, e.g. error trapping, Fire codes
Abstract
1,025,378. Error correction. TELEFUNKEN PATENTVERWERTUNGSGESELLSCHAFT G.m.b.H. Oct. 9, 1964 [Nov. 28, 1963], No. 41290/64. Heading G4A. In an error-correcting data transmission system, an n-digit check word is formed for each data word by adding without carries into an accumulator a characteristic n-digit word for each binary » 1 » in the data word, the receiver unit forming from the received data and check words an n-digit correction word which is all » 0 «s only if the transmission is error-free. The system is applicable to » group codes», reference being made to the book » Error Correcting Codes » by W. W. Peterson. As described, a 4-bit data word to be transmitted is provided with a 7-bit check word capable of correcting either single or double bit errors. As shown in Fig. 2, a counter 6 and associated recoder (not shown) provides inputs to AND gates 11-14 which inputs are arranged to represent four successive 7-bit words in synchronism with the four data bits to be transmitted which are applied to open the AND gates 11-14 when the data bit to be transmitted is a » 1 «, thereby causing a 7-bit word to be added without carries in EXCLUSIVE- OR gates 7-10 to the contents of a register 33, which at the conclusion of the addition stores a 7-bit check word transmitted after the data word to the receiver. Single error correction.-The receiver, Fig. 3 (not shown), is effective to correct a single bit error in the received data or check words, since a single error results in a 7-bit correction word which corresponds exactly with a 7-bit word whose position in a code table (given in the Specification) corresponds to the position in error. The receiver operates in two steps in the first of which a correction word is formed and in the second of which the received information is corrected. In the first step, a multiple contact 19 is in the position shown and the eleven incoming bits received at 17 are effective as in the transmitter to accumulate in a register 33 a 7-bit word formed by gating the contents of a counter 6, corresponding to the counter 6 of Fig 1 (not shown), to EXCLUSIVE-OR gates 7-10 if the incoming bit is «1», thereby forming a 7- bit correction word in the register 33. In the second step, the multiple contact 19 is changed over and the received information, which has been delayed in a shift register 18 is transmitted to an output 22 via an EXCLUSIVE-OR gate 23 whose other input is connected to a NOR gate 20 and, as the counter 6 is stepped through its eleven coded values, these are compared with the contents of the register 33. If a single error has occurred, the recognition of a successful comparison causes the NOR gate 20 to produce an output which corrects the erroneous bit at the EXCLUSIVE-OR gate 23. If the received data is correct, the contents of the register 33 is zero and the correctly received data is passed unchanged through the gate 23. If more than one error occurs, this is detected since the contents of the register 33 is non-zero, but correction is not possible. Double error correction.-Due to the chosen code, the correction word formed if a double error occurs is equal to the sum without carries of two code words whose position in the code table defines the positions in error. By providing an auxiliary register and a further multiple contact the receiver can be adapted (Fig. 4, not shown) to ascertain the positions in error.
GB41290/64A
1963-11-28
1964-10-09
Error-correcting data transfer system
Expired
GB1025378A
(en)
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
DET25151A
DE1238245B
(en)
1963-11-28
1963-11-28
Error-correcting data transmission system
Publications (1)
Publication Number
Publication Date
GB1025378A
true
GB1025378A
(en)
1966-04-06
Family
ID=7551880
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB41290/64A
Expired
GB1025378A
(en)
1963-11-28
1964-10-09
Error-correcting data transfer system
Country Status (3)
Country
Link
US
(1)
US3340507A
(en)
DE
(1)
DE1238245B
(en)
GB
(1)
GB1025378A
(en)
Families Citing this family (3)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3487362A
(en)
*
1967-04-10
1969-12-30
Ibm
Transmission error detection and correction system
CA932469A
(en)
*
1967-09-27
1973-08-21
International Business Machines Corporation
Arrangement on data processors for checking programmes
NL9001296A
(en)
*
1990-06-08
1992-01-02
Philips Nv
TELETEXT DECODER, AND AN ERROR DETECTION AND CORRECTION CIRCUIT.
Family Cites Families (3)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3123803A
(en)
*
1964-03-03
E de lisle ftai
US3159810A
(en)
*
1960-03-21
1964-12-01
Sylvania Electric Prod
Data transmission systems with error detection and correction capabilities
US3164804A
(en)
*
1962-07-31
1965-01-05
Gen Electric
Simplified two-stage error-control decoder
1963
1963-11-28
DE
DET25151A
patent/DE1238245B/en
active
Pending
1964
1964-10-09
GB
GB41290/64A
patent/GB1025378A/en
not_active
Expired
1964-11-30
US
US414799A
patent/US3340507A/en
not_active
Expired – Lifetime
Also Published As
Publication number
Publication date
DE1238245B
(en)
1967-04-06
US3340507A
(en)
1967-09-05
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